Sweeping drive unit and display device including the same

Description

1 / 46 Sweeping drive unit and display device including the same Technical Area

[0001] The present invention relates to a scanning driver and a display device including the same. Background of the invention

[0002] As the information society develops, the demand for display devices for displaying images increases in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart televisions.

[0003] Display devices can be flat panel display devices, such as liquid crystal display devices, quantum dot display devices, and organic light emitting display devices.

[0004] A display device includes a display panel that includes data lines, scan signal lines, and a plurality of pixels connected to the data lines and scan signal lines, a scan driver that provides scan signals to the scan signal lines, and a data driver that provides data voltages to the data lines.

[0005] The sweep driver can be formed in a non-visible area of ​​the display panel. The sweep driver formed in the display panel includes a plurality of thin-film transistors that are switched on and off in response to gate control signals. Because the thin-film transistors of the sweep driver are kept on or off for a certain period of time, the operating characteristics, such as the operating conditions, of the thin-film transistors must be kept constant. Petition 870250086416, dated 09 / 24 / 2025, page 29 / 84 2 / 46 Summary of the Invention Aspects to be achieved by the Invention

[0006] Aspects of the present invention provide a sweep driver capable of protecting thin-film transistors by being altered in the design structure to reduce a voltage difference between both ends of a thin-film transistor that is subjected to stress due to the amount of current or voltage initialization, and a display device including the sweep driver.

[0007] Aspects of the present invention also provide a sweep driver capable of reducing the electrical stress of thin-film transistors by improving the material of a semiconductor layer of at least one thin-film transistor connected directly to a pull-up node of each sweep signal output stage, and a display device including the sweep driver.

[0008] However, aspects of the present invention are not limited to those set forth herein. The above and other aspects of the present invention will become more apparent to those skilled in the art to which the present invention relates by consulting the detailed description of the present invention set forth below. Means of Achieving Aspects of the Invention

[0009] According to one aspect of the present invention, a sweep driver comprising stages that sequentially emit sweep signals to sweep signal lines during an active period of one nth frame, wherein N is a positive integer, and at least one of the stages comprises an output node controller that provides a gate voltage connected to a pull-up node in response to a gate control signal from a display driver, and an output controller that emits a sweep clock signal, which is fed into a sweep clock terminal, to a connected sweep signal line as a sweep signal when the gate voltage Petition 870250086416, dated 09 / 24 / 2025, page 30 / 84 3 / 46 connected is provided to the pull-up node.

[0010] In one embodiment, the output node controller comprises a thin-film transistor that is switched on in response to a simultaneous drive control signal, provides at least one sweep clock signal, which is fed into a first electrode, to the pull-up node to which a second electrode is connected, and periodically receives at least one sweep clock signal through the first electrode while it is switched off during the active period.

[0011] According to one aspect of the present invention, a display device comprising a plurality of pixels arranged in a display area of ​​a display panel, a touch detection unit mounted on the front of the display panel and integrally formed with the display panel, a touch driver that detects the touch of a human body or a touch pen using a plurality of touch electrodes arranged in the touch detection unit, a display driver that controls the data voltages supplied to the pixels and the display time of the pixel image, and a scan driver that sequentially drives the scan signal lines, which are connected to the pixels, in response to a gate control signal from the display driver.

[0012] In one embodiment, the sweep driver comprises stages that sequentially emit sweep signals to the sweep signal lines during an active period of one nth frame, wherein N is a positive integer, and at least one of the stages comprises an output node controller that provides a gate-on voltage to a pull-up node in response to a gate control signal from the display driver, and an output controller that emits a sweep clock signal, which is fed into a sweep clock terminal, to a connected sweep signal line as a sweep signal when the gate-on voltage is supplied to the node. Petition 870250086416, dated 09 / 24 / 2025, page 31 / 84 4 / 46 pull-up.

[0013] In one embodiment, the output node controller comprises a thin-film transistor that is switched on in response to a simultaneous drive control signal, provides at least one sweep clock signal, which is fed into a first electrode, to the pull-up node to which a second electrode is connected, and periodically receives at least one sweep clock signal through the first electrode while it is switched off during the active period. Effects of the Invention

[0014] A sweep driver and a display device including the same, according to the embodiments, are altered in the design structure to reduce the voltage difference between both ends of a thin-film transistor that is subjected to stress due to voltage initialization, etc. Therefore, the electrical stress of the thin-film transistors can be reduced and the reliability can be improved.

[0015] Furthermore, a sweep driver and a display device including the same, according to the embodiments, can enhance or stabilize electrical characteristics, such as high-speed drive, operating range variation, and suppression of threshold voltage fluctuation, by enhancing the material of a semiconductor layer of at least one thin-film transistor connected directly to a pull-up node of each sweep signal output stage.

[0016] However, the effects of the present invention are not limited to those set forth herein. The above and other effects of the present invention will become more apparent to those skilled in the art in the field to which the present invention relates, by reference to the claims. Brief Description of the Drawings

[0017] Figure 1 is a perspective view of a device of Petition 870250086416, dated 09 / 24 / 2025, page 32 / 84 5 / 46 display according to a modality;

[0018] Figure 2 is a cross-sectional view of the display device according to the embodiment;

[0019] Figure 3 is a plan view of a display unit of the display device according to the embodiment;

[0020] Figure 4 is a block diagram of a display panel and a display driver according to an embodiment;

[0021] Figure 5 is an example diagram of a scan driver according to an embodiment of the present invention;

[0022] Figure 6 is a detailed circuit diagram of a first embodiment of an nth stage of the sweep driver illustrated in Figure 5;

[0023] Figure 7 is a waveform diagram illustrating changes in voltage levels of detection control signals, sweep clock signals and a pull-up node during an active period of an nth frame period;

[0024] Figure 8 is a circuit diagram that illustrates a change in the voltage difference between the first and second electrodes of a fifth transistor illustrated in Figure 6;

[0025] Figure 9 is a detailed circuit diagram of a second embodiment of the nth stage of the sweep driver illustrated in Figure 5;

[0026] Figure 10 is a cross-sectional view illustrating the cross-sectional structure of the fifth and seventh transistors of the sweep driver illustrated in Figures 6 and 9;

[0027] Figures 11 and 12 are perspective views of an example application of a display device according to an embodiment of the present invention; and

[0028] Figures 13 and 14 are perspective views of an example of the application of a display device according to a fashion. Petition 870250086416, dated 09 / 24 / 2025, page 33 / 84 6 / 46 Validity of the present invention. Detailed Description of Preferred Options

[0029] The present invention will be described in more detail below, with reference to the accompanying drawings, in which preferred embodiments of the description are shown. This description may, however, be embodied in different forms and should not be interpreted as limited to the embodiments set forth herein. Instead, these embodiments are provided so that this description is complete and comprehensive, and fully conveys the scope of the description to those skilled in the art.

[0030] It will also be understood that when a layer is referred to as being “on top of” another layer or substrate, it may be directly on top of the other layer or substrate, or intermediate layers may also be present. The same reference numbers indicate the same components throughout the descriptive report.

[0031] It is understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below could be called a second element without departing from the teachings of the present invention. Similarly, the second element could also be called the first element.

[0032] Each of the features of the various embodiments of the present invention can be combined or combined with each other, partially or totally, and technically, various types of interlocking and actuation are possible. Each embodiment can be implemented independently of the other or can be implemented together in association.

[0033] The specific modalities will be described below. Petition 870250086416, dated 09 / 24 / 2025, page 34 / 84 7 / 46 reference to the attached drawings.

[0034] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0035] With reference to Figure 1, display device 10 can be applied to portable electronic devices such as cell phones, smartphones, tablets, personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, display device 10 can be applied as a display unit for a television, a notebook, a monitor, a billboard, or an Internet of Things (IoT) device. In another example, display device 10 can be applied to wearable devices such as smartwatches, cell phones, eyeglass-type displays, and head-mounted displays (HMDs).

[0036] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral, with short sides in a first direction DR1 and long sides in a second direction DR2. Each corner where a short side, extending in the first direction DR1, meets a long side, extending in the second direction DR2, may be rounded with a predetermined curvature or may be straight. The planar shape of the display device 10 is not limited to a quadrangular shape, but may also be similar to other polygonal, circular, or elliptical shapes.

[0037] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400 and a power supply unit 500.

[0038] Display panel 100 may include a main area MA and a sub-area SBA.

[0039] The main MA area may include a DA display area, Petition 870250086416, dated 09 / 24 / 2025, page 35 / 84 8 / 46 including pixels that display an image, and a non-display area (NDA) arranged around the DA display area. The DA display area may emit light from a plurality of emission areas or a plurality of aperture areas. For example, display panel 100 may include pixel circuits, including switching elements, a pixel definition layer that defines the emission areas or the aperture areas, and self-emitting light elements.

[0040] For example, each of the self-emitting light elements may include, but is not limited to, at least one of the following: an organic light-emitting diode, including an organic light-emitting layer, a quantum dot light-emitting diode, including a quantum dot light-emitting layer, an inorganic light-emitting diode, including an inorganic semiconductor, and a micro light-emitting diode.

[0041] The non-display NDA area may be an area outside the display DA area. The non-display NDA area may be defined as an area bordering the main MA area of ​​display panel 100. The non-display NDA area may include a gate driver (not shown) that provides gate signals to gate lines and load factor lines (not shown) that connect display driver 200 and the display DA area.

[0042] The SBA subarea may extend from one side of the main MA area. The SBA subarea may include a flexible material that can be bent, rolled, etc. For example, when the SBA subarea is bent, it may overlap the main MA area in a thickness direction (e.g., a third direction DR3). The SBA subarea may include the display driver 200 and the pad units connected to the circuit board 300. Optionally, the SBA subarea may be omitted, and the display driver 200 and the pad units may be arranged in the non-display NDA area. Petition 870250086416, dated 09 / 24 / 2025, p. 36 / 84 9 / 46

[0043] The display driver 200 can generate signals and voltages to drive the display panel 100. The display driver 200 can supply data voltages to the DL data lines. The display driver 200 can supply a power supply voltage to a power line and supply a gate control signal to a sweep driver (or gate driver). The display driver 200 can be formed as an integrated circuit and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be arranged in the SBA subarea and can be overlaid by the main area MA in the thickness direction (third direction DR3) by the curvature of the SBA subarea. In another example, the display driver 200 can be mounted on the circuit board 300.

[0044] The circuit board 300 can be attached to the display panel pad units 100 using an anisotropic conductive layer. The conductive wires of the circuit board 300 can be electrically connected to the display panel pad units 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film, such as a chip on film.

[0045] The 400 touch driver can be mounted on the circuit board. 300. The touch driver 400 can be electrically connected to a touch detection unit of the display panel 100. The touch driver 400 can provide a touch trigger signal to a plurality of touch electrodes of the touch detection unit and detect a change in capacitance between the touch electrodes. For example, the touch trigger signal can be a pulse signal with a predetermined frequency. The touch driver 400 can determine if an input has been made and calculate the coordinates of the input based on a change in capacitance between the electrodes. Petition 870250086416, dated 09 / 24 / 2025, page 37 / 84 10 / 46 touch. The 400 touch driver can be formed as an integrated circuit.

[0046] The power supply unit 500 can be arranged on the circuit board 300 to provide power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 can generate a first drive voltage and supply the first drive voltage to the first drive voltage lines VDL, it can generate a startup voltage and supply the startup voltage to the startup voltage lines VIL, and it can generate a common voltage and supply the common voltage to a common electrode, which is common to the light-emitting elements of a plurality of pixels. For example, the first drive voltage can be a high-potential voltage to drive the light-emitting elements, and each of the common voltages and the second drive voltage can be a low-potential voltage to drive the light-emitting elements.

[0047] Figure 2 is a cross-sectional view of the display device 10 according to the embodiment.

[0048] With reference to figure 2, the display panel 100 may include a display unit DU, a touch detection unit TSU and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin-film transistor layer TFTL, a light-emitting element layer EMTL and a encapsulation layer TFEL.

[0049] The SUB substrate can be a base substrate or a base element. The SUB substrate can be a flexible substrate that can be bent, rolled, etc. For example, the SUB substrate can include polymeric resin, such as polyimide (PI), but the present invention is not limited to this. For another example, the SUB substrate can include a glass material or a metallic material. Petition 870250086416, dated 09 / 24 / 2025, page 38 / 84 11 / 46

[0050] The TFTL thin-film transistor layer can be arranged on the SUB substrate. The TFTL thin-film transistor layer can include a plurality of thin-film transistors constituting pixel circuits. The TFTL thin-film transistor layer can further include gate lines, DL data lines, power lines, gate control lines, load factor lines connecting the display driver 200 and the DL data lines, and tap lines connecting the display driver 200 and the pad units. Each of the thin-film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the sweep driver (e.g., the gate driver) is formed on one side of the non-display NDA area of ​​the display panel 100, it can include thin-film transistors.

[0051] The TFTL thin-film transistor layer can be arranged in the DA display area, the NDA non-display area, and the SBA subarea. The pixel thin-film transistors, gate lines, DL data lines, and power lines of the TFTL thin-film transistor layer can be arranged in the DA display area. The gate control lines and load factor lines of the TFTL thin-film transistor layer can be arranged in the NDA non-display area. The tap lines of the TFTL thin-film transistor layer can be arranged in the SBA subarea.

[0052] The EMTL light-emitting element layer can be arranged on the TFTL thin-film transistor layer. The EMTL light-emitting element layer can include a plurality of light-emitting elements, each including a pixel electrode, a light-emitting layer and a common electrode stacked sequentially to emit light, and a pixel definition layer that defines the pixels. The light-emitting elements of the EMTL light-emitting element layer can be arranged in the DA display area. Petition 870250086416, dated 09 / 24 / 2025, page 39 / 84 12 / 46

[0053] The light-emitting layer can be a light-emitting organic layer that includes an organic material. The light-emitting layer can include a hole-carrying layer, a light-emitting organic layer, and an electron-carrying layer. When the pixel electrode receives a predetermined voltage through a thin-film transistor of the TFTL thin-film transistor layer and the common electrode receives a cathodic voltage, holes and electrons can move to the light-emitting organic layer through the hole-carrying layer and the electron-carrying layer, respectively. Then, the holes and electrons can be combined with each other in the light-emitting organic layer to emit light. For example, the pixel electrode can be an anode and the common electrode can be a cathode, but the present invention is not limited to this.

[0054] As another example, each of the light-emitting elements may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0055] The TFEL encapsulation layer can cover the top and side surfaces of the EMTL light-emitting element layer and can protect the EMTL light-emitting element layer. The TFEL encapsulation layer can include at least one inorganic layer and at least one organic layer to encapsulate the EMTL light-emitting element layer.

[0056] The TSU touch detection unit can be arranged in the TFEL encapsulation layer. The TSU touch detection unit can include a plurality of touch electrodes to capacitively detect user touch and touch lines connecting the touch electrodes and the 400 touch driver. For example, the unit of Petition 870250086416, dated 09 / 24 / 2025, page 40 / 84 13 / 46 TSU touch detection can detect user touch in a mutually capacitive or self-capacitive manner.

[0057] In another example, the TSU touch detection unit can be arranged on a separate SUB substrate, arranged within the DU display unit. In this case, the SUB substrate supporting the TSU touch detection unit can be a base element that encapsulates the DU display unit.

[0058] The touch electrodes of the TSU touch detection unit can be arranged in a touch sensor area overlapping the DA display area. The touch lines of the TSU touch detection unit can be arranged in a peripheral touch area overlapping the NDA non-display area.

[0059] The CFL color filter layer can be arranged in the TSU touch detection unit. The CFL color filter layer can include a plurality of color filters corresponding to a plurality of emission areas, respectively. Each of the color filters can selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The CFL color filter layer can absorb some of the light coming from outside the display device 10, thus reducing the reflected light caused by external light. Therefore, the CFL color filter layer can prevent color distortion caused by external light reflection.

[0060] Because the CFL color filter layer is arranged directly on the TSU touch detection unit, the display device 10 may not need a separate substrate for the CFL color filter layer. Therefore, the thickness of the display device 10 can be relatively reduced.

[0061] The SBA subarea of ​​display panel 100 may extend from one side of the main MA area. The SBA subarea may include a flexible material that can be bent, rolled, etc. For example, Petition 870250086416, dated 09 / 24 / 2025, page 41 / 84 14 / 46 When the SBA subarea is folded, it can be overlapped by the main MA area in the thickness direction (third direction DR3). The SBA subarea can include the display driver 200 and the pad units electrically connected to the circuit board 300.

[0062] Figure 3 is a plan view of the display unit DU of display device 10, according to the embodiment. Figure 4 is a block diagram of display panel 100 and display driver 200, according to an embodiment.

[0063] With reference to figures 3 and 4, display panel 100 may include the DA display area and the NDA non-display area.

[0064] The DA display area may include a plurality of PX pixels, a plurality of first VDL drive voltage lines connected to the PX pixels, a plurality of second drive voltage lines, a plurality of GL gate lines, a plurality of EML emission control lines, and a plurality of DL data lines.

[0065] Each of the PX pixels can be connected to a GL gate line, a DL data line, an EML emission control line, a first drive voltage line VDL, and a second drive voltage line. Each of the PX pixels can include at least one transistor, one light-emitting element, and one capacitor.

[0066] The GL gate lines can extend in the first direction DR1 and can be spaced apart in the second direction DR2, crossing the first direction DR1. The GL gate lines can be arranged along the second direction DR2. The GL gate lines can provide gate signals sequentially to the PX pixels.

[0067] EML emission control lines can extend in the first direction DR1 and can be spaced apart in the second direction DR2. EML emission control lines can be arranged along the second direction DR2. Emission control lines Petition 870250086416, dated 09 / 24 / 2025, page 42 / 84 15 / 46 EMLs can sequentially provide emission control signals to PX pixels.

[0068] DL data lines can extend in the second direction DR2 and can be spaced apart in the first direction DR1. DL data lines can be arranged along the first direction DR1. DL data lines can provide data voltages to PX pixels. A data voltage can determine the luminance of each of the PX pixels.

[0069] The first VDL drive voltage lines can extend in the second direction DR2 and can be spaced apart in the first direction DR1. The first VDL drive voltage lines can be arranged along the first direction DR1. The first VDL drive voltage lines can provide the first drive voltages to the PX pixels. The first drive voltages can be high-potential voltages to drive the light-emitting elements of the PX pixels.

[0070] The NDA non-display area may surround the DA display area. The NDA non-display area may include a 610 scan driver, a 620 emission control driver, FL load factor lines, a first GSL1 gate control line, and a second GSL2 gate control line.

[0071] Load factor lines FL can extend from display driver 200 to display area DA. Load factor lines FL can supply data voltages received from display driver 200 to data lines DL.

[0072] The first GSL1 port control line can extend from display driver 200 to scan driver 610. The first GSL1 port control line can provide a GCS port control signal received from display driver 200 to scan driver 610. Petition 870250086416, dated 09 / 24 / 2025, page 43 / 84 16 / 46

[0073] The second GSL2 port control line can extend from display driver 200 to emission control driver 620. The second GSL2 port control line can provide an ECS emission control signal received from display driver 200 to emission control driver 620.

[0074] The SBA subarea may extend from one side of the non-display NDA area. The SBA subarea may include the display driver 200 and the DP pad units. The DP pad units may be arranged closer to an edge of the SBA subarea than the display driver 200. The DP pad units may be electrically connected to the circuit board 300 via an anisotropic conductive layer.

[0075] The display driver 200 may include a timing controller 210 and a data driver 220.

[0076] Timing controller 210 can receive digital video data (DATA) and timing signals from circuit board 300. Timing controller 210 can control the timing operation of data driver 220 by generating a DCS data control signal based on the timing signals, it can control the timing operation of scan driver 610 by generating the GCS gate control signal, and it can control the timing operation of emission control driver 620 by generating the ECS emission control signal. Timing controller 210 can provide the GCS gate control signal to scan driver 610 via the first gate control line GSL1. Timing controller 210 can provide the ECS emission control signal to emission control driver 620 via the second gate control line GSL2.The timing controller 210 can provide the digital video data (DATA) and the data control signal (DCS) to the data driver 220.

[0077] The 220 data driver can convert video data Petition 870250086416, dated 09 / 24 / 2025, p. 44 / 84 17 / 46 digital DATA in analog data voltages and provide the analog data voltages to the DL data lines via the FL load factor lines. The gate signals of the 610 scan driver can select the PX pixels to which the data voltages should be provided, and the selected PX pixels can receive the data voltages via the DL data lines.

[0078] The power supply unit 500 can be arranged on the circuit board 300 to provide power supply voltages to the display driver 200 and the display panel 100. The power supply unit 500 can generate initial drive voltages and supply the initial drive voltages to the initial drive voltage lines VDL, it can generate startup voltages and supply the startup voltages to the startup voltage lines VIL, and it can generate a common voltage and supply the common voltage to the common electrode, which is common to the light-emitting elements of the PX pixels.

[0079] The scanning driver 610 can be disposed outside one side of the DA display area or on one side of the NDA non-display area, and the emission control driver 620 can be disposed outside the other side of the DA display area or on the other side of the NDA non-display area. However, the present invention is not limited to this. For another example, the scanning driver 610 and the emission control driver 620 can be disposed on either side of the NDA non-display area.

[0080] The 610 sweep driver may include a plurality of thin-film transistors that generate gate signals based on the GCS gate control signal. The 620 emission control driver may include a plurality of thin-film transistors that generate emission control signals based on the ECS emission control signal. For example, the thin-film transistors of the 610 sweep driver and the thin-film transistors of the 620 emission control driver may be formed in the same layer as the thin-film transistors. Petition 870250086416, dated 09 / 24 / 2025, page 45 / 84 18 / 46 fine pixel PX. The 610 scan driver can provide gate signals to the GL gate lines sequentially or simultaneously, and the 620 emission control driver can provide emission control signals to the EML emission control lines sequentially or simultaneously.

[0081] Figure 5 is an example diagram of a 610 scan driver according to an embodiment of the present invention.

[0082] With reference to figure 5, the 610 scan driver, according to the embodiment, includes a plurality of stages connected in a dependent manner to each other, that is, the nth stages STn. Here, n is a positive integer.

[0083] In figure 5, for ease of description, only the (n-2)th to (n+2)th stages STn-2 to STn+2 are illustrated based on an nth stage STn.

[0084] In the following description, a “previous stage” refers to a stage located ahead of the nth stage STn. A “next stage” refers to a stage located behind the nth stage STn. For example, a previous stage of the nth stage STn indicates the (n1)-th stage STn-1, and a next stage of the nth stage STn indicates the (n+1)-th stage STn+1.

[0085] The sweep clock lines and detection control lines may be arranged on one side of the (n-2)th to (n+2)th stages STn-2 to STn+2. A plurality of sweep clock signals CLK1 to CLK3, whose phases are sequentially delayed or alternated, are transmitted to the sweep clock lines, respectively, and a start signal ST, a line selection signal ES and a reset signal are transmitted to the detection control lines, respectively.

[0086] Clock signals for sweep CLK1 to CLK3, line selection signal ES, start signal ST and reset signal Petition 870250086416, dated 09 / 24 / 2025, p. 46 / 84 19 / 46 may be GCS gate control signals generated by display driver 200 and transmitted through the first GSL1 gate control lines. In Figure 5, three scan clock lines, two sensing control lines, and two power lines are illustrated as the first GSL1 gate control lines. However, the number of scan clock lines, sensing control lines, and power lines is not limited to these.

[0087] The 610 scan driver includes the (n-2)th to (n+2)th stages STn-2 to STn+2 connected to the first GSL1 port control lines, respectively.

[0088] Among all nth STn stages, the (n-2)th STn-2 stage emits an (n-2)th SCn-2 sweep signal to an (n2)th SCLn-2 sweep signal line, and the (n-1)th STn-1 stage emits an (n-1)th SCn-1 sweep signal to an (n-1)th SCLn-1 sweep signal line. Consequently, the nth STn stage can emit an nth SCn sweep signal to an nth SCLn sweep signal line. Next, the (n+1)th stage STn+1 emits an (n+1)th sweep signal SCn+1 to an (n+1)th sweep signal line SCLn+1, and the (n+2)th stage STn+2 emits an (n+2)th sweep signal SCn+2 to an (n+2)th sweep signal line SCLn+2.

[0089] Each of the (n-2)-th to (n+2)-th stages STn-2 to STn+2 includes a previous carrier terminal CPI, a next carrier terminal CNI, a first scan clock terminal SCI1, a second scan clock terminal SCI2, a third scan clock terminal SCI3, a first power supply terminal SSI1, a second power supply terminal SSI2, a sensing signal terminal RSI, and a scan output terminal SCO.

[0090] When the (n-2)th stage STn-2 is a first stage, the ST start signal can be entered into the previous carrier terminal CPI. Petition 870250086416, dated 09 / 24 / 2025, p. 47 / 84 20 / 46 of the (n-2)th stage STn-2 via a start signal line. As illustrated in Figure 5, the CPI upstream carrier terminal of each of the stages connected dependently after the first stage can be connected to the SCO scan output terminal of an immediately preceding stage. For example, the CPI upstream carrier terminal of the nth stage STn can be connected to the SCO scan output terminal of the (n-1)th stage STn-1 and can receive the SCn-1 scan signal from the (n-1)th stage STn-1 as an upstream carrier signal.

[0091] The next CNI carrier terminal of each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can be connected to the SCO scan output terminal of any of the following stages. For example, the next CNI carrier terminal of the nth stage STn can be connected to the SCO scan output terminal of the (n+1)th stage STn+1 and can receive the SCn+1 scan signal from the (n+1)th stage STn+1 as a next carrier signal.

[0092] The SCO scan output terminals of the (n-2)th to (n+2)th stages STn-2 to STn+2 are sequentially connected to the corresponding GL gate lines, i.e., to the SCL scan signal lines, respectively. Consequently, the SCL scan signal lines can be connected one by one to the SCO scan output terminals of all stages STn-2 to STn+2. For example, the (n-1)th SCL scan signal line n-1 is connected to the SCO scan output terminal of the (n-1)th stage STn-1, and the nth SCL scan signal line n is connected to the SCO scan output terminal of the nth stage STn. Furthermore, the (n+1)th SCL scan signal line n+1 can be connected to the SCO scan output terminal of the (n+1)th stage STn+1.

[0093] The RSI detection signal terminal of each of the (n-2)th to (n+2)th stages STn-2 to STn+2 receives the selection signal. Petition 870250086416, dated 09 / 24 / 2025, p. 48 / 84 21 / 46 line ES via a detection control line to which the ES line selection signal is transmitted. Alternatively, each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can receive a previous carrier signal via the RSI detection signal terminal.

[0094] Each of the (n-2)th to (n+2)th stages STn-2 to STn + 2 receives three scan clock signals, namely, the first to third scan clock signals CLK1 to CLK3, whose phases are sequentially alternated or delayed through the first scan clock terminal SCI1, the second scan clock terminal SCI2, and the third scan clock terminal SCI3.

[0095] For example, each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can receive the first CLK1 sweep clock signal through the first SCI1 sweep clock terminal and receive the second CLK2 sweep clock signal, whose phase is delayed relative to the first CLK1 sweep clock signal through the second SCI2 sweep clock terminal. Furthermore, each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can receive the third CLK3 sweep clock signal, whose phase is delayed relative to the second CLK2 sweep clock signal through the third SCI3 sweep clock terminal.

[0096] The (n-2)th to (n+2)th stages STn-2 to STn+2 sequentially transmit scan signals SCn-2 to SCn+2 to the scan signal lines SCLn-2 to SCLn+2 connected one by one to them via their respective scan output terminals SCO, respectively. For example, during at least one frame period, the (n-2)th stage STn-2 transmits the (n-2)th scan signal SCn-2 to the (n-2)th scan signal line SCLn-2 connected to the scan output terminal SCO. Then, the (n-1)th stage STn-1 transmits the (n-1)th scan signal SCn-1 to the (n-1)th scan signal line SCLn-1 connected to the terminal Petition 870250086416, dated 09 / 24 / 2025, p. 49 / 84 22 / 46 SCO scan output. Consequently, the (nth) stage STn outputs the (nth) scan signal SCn to the (nth) scan signal line SCLn connected to the SCO scan output terminal.

[0097] Furthermore, the (n+1)-nth stage STn+1 can output the (n+1)-nth scan signal SCn+1 to the (n+1)-nth scan signal line SCLn+1 connected to the scan output terminal SCO, and the (n+2)-nth stage STn+2 can output the (n+2)-nth scan signal SCn+2 to the (n+2)-nth scan signal line SCLn+2 connected to the scan output terminal SCO.

[0098] The emission control driver 620, which sequentially generates and emits emission signals in response to the ECS emission control signal received from the display driver 200, can also be structured to include the (n-2)th to (n+2)th stages STn-2 to STn+2, i.e., the nth stages STn. Therefore, a detailed description of the structure of the emission control driver 620 will be replaced by a description of the scanning driver 610.

[0099] Figure 6 is a detailed circuit diagram of a first embodiment of the nth STn stage of the 610 sweep driver illustrated in Figure 5. In particular, Figure 6 illustrates the nth STn stage between the (n-2)th to (n+2)th STn-2 to STn+2 stages as an example.

[00100] The nth stage STn includes an output node controller SCC and an output controller OUC. Additionally, the nth stage STn receives a gate-on voltage VGH through the first power supply terminal SSI1 and a gate-off voltage VGL through the second power supply terminal SSI2. Meanwhile, all stages, i.e., the (n-2)th to (n+2)th stages STn-2 to STn+2, receive a simultaneous drive control signal GCK during a simultaneous drive period in which they Petition 870250086416, dated 09 / 24 / 2025, pp. 50 / 84 23 / 46 are triggered simultaneously. However, the simultaneous drive control signal GCK is supplied at the same voltage level or at a similar level to the gate-off voltage VGL during an active period (e.g., an image display period) in which the (n-2)th to (n+2)th stages STn-2 to STn+2 are triggered sequentially. On the other hand, the gate-off voltage VGL can be generated and supplied at a lower level than the voltage level of the simultaneous drive control signal GCK generated during the active period.

[00101] The nth STn stage illustrated in Figure 6 can operate in response to the ST start signal received through the previous carrier terminal CPI. However, when dependently connected to the previous (n1)th STn stage n-1, the nth STn stage can operate in response to the (n-1)th SCn-1 sweep signal from the (n-1)th STn-1 stage received as the carrier signal. An example in which the nth STn stage is any of the nth STn stages that are dependently connected to the previous (n-1)th STn-1 stage will be described below.

[00102] The nth stage STn output node controller SCC enables the output controller OUC, providing a voltage of the same level as the gate-on voltage VGH to a pull-up node Q during the active period of each frame period. While the pull-up node Q is loaded and held at the gate-on voltage VGH, the gate-off voltage VGL is applied to a pull-down node QB.

[00103] Specifically, the output node controller SCC provides the gate-connected voltage VGH to the pull-up node Q in response to the line selection signal ES input during the active period or to a carrier signal from a previous stage, i.e., the (n-1)-th sweep signal SCn-1 from the (n-1)-th stage STn-1. Here, the line selection signal ES or the previous carrier signal can be at the gate voltage level. Petition 870250086416, dated 09 / 24 / 2025, p. 51 / 84 24 / 46 connected VGH. When the connected gate voltage VGH is applied to the pull-up node Q of the output node controller SCC, the pull-up node Q of the output node control unit SCC is enabled according to the level of the connected gate voltage VGH. The output node controller SCC controls the gate-off voltage VGL to be supplied to the pull-down node QB during a period in which the connected gate voltage VGH is supplied to the pull-up node Q.

[00104] When the pull-up node Q of the SCC output node controller is enabled, the OUC output controller sends the nth SCn scan signal to the nth SCLn scan signal line connected to the SCO scan output terminal in response to any one (e.g., CLK3) of the first to third CLK1 to CLK3 scan clock signals.

[00105] After the nth SCn scan signal is emitted, the output node controller SCC controls the gate-off voltage VGL to be supplied to the pull-up node Q in response to any one (e.g., CLK1) of the first to third CLK1 to CLK3 scan clock signals or to a subsequent carrier signal (e.g., the (n+1)-th SCn+1 scan signal of the (n+1)-th STn+1 stage). Consequently, the pull-up node Q is disabled by the gate-off voltage VGL.

[00106] The output node controller SCC provides the gate-connected voltage VGH to the pull-down node QB in response to the next carrier signal or to any one (e.g., CLK1) of the first to third CLK1 to CLK3 sweep clock signals for a period during which the pull-up node Q is held off.

[00107] When the pull-down node QB of the output node controller SCC is enabled by the gate-on voltage VGH, the output controller OUC provides the simultaneous drive control signal GCK, which is received at the gate-off voltage level VGL, to the nth Petition 870250086416, dated 09 / 24 / 2025, p. 52 / 84 25 / 46 sweep signal line SCLn. That is, when the pull-down node QB is enabled by the gate-on voltage VGH, the output controller OUC electrically connects the nth sweep signal line SCLn to an input terminal of the simultaneous drive control signal GCK.

[00108] The (n-2)th to (n+2)th stages STn-2 to STn+2 sequentially emit the nth SCn sweep signals to their respective SCLn sweep signal lines and then sequentially and repeatedly perform a hold operation on their respective SCLn sweep signal lines at the gate-off voltage VGL.

[00109] The nth stage STn SCC output node controller may include transistors T1 to T8, from the first to the eighth, and capacitors C1 and C2, from the first to the eighth. Either of the electrodes C1 and C2 of each of the transistors T1 to T8, from the first to the eighth, to be described later, may be a source electrode, and the other may be a drain electrode. Each of the transistors T1 to T8, from the first to the eighth, may be configured as an NMOS or PMOS transistor.

[00110] Specifically, one gate electrode of the first transistor T1 can be connected to the pull-up node Q, the first electrode of the first transistor T1 can be connected to the third sweep clock terminal SCI3, and the second electrode of the first transistor T1 can be connected to the front carrier terminal CPI and the first electrode of the second transistor T2. The first transistor T1 can be turned on when the pull-up node Q is enabled by the gate activation voltage VGH and can provide the third sweep clock signal CLK3 to the first capacitor C1 and the second transistor T2 formed in parallel.

[00111] A gate electrode of the second transistor T2 is connected to the pull-down node QB, and the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, to the pull-up node. Petition 870250086416, dated 09 / 24 / 2025, pp. 53 / 84 26 / 46 Q or to the previous carrier terminal CPI. Additionally, the second electrode of the second transistor T2 is connected to the second power supply terminal SSI2, to which the gate-off voltage VGL is applied. The second transistor T2 can be turned on when the pull-down node QB is enabled by the gate-on voltage VGH and can supply the gate-off voltage VGL to the first transistor T1 or to the pull-up node Q.

[00112] One gate electrode of the third transistor T3 is connected to the pull-up node Q, and the first electrode of the third transistor T3 is connected to the first sweep clock terminal SCI1. Additionally, the second electrode of the third transistor T3 can be connected to the pull-down node QB. The third transistor T3 can be turned on when the pull-up node Q is enabled by the gate-on voltage VGH and can provide the first sweep clock signal CLK1 to the pull-down node QB.

[00113] One gate electrode of the fourth transistor T4 is connected to the sensing signal terminal RSI or the leading carrier terminal CPI, and the first electrode of the fourth transistor T4 is connected to the first power supply terminal SSI1, to which the gate-on voltage VGH is applied. Additionally, the second electrode of the fourth transistor T4 is connected to the pull-up node Q. The fourth transistor T4 is turned on in response to the line selection signal ES from the sensing signal terminal RSI or the leading carrier signal and supplies the gate-on voltage VGH to the pull-up node Q. Consequently, the fourth transistor T4 can enable the pull-up node Q at the gate-on voltage VGH level in response to the line selection signal ES from the sensing signal terminal RSI or the leading carrier signal.

[00114] A gate electrode of the fifth transistor T5 is connected to the input terminal where the simultaneous drive control signal GCK is fed by the display driver 200, and the first electrode of the fifth transistor T5 is connected to the pull-up node Q. Additionally, the second electrode of the fifth transistor T5 can be connected to either (by Petition 870250086416, dated 09 / 24 / 2025, pp. 54 / 84 27 / 46 example, the third clock scan terminal SCI3) from the first to the third clock scan terminals SCI1 to SCI3.

[00115] The fifth transistor T5 can provide any sweep clock signal (e.g., the third sweep clock signal CLK3) to the pull-up node Q in response to the input of the simultaneous drive control signal GCK at the gate-on voltage level VGH during the simultaneous drive period in which the (n-2)th to (n+2)th stages STn-2 to STn+2 are driven simultaneously.

[00116] Conversely, the fifth transistor T5 receives the simultaneous drive control signal GCK, provided at the same voltage level or at a similar level to the gate-off voltage VGL, through the gate electrode during the active period (e.g., the image display period) in which the (n-2)th to (n+2)th stages STn-2 to STn+2 are driven sequentially. Consequently, the fifth transistor T5 is held off during the active period.Therefore, the fifth transistor T5 receives any sweep clock signal (e.g., the third sweep clock signal CLK3) through the second electrode during a period in which the pull-up node Q is initialized by any sweep clock signal (e.g., the third sweep clock signal CLK3) after being enabled by the gate-on voltage VGH. Consequently, a voltage difference between the first and second electrodes of the fifth transistor T5 during the period in which the pull-up node Q is initialized can be maintained as a difference between the voltage of any sweep clock signal (e.g., the third sweep clock signal CLK3) and the voltage of the initialized pull-up node Q.

[00117] One gate electrode of the sixth transistor T6 is connected to the third sweep clock terminal SCI3, and the first electrode of the sixth transistor T6 is connected to the pull-up node Q. Additionally, the second electrode of the sixth transistor T6 is connected to the second electrode of Petition 870250086416, dated 09 / 24 / 2025, page 55 / 84 28 / 46 first transistor T1 or to the first electrode of the seventh transistor T7. Consequently, the sixth transistor T6 electrically connects the pull-up node Q to the second electrode of the first transistor T1 or to the first electrode of the seventh transistor T7 in response to the third sweep clock signal CLK3. The sixth transistor T6 can serve as a diode between the pull-up node Q and the first capacitor C1.

[00118] A gate electrode of the seventh transistor T7 is connected to the pull-down node QB, and the first electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6. Furthermore, the second electrode of the seventh transistor T7 is connected to the second electrode of the first transistor T1 and to the first capacitor C1. Consequently, the seventh transistor T7 is turned on when the pull-down node QB is enabled and electrically connects the second electrode of the sixth transistor T6 to the first capacitor C1 and to the second electrode of the first transistor T1. The seventh transistor T1 acts as a diode to keep the sixth transistor T6 and the first transistor T1 off during the enabling period of the pull-down node QB.

[00119] A gate electrode of the eighth transistor T8 can be connected to the first or second sweep clock terminal SCI1 or SCI2, and the first electrode of the eighth transistor T8 can be connected to the first power supply terminal SS11, to which the gate-on voltage VGH is applied, or to the second electrode of the third transistor T3. Additionally, the second electrode of the eighth transistor T8 is connected to the pull-down node QB. For example, the gate electrode of the eighth transistor T8 can be connected to the first sweep clock terminal SCI1, and the first electrode of the eighth transistor T8 can be connected to the first power supply terminal SS11. In this case, the eighth transistor T8 can be turned on in response to the first sweep clock signal CLK1 and can enable the pull-down node QB at the gate-on voltage level VGH. Petition 870250086416, dated 09 / 24 / 2025, pp. 56 / 84 29 / 46

[00120] The OUC output controller includes a DT pull-up transistor and a VT pull-down transistor.

[00121] The pull-up transistor DT has a first electrode connected to the third sweep clock terminal SCI3, a gate electrode connected to the pull-up node Q, and a second electrode connected to the sweep output terminal SCO. The pull-up transistor DT is connected by the gate-connected voltage VGH of the pull-up node Q and sends any sweep clock signal to the third sweep clock terminal SCI3, for example, the third sweep clock signal CLK3 to the sweep output terminal SCO. Consequently, the nth sweep signal SCn at the level of the gate-connected voltage VGH can be supplied to the nth sweep signal line SCLn.

[00122] The pull-down transistor VT may have a gate electrode connected to the pull-down node QB, a first electrode connected to the sweep output terminal SCO, and a second electrode connected to the input terminal where the simultaneous drive control signal GCK is applied or to the second power supply terminal SSI2. The pull-down transistor VT is driven by the drive voltage VGH received through the pull-down node QB and transmits the simultaneous drive control signal GCK at the drive voltage level VGL to the sweep output terminal SCO. Alternatively, the pull-down transistor VT may be driven by the drive voltage VGH received through the pull-down node QB and may apply the drive voltage VGL, which is applied to the second power supply terminal SSI2, to the sweep output terminal SCO.Therefore, the nth sweep signal line SCLn connected to the sweep output terminal SCO can be maintained at the drive voltage level VGL during the on-time of the pull-down transistor VT.

[00123] Figure 7 is a waveform diagram illustrating changes in voltage levels of the detection control signals, signals Petition 870250086416, dated 09 / 24 / 2025, p. 57 / 84 30 / 46 clock sweep and Q-node pull-up during the active period of the nth frame period.

[00124] With reference to Figure 7, the line selection signal ES, the start signal ST, and the sweep clock signals CLK1 to CLK3, from the first to the third, are signals generated at the level of the connected gate voltage VGH during a horizontal period of 1H. The line selection signal ES, inserted at each RSI sensing signal terminal, can be generated every horizontal period of 1H, so that the connected gate voltage VGH can be supplied to the pull-up node Q of each of the stages STn-2 to STn+2 during the active period. Even if the line selection signal ES from the RSI sensing signal terminal is not generated and supplied, it can be replaced by the start signal ST or by a carrier signal from a previous stage (i.e., a previous carrier signal).

[00125] The first to third sweep clock signals CLK1 to CLK3 are clock signals whose phases are sequentially delayed by at least one horizontal period of 1H and repeatedly alternated.Each of the first through third sweep clock signals, CLK1 to CLK3, can be generated at the gate-on voltage level VGH for at least one horizontal period of 1H and can be generated at the gate-off voltage level VGL for at least one horizontal period of 1H. Here, the generation period, pulse width, and amplitude of each of the first through third sweep clock signals CLK1 to CLK3 are not limited to those in Figure 7 and can be altered in various ways.

[00126] The gate-on voltage VGH can be the high-output gate logic voltage (or the low-output gate logic voltage) that can connect the thin-film transistors included in each of the (n2) to (n+2)-th stages STn-2 to STn+2 of the 610 sweep driver and the PX subpixel thin-film transistors. The gate-off voltage VGH can be the low-output gate logic voltage (or the Petition 870250086416, dated 09 / 24 / 2025, pp. 58 / 84 31 / 46 high output gate logic voltage) which can turn off the thin-film transistors of the (n-2) to (n+2)-th stages STn-2 to STn+2 of the 610 sweep driver and the thin-film transistors of the PX subpixels.

[00127] The operation of the nth stage STn during the active period of any frame will be briefly described below with reference to figures 6 and 7.

[00128] First, the fourth transistor T4 is connected in response to the line selection signal ES from the detection signal terminal RSI or the start signal ST and provides the gate-connected voltage VGH to the pull-up node Q. Consequently, the pull-up node Q is enabled.

[00129] Next, the first transistor T1 is turned on when the pull-up node Q is enabled by the gate-on voltage VGH and charges the first capacitor C1. Furthermore, the pull-up transistor DT is connected by the gate-on voltage VGH of the pull-up node Q and outputs the third sweep clock signal CLK3, which is fed into the third sweep clock terminal SCI3, to the sweep output terminal SCO. Consequently, the pull-up node Q is initialized, and the nth sweep signal SCn from the gate-on voltage VGH is supplied to the nth sweep signal line SCLn.

[00130] Figure 8 is a circuit diagram illustrating a change in the voltage difference between the first and second electrodes of the fifth transistor T5 illustrated in Figure 6.

[00131] With reference to figures 6 to 8, the fifth transistor T5 receives any sweep clock signal (e.g., the third sweep clock signal CLK3) through the second electrode during a period in which the pull-up node Q is initialized by any sweep clock signal (e.g., the third sweep clock signal CLK3) after being enabled by the gate-on voltage VGH.

[00132] The Q pull-up node can be initialized up to approximately 21 V, Petition 870250086416, dated 09 / 24 / 2025, p. 59 / 84 32 / 46 depending on the gate-on voltage level VGH and the voltage level of the third sweep clock signal CLK3, and the initialization voltage is applied to the first electrode of the fifth transistor T5. During the initialization period of the pull-up node Q, the third sweep clock signal CLK3 of approximately 12 V, which is the gate-on voltage level VGH, can be supplied to the first electrode of the fifth transistor T5.

[00133] Thus, during the period in which the pull-up node Q is initialized, the voltage difference between the first and second electrodes of the fifth transistor T5 can be maintained at the difference between the voltage of any sweep clock signal (e.g., the third sweep clock signal CLK3) and the voltage of the initialized pull-up node Q, for example, can be maintained at a voltage difference of about 9 V.

[00134] Next, the eighth transistor T8 is turned on in response to the first or second CLK1 or CLK2 sweep clock signals and a subsequent carrier signal, enabling the pull-down node QB at the gate-on voltage level VGH. The pull-up node Q is disabled at the gate-off voltage level VGL. The voltages of the first and second electrodes of the fifth transistor T5 can, for example, equalize to 0 V.

[00135] Meanwhile, the pull-down transistor VT is turned on by the gate-on voltage VGH of the pull-down node QB and applies the simultaneous drive control signal GCK at the same gate-off voltage level VGL to the sweep output terminal SCO. Consequently, the nth sweep signal line SCLn connected to the sweep output terminal SCO can be maintained at the gate-off voltage VGL during the on period of the pull-down transistor VT.

[00136] Figure 9 is a detailed circuit diagram of a second embodiment of the n STn stage of the 610 sweep driver illustrated in Figure 5.

[00137] With reference to figure 9, an output node controller Petition 870250086416, dated 09 / 24 / 2025, pp. 60 / 84 33 / 46 The nth stage STn's SCC may also include a ninth transistor T9 that disables a pull-up node Q using a previous carrier signal at the level of a gate-off voltage VGL in response to a subsequent carrier signal from a next STn+1 stage.

[00138] A gate electrode of the ninth transistor T9 is connected to a nearby carrier terminal CNI, and a first electrode of the ninth transistor T9 is connected to a previous carrier terminal CPI or to a second power supply terminal SSI2. Additionally, a second electrode of the ninth transistor T9 is connected to the pull-up node Q. Consequently, the ninth transistor T9 can supply a voltage at the same level as the gate-off voltage VGL to the pull-up node Q in response to the nearby carrier signal from the next stage STn+1.

[00139] As described above, the SCC output node controllers of all stages, i.e., the (n-2)th to (n+2)th stages STn-2 to STn+2, may include each of the first to eighth transistors T1 to T8 or the first to ninth transistors T1 to T9. At least one of the first to ninth transistors T1 to T9 of each STn stage, for example, the first transistor T1, the third transistor T3 and the fourth transistor T4, as well as the fifth transistor T5, enable the pull-up node Q using the gate-on voltage VGH and, during a period in which the enabled pull-up node Q is initialized to a voltage greater than the gate-on voltage VGH by a CLK3 sweep clock signal, receives the initialized voltage through any electrode.Consequently, the first, third, fourth, and fifth transistors T1, T3, T4, and T5 can be subjected to high potential and high voltage levels, and the current and voltage characteristics, as well as the limiting voltage characteristics of their semiconductor layers (or active layers), can be altered by the influence of these high potential and high voltage levels. If the current and voltage characteristics of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 are altered, then... Petition 870250086416, dated 09 / 24 / 2025, pp. 61 / 84 34 / 46 The voltage and current output characteristics of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may deteriorate, thus reducing the output of each of the STn-2 to STn+2 stages or decreasing reliability.

[00140] In this sense, the semiconductor layer (or active layer) of at least one of the first to ninth transistors T1 to T9 of each STn stage may be made of a different oxide semiconductor material than the semiconductor layer (or active layer) of at least one other transistor T1 to T9.

[00141] For example, the semiconductor layer (or active layer) of at least one transistor T1, T3, T4, or T5 that is directly connected to the pull-up node Q and subjected to high potential and high voltage between the first to ninth transistors T1 to T9 of each STn stage may include a different oxide semiconductor material than the semiconductor layer (or active layer) of at least one other transistor T2, T6, T7, or T8 that is not directly connected to the pull-up node Q.

[00142] In particular, the semiconductor layers (or active layers) of the first, third, fourth, and fifth transistors T1, T3, T4, and T5, connected directly to the pull-up node Q between the first and ninth transistors T1 to T9 of each STn stage, can be made of a different oxide semiconductor material that increases a current range. Consequently, the current and current transfer rate of the first, third, fourth, and fifth transistors T1, T3, T4, and T5 can be increased.

[00143] Figure 10 is a cross-sectional view illustrating the cross-sectional structure of the fifth and seventh transistors T5 and T7 of the 610 sweep driver illustrated in Figures 6 and 9.

[00144] With reference to figures 9 and 10, at least one transistor indirectly connected to the pull-up node Q, for example, transistors T2, T6, T7 and T8 among a plurality of transistors T1 to T9 included Petition 870250086416, dated 09 / 24 / 2025, pp. 62-84 35 / 46 in each STn stage includes an active first layer ACT1 containing an oxide semiconductor.

[00145] On the other hand, at least one transistor connected directly to the pull-up node Q, for example, the first, third, fourth and fifth transistors T1, T3, T4 and T5 among transistors T1 to T9 included in each STn stage include a second active layer ACT2 including an oxide semiconductor different from the oxide semiconductor of the first active layer ACT1.

[00146] Specifically, a BR barrier layer is formed on the SUB substrate in which each STn stage is formed, and the TFTL thin-film transistor layer including a plurality of T1 to T9 transistors from each STn stage is formed on the BR barrier layer.

[00147] The SUB substrate can be a rigid or flexible substrate, which can be bent or rolled. The SUB substrate can be made of an insulating material, such as glass, quartz, or polymeric resin. The polymeric material can be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyalylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the SUB substrate can include a metallic material.

[00148] The BR barrier layer can be disposed on the SUB substrate. The BR barrier layer can be a layer to protect the TFTL thin-film transistor layer from moisture introduced through the SUB substrate, which is vulnerable to moisture penetration. The BR barrier layer can be composed of a plurality of inorganic layers stacked alternately. For example, the BR barrier layer can be a multilayer in which one or more inorganic layers are selected from a nitride layer of Petition 870250086416, dated 09 / 24 / 2025, pp. 63 / 84 36 / 46 silicon, a layer of silicon oxynitride, a layer of silicon oxide, a layer of titanium oxide, and a layer of aluminum oxide are stacked alternately.

[00149] The TFTL thin-film transistor layer including a plurality of T1 to T9 transistors from each STn stage is formed in the BR barrier layer.

[00150] The TFTL thin-film transistor layer of at least one transistor indirectly connected to the pull-up node Q, for example, the TFTL thin-film transistor layer of the seventh transistor T7 includes a first gate electrode GEb7, an intermediate insulating layer BF, the first active layer ACT1, the first and second gate insulating layers GTI1 and GTI2, and a second gate electrode GE7.

[00151] The intermediate insulating layer BF is formed to cover the barrier layer BR, as well as the first gate electrode GEb7.

[00152] The first active layer ACT1 is formed to cover the first gate electrode GEb7 with the intermediate insulating layer BF interposed between them, thus forming a seventh channel region CH7. A first electrode E71 and a second electrode E72 can be defined on either side of the first active layer ACT1, respectively.

[00153] The first insulating layer of gate GTI1 is formed to overlap the first gate electrode GEb7 with the first active layer ACT1 interposed between them, and the second insulating layer of gate GTI2 is formed to overlap the first gate electrode GEb7 with the first insulating layer of gate GTI1 interposed between them.

[00154] The second GE7 gate electrode is formed to overlap the first GEb7 gate electrode with the first and second GTI1 and GTI2 gate insulating layers interposed between them.

[00155] The intermediate insulating layer BF may include a layer Petition 870250086416, dated 09 / 24 / 2025, pages 64 / 84 37 / 46 inorganic, for example, a layer of silicon nitride, a layer of silicon oxynitride, a layer of silicon oxide, a layer of titanium oxide, or a layer of aluminum oxide. The intermediate insulating layer BF may include a plurality of inorganic layers.

[00156] The first active ACT1 layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. When the first active ACT1 layer includes an oxide semiconductor material, it may include indium gallium zinc oxide (IGZO).

[00157] When the first active ACT1 layer includes polycrystalline silicon or an oxide semiconductor material, a source region and a drain region in the first active ACT1 layer can be ion-doped conductive regions to have conductivity.

[00158] The first insulating layer of GTI1 gate may include at least one of the following: tetraethyl orthosilicate (TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first insulating layer of GTI1 gate may have a double-layer structure, in which a silicon nitride layer with a thickness of 40 nm and a tetraethyl orthosilicate layer with a thickness of 80 nm are stacked sequentially. The second insulating layer of GTI2 gate may include the same material and structure as the first insulating layer of GTI1 gate described above.

[00159] Meanwhile, at least one transistor connected directly to the pull-up node Q, for example, the first, third, fourth and fifth transistors T1, T3, T4 and T5 among transistors T1 to T9 included in each STn stage include the second active layer ACT2 including an oxide semiconductor different from the oxide semiconductor of the first active layer ACT1.

[00160] For example, the TFTL thin-film transistor layer Petition 870250086416, dated 09 / 24 / 2025, pages 65 / 84 38 / 46 of the fifth transistor T5 connected directly to the pull-up node Q includes a first gate electrode GEb5, an intermediate insulating layer BF, a second active layer ACT2, the first and second gate insulating layers GTI1 and GTI2, and a second gate electrode GE5.

[00161] The intermediate insulating layer BF is formed to cover the barrier layer BR, as well as the first gate electrode GEb5.

[00162] The second active layer ACT2 is formed to cover the first gate electrode GEb5 with the intermediate insulating layer BF interposed between them, thus forming a fifth channel region CH5. A first electrode E51 and a second electrode E52 can be defined on either side of the second active layer ACT2, respectively.

[00163] The first insulating layer of the GTI1 gate is formed to overlap the first GEb5 gate electrode with the second active layer ACT2 interposed between them, and the second insulating layer of the GTI2 gate is formed to overlap the first GEb5 gate electrode with the first insulating layer of the GTI1 gate interposed between them.

[00164] The second GE7 gate electrode is formed to overlap the first GEb5 gate electrode with the first and second GTI1 and GTI2 gate insulating layers interposed between them.

[00165] The second active layer ACT2 may include a different oxide semiconductor material than the first active layer ACT1. For example, when the first active layer ACT1 is an oxide semiconductor, including indium gallium zinc oxide (IGZO), the second active layer ACT2 may be an oxide semiconductor, including indium gallium zinc tin oxide (IGZTO). When the second active layer ACT2 includes a different oxide semiconductor material than the first active layer ACT1, a source region and a drain region in the second active layer ACT2 may be conductive regions doped with Petition 870250086416, dated 09 / 24 / 2025, pp. 66 / 84 39 / 46 ions to achieve conductivity.

[00166] Because the first active layer ACT1 and the second active layer ACT2 are semiconductor layers made of different materials, they can be formed on the SUB substrate through different processes.

[00167] The second, sixth, seventh and eighth transistors T2, T6, T7 and T8 that require high switching speed may include the first active layer ACT1 made of indium gallium zinc oxide (IGZO).

[00168] However, the first, third, fourth, and fifth transistors T1, T3, T4, and T5, which require a wide current transfer range and high reliability, may include the second active layer ACT2, made of indium gallium zinc tin oxide (IGZTO). In other words, the first, third, fourth, and fifth transistors T1, T3, T4, and T5, which are directly connected to the pull-up node Q and require high reliability, may include a different oxide semiconductor material than the second, sixth, seventh, and eighth transistors T2, T6, T7, and T8. Consequently, both the high reliability and high speed of each STn stage can be met.

[00169] Among the transistors T1 to T9 included in each STn stage, the third and fourth transistors T3 and T4 connected directly to the pull-up node Q may include the second active layer ACT2 including an oxide semiconductor different from the first active layer ACT1, and the first transistor T1 connected directly to the pull-up node Q may include the first active layer ACT1 including an oxide semiconductor.

[00170] Alternatively, among the transistors T1 to T9 included in each STn stage, the first transistor T1 connected directly to the pull-up node Q may include the second active layer ACT2, including a different oxide semiconductor than the first active layer ACT1 (?), and the third and fourth transistors T3 and T4 connected directly to the pull-up node Q may include the first active layer ACT1, including a Petition 870250086416, dated 09 / 24 / 2025, pp. 67 / 84 40 / 46 oxide semiconductor. The fifth transistor T5 may include the second active layer ACT2, which includes a different oxide semiconductor than the first active layer ACT1.

[00171] The OUC output controller pull-down transistor VT may include the first active layer ACT1, which includes an oxide semiconductor. On the other hand, the OUC output controller pull-up transistor DT, which is directly connected to the pull-up node Q, may include the second active layer ACT2, which includes an oxide semiconductor material different from the first active layer ACT1 of the VT pull-down transistor.

[00172] Figures 11 and 12 are perspective views of an example application of a display device 10 according to an embodiment of the present invention.

[00173] Figures 11 and 12 illustrate an example in which the display device 10 is applied as a foldable display device, which is folded in a first direction (X-axis direction). The display device 10 can maintain both the folded and unfolded states. The display device 10 can be folded inwards, with a front surface arranged internally. When the display device 10 is folded inwards, parts of the front surface of the display device 10 can face each other. Alternatively, the display device 10 can be folded outwards, with the front surface arranged externally. When the display device 10 is folded outwards, parts of the rear surface of the display device 10 can face each other.

[00174] A first non-foldable area NFA1 can be arranged on one side, for example, on the right side of a foldable area FDA. A second non-foldable area NFA2 can be arranged on the other side, for example, on the left side of the foldable area FDA. A touch detection unit TSU, according to an embodiment of the present invention. Petition 870250086416, dated 09 / 24 / 2025, pages 68 / 84 41 / 46 specification, can be formed and arranged in the first non-folding area NFA1 and the second non-folding area NFA2.

[00175] A first folding line FOL1 and a second folding line FOL2 can extend in a second direction (Y-axis direction), and the display device 10 can be folded in the first direction (X-axis direction). Therefore, since the length of the display device 10 in the first direction (X-axis direction) can be halved, the user can easily carry the display device 10.

[00176] The direction in which the first folding line FOL1 and the second folding line FOL2 extend is not limited to the second direction (Y-axis direction). For example, the first folding line FOL1 and the second folding line FOL2 can also extend in the first direction (X-axis direction), and the display device 10 can also be folded in the second direction (Y-axis direction). In this case, the length of the display device 10 in the second direction (Y-axis direction) can be reduced by about half. Alternatively, the first folding line FOL1 and the second folding line FOL2 can extend in the diagonal direction of the display device 10 between the first direction (X-axis direction) and the second direction (Y-axis direction). In this case, the display device 10 can be folded into a triangular shape.

[00177] When the first folding line FOL1 and the second folding line FOL2 extend in the second direction (Y-axis direction), the length of the folding area FDA in the first direction (X-axis direction) may be less than the length of the folding area FDA in the second direction (Y-axis direction). Furthermore, the length of the first non-folding area NFA1 in the first direction (X-axis direction) may be greater than the length of the folding area FDA in the first direction (X-axis direction). The length of the second non-folding area Petition 870250086416, dated 09 / 24 / 2025, pp. 69 / 84 The foldable length of a 42 / 46 NFA2 in the first direction (X-axis direction) can be greater than the foldable length of an FDA in the first direction (X-axis direction).

[00178] A first display area DA1 can be arranged on the front of the display device 10. The first display area DA1 can overlap the foldable area FDA, the first non-foldable area NFA1, and the second non-foldable area NFA2. Therefore, when the display device 10 is unfolded, an image can be displayed on the front of the foldable area FDA, the first non-foldable area NFA1, and the second non-foldable area NFA2 of the display device 10.

[00179] A second display area DA2 can be arranged on the back of the display device 10. The second display area DA2 can overlap the second non-folding area NFA2. Therefore, when the display device 10 is folded, an image can be displayed on the front of the second non-folding area NFA2 of the display device 10.

[00180] In Figures 11 and 12, a through hole TH, in which an SDA camera is formed, is arranged in the first non-foldable area NFA1. However, the present invention is not limited to this. The through hole TH or the SDA camera may also be arranged in the second non-foldable area NFA2 or in the foldable area FDA.

[00181] Figures 13 and 14 are perspective views of an example application of a display device 10 according to an embodiment of the present invention.

[00182] Figures 13 and 14 illustrate an example in which the display device 10 is applied as a foldable display device, which is folded in a second direction (Y-axis direction). The display device 10 can maintain both the folded and unfolded states. The display device 10 can be folded inwards, Petition 870250086416, dated 09 / 24 / 2025, pp. 70 / 84 43 / 46 with an internally arranged front surface. When the display device 10 is folded inwards, parts of the front surface of the display device 10 may face each other. Alternatively, the display device 10 may be folded outwards, with the front surface arranged externally. When the display device 10 is folded outwards, parts of the rear surface of the display device 10 may face each other.

[00183] The display device 10 may include a foldable FDA area, a first non-foldable NFA1 area, and a second non-foldable NFA2 area. The foldable FDA area may be an area where the display device 10 is foldable, and the first non-foldable NFA1 area and the second non-foldable NFA2 area may be areas where the display device 10 is not foldable. The first non-foldable NFA1 area may be located on one side, for example, at the bottom of the foldable FDA area. The second non-foldable NFA2 area may be located on the other side, for example, at the top of the foldable FDA area.

[00184] A TSU touch detection unit according to an embodiment of the present specification may be formed and arranged in each of the first non-foldable area NFA1 and the second non-foldable area NFA2.

[00185] The foldable area FDA can be a curved area with a predetermined curvature in a first foldable line FOL1 and a second foldable line FOL2. Therefore, the first foldable line FOL1 can be a boundary between the foldable area FDA and the first non-foldable area NFA1, and the second foldable line FOL2 can be a boundary between the foldable area FDA and the second non-foldable area NFA2.

[00186] The first folding line FOL1 and the second folding line FOL2 can extend in a first direction (X-axis direction), as illustrated in figures 13 and 14, and the display device 10 can be folded in a second direction (Y-axis direction). Therefore, Petition 870250086416, dated 09 / 24 / 2025, pp. 71 / 84 44 / 46 as the length of the display device 10 in the second direction (Y-axis direction) can be reduced by about half, the user can easily carry the display device 10.

[00187] The direction in which the first folding line FOL1 and the second folding line FOL2 extend is not limited to the first direction (X-axis direction). For example, the first folding line FOL1 and the second folding line FOL2 can also extend in the second direction (Y-axis direction), and the display device 10 can also be folded in the first direction (X-axis direction). In this case, the length of the display device 10 in the first direction (X-axis direction) can be reduced by about half. Alternatively, the first folding line FOL1 and the second folding line FOL2 can extend in the diagonal direction of the display device 10 between the first direction (X-axis direction) and the second direction (Y-axis direction). In this case, the display device 10 can be folded into a triangular shape.

[00188] When the first foldable line FOL1 and the second foldable line FOL2 extend in the first direction (X-axis direction), as illustrated in Figures 13 and 14, a foldable area length FDA in the second direction (Y-axis direction) can be shorter than a foldable area length FDA in the first direction (X-axis direction). Furthermore, a length of the first non-foldable area NFA1 in the second direction (Y-axis direction) can be longer than a foldable area length FDA in the second direction (Y-axis direction). A length of the second non-foldable area NFA2 in the second direction (Y-axis direction) can be longer than a foldable area length FDA in the second direction (Y-axis direction).

[00189] A first display area DA1 can be arranged on the front of the display device 10. The first display area DA1 can overlap the foldable area FDA, the first area does not Petition 870250086416, dated 09 / 24 / 2025, pp. 72 / 84 45 / 46 foldable NFA1 and the second non-foldable area NFA2. Therefore, when display device 10 is unfolded, an image can be displayed on the front of the foldable FDA area, the first non-foldable area NFA1 and the second non-foldable area NFA2 of display device 10.

[00190] A second display area DA2 can be arranged on the back of the display device 10. The second display area DA2 can overlap the second non-folding area NFA2. Therefore, when the display device 10 is folded, an image can be displayed on the front of the second non-folding area NFA2 of the display device 10.

[00191] In figures 13 and 14, a through hole TH, in which an SDA camera is placed, is arranged in the second non-foldable area NFA2. However, the present invention is not limited to this. The through hole TH can also be arranged in the first non-foldable area NFA1 or in the foldable area FDA.

[00192] A sweep driver and a display device including the same, according to the embodiments, are altered in the design structure to reduce the voltage difference between both ends of a thin-film transistor that is subjected to stress due to voltage initialization, etc. Therefore, the electrical stress of the thin-film transistors can be reduced and the reliability can be improved.

[00193] Furthermore, a sweep driver and a display device including the same, according to the embodiments, can enhance or stabilize electrical characteristics, such as high-speed drive, operating range variation, and suppression of threshold voltage fluctuation, by enhancing the material of a semiconductor layer of at least one thin-film transistor connected directly to a pull-up node of each sweep signal output stage. Petition 870250086416, dated 09 / 24 / 2025, pp. 73 / 84 46 / 46

[00194] However, the effects of the present invention are not limited to those set forth herein. The above and other effects of the present invention will become more apparent to those skilled in the art in the field to which the present invention relates by reference to the claims.

[00195] Upon completion of the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the preferred embodiments disclosed are used only in a generic and descriptive sense, and not for purposes of limitation. Reference Listing 10: display device 200: display driver 100: display panel 210: timing controller 220: data driver 300: circuit board 400: touch driver 610: scan driver 500: power supply unit Petition 870250086416, dated 09 / 24 / 2025, pp. 74 / 84

Claims

1 / 9 CLAIMS 1. Sweep driver, characterized in that it comprises stages that sequentially emit sweep signals to sweep signal lines during an active period of one nth frame, wherein N is a positive integer, and at least one of the stages comprises: an output node controller that provides a gate voltage connected to a pull-up node in response to a gate control signal from a display driver;and an output controller that outputs a sweep clock signal, which is fed into a sweep clock terminal, to a connected sweep signal line as a sweep signal when gate-on voltage is supplied to the pull-up node, wherein the output node controller comprises a thin-film transistor that is switched on in response to a simultaneous drive control signal, supplies at least one sweep clock signal, which is fed into a first electrode, to the pull-up node to which a second electrode is connected, and periodically receives at least one sweep clock signal through the first electrode while it is switched off during the active period.

2. Sweep driver, according to claim 1, characterized in that the output node driver comprises: a first transistor is switched on when the pull-up node is enabled by the gate-on voltage and provides any sweep clock signal to a first capacitor connected to it in parallel; a second transistor is switched on when a pull-down node is enabled by the gate-on voltage and provides a gate-off voltage to the first transistor; a third transistor is switched on when the pull-up node is enabled by the gate-on voltage and provides another sweep clock signal to the pull-down node; a fourth transistor is switched on in response to a line selection signal from a sensing signal terminal or a previous carrier signal and provides the gate-on voltage to the pull-up node;A fifth transistor is switched on in response to the simultaneous drive control signal and provides at least one sweep clock signal to the pull-up node during a period of simultaneous drive and periodically receives at least one sweep clock signal through a first electrode while being switched off in response to the simultaneous drive control signal at the gate-off voltage level during the active period; a sixth transistor electrically connects the pull-up node to another transistor or to the first capacitor in response to any sweep clock signal; a seventh transistor is switched on when the pull-down node is enabled and electrically connects the sixth transistor to the first capacitor and to the first transistor; and an eighth transistor is switched on in response to a next carrier signal or another sweep clock signal and provides the gate-on voltage to the pull-down node.

3. A sweep driver, according to claim 2, characterized in that the output driver comprises: a pull-up transistor connected by the gate-connected voltage of the pull-up node and emitting any sweep clock signal, which is fed into the sweep clock terminal, to a sweep output terminal and to the sweep signal line; and a pull-down transistor connected by the gate-connected voltage of the pull-down node and sending the gate-connected voltage to the sweep output terminal and to the sweep signal line.

4. Sweep driver, according to claim 2, Petition 870250086416, dated 09 / 24 / 2025, p. 76 / 84 3 / 9 characterized in that the output node driver further comprises a ninth transistor that disables the pull-up node using the gate off voltage or any sweep clock signal in response to the next carrier signal of a next stage.

5. A sweep driver, according to claim 4, characterized in that at least one of the second, seventh, and eighth transistors indirectly connected to the pull-up node between the first and ninth transistors included in the output node driver comprises a first active layer comprising an oxide semiconductor, and at least one of the first, third, fourth, fifth, and ninth transistors directly connected to the pull-up node between the first and ninth transistors included in the output node driver comprises a second active layer comprising an oxide semiconductor different from the oxide semiconductor of the first active layer.

6. A sweep driver, according to claim 2, characterized in that the first transistor has a gate electrode connected to the pull-up node, a first electrode connected to a second sweep clock terminal, and a second electrode connected to a leading carrier terminal and a first electrode of the second transistor; the second transistor has a gate electrode connected to the pull-down node, a first electrode connected to the second electrode of the first transistor and to the leading carrier terminal, and a second electrode connected to a gate-off voltage power supply terminal; the third transistor has a gate electrode connected to the pull-up node, a first electrode connected to a first sweep clock terminal, and a second electrode connected to the pull-down node; the fourth transistor has a gate electrode connected to the sensing signal terminal or to the leading carrier terminal.The fifth transistor has a gate electrode connected to an input terminal where the simultaneous drive control signal is inserted, the second electrode connected to the pull-up node, and a second electrode connected to either clock sweep terminal. The sixth transistor has a gate electrode connected to the second clock sweep terminal, a first electrode connected to the pull-up node, and a second electrode connected to the second electrode of the first transistor or the first electrode of the seventh transistor. The seventh transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the sixth transistor, and a second electrode connected to the second electrode of the first transistor and the first capacitor.The eighth transistor has a gate electrode connected to the first clock sweep terminal, a first electrode connected to the gate-on voltage power supply terminal, and a second electrode connected to the pull-down node.

7. A sweep driver, according to claim 6, characterized in that the output driver comprises: a pull-up transistor having a first electrode connected to the second sweep clock terminal, a gate electrode connected to the pull-up node, and a second electrode connected to the sweep output terminal; and a pull-down transistor having a first electrode connected to the sweep output terminal, a gate electrode connected to the pull-down node, and a second electrode connected to a second power supply terminal at the same level as the gate off voltage.

8. Sweep driver, according to claim 7, characterized in that the pull-down transistor comprises a first active layer comprising an oxide semiconductor, and the pull-up transistor comprises a second active layer comprising Petition 870250086416, dated 09 / 24 / 2025, page 78 / 84 5 / 9 ences an oxide semiconductor different from the oxide semiconductor of the first active layer.

9. Sweep driver, according to claim 7, characterized in that the output node driver further comprises a ninth transistor having a gate electrode connected to a next carrier terminal, a first electrode connected to the previous carrier terminal or to the gate off voltage power supply terminal, and a second electrode connected to the pull-up node.

10. A sweep driver, according to claim 9, characterized in that at least one of the second, seventh, and eighth transistors indirectly connected to the pull-up node between the first and ninth transistors included in the output node driver comprises a first active layer comprising an oxide semiconductor, and at least one of the first, third, fourth, fifth, and ninth transistors directly connected to the pull-up node between the first and ninth transistors included in the output node driver comprises a second active layer comprising an oxide semiconductor different from the oxide semiconductor of the first active layer.

11. Scanning driver, according to claim 10, characterized in that the first active layer comprises indium gallium zinc oxide, and the second active layer comprises indium gallium zinc tin oxide.

12. Display device, characterized in that it comprises: a plurality of pixels arranged in a display area of ​​a display panel; a touch detection unit mounted on the front of the display panel and integrally formed with the display panel; a touch driver that detects the touch of a human body or a touch pen using a plurality of touch electrodes arranged in the touch detection unit; a display driver that controls the data voltages supplied to the pixels and the display time of the pixel image;and a scan driver that sequentially drives scan signal lines, which are connected to the pixels, in response to a gate control signal from the display driver, wherein the scan driver comprises stages that sequentially emit scan signals to the scan signal lines during an active period of one nth frame, wherein N is a positive integer, and at least one of the stages comprises: an output node controller that provides a gate voltage connected to a pull-up node in response to a gate control signal from the display driver;and an output controller that outputs a sweep clock signal, which is fed into a sweep clock terminal, to a connected sweep signal line as a sweep signal when gate-on voltage is supplied to the pull-up node, wherein the output node controller comprises a thin-film transistor that is switched on in response to a simultaneous drive control signal, supplies at least one sweep clock signal, which is fed into a first electrode, to the pull-up node to which a second electrode is connected, and periodically receives at least one sweep clock signal through the first electrode while it is switched off during the active period.

13. Display device according to claim 12, characterized in that the output node controller comprises: a first transistor is switched on when the pull-up node is enabled by the gate-on voltage and providing any sweep clock signal to a first capacitor connected to it in parallel; Petition 870250086416, dated 09 / 24 / 2025, pp. 80 / 84 7 / 9; a second transistor is switched on when a pull-down node is enabled by the gate-on voltage and providing a gate-off voltage to the first transistor; a third transistor is switched on when the pull-up node is enabled by the gate-on voltage and providing another sweep clock signal to the pull-down node; a fourth transistor is switched on in response to a line selection signal from a sensing signal terminal or a previous carrier signal and providing the gate-on voltage to the pull-up node;A fifth transistor is switched on in response to the simultaneous drive control signal and provides at least one sweep clock signal to the pull-up node during a period of simultaneous drive and periodically receives at least one sweep clock signal through a first electrode while being switched off in response to the simultaneous drive control signal at the gate-off voltage level during the active period; a sixth transistor electrically connects the pull-up node to another transistor or to the first capacitor in response to any sweep clock signal; a seventh transistor is switched on when the pull-down node is enabled and electrically connects the sixth transistor to the first capacitor and to the first transistor; and an eighth transistor is switched on in response to the next carrier signal or another sweep clock signal and provides the gate-on voltage to the pull-down node.

14. Display device according to claim 13, characterized in that the output node controller further comprises a ninth transistor that disables the pull-up node using the gate-off voltage or any sweep clock signal in response to the next carrier signal from a next stage. Petition 870250086416, dated 09 / 24 / 2025, pp. 81 / 84 8 / 9 15. Display device according to claim 13, characterized in that the first transistor has a gate electrode connected to the pull-up node, a first electrode connected to a second sweep clock terminal and a second electrode connected to a leading carrier terminal and a first electrode of the second transistor; the second transistor has a gate electrode connected to the pull-down node, a first electrode connected to the second electrode of the first transistor and to the leading carrier terminal and a second electrode connected to a gate-off voltage power supply terminal; the third transistor has a gate electrode connected to the pull-up node, a first electrode connected to a first sweep clock terminal and a second electrode connected to the pull-down node; the fourth transistor has a gate electrode connected to the sensing signal terminal or to the leading carrier terminal.The fifth transistor has a gate electrode connected to an input terminal where the simultaneous drive control signal is inserted, the second electrode connected to the pull-up node, and a second electrode connected to either clock sweep terminal. The sixth transistor has a gate electrode connected to the second clock sweep terminal, a first electrode connected to the pull-up node, and a second electrode connected to the second electrode of the first transistor or the first electrode of the seventh transistor. The seventh transistor has a gate electrode connected to the pull-down node, the first electrode connected to the second electrode of the sixth transistor, and a second electrode connected to the second electrode of the first transistor and the first capacitor.and the eighth transistor has a gate electrode connected to the first clock sweep terminal, a first electrode connected to the gate-on voltage power supply terminal, and a second electrode connected to the pull-down node.

16. Display device according to claim 15, characterized in that the output controller comprises: a pull-up transistor having a first electrode connected to the second clock sweep terminal, a gate electrode connected to the pull-up node and a second electrode connected to a sweep output terminal; and a pull-down transistor having a first electrode connected to the sweep output terminal, a gate electrode connected to the pull-down node and a second electrode connected to a second power supply terminal.

17. Display device according to claim 15, characterized in that the output node controller further comprises a ninth transistor having a gate electrode connected to a next carrier terminal, a first electrode connected to the previous carrier terminal or to the gate off voltage power supply terminal, and a second electrode connected to the pull-up node.

18. Display device according to claim 17, characterized in that at least one of the second, seventh, and eighth transistors indirectly connected to the pull-up node between the first and ninth transistors included in the output node controller comprises a first active layer comprising an oxide semiconductor, and at least one of the first, third, fourth, fifth, and ninth transistors directly connected to the pull-up node between the first and ninth transistors included in the output node controller comprises a second active layer comprising an oxide semiconductor different from the oxide semiconductor of the first active layer. Petition 870250086416, dated 09 / 24 / 2025, pp. 83 / 84

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