Pixel drive circuit and display panel

Description

1 / 25 PIXEL DRIVE CIRCUIT AND DISPLAY PANEL TECHNICAL FIELD

[0001] This application relates to the field of display technology and, specifically, relates to a pixel drive circuit and a display panel. BACKGROUND

[0002] With the continuous development of AMOLED (Active Matrix Organic Light Emitting Diode) display panels in the consumer market, consumers have increasingly higher requirements for the optical performance of AMOLED display panels. As an index for evaluating the optical performance of AMOLED display panels, flicker (image flicker) is of great importance to guide researchers in researching and developing AMOLED display panels.

[0003] Currently, AMOLED display panels have a serious image flicker problem during low refresh rate display.

[0004] The specific reason is as follows: During low-frequency display of an AMOLED display panel, a displayed image structure typically includes a recording structure and a holding structure. The holding structure includes at least one substructure. During the recording structure and the first substructure of the holding structure, there is a difference in the resetting effect of the drive transistor characteristics of the AMOLED display panel, which leads to a difference between the brightness of the AMOLED display panel in the recording structure and the brightness in the first substructure of the holding structure, thus causing the image flicker problem. SUMMARY

[0005] The present application provides a pixel drive circuit and a display panel, aiming to solve the technical problem in existing technology where a display panel Petition 870250116321, dated 12 / 17 / 2025, page 9 / 67 2 / 25 exhibits image flicker due to the brightness difference between a recording structure and the first substructure of a retention structure.

[0006] In a first aspect, the present application provides a pixel drive circuit, including: a drive transistor; a first light-emitting control module, where a control terminal of the first light-emitting control module is configured to access a first enable signal, an input terminal of the first light-emitting control module is configured to access a first power signal, and an output terminal of the first light-emitting control module is electrically connected to a first electrode of the drive transistor; a second light-emitting control module, where a control terminal of the second light-emitting control module is configured to access a second enabling signal, and an output terminal of the second light-emitting control module is electrically connected to a second electrode of the drive transistor; A data recording module, where a first control terminal of the data recording module is configured to access a first control signal, a second control terminal of the data recording module is configured to access a second control signal, an input terminal of the data recording module is configured to access a data signal, where the data recording module is electrically connected to a port, to the first electrode and to the second electrode of the drive transistor; and a first initialization module, where a control terminal of the first initialization module is configured to access a third control signal, an input terminal of the first initialization module is configured to access a Petition 870250116321, dated 12 / 17 / 2025, page 10 / 67 3 / 25 first startup signal, and an output terminal of the first startup module is electrically connected to an input terminal of the second light-emitting control module; wherein a pixel drive circuit timing sequence includes a recording structure and a holding structure, and the recording structure includes a first reset phase and a data recording phase performed sequentially; wherein, in the first reset phase, the first light-emitting control module is configured to record the first power-on signal on the first electrode and the second electrode of the drive transistor, or the first initialization module and the second light-emitting control module are configured to record the first initialization signal on the first electrode and the second electrode of the drive transistor.

[0007] Optionally, in some embodiments of the present application, the retention structure includes at least one substructure; and when the brightness of the recording structure is less than the brightness of the first substructure of the retention structure, the first power signal is recorded on the first electrode and on the second electrode of the drive transistor in the first reset stage by the first light-emitting control module in response to the first enable signal.

[0008] Optionally, in some embodiments of this application, the first control signal and the third control signal are the same signal.

[0009] Optionally, in some embodiments of the present application, the pixel drive circuit additionally includes a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, and an input terminal of the second initialization module is configured to access a second Petition 870250116321, dated 12 / 17 / 2025, page 11 / 67 4 / 25 initialization signal, and one output terminal of the second initialization module is electrically connected to the gate of the drive transistor; where, in the first reset phase, the second initialization module writes the second initialization signal to the gate of the drive transistor in response to the fourth control signal.

[0010] Optionally, in some embodiments of the present application, the second initialization module includes a fifth transistor, wherein one gate of the fifth transistor is configured to access the fourth control signal, one from a source and a drain of the fifth transistor is configured to access the second initialization signal, and another from the source and drain of the fifth transistor is electrically connected to the gate of the drive transistor.

[0011] Optionally, in some embodiments of the present application, the fifth transistor is an N-type oxide transistor.

[0012] Optionally, in some embodiments of the present application, the retention structure includes at least one substructure; and when the brightness of the recording structure is greater than the brightness of a first substructure of the retention structure, the first initialization signal is recorded on the first electrode and on the second electrode of the drive transistor in the first reset phase by the first initialization module in response to the third control signal and by the second light-emitting control module in response to the second enabling signal.

[0013] Optionally, in some embodiments of the present application, the pixel drive circuit additionally includes a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, and an input terminal of the second initialization module is configured to access a second Petition 870250116321, dated 12 / 17 / 2025, page 12 / 67 5 / 25 initialization signal, and one output terminal of the second initialization module is electrically connected to the gate of the drive transistor; where the recording structure additionally includes a second reset phase, and the second reset phase is presented between the first reset phase and the data recording phase; where, in the second reset phase, the second initialization module writes the second initialization signal to the gate of the drive transistor in response to the fourth control signal.

[0014] Optionally, in some embodiments of this application, the first control signal and the third control signal are different signals.

[0015] Optionally, in some embodiments of the present application, the first light-emitting control module includes a first transistor, where one gate of the first transistor is configured to access the first enabling signal, one from a source and a drain of the first transistor is configured to access the first power signal, and another from the source and drain of the first transistor is electrically connected to the first electrode of the drive transistor.

[0016] Optionally, in some embodiments of the present application, the second light-emitting control module includes a second transistor, wherein one gate of the second transistor is configured to access the second enabling signal, one from a source and one from a drain of the second transistor is electrically connected to the second electrode of the driving transistor, and another from the source and drain of the second transistor is electrically connected to the first starting module.

[0017] Optionally, in some embodiments of the present application, the data recording module includes a third transistor and a fourth transistor, where a gate of the third Petition 870250116321, dated 12 / 17 / 2025, page 13 / 67 6 / 25 transistor is configured to access the first control signal, one from the source and drain of the third transistor is configured to access the data signal, another from the source and drain of the third transistor is electrically connected to the first electrode of the drive transistor, one gate of the fourth transistor is configured to access the second control signal, one from the source and drain of the fourth transistor is electrically connected to the second electrode of the drive transistor, and another from the source and drain of the fourth transistor is electrically connected to the gate of the drive transistor.

[0018] Optionally, in some embodiments of the present application, the first initialization module includes a sixth transistor, wherein one gate of the sixth transistor is configured to access the third control signal, one from a source and a drain of the sixth transistor is configured to access the first initialization signal, and another from the source and drain of the sixth transistor is electrically connected to the second light-emitting control module.

[0019] Optionally, in some embodiments of the present application, the pixel drive circuit additionally includes a first capacitor, where one electrode plate of the first capacitor is electrically connected to the gate of the drive transistor, and another electrode plate of the first capacitor is configured to access the first power supply signal.

[0020] Optionally, in some embodiments of the present application, the pixel drive circuit additionally includes a second capacitor, where one electrode plate of the second capacitor is electrically connected to the gate of the drive transistor, and another electrode plate of the second capacitor is configured to access the first control signal.

[0021] Optionally, in some embodiments of the present application, the first light-emitting control module includes a first transistor, where a gate of the first transistor is Petition 870250116321, dated 12 / 17 / 2025, page 14 / 67 7 / 25 configured to access the first enable signal, one from a source and one drain of the first transistor is configured to access the first power supply signal, and another from the source and drain of the first transistor is electrically connected to the first electrode of the drive transistor; The second light-emitting control module includes a second transistor, where one gate of the second transistor is configured to access the second enabling signal, and one source and one drain of the second transistor is electrically connected to the second electrode of the driving transistor; The data recording module includes a third transistor and a fourth transistor, where one gate of the third transistor is configured to access the first control signal, one from a source and a drain of the third transistor is configured to access the data signal, another from the source and drain of the third transistor is electrically connected to the first electrode of the drive transistor, one gate of the fourth transistor is configured to access the second control signal, one from the source and drain of the fourth transistor is electrically connected to the gate of the drive transistor, and another from the source and drain of the fourth transistor is electrically connected to the second electrode of the drive transistor; The first initialization module includes a sixth transistor, where one gate of the sixth transistor is configured to access the third control signal, one from a source and a drain of the sixth transistor is configured to access the first initialization signal, and another from the source and drain of the sixth transistor is electrically connected to another from the source and drain of the second transistor; and the first transistor, the drive transistor, the second transistor, the third transistor, and the sixth transistor are low-temperature P-type polysilicon transistors, and the fourth transistor is an N-type oxide transistor. Petition 870250116321, dated 12 / 17 / 2025, page 15 / 67 8 / 25

[0022] Optionally, in some embodiments of the present application, the timing sequence for triggering the pixel drive circuit additionally includes a third reset phase and a light emission phase after the data recording phase; During the data recording phase, the data recording module transmits the compensated data signal to the drive transistor gate in response to the first control signal and the second control signal; In the third reset phase, the first light-emitting control module records the first power signal on the first electrode and the second electrode of the drive transistor in response to the first enable signal; and in the light-emitting phase, a light-emitting device is controlled to emit light by the first light-emitting control module in response to the first enable signal and by the second light-emitting control module in response to the second enable signal.

[0023] Optionally, in some embodiments of the present invention, in the retention structure, the data recording module is additionally configured to record the data signal on the first electrode and on the second electrode of the drive transistor at least once.

[0024] In a second aspect, the present invention further provides a display panel, wherein the display panel includes a plurality of pixel units arranged in an arrangement, and the pixel units include the pixel drive circuit mentioned above. BENEFICIAL EFFECTS

[0025] The present application provides a pixel drive circuit and a display panel. The pixel drive circuit includes a first light-emitting control module, a drive transistor, a second light-emitting control module. Petition 870250116321, dated 12 / 17 / 2025, page 16 / 67 9 / 25 of light, a data recording module, and a first initialization module. In the present application, before the data recording phase, the first power supply signal is recorded on the first electrode and the second electrode of the drive transistor through the first light-emitting control module, or the first initialization signal is recorded on the first electrode and the second electrode of the drive transistor through the first initialization module and the second light-emitting control module, so as to reset the potentials of the first electrode and the second electrode of the drive transistor.Thus, the gate-source voltage of the drive transistor is changed, and the reset effect of the drive transistor on the recording structure is adjusted, which can reduce the difference in the characteristic reset effect of the drive transistor between the recording structure and the holding structure, further reduce the brightness difference between the recording structure and the holding structure, and improve image flicker. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a schematic diagram of a first circuit structure of the pixel drive circuit provided by an embodiment of the present application; FIG. 2 is a schematic diagram of a signal timing sequence of a pixel drive circuit recording structure shown in FIG. 1; FIG. 3 is a schematic diagram of a second circuit structure of the pixel drive circuit provided by an embodiment of the present application; FIG. 4 is a schematic diagram of a signal timing sequence of a recording structure of the pixel drive circuit shown in FIG. 3; FIG. 5 is a schematic diagram of the signal timing sequences of a recording structure and a Petition 870250116321, dated 12 / 17 / 2025, page 17 / 67 10 / 25 pixel drive circuit retention structure shown in FIG. 3; FIG. 6 is a schematic diagram of a display panel structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of this application will be described below, with reference to the attached drawings in the embodiments of this application. The embodiments described are used only to explain the ideas of the invention and should not be considered as limiting the scope of protection of this application.

[0028] In the description of the present application, it should be understood that the terms first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with first, second, etc. may explicitly or implicitly include one or more of the features and, therefore, cannot be understood as limiting the present application. Furthermore, it should be noted that, unless clearly specified and otherwise limited, the terms connected and connection should be understood in a broad sense. For example, they may be mechanical connections or electrical connections; they may be direct connections or indirect connections via an intermediate medium, or they may be internal communication between two components.For those skilled in the art, the specific meanings of the terms above in this application may be understood according to specific situations.

[0029] The present application provides a pixel drive circuit and a display panel, which will be described in detail below. It should be noted that the order of description of the following Petition 870250116321, dated 12 / 17 / 2025, page 18 / 67 The 11 / 25 options are not intended to limit the preferential order of the options in this application.

[0030] See FIGS. 1 to 3. FIG. 1 is a schematic diagram of a first circuit structure of the pixel drive circuit provided by an embodiment of the present application, FIG. 2 is a schematic diagram of a signal timing sequence of a recording structure of the pixel drive circuit shown in FIG. 1, and FIG. 3 is a schematic diagram of a second circuit structure of the pixel drive circuit provided by an embodiment of the present application. In embodiments of the present application, the pixel drive circuit 100 includes a first light-emitting control module 101, a drive transistor DT, a second light-emitting control module 102, a data recording module 103, and a first initialization module 105.

[0031] A control terminal of the first light-emitting control module 101 is configured to access a first enable signal EM_L. An input terminal of the first light-emitting control module 101 is configured to access a first power signal ELVDD. An output terminal of the first light-emitting control module 101 is electrically connected to a first node A.

[0032] The first light-emitting control module 101 includes, among other things, a first transistor T1. One gate of the first transistor T1 is configured to access the first enable signal EM_L. One source and one drain of the first transistor T1 is configured to access the first power supply signal ELVDD. Another source and drain of the first transistor T1 is electrically connected to the first node A.

[0033] A first electrode of the DT drive transistor is electrically connected to the first node A. A second electrode of the DT drive transistor is electrically connected to a second node B. A gate of the DT drive transistor is Petition 870250116321, dated 12 / 17 / 2025, page 19 / 67 12 / 25 electrically connected to a third node Q.

[0034] The first electrode is one of a source and one of a drain of the DT drive transistor, and the second electrode is another of the source and one of the drain of the DT drive transistor.

[0035] A control terminal of the second light-emitting control module 102 is configured to access a second EM_R enable signal. An input terminal of the second light-emitting control module 102 is electrically connected to the second node B. An output terminal of the second light-emitting control module 102 is electrically connected to a fourth node C, that is, electrically connected to an output terminal of the first initialization module 105.

[0036] The second light-emitting control module 102 includes, among other things, a second transistor T2. One gate of the second transistor T2 is configured to access the second enable signal EM_R. One from a source and one from a drain of the second transistor T2 are electrically connected to the second node B. Another from a source and one from a drain of the second transistor T2 are electrically connected to the fourth node C.

[0037] A first control terminal of the data recording module 103 is configured to access a first control signal PScan(n). A second control terminal of the data recording module 103 is configured to access a second control signal Nscan(n+10). An input terminal of the data recording module 103 is configured to access a data signal Dados. The data recording module 103 is electrically connected to the first node A, the second node B, and the third node Q.

[0038] The data recording module 103 includes, among others, a third transistor T3 and a fourth transistor T4. One gate of the third transistor T3 is configured to access the first control signal PScan(n). One of the source and drain of the third transistor T3 is configured to access the signal of Petition 870250116321, dated 12 / 17 / 2025, page 20 / 67 13 / 25 Data. Another source and drain of the third transistor T3 is electrically connected to the first node A. A gate of the fourth transistor T4 is configured to access the second control signal NScan(n+10). One source and one drain of the fourth transistor T4 is electrically connected to the second node B. Another source and drain of the fourth transistor T4 is electrically connected to the third node Q.

[0039] A control terminal of the first initialization module 105 is configured to access a third control signal PScan(n) / PScan(n-1). An input terminal of the first initialization module 105 is configured to access a first initialization signal Vi1.

[0040] The first initialization module 105 includes, among others, a sixth transistor T6. One gate of the sixth transistor T6 is configured to access the third control signal PScan(n) / PScan(n-1). One of the source and drain of the sixth transistor T6 is configured to access the first initialization signal Vi1. Another of the source and drain of the sixth transistor T6 are electrically connected to the fourth node C.

[0041] In embodiments of the present application, the timing sequence of the pixel drive circuit 100 includes a recording structure and a holding structure. The recording structure includes a first reset phase M1 and a data recording phase M2 performed sequentially. In the first reset phase M1, the first electrode and the second electrode of the drive transistor DT are recorded with the first power-on signal ELVDD or the first initialization signal Vi1.

[0042] The recording structure includes a substructure, and the retention structure includes at least one substructure. It can be understood that the display panel may include multiple display frequencies, such as 30 Hz, 60 Hz, 120 Hz, etc. For example, taking 120 Hz as a reference, when the panel of Petition 870250116321, dated 12 / 17 / 2025, page 21 / 67 When the 14 / 25 display shows at 120 Hz, the timing sequence of the 100-pixel drive circuit includes only one recording structure, and the recording structure includes one substructure. When the display panel shows at 30 Hz, the timing sequence of the 100-pixel drive circuit includes one recording structure and one holding structure. The recording structure includes one substructure, and the holding structure includes three substructures. That is, when the display panel shows at 120 Hz, one structure of the displayed image includes one substructure. When the display panel shows at 30 Hz, which is a low-frequency display, one structure of the displayed image includes three substructures. The 100-pixel drive circuit records the offset data signal Data at the gate of the DT drive transistor only in the recording structure.

[0043] In the pixel drive circuit 100 provided by the embodiments of the present application, before the data recording phase M2, the first ELVDD power supply signal is recorded on the first electrode and second electrode of the drive transistor DT via the first light emission control module 101, or the first initialization signal Vi1 is recorded on the first electrode and second electrode of the drive transistor DT via the first initialization module 105 and the second light emission control module 102, so as to reset the potentials of the first electrode and second electrode of the drive transistor DT.Thus, by changing the gate-source voltage Vgs of the drive transistor DT, the reset effect of the drive transistor DT on the recording structure is adjusted, the difference in the characteristic reset effect of the drive transistor DT between the recording structure and the first substructure of the holding structure is reduced, further reducing the brightness difference between the recording structure and the first substructure. Petition 870250116321, dated 12 / 17 / 2025, page 22 / 67 15 / 25 of the retention structure, and improving image flicker.

[0044] In some embodiments of the present application, the pixel drive circuit 100 additionally includes a second initialization module 104, a first capacitor Cst and a light-emitting device D.

[0045] A control terminal of the second initialization module 104 is configured to access a fourth control signal NScan(n). An input terminal of the second initialization module 104 is configured to access a second initialization signal Vi2. An output terminal of the second initialization module 104 is connected to the third node Q.

[0046] The second initialization module 104 includes, among others, a fifth transistor T5. One gate of the fifth transistor T5 is configured to access the fourth control signal NScan(n). One of the source and drain of the fifth transistor T5 is configured to access the second initialization signal Vi2. Another of the source and drain of the fifth transistor T5 is connected to the third node Q.

[0047] One electrode plate of the first capacitor Cst is connected to the third node Q. Another electrode plate of the first capacitor Cst is configured to access the first power supply signal ELVDD.

[0048] One end of the light-emitting device D is connected to the fourth node C. The other end of the light-emitting device D is configured to access a second VSS power signal.

[0049] The voltage of the first ELVDD power supply signal is greater than the voltage of the second VSS power supply signal. The light-emitting device D can be a mini light-emitting diode, a micro light-emitting diode, or an organic light-emitting diode, which is not specifically limited in the embodiments of the present application.

[0050] It should be noted that the transistors adopted in Petition 870250116321, dated 12 / 17 / 2025, page 23 / 67 16 / 25 All embodiments of the present application may be thin-film transistors, field-effect transistors, or other devices with the same characteristics, and the source and drain of the transistor are interchangeable. In the embodiments of the present application, to distinguish the two electrodes of the transistor, except for the gate electrode, one electrode is called the source and the other electrode is called the drain. According to the form in the drawings, the middle terminal of the transistor is the gate, the signal input terminal is the drain, and the output terminal is the source. Furthermore, the transistors adopted in the embodiments of the present application may include P-type transistors and / or N-type transistors. Among them, the P-type transistor is switched on when the gate is at a low level and switched off when the gate is at a high level; the N-type transistor is switched on when the gate is at a high level and switched off when the gate is at a low level.

[0051] Furthermore, to improve the performance of the 100-pixel drive circuit, the transistors provided in the embodiments of this application are low-temperature polysilicon thin-film transistors and oxide semiconductor thin-film transistors. The oxide semiconductor thin-film transistors may be oxide thin-film transistors, such as gallium-indium-zinc oxide thin-film transistors. In the embodiments of this application, the two types of thin-film transistors mentioned above are applied in the same 100-pixel drive circuit, and the oxide thin-film transistor is used as a device in a position with high leakage current in the 100-pixel drive circuit, so as to effectively prevent load leakage at the gate of the corresponding DT drive transistor during low-frequency drive and, additionally, avoid the flickering problem in the display image.

[0052] Specifically, the following modalities of this request are described considering that the first Petition 870250116321, dated 12 / 17 / 2025, p. 24 / 67 17 / 25 transistor T1, the drive transistor DT, the second transistor T2, the third transistor T3, and the sixth transistor T6 in the 100-pixel drive circuit are low-temperature P-type polysilicon transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type oxide transistors as examples, but this cannot be understood as a limitation to the present application.

[0053] Continue referring to FIGS. 1 and 2. In some embodiments of the present application, the retention structure includes at least one substructure. When the brightness of the recording structure is less than the brightness of the first substructure of the retention structure, the first ELVDD power signal is recorded on the first electrode and the second electrode of the drive transistor DT in the first reset stage M1 by the first light-emitting control module 101 in response to the first enable signal EM_L.

[0054] Specifically, in the first reset phase M1, the first enable signal EM_L is at a low level and the first transistor T1 is turned on. The first power supply signal ELVDD is recorded on the first electrode and the second electrode of the drive transistor DT via the first transistor T1 and the drive transistor DT.

[0055] Furthermore, in the first reset phase M1, the second initialization module 104 writes the second initialization signal Vi2 to the gate of the drive transistor DT in response to the fourth control signal Nscan(n).

[0056] Specifically, in the first reset phase M1, the fourth control signal Nscan(n) is high, and the fifth transistor T5 is turned on. The second initialization signal Vi2 is written to the gate of the drive transistor DT through the fifth transistor T5.

[0057] That is, in the embodiments of the present application, both the first light-emitting control module 101 and the second Petition 870250116321, dated 12 / 17 / 2025, page 25 / 67 18 / 25 initialization module 104 operates in the first reset phase M1. Obviously, by controlling the timing sequences of the fourth control signal NScan(n) and the first enable signal EM_L, the first light-emitting control module 101 and the second initialization module 104 can also be controlled to operate in phases, which is not specifically limited in the present application.

[0058] It can be understood that recording the first ELVDD power supply signal on the first electrode on the second electrode of the DT drive transistor can cause the gate source voltage Vgs of the DT drive transistor to be at a fixed value, i.e., Vgs = Vgd = Vi2-ELVDD. Since the voltage value of the first ELVDD power supply signal is relatively large, the voltage difference of Vgs / Vgd is increased, i.e., the characteristic reset effect of the DT drive transistor is enhanced, which can effectively improve the brightness of the display panel in the recording structure and reduce flicker caused by the low brightness of the recording structure.

[0059] In embodiments of the present application, in the data recording phase M2, the data recording module 103 transmits the compensated data signal Dados to the third node Q in response to the first control signal PScan(n) and the second control signal Nscan(n+10), i.e., it records the compensated data signal at the gate of the drive transistor DT.

[0060] Specifically, in the M2 data recording phase, the first control signal PScan(n) is at a low level, the second control signal Nscan(n+10) is at a high level, and both the third transistor T3 and the fourth transistor T4 are on. The M2 data recording phase includes compensation for the threshold voltage of the drive transistor DT. Therefore, the compensated data signal, specifically Vdata+Vth, is recorded at the third node Q, where Vth is the threshold voltage of the drive transistor. Petition 870250116321, dated 12 / 17 / 2025, page 26 / 67 19 / 25

[0061] In embodiments of the present application, the first control signal PScan(n) and the third control signal PScan(n) are the same signal. Thus, in the data recording phase M2, the first initialization module 105 and the data recording module 103 operate simultaneously. The first initialization module 105 records the first initialization signal Vi1 on the fourth node C in response to the third control signal PScan(n), thereby resetting the anode of the light-emitting device D and improving display uniformity.

[0062] Specifically, in the M2 data recording phase, the third control signal PScan(n) is at a low level, and the sixth transistor T6 is turned on. The first initialization signal Vi1 is recorded in the fourth node C through the sixth transistor T6.

[0063] In embodiments of the present application, the timing sequence for triggering the pixel drive circuit 100 additionally includes a third reset phase M3 and a light emission phase M4 after the data recording phase M2.

[0064] In the third phase of the M3 reset, the first light-emitting control module 101 records the first ELVDD power supply signal on the first electrode and on the second electrode of the drive transistor DT in response to the first EM_L enable signal.

[0065] Specifically, in the third reset phase M3, the first enable signal EM_L is at a low level, and the first transistor T1 is turned on. The first power supply signal ELVDD is recorded on the first electrode and the second electrode of the drive transistor DT via the first transistor T1 and the drive transistor DT.

[0066] It can be understood that in the third phase of the M3 reset, the first light-emitting control module 101 is used to transmit the first ELVDD power supply signal to the first electrode and the second electrode of the transistor. Petition 870250116321, dated 12 / 17 / 2025, page 27 / 67 20 / 25 DT drive, so that, under different Data signals, the 100-pixel drive circuit can reset the potentials of the first electrode and the second electrode of the DT drive transistor to the same value, reducing the impact on the characteristics of the DT drive transistor.

[0067] In the light emission phase M4, the light-emitting device D is controlled to emit light by the first light-emitting control module 101 in response to the first enable signal EM_L and by the second light-emitting control module 102 in response to the second enable signal EM_R.

[0068] Specifically, in the light-emitting phase M4, both the first enabling signal EM_L and the second enabling signal EM_R are at a low level, and both the first transistor T1 and the second transistor T2 are switched on. Current flows to the light-emitting device D through the first transistor T1, the drive transistor DT, and the second transistor T2, thus allowing the light-emitting device D to emit light normally.

[0069] In some embodiments of the present application, the 100 pixel drive circuit additionally includes a second Cboost capacitor. One electrode plate of the second Cboost capacitor is electrically connected to the third node Q. Another electrode plate of the second Cboost capacitor is configured to access the first control signal PScan(n).

[0070] The function of the second Cboost capacitor is to adjust the potential of the third node Q, that is, to adjust the gate potential of the drive transistor DT. This alters the variation range of different Data signals and improves the image flicker phenomenon caused by high leakage current in the display panel.

[0071] See FIG. 3 and FIG. 4. FIG. 4 is a schematic diagram of a signal timing sequence of a pixel drive circuit recording structure. Petition 870250116321, dated 12 / 17 / 2025, page 28 / 67 21 / 25 shown in FIG. 3. The 100 pixel drive circuit shown in FIG. 3 differs from the 100 pixel drive circuit shown in FIG. 1 because, in embodiments of the present application, the holding structure includes at least one substructure and, when the brightness of the recording structure is greater than the brightness of the first substructure of the holding structure, then, in the first reset phase M1, the first initialization module 105 records the first initialization signal Vi1 on the fourth node C in response to the third control signal PScan(n1), and the second light-emitting control module 102 records the first initialization signal Vi1 on the first electrode and on the second electrode of the drive transistor DT in response to the second enable signal EM_R.

[0072] Specifically, in the first phase of resetting M1, both the third control signal PScan(n-1) and the second enable signal EM_R are at a low level, the sixth transistor T6 and the second transistor T2 are turned on, and the first initialization signal Vi1 is written to the first electrode and the second electrode of the drive transistor DT through the sixth transistor T6 and the second transistor T2.

[0073] In embodiments of the present application, the recording structure additionally includes a second M5 reset phase, and the second M5 reset phase is presented between the first M1 reset phase and the M2 data recording phase.

[0074] In the second reset phase M5, the second initialization module 104 writes the second initialization signal Vi2 to the gate of the drive transistor DT in response to the fourth control signal Nscan(n), in order to complete the initialization of the gate of the drive transistor DT.

[0075] Specifically, in the second reset phase M5, the fourth control signal Nscan(n) is high, and the fifth transistor T5 is switched on. The second initialization signal Petition 870250116321, dated 12 / 17 / 2025, page 29 / 67 22 / 25 Vi2 is recorded on the gate of the drive transistor DT through the fifth transistor T5.

[0076] It can be understood that recording the first initialization signal Vi1 on the first electrode and the second electrode of the drive transistor DT can cause the gate-source voltage Vgs of the drive transistor DT to be at a fixed value Vgs = Vgd = Vi2-Vi1. Since the voltage value of the first initialization signal Vi1 is relatively small, the voltage difference of Vgs / Vgd is reduced, that is, the resetting effect characteristic of the drive transistor DT is reduced, which can effectively reduce the brightness of the recording structure and improve the flicker caused by the high brightness of the recording structure.

[0077] In embodiments of the present application, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals.

[0078] It can be understood that, when recording the first initialization signal Vi1 on the first electrode and the second electrode of the drive transistor DT in the first reset phase M1, the first initialization module 105 and the second light-emitting control module 102 need to operate simultaneously. The data recording phase M2 occurs after the first reset phase M1. Therefore, the first control signal PScan(n) and the third control signal PScan(n-1) are different signals, so as to ensure the normal operation of the pixel drive circuit 100.

[0079] In embodiments of the present application, the timing sequence for triggering the pixel drive circuit 100 additionally includes a third reset phase M3 and a light-emitting phase M4 after the data recording phase M2, which may be referred to in the embodiments above and will not be repeated herein.

[0080] In the modalities of the present request, in the structure of Petition 870250116321, dated 12 / 17 / 2025, page 30 / 67 23 / 25 retention, the data recording module 103 is additionally configured to record the Data signal on the first electrode and on the second electrode of the drive transistor DT at least once.

[0081] Specifically, see FIG. 3 and FIG. 5. FIG. 5 is a schematic diagram of the signal timing sequences of a recording structure and a holding structure of the pixel drive circuit shown in FIG. 3. The embodiments of the present application are described considering that the holding structure includes two substructures, namely, a first substructure and a second substructure, as an example.

[0082] The signal timing sequences of the first substructure and the second substructure are the same. The difference with respect to the recording structure is that, in the first substructure or the second substructure, the timing sequence for triggering the pixel drive circuit 100 does not include the first reset phase M1. Furthermore, in the data recording phase M2, the fourth control signal NScan(n) is always held at a low level, and both the fourth transistor T4 and the fifth transistor T5 are always off. When the first control signal PScan(n) is at a low level, the third transistor T3 is turned on, and the data recording module 103 records the data signal Dados on the first electrode and the second electrode of the drive transistor DT, i.e., it resets the first electrode and the second electrode of the drive transistor DT.It can be observed that the first and second electrodes of the DT drive transistor are redefined in each substructure of the retention structure.

[0083] In the first substructure or the second substructure, the gate of the DT drive transistor maintains the data signal Data recorded in the recording structure. It should be noted that the data signal Data recorded in the recording structure is different from the data signal Data recorded in the structure of Petition 870250116321, dated 12 / 17 / 2025, page 31 / 67 24 / 25 retention.

[0084] See Figure 6. FIG. 6 is a schematic diagram of a display panel structure provided by an embodiment of the present application. Embodiments of the present invention further provide a display panel 1000, including a plurality of pixel units 110 arranged in an arrangement. Each pixel unit 110 includes the pixel drive circuit 100 according to any of the above embodiments, which may be referred to in the content above and will not be repeated herein.

[0085] In embodiments of the present invention, the display panel 1000 may be an OLED (Organic Light Emitting Diode) display panel, a Mini LED (Mini Light Emitting Diode) display panel, a Micro LED (Micro Light Emitting Diode) display panel, or the like.

[0086] In the display panel 1000 provided by the embodiments of the present application, the pixel drive circuit 100 includes a first light-emitting control module, a drive transistor, a second light-emitting control module, a data recording module, a second initialization module, a first initialization module, a first capacitor, and a light-emitting device. In the embodiments of the present application, before the data recording phase, the first power-on signal or the first initialization signal is recorded on the first electrode and the second electrode of the drive transistor in the first reset phase, so that the reset effect of the drive transistor on the recording structure can be adjusted by changing the gate-source voltage of the drive transistor.The difference in the characteristic resetting effect of the drive transistor between the recording structure and the holding structure can be reduced; in addition, the difference in brightness of the display panel between the recording structure and the holding structure can be reduced. Petition 870250116321, dated 12 / 17 / 2025, page 32 / 67 25 / 25 the retention structure can be reduced, and image flicker can be improved.

[0087] The text above describes the pixel drive circuit and display panel provided by the embodiments of the present application. The above description serves only to assist in understanding the method and central idea of ​​the present application. The present application may have other diverse embodiments. Without departing from the spirit and essential points of the present application, those skilled in the art may make various corresponding alterations and modifications in accordance with the present application, but such corresponding alterations and modifications must all be within the scope of protection of the claims appended to the present application. Petition 870250116321, dated 12 / 17 / 2025, page 33 / 67

Claims

1 / 7 CLAIMS 1. Pixel drive circuit, characterized in that it comprises: a drive transistor; a first light-emitting control module, wherein a control terminal of the first light-emitting control module is configured to access a first enable signal, an input terminal of the first light-emitting control module is configured to access a first power signal, and an output terminal of the first light-emitting control module is electrically connected to a first electrode of the drive transistor; a second light-emitting control module, wherein a control terminal of the second light-emitting control module is configured to access a second enable signal, and an output terminal of the second light-emitting control module is electrically connected to a second electrode of the drive transistor;a data recording module, wherein a first control terminal of the data recording module is configured to access a first control signal, a second control terminal of the data recording module is configured to access a second control signal, an input terminal of the data recording module is configured to access a data signal, wherein the data recording module is electrically connected to a port, to the first electrode and to the second electrode of the drive transistor;and a first initialization module, wherein a control terminal of the first initialization module is configured to access a third control signal, an input terminal of the first initialization module is configured to access a first initialization signal, and an output terminal of the first initialization module is electrically connected to an input terminal of the second light-emitting control module; wherein a pixel drive circuit timing sequence comprises a recording structure and a holding structure, and the recording structure comprises a first reset phase and a data recording phase performed sequentially;wherein, in the first reset phase, the first light-emitting control module is configured to record the first power supply signal on the first electrode and the second electrode of the drive transistor, or the first initialization module and the second light-emitting control module are configured to record the first initialization signal on the first electrode and the second electrode of the drive transistor.

2. Pixel drive circuit, according to claim 1, characterized in that the holding structure comprises at least one substructure; and when the brightness of the recording structure is less than the brightness of the first substructure of the holding structure, the first power signal is recorded on the first electrode and the second electrode of the drive transistor in the first reset stage by the first light-emitting control module in response to the first enable signal.

3. Pixel drive circuit according to claim 2, characterized in that the first control signal and the third control signal are the same signal.

4. Pixel drive circuit, according to claim 2, characterized in that it further comprises a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the drive transistor; wherein, in the first reset phase, the second initialization module writes the second initialization signal to the gate of the drive transistor in response to the fourth control signal.

5. Pixel drive circuit, according to claim 4, characterized in that the second initialization module comprises a fifth transistor, wherein one gate of the fifth transistor is configured to access the fourth control signal, one source and one drain of the fifth transistor is configured to access the second initialization signal, and another source and drain of the fifth transistor is electrically connected to the gate of the drive transistor.

6. Pixel drive circuit according to claim 5, characterized in that the fifth transistor is an N-type oxide transistor.

7. Pixel drive circuit, according to claim 1, characterized in that the holding structure comprises at least one substructure; and when the brightness of the recording structure is greater than the brightness of a first substructure of the holding structure, the first initialization signal is recorded on the first electrode and on the second electrode of the drive transistor in the first reset phase by the first initialization module in response to the third control signal and by the second light-emitting control module in response to the second enabling signal.

8. Pixel drive circuit according to claim 7, characterized in that it further comprises a second initialization module, wherein a control terminal of the second initialization module is configured to access a fourth control signal, an input terminal of the second initialization module is configured to access a second initialization signal, and an output terminal of the second initialization module is electrically connected to the gate of the drive transistor; wherein the recording structure further comprises a second reset phase, and the second reset phase is presented between the first reset phase and the data recording phase; wherein, in the second reset phase, the second initialization module records the second initialization signal at the gate of the drive transistor in response to the fourth control signal.

9. Pixel drive circuit according to claim 7, characterized in that the first control signal and the third control signal are different signals.

10. Pixel drive circuit, according to claim 1, characterized in that the first light-emitting control module comprises a first transistor, wherein one gate of the first transistor is configured to access the first enable signal, one from a source and a drain of the first transistor is configured to access the first power supply signal, and another from the source and drain of the first transistor is electrically connected to the first electrode of the drive transistor.

11. Pixel drive circuit, according to claim 1, characterized in that the second light-emitting control module comprises a second transistor, wherein one gate of the second transistor is configured to access the second enable signal, one from a source and one from a drain of the second transistor is electrically connected to the second electrode of the drive transistor, and another from the source and drain of the second transistor is electrically connected to the first initialization module.

12. Pixel drive circuit, according to claim 1, characterized in that the data recording module comprises a third transistor and a fourth transistor, Petition 870250088556, dated 09 / 30 / 2025, page 14 / 18 5 / 7, wherein one gate of the third transistor is configured to access the first control signal, one source and one drain of the third transistor is configured to access the data signal, another source and drain of the third transistor is electrically connected to the first electrode of the drive transistor, one gate of the fourth transistor is configured to access the second control signal, one source and drain of the fourth transistor is electrically connected to the second electrode of the drive transistor, and another source and drain of the fourth transistor is electrically connected to the gate of the drive transistor.

13. Pixel drive circuit, according to claim 1, characterized in that the first initialization module comprises a sixth transistor, wherein one gate of the sixth transistor is configured to access the third control signal, one source and one drain of the sixth transistor is configured to access the first initialization signal, and another source and drain of the sixth transistor is electrically connected to the second light-emitting control module.

14. Pixel drive circuit, according to claim 1, characterized in that it further comprises a first capacitor, wherein one electrode plate of the first capacitor is electrically connected to the gate of the drive transistor, and another electrode plate of the first capacitor is configured to access the first power supply signal.

15. Pixel drive circuit, according to claim 1, characterized in that it further comprises a second capacitor, wherein one electrode plate of the second capacitor is electrically connected to the gate of the drive transistor, and another electrode plate of the second capacitor is configured to access the first control signal.

16. Pixel drive circuit, according to claim 1, characterized in that the first light-emitting control module comprises a first transistor, wherein one gate of the first transistor is configured to access the first enable signal, one from a source and one from a drain of the first transistor is configured to access the first power supply signal, and another from the source and one from the drain of the first transistor is electrically connected to the first electrode of the drive transistor; the second light-emitting control module comprises a second transistor, wherein one gate of the second transistor is configured to access the second enable signal, and one from a source and one from a drain of the second transistor is electrically connected to the second electrode of the drive transistor;The data recording module comprises a third transistor and a fourth transistor, wherein one gate of the third transistor is configured to access the first control signal, one from a source and one from a drain of the third transistor is configured to access the data signal, another from the source and one from the drain of the third transistor is electrically connected to the first electrode of the drive transistor, one gate of the fourth transistor is configured to access the second control signal, one from the source and one from the drain of the fourth transistor is electrically connected to the gate of the drive transistor, and another from the source and one from the drain of the fourth transistor is electrically connected to the second electrode of the drive transistor;The first initialization module comprises a sixth transistor, wherein one gate of the sixth transistor is configured to access the third control signal, one from the source and drain of the sixth transistor is configured to access the first initialization signal, and another from the source and drain of the sixth transistor is electrically connected to another from the source and drain of the second transistor; and the first transistor, the drive transistor, the second transistor, the third transistor, and the sixth transistor are P-type low-temperature polysilicon transistors, and the fourth transistor is an N-type oxide transistor.

17. Pixel drive circuit, according to claim 1, characterized in that the timing sequence of the pixel drive circuit further comprises a third reset phase and a light emission phase after the data recording phase; in the data recording phase, the data recording module transmits the offset data signal to the gate of the drive transistor in response to the first control signal and the second control signal; in the third reset phase, the first light-emitting control module records the first power supply signal on the first electrode and the second electrode of the drive transistor in response to the first enable signal;In the light-emitting phase, a light-emitting device is controlled to emit light by the first light-emitting control module in response to the first enable signal and by the second light-emitting control module in response to the second enable signal.

18. Pixel drive circuit, according to claim 1, characterized in that, in the retention structure, the data recording module is additionally configured to record the data signal on the first electrode and on the second electrode of the drive transistor at least once.

19. Display panel, characterized in that it comprises a plurality of pixel units arranged in an array, and the pixel units comprise the pixel drive circuit as defined in claim 1. Petition 870250088556, dated 09 / 30 / 2025, pp. 17 / 18

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