Mcu synchronization of the power converter

Description

1 / 14 Power Converter MCU Synchronization

[001] This application claims priority over U.S. Provisional Patent Application No. 63 / 497,350, filed April 20, 2023, and incorporated herein by reference. Technical Field of the Invention

[002] This patent application relates to power converter technology, namely AC to DC rectifiers and battery chargers, DC to AC inverters, AC to AC converters, such as AC motor controllers, and DC to DC converters. History of the Invention

[003] A power converter may have a microcontroller unit (MCU) programmed to provide the timing of the power switches for power converter operation. The power converter usually has a reference signal to which the MCU responds to determine the switching mode or state. When two or more power converters work together, for example, when two power converters work in parallel to provide a common single-phase output or in three-phase power converters, a single controller is typically used to drive separate power converter circuits for each phase. Summary of the Invention

[004] The applicant found that a power converter controlled by an MCU can be effectively synchronized using a signal received by a hardware subsystem of the MCU. The synchronization signal can control multiple power converters and can be generated by a power converter or a synchronization controller with the synchronization signal generated using a hardware subsystem of an MCU. Petition 870250093832, dated 10 / 14 / 2025, page 9 / 101 2 / 14

[005] Direct Memory Access (DMA) is a feature of an MCU that allows certain MCU hardware subsystems to access the MCU's main memory independently of the central processing unit (CPU). The applicant has found that an MCU timer subsystem can be used to write a synchronization value to memory using DMA, which is then accessed by software running on the MCU to control the switching states of the power converter. Brief Description of the Drawings

[006] The invention will be better understood by means of the following detailed description of the applications of the invention with reference to the accompanying drawings, in which:

[007] Figure 1 is a circuit diagram of a five-level inverter having six power switches, as known in the prior art.

[008] Figure 2 is a graph of a sinusoidal voltage reference signal and four carrier reference signals, Cr1 to Cr4, as can be used in a five-level power inverter or rectifier design, as known in the prior art.

[009] Figure 3 is a block diagram of an MCU power converter configured to receive a high-frequency synchronization PWM signal from a reference distributor on its timer and set a synchronization value in memory from the timer, according to an application.

[010] Figure 4 is a block diagram of an MCU configured as a reference distributor, according to an application.

[011] Figure 5 is an illustration of a multiple power converter system, according to some applications. Petition 870250093832, dated 10 / 14 / 2025, page 10 / 101 3 / 14

[012] Figure 6 is an illustration of a system of synchronized and geographically dispersed power inverters.

[013] Figure 7 is a block diagram showing a reference distributor emitting a low-frequency main phase drive signal using its timer to synchronize an MCU-based power converter that receives the drive signal in its timer to synchronize a downstream high-frequency timer and set a synchronization value in memory, according to an application. Detailed Description of the Invention

[014] Figure 1 is a circuit diagram of one type of inverter. It should be noted that the applications described here are not limited to the number of power converter levels or the type of power conversion. Several power switches, in the example in Figure 1, this number is six, are controlled by a controller, and in the applications described here, the controller is a microcontroller unit (MCU). In Figure 1, a DC source V1 is the power input, for example, a battery or solar panel input, and the power output is AC power. Other circuit elements, such as inductors and capacitors, can help stabilize the power conversion.

[015] In a conventional power conversion circuit, the gate signals for the power switches can be generated using digital and analog circuits, rather than software. Figure 2 illustrates the AC output sine wave signal, Vr, along with high-frequency carrier signals used to define the gate signals for the switches in Figure 1. As is known in the art, the carrier signals typically have a much higher frequency than illustrated. The carrier signal oscillates between being higher than the reference Vr and lower than the reference Vr, resulting in a duty cycle that is imposed on the gate signals for the switches. Petition 870250093832, dated 10 / 14 / 2025, page 11 / 101 4 / 14 of power. The inverter in Figure 1 is a five-level inverter, meaning that the switches cause the output to have pulse width modulation between 0V and V2 in the first 45 degrees of the sine wave, between V2 and V1 in the next 90 degrees of the sine wave, between 0V and V2 in the next 45 degrees, between 0V and -V2 in the next 45 degrees, between -V2 and -V1 in the next 90 degrees, and between -V2 and 0V in the last 45 degrees of the 360-degree sine waveform. V2 has a value of ^1. Thus, the output of the inverter circuit in Figure 1 will follow Vr.

[016] When implementing switch gate control using a In MCUs, software decisions are made to define the instantaneous gate signals, i.e., ON or OFF. Such software decisions can replicate the hardware behavior using carrier signals, as illustrated in Figure 2.

[017] When an MCU-based power converter is operating alone and does not need to be synchronized, it can generate its own Vr in the software. However, when Vr needs to be synchronized, the MCU-based power converter will need to have an accurate real-time Vr value.

[018] A typical MCU will have several hardware components capable of receiving an input that can be used to receive a reference signal. For example, a data signal might be received from a serial port interface. An MCU's integrated analog-to-digital converter (ADC) might receive an analog reference signal and convert it into a digital value that the MCU's processor can read. These options are too slow to allow reliable real-time synchronization. If the processor has to take a value received from a serial port and store it in memory, the delay in Petition 870250093832, dated 10 / 14 / 2025, page 12 / 101 5 / 14 Accessing a current Vr value can lead to lack of synchronization and loss of efficiency.

[019] In the application of Figure 3, the MCU may have two hardware timer circuits. A first hardware timer is configured to measure an input PWM synchronization signal. The PWM synchronization signal varies from a minimum pulse width (non-zero) to a maximum pulse width (non-100%) which represents the instantaneous Vr value. When the reference value is an alternating signal, as illustrated in Figure 2, the variation in pulse width will be mapped to a variation in Vr from -V1 to +V1. The synchronization signal has a relatively high frequency compared to the frequency of the Vr signal, so the Vr value measured by the timer is updated frequently and in real time. For example, the synchronization signal may be above 5 kHz, for example, around 30 kHz.The timer measures the pulse duration and records it in one of its registers, optionally publishing it to the MCU's memory using the MCU's DMA.

[020] The software executed by the MCU processor can set the gate signals on the MCU output pins in real time to provide PWM to the power converter circuit. The gate signals can be controlled directly by the CPU core, operating in GPIO (general-purpose input / output) mode, or they can be controlled by a second hardware timer. This second hardware timer can be regularly updated by the CPU core with new pulse widths to be applied to the output pins. The gate signals can be updated at the execution speed of the gate control program code. When Vr changes its value, the program code will accordingly and immediately change the duty cycle of the gate states. For example, the Petition 870250093832, dated 10 / 14 / 2025, page 13 / 101 6 / 14 The program code can complete a loop, such as a for loop or a do loop, for a duration defined by the Vr reference. When the timer changes the value of Vr in memory using DMA, this will immediately change the loop duration.

[021] Although Figure 3 illustrates the MCU providing individual outputs for each of the power switches, it will be observed that it is possible to generate fewer gate signals and use logic gates and / or inverters to provide the signals applied to the gates of all the power switches.

[022] It will also be observed that, although the MCU outputs to the power converter circuit are shown as power switches associated with an inverter, as illustrated in Figure 1, it will be observed that power switches associated with a buck or boost DC / DC converter, which is part of the power converter circuit, can also be controlled. Adjusting the buck / boost allows adjusting the amplitude of the AC output voltage of an inverter or the DC output voltage of a rectifier, while the power switches in Figure 1 are switched according to the phase of the AC signal. Synchronization of the amplitudes of the power converters can be achieved using a hardware timer in a manner similar to phase synchronization or, if amplitude synchronization is less time-sensitive, it can be sent from the main controller to the MCUs via data bus signaling.

[023] The use of the hardware timer, which operates independently of the processor to update the current value of Vr, allows the software to have access to the more accurate value of Vr during execution.

[024] As illustrated in Figure 4, there is a centralized reference. It propagates the reference sinusoidal wave, representing the amplitudes that must be transmitted to the electrical network in the case of an inverter (for an AC converter). Petition 870250093832, dated 10 / 14 / 2025, page 14 / 101 7 / 14 (CC, which can represent the input AC voltage). This reference sine wave is pulse-width modulated on a wire. A separate timer can be used for each power converter, so that the timer output goes to a single power converter. The pulse widths, therefore, represent the amplitude of the sine wave at any given time. As described with reference to Figure 3 above, the distributed inverters are receivers of this pulse-width modulated signal. The pulse width can be retrieved and stored in the inverters' memory at a known location. When it is necessary to decide which voltage level to transmit to the power grid, the software running on each inverter can consult the retrieved amplitude.

[025] To achieve this sine wave propagation with high precision and determinism, using common off-the-shelf microcontrollers, a hardware timer is used. The timer can operate at a much higher speed than the propagating sine wave. As this timer advances, it triggers a DMA operation that copies an amplitude value of the sine wave from a reference table in memory to a hardware register associated with the timer. The index in the table can be advanced with each cycle of the timer clock until the end of the table, at which point the index is reset to the beginning of the table. In this way, DMA is used to read real-time values ​​at intervals defined by the timer and not by the MCU processor of the reference distributor. This hardware register controls the pulse width sent to downstream inverters or power converters.The mentioned sinusoidal wave amplitude values ​​were pre-filled in the table, and the DMA mechanism advances through them one by one, in a circular fashion; that is, it can return to time slot 0 after having gone through all the inputs. Petition 870250093832, dated 10 / 14 / 2025, page 15 / 101 8 / 14

[026] At the other end, inverters / power converters that receive the PWM-encoded sine wave can also use a hardware timer, this time in PWM input mode, as described above with reference to Figure 3. Figure 5 illustrates how a reference distributor can control multiple power converters; in the example, the distributor controls three inverters.

[027] The use of hardware timers allows this work to be performed without any software intervention after the hardware timers have been configured on both devices, thus providing this functionality without overloading the software.

[028] An example MCU code for setting and loading PWM values ​​into the circular memory table in the emitter could be: buildPwmEncodedSamples() numSamples = pwmRate / encodedSignalPeriod for (index: numSamples) sampleToEncode = $!n(2*pi*index / numSamples) samplesfindex] = sampleToEncode * pwmResolution

[029] An example of a suitable MCU is an STM32 microcontroller from STMicroelectronics. The command / instruction / configuration provided to the STM32, to make the transmitter's DMA controller advance its index in the circular memory table and load the digital PWM value into the register at fixed intervals (without jitter), could be: Si artPwm Generat ion () setTimerMode(timer, pwmGeneration, enablePreload, resetCounterOnPeriodEnd, triggerOutputOnReset) setDmaMode(memoryToPenpheral) HAL_TIMEx_PWMN_Start(timer, channel) HA L_ TIM_ DMABurst_ MuItíWríteStart(time r, counterCompareRegister, samples , numSamples) Petition 870250093832, dated 10 / 14 / 2025, page 16 / 101 9 / 14

[030] Timers can run continuously by default. Providing the resetCounterOnPeriodEnd argument above causes the timer to generate a precise period. triggerOutputOnReset causes the DMA to be triggered at the end of a period, which is important for synchronization.

[031] The command given to the receiver timer to measure the synchronization pulse, convert it into a digital value, and store it in the register can be: StartPwmMeasurementí) setTímerModettimer, pwmlnput, resetOnExternalRismgEdge, latchOnEx internalFallingEdge) HAL_TIM_iC_Starl (timer, channel)

[032] At this point, the counter register may contain the hardware-measured pulse from the last period.

[033] Although the reference distributor is illustrated as an independent component in Figures 4 and 5, it should be understood that the MCU that generates the synchronization signal can also control the gate signal associated with one of the power converters.

[034] When many power converter arrays, particularly power inverters, are deployed in geographically dispersed locations, even though they contribute to the same power grid, synchronization of the inverters is still necessary, but the use of a wired PWM-encoded signal over long distances is no longer desirable. To this end, the inverter and clock master array described earlier can be replicated at each location, as illustrated in Figure 6. The distributed clock master arrays can then be synchronized with a universal wireless reference. This reference can be the cellular network reference, the reference pulse of GPS signals, or others. Petition 870250093832, dated 10 / 14 / 2025, page 17 / 101 10 / 14

[035] This reference pulse can be used as a starting point for navigating the pre-populated memory or the sinusoidal wave sample table that is copied via DMA operations.

[036] Similarly, local synchronization of power converters can use a low-frequency pulse from a distributor, for example, as illustrated in the application in Figure 7. At a frequency of 50 Hz or 60 Hz, a timer in the distributor's MCU can generate a synchronization signal for Vr. Note that this synchronization signal can be at half or twice the frequency of Vr, or at any desired multiple / fraction. This synchronization signal can be used by the receiving MCU to trigger higher-frequency timers, for example, a "downstream" timer operating at the frequency of the reference distributor in Figure 4.

[037] The downstream timer can be used to trigger a DMA operation to obtain a digital value from a table, as in the application in Figure 4, and then place that value in memory for the software, as in Figure 3, or trigger a DMA operation to change an indirect memory access pointer so that the software directly accesses the correct value from the table.

[038] However, by resetting the downstream timer with the receiver timer, it will not be possible for the different MCU power converters that receive the same synchronization signal to experience deviations over time.

[039] It will be observed in the application of Figure 7 that two or more MCU-based power converters, such as a PUC5 inverter, can be frequency synchronized so that the processes do not deviate over time. Such power converters can be phase-locked so that the decision points (for PWM pulses, for example) are Petition 870250093832, dated 10 / 14 / 2025, page 18 / 101 11 / 14 well controlled (whether perfectly synchronized or intentionally offset).

[040] In the case of multiple inverter combinations, they must be synchronized to trigger the exact same voltage level on the grid at the exact same time. If each inverter has its own MCU, it is possible to synchronize with the connected grid, with recovery via a PLL (phase-locked loop). The PLL is normally used to recover clock and phase information from an electrical grid. In this application, the PLL is being used, for example, in inverters not connected to the grid, where the inverters are grouped to “form a local network”.

[041] It will be observed that, in the context of an MCU, there are two different types of PLL that may be involved. One type is a software process that analyzes sampled data. In the case of power inverters, this sampled data may be the 50 Hz or 60 Hz voltage signal from the grid. Phase and frequency information can be retrieved and used to inject voltage synchronously into the grid and / or intentionally phase-shift the current and voltage to adjust the active versus reactive power supply. In rectifier mode, phase and frequency information can be used to activate the switches at the right time. The other type is a hardware component used to create a clock for a hardware circuit based on a reference clock, typically obtained from a crystal-based oscillator. In this way, the CPU can build an internal clock in the hundreds of MHz range from a crystal in the tens of MHz range.

[042] An example of a suitable MCU is an STM32 microcontroller from STMicroelectronics. The phase-locked loops (PLLs) of the MCUs can operate in fractional mode, providing dynamic adjustment. A reference pulse can be sent from the distributor or from the main control (via a timer). Petition 870250093832, dated 10 / 14 / 2025, page 19 / 101 12 / 14 of the hardware) and measured by a hardware timer in each of the power converters (referred to as Control Puc5 in Figure 7). The clock synchronization manager waits for a specific series of clock increments between two pulses and adjusts the fractional component of the PLL to reach its target. The hardware timers downstream of the power converter MCU will be initiated by a trigger propagated from the clock synchronization manager timer. Inside the MCU, the input to a proportional integral (PI) controller is the captured count, whose target value is 0.

[043] In the specific example in Figure 7, it will be observed that the MCU of the main control or synchronization distributor may have a nominal frequency of 478.5 MHz, so there is room for adjustment towards 480 MHz. 478.5 MHz also has the advantage of being able to be divided into whole units.

[044] The timer that receives the low-frequency synchronization signal can be reversed at the expected cycle count (478.5 MHz / 2 / 60 Hz = 3987500 cycles). It can have a counter delay value of 1 which is exactly 0 if the local clock is synchronized with the master clock (of the Main Control). Frequency errors can be accumulated and sent to a PI controller to be reduced to 0. The output of the PI controller can control the fractional part of a PLL.

[045] When combining power converters, the PWM on the boost or buck converter side operating at the same frequency can be phase-shifted to reduce current ripple. For example, the opposition of two inverters by 180 degrees can be achieved by taking into account the LSB of the inverter's address bit (in the case of bus control, for example, using a CAN bus) and inverting the appropriate serration when synchronizing with the Petition 870250093832, dated 10 / 14 / 2025, page 20 / 101 13 / 14 reference pulse. The goal here is to shift the power switches (e.g., IGBTs) by 180 degrees in the period, on the boost or buck converter side of the design. This way, the resulting current ripple is reduced and constant. In the case of three inverters, the shift can be 120 degrees, and in the case of four inverters, 90 degrees. Therefore, the phase shift for the boost / buck stage of the power converters is 360 degrees / the number of power converters combined.

[046] In the case of an STM32 microcontroller and, in particular, STM32H743, the selected input timer can be TIM2, since it is a 32-bit timer (which provides the correct precision) and can send trigger events to TIM1, 3, 4, 8, 12 and HRTIM.

[047] An example of the command given to the transmitter timer to generate the 60 Hz clock (50 Hz in Europe) is: StartPu!seGeneration() setTimerMode(timer, pwmGeneration, enablePreload, resetCounterOnPeriodEnd) HAL_T!MER_PWM_Start(timerfchannel)

[048] An example of the command given to the receiver timer to synchronize its master clock with the transmitter timer signal, and the command given to generate higher-speed subdivided clocks is: StartPwmMeasurement() setTimerMode(timer2, pwmfnput, nominaiPeriod, resetOnExternalRísingEdge, lalchOnExternalFaliíngEdge, triggerOutpul) HALTS MICStart (timer2, channel, onlnpuiRisinEdge)

[049] How other timers can be configured to start on timer 2 trigger, and how the clocks for all other timers (as well as the CPU core) can be derived from the same Petition 870250093832, dated 10 / 14 / 2025, page 21 / 101 14 / 14 PLL, all internal modules can be synchronized and aligned in phase with timer 2.

[050] An example of the command given to the receiver to create the index value for reading the table and storing the PWM value in the register is: setTimerMode(timer2, counterMode, enablePreload, resetCounterOnPeriodEnd, triggerOutputOnReset) setDmaModefdmaChannel, memoryToMemory, sourceCircularMode, destFixedAddress Mode) startDma(dmaChannel, samples, numSamples, currentsample) HA L_ TI M_ P WM_ Start(timer2)

[051] It will be observed that measuring the duration between pulses on timer 2 on each downstream board provides synchronization. If the upstream and downstream boards are perfectly synchronized, the period measured on the downstream board will have exactly the same duration as on the upstream board. Any error (difference between the nominal period and the measured period) can be sent to a PI controller, whose output can be recorded in the PLL's precision adjustment register. Petition 870250093832, dated 10 / 14 / 2025, page 22 / 101

Claims

1 / 4 CLAIMS 1. A method for synchronizing a plurality of power converters, each having power switches controlled by a microcontroller unit (MCU) having a processor, a memory, at least one integrated hardware timer and direct memory access (DMA), the method being characterized by: providing a synchronization signal to said hardware timer of said MCU of each of said plurality of power converters; in each of said plurality of power converters, executing processor instructions stored in said memory to issue control signals to said power switches, said processor instructions referencing a value in said memory that defines a duty cycle for controlling said power switches;and in each of the aforementioned plurality of power converters, use an output of the aforementioned hardware timer to control, using DMA, the change of the aforementioned value in the aforementioned memory.

2. A method for synchronizing a plurality of power converters, according to claim 1, characterized in that said synchronization signal is a pulse stream whose pulse length defines an instantaneous reference, and said use of an output of said hardware timer to control, using DMA, the alteration of said value in said memory at a frequency of said synchronization signal.

3. A method for synchronizing a plurality of power converters, according to claim 2, characterized by said synchronization signal having a frequency above 5 kHz, with a maximum frequency of said power converters being above 10 kHz.

4. A method for synchronizing a plurality of power converters, according to claim 1, characterized in that said synchronization signal is a pulse stream that defines a phase reference point of a reference signal, and said use of an output of said hardware timer to control, using DMA, the change of said value in said memory comprising the use of said synchronization signal to trigger a downstream timer, using a count value of said downstream timer to change said value in said memory.

5. A method for synchronizing a plurality of power converters, according to claim 4, characterized in that, in each of said plurality of power converters, a table of reference values ​​is stored in said memory, an index of said table is altered with each count value of said downstream timer, and DMA is used to alter said value in said memory using the value in said table pointed to by said index.

6. A method for synchronizing a plurality of power converters, according to claim 4 or 5, characterized in that said synchronization signal has a frequency of 50 Hz or 60 Hz, with a maximum frequency of said power converters being above 10 kHz.

7. Power converter, characterized by: a plurality of power switches; a microcontroller unit (MCU) connected to the ports of said plurality of power switches and having a processor, a Petition 870250093832, dated 10 / 14 / 2025, page.24 / 101 3 / 4 memory at least one integrated hardware timer and direct memory access (DMA); said hardware timer of said MCU capable of receiving a synchronization signal; said memory storing switch control reference values ​​and processor instructions that, when executed by said processor, cause said processor to: issue control signals to said power switches, said processor instructions referencing one of said switch control reference values ​​in said memory that defines a duty cycle for controlling said power switches; and use an output of said hardware timer to control, using DMA, the change of said value in said memory.

8. Power converter, according to claim 7, characterized in that said synchronization signal is a pulse stream whose pulse length defines an instantaneous reference, and said instructions that cause said processor to use an output of said hardware timer to control, using DMA, the change of said value in said memory change said value at a frequency of said synchronization signal.

9. Power converter, according to claim 8, characterized in that said control reference values ​​of the switch correspond to said synchronization signal having a frequency above 5 kHz, with a maximum frequency of said power switches being above 10 kHz.

10. Power converter, according to claim 7, characterized in that said synchronization signal is a pulse stream that defines a phase reference point of a reference signal, and said use of an output of said hardware timer to control, using DMA, the alteration of said value in said memory comprising the use of said synchronization signal to trigger a downstream timer, using a count value of said downstream timer to alter said value in said memory.

11. Power converter, according to claim 10, characterized by said switch control reference values ​​comprising a table of reference values, and said instructions causing said processor to change an index of said table with each count value of said downstream timer, and use DMA to change said value in said memory, using the value in said table pointed to by said index.

12. Power converter, according to claim 10 or 11, characterized in that said synchronization signal has a frequency of 50 Hz or 60 Hz, with a maximum frequency of said power switches being above 10 kHz. Petition 870250093832, dated 14 / 10 / 2025, p. 26 / 101

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