Chiplet arrangement

Description

1 / 39 “CHIPLET ARRANGEMENT” FIELD OF TECHNIQUE

[001] The present disclosure relates to chiplets. More precisely, this disclosure relates to a microservices architecture of chiplet arrays. Embodiments of the invention include, for example, chiplet arrays and methods of configuring such chiplet arrays. BACKGROUND

[002] According to Moore's Law, the number of transistors in an integrated circuit (IC) doubles every two years. However, due to high costs, the rate of improvement in silicon manufacturing is slowing, and it is increasingly challenging to produce commercially viable chips at ever smaller scales. Current development of monolithic chips faces not only economic limitations, but also limitations in terms of supply / demand, flexibility, and competitiveness. Generally, from the initial design phases, the chip is conceived without the possibility of future change or evolution. This hinders hardware reuse.

[003] In response to this situation, chiplets emerged as a promising solution. In general, a chiplet is a modular semiconductor component that is configured to perform a specific function or a subset of functions of a larger integrated circuit. A chiplet can be combined with other chiplets to form a more complex integrated circuit, offering greater flexibility in design and manufacturing.

[004] The concept of chiplets has existed for several decades, with the first examples appearing in the 1980s. At that time, chiplets were mainly used for memory and I / O functions, and were assembled in separate packages that were connected to the main processor via a bus interface. In recent years, chiplets have attracted renewed interest due to advances in semiconductor manufacturing technology and the growing Petition 870250095042, dated 10 / 17 / 2025, page 8 / 57 2 / 39 complexity of modern electronic devices. By dividing a complex system or a system on a chip (SoC) into smaller, more manageable components, chiplets offer several advantages.

[005] To facilitate the use of chiplets, industry groups and standards bodies have developed interfaces and protocols for connection and communication between chiplets. Examples include the Chiplet Integration Interface (CII) from the Semiconductor Industry Association (SIA) and the Advanced Interface Bus (AIB) from the Open Compute Project (OCP). Chiplets are a promising approach for the design and manufacture of complex semiconductor devices, offering greater flexibility, efficiency, throughput, scalability, optimized performance, and reliability.

[006] The flexibility in chiplet design and manufacturing facilitates the provisioning of hardware that can be configured to perform a wide variety of tasks. However, a chiplet is a fixed solution, similar to the creation of PCBs that serve a specific task or functionality. Although standardization work is progressing, the full potential of chiplets still needs to be explored. SUMMARY

[007] In view of the above and other considerations, the various modalities of the present disclosure have been conceived. The present disclosure, therefore, acknowledges the fact that there is a need for alternatives (e.g., improvements) to the existing technique described above.

[008] One objective of some embodiments is to resolve, mitigate, attenuate, or eliminate at least some of the aforementioned deficiencies or other disadvantages. To this end, a new type of chiplet arrangement is proposed. More specifically, an objective of the invention is to provide a chiplet arrangement that is configurable and can be used more efficiently than in Petition 870250095042, dated 10 / 17 / 2025, page 9 / 57 3 / 39 prior art. These objects are addressed by the art presented in the appended independent claims, with preferred embodiments defined in the related dependent claims.

[009] In a first aspect, a chiplet array is presented. The chiplet array is controllable by an external communication interface. The chiplet array comprises at least one chiplet connected to a chiplet network. The at least one chiplet comprises at least one hardware resource. The chiplet array has a chiplet control plane configured to orchestrate one or more microsystems. Each microsystem comprises at least one hardware resource and an addressable connection on the chiplet network. The chiplet control plane is further configured to expose one or more microsystems as microservices on the external communication interface.

[010] In some variants, the chiplet array comprises two or more chiplets connected by the chiplet network. This is beneficial because additional chiplets allow for further degrees of freedom in the provision of microsystems and microservices.

[011] In some variants, the chiplet control plane is configured to set up microsystem instantiation based on the availability and / or utilization of hardware resource(s). This is advantageous because it allows for optimization of resource utilization (i.e., resource utilization rate), thereby saving energy consumption.

[012] In some variants, the chiplet control plane is configured to set up microservice instantiation based on the availability and / or utilization of hardware resource(s). This is advantageous because it allows for optimization of resource utilization, thereby reducing power consumption.

[013] In some variants, the chiplet control plane comprises a configurable resource orchestrator for instantiating microsystems of the array. Petition 870250095042, dated 10 / 17 / 2025, page 10 / 57 4 / 39 of chiplets. The resource orchestrator provides advantages such as optimized, increased or enhanced resource utilization, automated management, improved scalability, flexible deployment, and high availability and resilience (to prolonged, variable and / or disruptive resource demand).

[014] In some variants, the resource orchestrator comprises a preconfigured microsystem of the chiplet array associated with one or more preconfigured microservices of the chiplet array.

[015] In some variants, the resource orchestrator is additionally configurable to instantiate microservices associated with specific microsystems.

[016] In some variants, each instantiated microsystem is configured to consume or produce one or more microservices associated with the microsystem.

[017] In some variants, at least one microsystem is configured to consume or produce one or more microservices associated with at least one other microsystem.

[018] In some variants, the chiplet control plane comprises a network manager configured to control communication between the microsystems and the external communication interface of the chiplet array. This is advantageous because the network manager provides centralized control, enhanced network security, improved network performance and reliability, and simplified network administration.

[019] In some variants, the network manager is a preconfigured microsystem of the chiplet array associated with one or more preconfigured microservices of the chiplet array.

[020] In some variants, the control plane comprises a resource register that contains data indicating at least some of the hardware resources of the chiplet array. The resource register is advantageous because it provides Petition 870250095042, dated 10 / 17 / 2025, page 11 / 57 5 / 39 Centralized visibility and resource management, simplified resource discovery and allocation, and improved resource utilization and efficiency.

[021] In some variants, the resource register comprises data indicating all the hardware resources of all the chiplets in the chiplet array.

[022] In some variants, the control plane comprises a resource scheduler configured to schedule the use of resources. The resource scheduler is advantageous because it provides optimized resource allocation, improved resource utilization and performance, and automated resource allocation and scheduling management.

[023] In some variants, the resource scheduler is a preconfigured microsystem of the chiplet array associated with one or more preconfigured microservices of the chiplet array.

[024] In some variants, at least one hardware feature is a network interface configured to connect the chiplet to the chiplet network.

[025] In some variants, at least one hardware feature is a computational hardware feature, such as a CPU, a GPU, or a microcontroller.

[026] In some variants, at least one hardware resource is a memory hardware resource, such as a data storage unit, volatile memory, or non-volatile memory.

[027] In some variants, at least one hardware feature is a sensor hardware feature, such as a data acquisition unit, a temperature sensor, a pressure sensor, a light sensor, an optical sensor, or a fingerprint sensor.

[028] In some variants, at least one hardware feature is a peripheral hardware feature, such as an interrupt controller, a controller Petition 870250095042, dated 10 / 17 / 2025, page 12 / 57 6 / 39 DMA, a digital I / O, a DAC, an ADC, or a clock.

[029] In some variants, at least one hardware feature is a communication hardware feature, such as an I2C interface, a PCIe interface, or a UCIe interface.

[030] In some variants, at least one hardware feature is an actuator hardware feature, such as a speaker, a sound signal, a light source, or a screen.

[031] In some variants, each hardware feature provides at least one dedicated hardware functionality.

[032] In some variants, the chiplet arrangement is a package of chiplets that is part of an integrated circuit, IC.

[033] In a second aspect, a method for configuring a chiplet array is presented in accordance with the first aspect. The method is executed by the chiplet array control plane. The method comprises obtaining a request indicating a microsystem to be instantiated and instantiating a microsystem in accordance with the request obtained.

[034] In some variants, the request comprises a resource recipe indicating one or more hardware requirements of the microsystem to be instantiated.

[035] In some variants, instantiation additionally involves selecting hardware resources that meet the indicated hardware requirements, obtaining assigned scheduling data associated with the selected hardware resources.

[036] In some variants, at least one of the hardware resources is selected as a computational hardware resource, and the request additionally comprises program instructions that, when executed by the selected computational hardware resource, instantiate the microsystem indicated by the request. Petition 870250095042, dated 10 / 17 / 2025, page 13 / 57 7 / 39 bidding.

[037] In some variants, instantiation additionally involves deploying the microsystem by executing program instructions on the selected computational hardware resource.

[038] In some variants, the instantiation of the microsystem is based on the availability and / or use of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[039] The embodiments of the invention will be described below; reference will be made to the attached diagrammatic drawings which illustrate non-limiting examples of how the inventive concept can be reduced to practice.

[040] Figure 1 is a schematic view of a chiplet arrangement according to some examples of the present disclosure;

[041] Figure 2 is a schematic view of a chiplet according to some examples of the present disclosure;

[042] Figure 3 is a schematic view of a microsystem associated with a microservice according to some examples of the present disclosure;

[043] Figure 4 is a schematic view of a chiplet arrangement according to some examples of the present disclosure;

[044] Figure 5 is a schematic view of a control plane according to some examples of the present disclosure;

[045] Figure 6 is a SysML sequence diagram of dynamic instantiation of a microsystem according to some examples of the present disclosure;

[046] Figure 7 is a SysML model of a resource security microsystem in a chiplet array according to some examples of the present disclosure; and

[047] Figure 8 is a schematic view of a method of configuring a chiplet array according to some examples of the present disclosure. Petition 870250095042, dated 10 / 17 / 2025, page 14 / 57 8 / 39 DETAILED DESCRIPTION OF MODALITIES

[048] Further on in this document, certain embodiments will be described more fully with reference to the accompanying drawings. The invention can, however, be embodied in many different ways and should not be interpreted as limited to the embodiments presented herein; rather, these embodiments are provided by way of example so that this disclosure may be complete and comprehensive, and fully convey the scope of the invention, as defined in the appended claims, to those skilled in the art.

[049] Similarly, the term “connected,” or “operationally connected,” is defined as connected, though not necessarily directly, and not necessarily mechanically. Two or more items that are “coupled” or “connected” may be integral to each other. The terms “a” and “an” are defined as one or more, unless this disclosure explicitly requires otherwise. The terms “substantially,” “approximately,” and “about” are defined as broadly, but not necessarily entirely, as specified, as understood by a person of ordinary skill in the art. The terms “comprises” (and any forms thereof), “has” (and any forms thereof), “includes” (and any forms thereof), and “contains” (and any forms thereof) are open linking verbs. As a result, a method that “comprises,” “has,” “includes,” or “contains” one or more steps, possesses those one or more steps, but is not limited to possessing only those one or more steps.

[050] For the present disclosure, a chiplet is commonly a small integrated circuit (IC) comprising a well-defined subset of functionalities. It is designed to be combined with other chiplets to form a chiplet array. The chiplet array may (but is not required to) be provided on a common interposer in a single package.

[051] Chiplets have several advantages compared, for example, with Petition 870250095042, dated 10 / 17 / 2025, page 15 / 57 9 / 39 large-scale integrated circuits (ICs). Because chiplet arrays separate different functions into distinct chiplets, they make it easier to isolate and correct defects during manufacturing. This can lead to higher overall yield rates and lower costs. By mixing and matching different chiplets, designers can create customized chiplet arrays in the form of systems-on-chips (SoCs) that are optimized for specific applications. This can result in more efficient and higher-performing devices. By working with smaller, more manageable constituent components in the form of chiplets, designers can iterate faster and test individual constituent components more thoroughly before integrating them into a larger system of a 100 chiplet array. Designers can also add or remove component(s) from the SoC in real time if needed.This makes it more convenient for design engineers to scale the performance and complexity of the overall system. Chiplets enable companies to take advantage of economies of scale and reuse existing chip designs, which reduces the cost of new developments. Chiplets support a variety of applications, ranging from high-power systems (servers in data centers) to battery-powered devices (smartwatches). The philosophy behind chiplets allows for interoperability between different chiplet vendors. This leads to improved performance compared to a single monolithic chip solution.

[052] The configurability of chiplets, from a hardware perspective, has historically been isolated from the corresponding software configurability. The software functionality of a chiplet is generally limited to the functionality provided by each of the different chiplets. Each chiplet is addressed using a hardware abstraction layer (HAL), usually specific to each chiplet. To enable the full flexibility of a chiplet and also increase the utilization of SoC resources, the inventors of the present disclosure Petition 870250095042, dated 10 / 17 / 2025, page 16 / 57 10 / 39 found that a chiplet, or a set of chiplets, can be shared and used with a plurality of microservices.

[053] In general, microservices are a software architecture approach in which a large application is divided into small, independent, and loosely coupled services that can be developed, deployed, and maintained separately. Each microservice typically performs a specific function (e.g., business function, etc.) and communicates with other microservices through lightweight mechanisms such as HTTP or messaging protocols. This approach enables faster and more efficient application development, deployment, and scaling, as well as greater resilience and fault tolerance. Microservices also allow teams to work independently on different parts of the application, with each team responsible for developing and maintaining its own microservice. This approach can improve overall development speed and reduce the risk of conflicts or dependencies between teams.In general, microservices can provide greater agility, scalability, and reliability in large and complex information systems / computers.

[054] Historically, microservices were designed to be deployed as independent, lightweight components that can run on a distributed system of common hardware. This allows for greater scalability and fault tolerance than running a monolithic application on a single server. A common hardware configuration for microservices is cloud-based infrastructure. A common choice is to deploy microservices in the cloud using services such as Amazon Web Services (AWS), Microsoft Azure, or Google Cloud Platform (GCP). These cloud providers offer a variety of services and tools for running and managing microservices, including container orchestration platforms such as Kubernetes. Alternatively, microservices can run on virtual machines (VMs) using hypervisors. Petition 870250095042, dated 10 / 17 / 2025, page 17 / 57 11 / 39 such as VMware or Hyper-V. This allows for greater flexibility in deploying and scaling microservices across different hardware configurations. In some cases, microservices can be deployed on edge devices such as Internet of Things (IoT) devices or embedded systems. This requires a lightweight runtime environment that can operate on resource-constrained hardware.

[055] In general, it is generally accepted that microservices evolved from service-oriented architecture (SOA) and are commonly considered a subset of SOA. Microservices and SOA share many attributes, non-functional requirements, that are provided by the architecture and are essential for this work. For example, systems are able to discover services at runtime, without needing to have their address fixed at design time. This is usually achieved through some kind of service registry, where service providers advertise their offerings, enabling consumers to find them even in dynamic environments. Generally, services communicate only through designed APIs, containing the concepts of information hiding and encapsulation. In this way, services do not share dependencies with each other and can be modified internally as needed without impacting the behavior of other services.Furthermore, service exchanges typically occur at runtime and can change based on current conditions. Therefore, services do not need to be aggregated before deployment, as is the case with early linking, allowing the application to self-correct and optimize in the runtime environment. These capabilities require more logic, which can be added to each system or delegated to a mediator that will organize the network.

[056] Figure 1 shows a simplified view of a 100-chiplet arrangement. The 100-chiplet arrangement comprises a plurality of chiplets Petition 870250095042, dated 10 / 17 / 2025, page 18 / 57 12 / 39 110a, 110b, 110c, 110d, 110e. The arrangement of chiplets 100 in Figure 1 is revealed to comprise a plurality of chiplets 110a, 110b, 110c, 110d, 110e, that is, two or more chiplets, but those skilled in the art will recognize that an arrangement of chiplets 100 may sometimes include a single chiplet 110a, 110b, 110c, 110d, 110e. The chiplets 110a, 110b, 110c, 110d, 110e are connected by a network of chiplets 120 enabling communication between the chiplets 110a, 110b, 110c, 110d, 110e. The chiplet array 100 is controllable by an external interface 150 that enables the chiplet array 100 to control, be controlled by, or otherwise interact with one or more external systems 10. The chiplets 110a, 110b, 110c, 110d, 110e of the chiplet array 100 may be arranged in a common interposer 130 and optionally form a chiplet package 140.In other examples of the present disclosure, the chiplet arrangement 100 may comprise several chiplets 110a, 110b, 110c, 110d, 110e arranged in different interposers 130 and / or forming different chiplet packages 140. Regardless of the arrangement or the number of chiplets 110a, 110b, 110c, 110d, 110e, the chiplets 110a, 110b, 110c, 110d, 110e are connected by the chiplet network 120. A chiplet arrangement 100 according to the present disclosure may be referred to as one or more of a multi-chip module (MCM), hybrid IC, 2.5D IC, or an advanced package.

[057] The 120 chiplet network can be any suitable network or corresponding connection that enables communication between chiplets 110a, 110b, 110c, 110d, 110e, and / or between chiplets 110a, 110b, 110c, 110d, 110e and the external interface 150. In some examples, the 120 chiplet network may be a network configured according to one or more network standards such as UCIe, Bunch of Wires (BoW), OpenHBI, or OIF XSR. The 120 chiplet network is not necessarily formed by a single physical or virtual network, but may consist of a combination of one or more physical networks and / or one or more virtual networks. This will be explained in more detail in subsequent sections. Petition 870250095042, dated 10 / 17 / 2025, page 19 / 57 13 / 39

[058] Figure 1 shows the arrangement of chiplets 100 comprising five chiplets 110a, 110b, 110c, 110d, 110e. This serves only as an illustrative example, and those skilled in the art will recognize that the arrangement of chiplets 100 can comprise any number of chiplets 110a, 110b, 110c, 110d, 110e. In fact, as mentioned and as will be evident after assimilation of the complete revelation, the teachings presented in this document are also applicable to a single chiplet 110a, 110b, 110c, 110d, 110e.

[059] Those skilled in the art will recognize that the chiplets 110a, 110b, 110c, 110d, 110e, the chiplet arrangements 100, and other features presented herein may be represented in a simplified and / or condensed manner in order to make the present disclosure as efficient as possible. For example, the chiplet arrangement 100 of Figure 1 will generally require some form of power distribution in order to supply and / or control power to the chiplets 110a, 110b, 110c, 110d, 110e. These features and configurations are well known to those skilled in the art and need not be explained in detail.

[060] Figure 2 shows a simplified block diagram illustrating a chiplet 110. The chiplet 110 comprises at least one hardware resource 112a, 112b, 112c. The chiplet 110 in Figure 2 is shown with three hardware resources 112a, 112b, 112c, but any number of hardware resources is applicable. At least one of the hardware resources 112a, 112b, 112c of the chiplet 110 is addressable on the network of chiplets 120. For this purpose, a first hardware resource 112a could be a network interface hardware resource configured to connect the chiplet 110 and communicate through the network of chiplets 120. A second hardware resource 112b could be a computational hardware resource such as a CPU, a GPU, or a microcontroller. A third 112c hardware resource could be a data storage unit, that is, a memory hardware resource such as volatile memory or non-volatile memory. Petition 870250095042, dated 10 / 17 / 2025, page 20 / 57 A chiplet 110 comprising a network interface hardware resource, a computational hardware resource, and a memory hardware resource can be considered a minimal chiplet 110. However, not all hardware resources 112a, 112b, 112c may be addressable through the network of chiplets 120, and from a chiplet 100 arrangement perspective, a specific chiplet 110 may comprise only one computational hardware resource as a resource addressable only by that specific chiplet 110.

[061] Chiplet 110 may comprise additional hardware features 112a, 112b, 112c such as, but not limited to, sensor hardware features. Sensor hardware features, i.e., data acquisition units, may be exemplified as a temperature sensor, a pressure sensor, a light sensor, an optical sensor, a voltage sensor, a fingerprint sensor, etc. Additionally or alternatively, chiplet 110 may comprise hardware features 112a, 112b, 112c in the form of peripheral hardware features. Peripheral hardware features may be exemplified as, but not limited to, an interrupt controller, a DMA controller, a digital / analog I / O, a DAC, an ADC, a clock, a peripheral I / O device, a peripheral storage device, a peripheral display device, a peripheral communication device, etc.Alternatively, or additionally, chiplet 110 may comprise hardware features 112a, 112b, 112c in the form of a communication hardware feature. Communication hardware features may include, but are not limited to, a PCIe interface or a UCIe interface. Alternatively, or additionally, chiplet 110 may comprise hardware features 112a, 112b, 112c in the form of an actuator hardware feature. Actuator hardware features may include, but are not limited to, a loudspeaker, a sound signal, a switch, a light source, a screen, etc.

[062] The inventors of the present revelation realized that, not only the Petition 870250095042, dated 10 / 17 / 2025, page 21 / 57 15 / 39 microservices can be deployed and run by chiplets 110, but the chiplets 110 themselves can be managed and controlled in a manner corresponding to the microservices. That is, the hardware resources 112 of a chiplet 110, or a plurality of chiplets 110, can be configured to form a microsystem 200, see Figure 3.

[063] Figure 3 shows a microsystem 200 according to the present disclosure. The microsystem 200 provides behavior based on stored or retrieved data and the calculation performed immediately afterward. The resulting capabilities are externally exposed through one or more microservices 400 produced. A microsystem 200 is composed of (e.g., comprises, is configured with) one or more hardware resources 112 that execute one or more tasks and processes to form the functionality. A specific microsystem 200 may be associated with one or more hardware resources 112 of a specific chiplet 110 of the chiplet array 100, or associated with hardware resources 112 of two or more chiplets 110 of the chiplet array 100. As will be explained in later sections, microsystems 200 can be dynamically instantiated and subsequently reconfigured at runtime.This allows for the flexible use and reuse of the hardware resources involved. The microsystem may comprise configurable or static software (program instructions) stored and executable by the hardware resource(s) of the microsystem. It should be mentioned that there are microsystems defined exclusively by hardware resources that provide the desired functionality without requiring software.

[064] The orchestration of the microsystem(s) 200 is provided by a control plane 300. The orchestration, by the control plane 300, of one or more microsystems 200 may include, but is not limited to, managing the microsystems 200, coordinating the deployment of microsystems 200, scaling the microsystems Petition 870250095042, dated 10 / 17 / 2025, page 22 / 57 16 / 39 200 and / or control the operation of 200 microsystems. The 300 control plane is additionally configured advantageously to orchestrate the 400 microservices exposed on the external communication interface 150. The orchestration, by the 300 control plane, of one or more 400 microservices may include, but is not limited to, managing the 400 microservices, coordinating the deployment of 400 microservices, scaling the 400 microservices, and / or controlling the operation of 400 microservices. The 300 control plane is additionally configured advantageously to orchestrate the linking (association) between a specific 200 microsystem and one or more 400 microservices.

[065] Advantageously, microservices 400 are registered in an external resource registry associated with external system 10. The registration of microservices 400 in the external resource registry of external system 10 can be provided by control plane 300. One or more microsystems 200 may be equipped with software instructions, enabling the microsystem(s) 200 to register (through control plane 300) their associated microservices 400 in the external resource registry of external system 10.

[066] The 300 control plane can be formed as a centralized control plane and will generally be described as such. However, it should be emphasized that the present disclosure is also applicable, without limitation, to decentralized or distributed implementations of the 300 control plane.

[067] To exemplify the functionality of the control plane, control plane 300 can be configured to discover and manage the available hardware resources 112 and microsystems 200. This involves monitoring resource usage and availability, as well as allocating and deallocating resources as needed. Control plane 300 can, additionally or alternatively, be configured to deploy and manage microservices 400 on the available hardware resources 112 by its associated microsystem 200. This involves ensuring that each Petition 870250095042, dated 10 / 17 / 2025, page 23 / 57 17 / 39 microservice 400 should be deployed in a suitable location and be able to communicate with other microservice 400s as needed. Control plane 300 can additionally or alternatively be configured to provide service scaling. That is, as the demand for a specific microservice 400 increases or decreases, control plane 300 can be configured to scale the microservice 400 up or down as needed. This may involve adding or removing instances of the microservice 400 and / or adjusting the microsystem allocated to each instance of the microservice 400. Control plane 300 can additionally or alternatively be configured to provide health monitoring of the chiplet array 100. This may include monitoring the health of each microservice 400 and / or microsystem 200, as well as detecting and, advantageously, responding to failures or other problems as they arise.This may involve performing automatic integrity checks, restarting failed 200 microsystems and / or 400 microservices, and / or triggering alert notifications when problems occur. The 300 control plane may additionally or alternatively be configured to manage updates to 200 microservices and / or 400 microsystems to ensure that new versions of the services are deployed and made available in a controlled and secure manner.

[068] By using an SOA approach in the implementation of control plane 300, control plane 300 can be created by a set of microsystems 200 with associated microservices 400. This is schematically shown in Figure 4. It can be assumed that control plane 300 is instantiated and executed locally in each array of chiplets 100.

[069] With reference to Figure 4, an exemplary embodiment of the chiplet arrangement 100 comprising an advantageous control plane 300 will be presented. In Figure 4, the control plane 300 comprises a resource orchestrator 410. The resource orchestrator 410 can be configured to orchestrate Petition 870250095042, dated 10 / 17 / 2025, page 24 / 57 18 / 39 and coordinate the integration and instantiation of microsystems 400 and their produced and consumed microservices 200. A microsystem integration can be requested through the resource orchestrator 410 exposed as an associated microservice 410 on the external communication interface 150. These integration requests can indicate which hardware resources 112 of the chiplet array 100 should be integrated and, if applicable, provide any suitable microsystem executable code. Additionally, lifetime data can be provided, ranging from the completion of the first service request to the maximum lifetime. The maximum lifetime can be determined, for example, by the ServiceRegistry and SystemRegistry located at the edge or in the cloud, where the microsystem may need to register. If necessary, an advanced security integration scheme can be deployed; this will be explained in more detail in later sections.It should be mentioned that the microsystems 200 of the chiplet array 100 are not necessarily static. That is, the microsystems 200 can be formed in a static structure, a dynamic structure, a fluid structure, a flexible layout, evolutionary compositions, or combinations thereof. The orchestration of microsystems 200 can be renewed, updated, or dynamically altered through new requests to the resource orchestrator 410. The resource orchestrator can provide orchestration information to a network manager 440 of the control plane 300. This can be provided to configure proper communication between integrated hardware resources 112. A service integration request will generally integrate and instantiate a microsystem 200 composed of a set of prescribed hardware resources 112, for example, CPU, timer, memory, ADC, etc.

[070] The resource orchestrator 410 may comprise a preconfigured microsystem 200 of the chiplet array 200 associated with one or more preconfigured microservices 410 of the chiplet array 100. That is, the orchestrator Petition 870250095042, dated 10 / 17 / 2025, page 25 / 57 19 / 39 of resources can be preconfigured. In Figure 4, resource orchestrator 410 is shown as a microservice 400. The subject matter expert will understand that this microservice 410 is associated with a specific microsystem 200. Microservice 400 will be exposed by control plane 300, and control plane 300 will provide an interface between microservice 400 and a specific microsystem 200.

[071] Figure 4 further shows the control plane 300 comprising a resource scheduler 420. The resource scheduler 420 can be provided to ensure the timely availability of a desired microsystem 200. Hardware resource scheduling is advantageous for achieving the requested performance and obtaining maximum benefit from the potential of the chiplet array 100. The resource scheduler is advantageously configured to balance a real-time requirement with other types of priorities and / or policies. Those skilled in the art will understand that this scheduling depends on application strategies, policies, regulations, etc. A wide variety of such scheduling algorithms are available and have been previously published1 (the references in the footnote are incorporated in full herein to provide con- 1S. Singh and I. Chana, “A survey on resource scheduling in cloud computing: Issues and challenges,” Journal of Grid Computing, no.DOI 10.1007 / s10723015-9359-2, pp. 217-264, 2016. Z.-H. ZHAN, X.-F. LIU, Y.-J. GONG, J. ZHANG, HS-H. CHUNG, and Y. LI, “Cloud computing resource scheduling and a survey of its evolutionary approaches,” ACM Computing Surveys, vol. 47, no. 4, July 2015. M. Kumar, S. C. Sharma, A. Goel, and S. P. Singh, “A comprehensive survey for scheduling techniques in cloud computing,” Journal of Network and Computer Applications, vol. 143, pp. 1-33, 2019. Petition 870250095042, dated 10 / 17 / 2025, page 26 / 57 20 / 39 text to the modalities of this disclosure). From this, resource scheduling can be considered an engineering optimization problem and will not be detailed further in this disclosure.

[072] It should be mentioned that the 420 resource scheduler can be located internally or externally to the 100 chiplet array. In Figure 4, the 420 resource scheduler is shown as internal to the 100 chiplet array, but this is only one alternative, and other implementations can be considered depending on the application.

[073] Like the 410 resource orchestrator, the 420 resource scheduler can be preconfigured. In Figure 4, the 420 resource scheduler is shown as a 400 microservice, but those skilled in the art will understand that this 420 microservice is associated with a specific 200 microsystem.

[074] The exemplary control plane 300 in Figure 4 comprises a resource register 430. The resource register 430 can be configured to store data related to the hardware resources 112 of the chiplet array 100. Advantageously, the data comprises information indicating one or more of a resource ID for each hardware resource 112, a physical address for each hardware resource 112 of the chiplet array 100, and / or an electrical address for each hardware resource 112 of the chiplet array 100. The resource register may additionally comprise data associated with hardware resources of the chiplet array 100, such as resource specification, configuration data, and / or metadata. This data is generally generated at design time and, advantageously, deployed to the resource register 430 at chiplet production time.It should be mentioned that resource register 430 does not need to include data associated with all hardware resources 112 of the chiplet array 100.

[075] In the chiplet arrangement 100 of Figure 4, the control plane 300 Petition 870250095042, dated 10 / 17 / 2025, page 27 / 57 21 / 39 additionally comprises a network manager 440. The network manager 440 is advantageously configured for dynamically configured network connections of the chiplet array 100. That is, the network manager 440 is configured to create suitable communication channels for the microsystems 200 of the chiplet array. The network manager can be configured to interface with a variety of bus technologies, such as, but not limited to, PCI or UCPI. The network manager 440 can also be configured to communicate with a variety of components (hardware resources 112, chiplet network 120, external communication interface 150, etc.) of the chiplet array 100. Advantageously, each chiplet 110 and the instantiated microsystem 200 are identified on the external communication interface 150, exposing their associated microservices 400.The network manager is advantageously configured to ensure efficient and reliable communication between internal devices of the 100-chiplet array and between internal devices of the 100-chiplet array and devices external to the 100-chiplet array. This may involve measures such as implementing efficient protocols for data transmission across the 120-chiplet network, minimizing latency and / or maximizing bandwidth. Furthermore, the implementation of error correction mechanisms, flow control mechanisms, and error and exception handling mechanisms can be provided to increase efficiency and reliability in communication.

[076] Like the resource orchestrator 410, the network manager 440 can be preconfigured. The microservice 400 will be exposed by the control plane 300, and the control plane 300 will provide an interface between the microservice 400 and a specific microsystem 200. This is illustrated in Figure 4 by the network manager 440 (the microservice 200 of the control plane) providing an external communication interface 150 at an application level (dashed line in Figure 4). The physical connection of the external communication interface 150 is provided by a Petition 870250095042, dated 10 / 17 / 2025, page 28 / 57 22 / 39 suitable hardware resource 112e that is comprised in a microsystem 230 (solid line in Figure 4). In Figure 4, resource manager 440 is shown as a microservice 400, but those skilled in the art will understand that this microservice 440 is associated with a specific microsystem 200.

[077] The 100 chiplet arrangement in Figure 4 is an exemplary 100 chiplet arrangement and the features described in reference to Figure 4 are optional and may be freely combined with each other or with any other features described in this document.

[078] With reference to Figure 5, some additional example microservices 400 will be presented. In Figure 5, the control plane 300 of the chiplet array 100 comprises a resource monitor 450 associated with a specific microsystem 200 (not shown in Figure 5). The resource monitor 450 can be configured to capture the status of a wide variety of hardware resources 112 and their current and / or specified capacities. Consequently, the status types and capacity types advantageously form part of the metadata recorded for each hardware resource 112 in the resource register 430. The transfer of this status data can be provided by electrical communication and / or through a monitoring microservice request. The resource monitor 450 can be configured to provide access to historical data. Historical data can be accessed to proceed with, for example, predictive maintenance, optimization, etc.Advantageously, historical data is only available for a limited time, usually determined by storage capacity relative to the amount of historical data generated. The resource monitor 450 advantageously resides in the arrangement of chiplets 100 to enable proper monitoring of its hardware resources 112.

[079] In Figure 5, control plane 300 of chiplet array 100 additionally comprises a resource security microservice 460 associated Petition 870250095042, dated 10 / 17 / 2025, page 29 / 57 23 / 39 associated with a specific microsystem 200 (not shown in Figure 5). In general, some form of security is advantageous in most applications. Depending on the application requirements and hardware capabilities, the security measures of the chiplet of interest may comprise one or more of the following: physical tamper detection, encryption of data transferred by chiplet electrical communication (chiplet network 120 etc.), secure software integration, allowing, for example, over-the-air (OTA) software updates, secure hardware integration, etc. The detection of these security issues and the corresponding actions are advantageously initiated and monitored by the resource security microservice. Advantageously, any available types of security issue detection and actions offered by the resource security microservice 460 can be part of the metadata recorded in the resource registry 430.

[080] In Figure 5, the control plane 300 of the chiplet array 100 additionally comprises a debugger 470 with an associated microsystem 200 (not shown in Figure 5). The debugger 470 is advantageous for supporting, for example, testing and validation of the chiplet array 100, the control plane 300, and instantiated microsystems 200. The debugger 470 can be configured to trace the execution of software instructions in real time, allowing developers to identify potential problems with hardware access, timing, and / or synchronization. The debugger 470 can be configured to monitor memory access in real time, allowing developers to detect and diagnose problems with memory corruption, buffer overflow, or other memory-related issues.The 470 debugger can be configured to inspect hardware register values ​​from one or more hardware resources in real time, allowing developers to diagnose problems related to hardware configuration or control. The 470 debugger can be configured to set breakpoints and / or watch points. Petition 870250095042, dated 10 / 17 / 2025, page 30 / 57 24 / 39 specific program instructions or memory addresses, allowing developers to interrupt execution and inspect the system state at critical points. The 470 debugger can be configured to provide detailed performance profile information, allowing developers to identify performance bottlenecks and optimize code for better hardware utilization.

[081] As mentioned, the 400 microservices exemplified above and associated 200 microsystems are provided for explanatory purposes and should in no way be interpreted as limiting. As indicated in Figure 5, the 300 control plane may well comprise other 200 microservices with associated 200 microsystems. The examples presented in reference to, for example, Figures 4 and 5, can be freely combined with each other.

[082] In general, dynamic instantiation refers to the ability to create and configure instances of a design or component during execution. In the present disclosure and associated architecture, this refers to the ability to dynamically create and configure instances of 200 microsystems. The use of dynamic instantiation will allow flexibility and scalability in system design, as it enables the creation of customized 200 microsystems on demand and can further reduce costs by allowing the reuse of existing 110 chiplets. For this purpose, the 100 chiplet array is advantageously configurable to host one or more 200 microsystems. Each 200 microsystem is configured to produce and / or consume one or more 400 microservices. Advantageously, these 200 microsystems are configured to dynamically create an instance during runtime.To enable this instantiation, the chiplet array 100 can be configured to expose its hardware resources 112, and its allocation to integrated microsystems and its current usage / availability status.

[083] Consequently, to instantiate a microsystem 200, the disposi Petition 870250095042, dated 10 / 17 / 2025, page 31 / 57 25 / 39 chiplet 100 configuration is advantageously configured to dynamically integrate chiplets 110 and the necessary program instructions at runtime to form microsystems 200. Furthermore, the architecture allows the use of resources allocated to microsystems that are not in operation. This is provided by the control plane 300 of the present disclosure.

[084] With reference to Figure 6, an example of dynamic instantiation of a microsystem will be explained. Figure 6 shows a sequence diagram from the Systems Modeling Language (SysML). As is known to those skilled in the art, a SysML diagram is a type of diagram that shows the interactions between system components or actors over time. In Figure 6, the interactions between the system components or actors are shown as a series of events, with arrows indicating the flow of control between them. The events are organized along a timeline, with time progressing from top to bottom. The sequence is initiated by obtaining an integration request, indicated by the arrow in the upper left corner of Figure 6. The process will be explained below.

[085] (1) Resource orchestrator 410 receives the service request with a microsystem recipe 105. The microsystem recipe 105 comprises data necessary to instantiate a new microsystem 200 and its microservice 400. This data may be indicative of, for example, scheduling conditions, program instructions, configuration parameters, policies, a security certificate, etc.

[086] (2) Resource orchestrator 410 queries resource register 430 for available hardware resources 112 that match microsystem recipe 105. Resource orchestrator 410 examines the list of available resources and selects those that meet the requirements of that specific microsystem recipe 105. This process step is provided to ensure that the re Petition 870250095042, dated 10 / 17 / 2025, page 32 / 57 26 / 39 selected hardware courses 112 are available and meet the requirements of the microsystem recipe 105, thus enabling its composability.

[087] (3) After determining a selection of hardware resources 112 that will conform to the microsystem recipe requirements 105, the resource orchestrator 410 requests the resource scheduler 420 to assign scheduled times and slots. This may include tasks such as resource scheduling, prioritization, etc.

[088] (4) The result of the operations of resource scheduler 420 provides microsystem deployment data. The microsystem deployment data is provided to network manager 440. Network manager 440 is configured to, based on the microsystem deployment data, deploy a communication integration between the orchestrated hardware resources 112 and start the execution of the instantiated microsystem 200. This deployment will be configured to last for the lifetime requested in the resource recipe.

[089] (5) Microsystem 200 can be deployed in response to resources that are being configured with the parameters indicated in the microsystem recipe 105 and the program instructions are executed by a processing circuit (hardware resource 112 in the form of a processing circuit). Advantageously, deployment is performed in response to hardware resources 112 that have been scheduled and the chiplet network 120 has been configured for them.

[090] (6) The instantiated microsystem 200 is advantageously tested before being determined as ready for use. Tests can be performed to ensure that the overall operation of the microsystem is in accordance with the service request and the microsystem 105 recipe.

[091] (7) If the test results are positive, microsystem 200 is configured and a registry update is sent to resource registry 430 Petition 870250095042, dated 10 / 17 / 2025, page 33 / 57 27 / 39 to list and store information about the microsystem 200, the microservice instances, and the hardware resources 112 used for this task.

[092] (8) In response to the integration of microsystem 200, the microservice operation can be started.

[093] As exemplified by the process in Figure 6, the operation and use of a microsystem 200 can begin in response to the deployed microsystem 200 reaching a steady state. In the steady state, the microsystem 200 is configured as needed and provided with the software necessary for the microsystem's use. Once the intended microsystem(s) 200 is / are instantiated, the microservice(s) 400 associated with the microsystem(s) 200 is / are exposed on the external communication interface 150 and / or on the chip network 120 and made available for use. From the above, an architecture is presented that allows hardware capabilities to be exposed as a set of microservices 400, which can be dynamically updated and extended according to the current needs of the chiplet array 100.The operation of the available 400 microservices can encompass the management of various dimensions, such as functionality, security, maintenance, evolution, re-engineering, and deployment.

[094] Microservices 400 are exposed on the chiplet network 120 and / or the external communication interface 150 through network manager 440. Network manager 440 is advantageously configured to provide the chiplet array 100 with an IP address, making it accessible on the external communication interface 150. Network manager 440 is advantageously configured to also provide capabilities to communicate locally with other chiplets 110 in the same chiplet array 100. Control plane 300 enables orchestration and registration of microservices 200. The control plane is based on SOA principles; a well-established technology, therefore, it is only briefly discussed here. Petition 870250095042, dated 10 / 17 / 2025, page 34 / 57 28 / 39

[095] System of Systems (SoS) functionality refers to the collective behavior and capabilities of a group of interconnected software systems that together form a larger, more complex system. SoS functionality is concerned with how these individual systems work together to achieve a common goal or set of goals, and how they communicate and share information to achieve those goals. This includes issues such as interoperability, data exchange, and system integration. SoS functionality is generally important in large-scale software systems, where multiple independent systems need to work together to achieve a common goal.As those skilled in the art will understand, the effective functionality of a System of Service (SoS) requires careful planning and design, as well as robust communication protocols and system interfaces, to ensure that each system is able to interact effectively with the others.

[096] To integrate the 100 chiplet array into a SoS functionality, the fundamental properties of SOA—search, loose coupling, and late association—are advantageously supported by the SoS functionality. The Eclipse Arrowhead architecture is commonly known and provides a basic control plane that meets SOA principles such as search, late association, loose coupling, and security measures such as authentication, authorization, etc., in addition to other optional security measures. As an example, the basic control plane capabilities are provided in the reference implementation of the Eclipse Arrowhead architecture by the mandatory microsystems of ServiceRegistry (search), Orchestration (late association, loose coupling), and Authorisation (authorization, authentication). The SoS functionality can provide these functionalities by (based on Eclipse Arrowhead terminology):

[097] • a ServiceRegistry and an associated ServiceDiscovery microservice

[098] • an Orchestration system and its associated Orchestra microservice Petition 870250095042, dated 10 / 17 / 2025, page 35 / 57 29 / 39 tion, that is, the resource orchestrator 410 and its associated microsystem 200.

[099] • AA (Authentication, Authorization) security can be provided by an Authorization system and an associated GetPublicKey microservice.

[0100] • Additional control plane 300 services such as integration security, interoperability translators and adapters, workflow management and execution2 (the reference in the footnote is fully incorporated to provide context to the modalities of this disclosure), autonomous SoS maintenance and re-engineering3 (the reference in the footnote is fully incorporated to provide context to the modalities of this disclosure).

[0101] Some details of how these above microservices are consumed by chiplet microsystems are exemplified by the SysML model shown in Figure 7. Figure 7 shows an example implementation of a ResourceSecurity microsystem in a 100 chiplet array. In the example in Figure 7, the ability of the ResourceSecurity microsystem to consume the ServiceDiscovery, Orchestration, and GetPublicKey example microservices is advantageous for the 300 control plane.

[0102] With reference to Figure 8, a method 500 for configuring a chiplet array 100 will be presented. The chiplet array 100 can be any chiplet array 100, configured with any chiplets 110 and / or resources presented in this document with reference to any figure or example. The method 500 is advantageously executed by the control plane 300 of the chiplet array 100. The method 500 comprises obtaining a request, 2“Workflow management solutions based on microservices,” Applied Sciences. 3A. N. Lam, O. Haugen, and J. Delsing, “Dynamical orchestration and configuration services in industrial IoT systems: An autonomic approach,” IEEE Open Journal of the Industrial Electronics Society, vol. 3, pp. 128-145, 2022. Petition 870250095042, dated 10 / 17 / 2025, page 36 / 57 30 / 39 For example, a service request indicates a microsystem 200 to be instantiated. Microsystem 200 can be indirectly indicated by specifying a particular functionality that microsystem 200 should be configured to perform. Alternatively, microsystem 200 can be directly indicated by specifying hardware resources 112 that should comprise microsystem 200. It may happen that a portion of microsystem 200 is indicated indirectly, while another portion is indicated directly. Advantageously, the request includes a resource recipe 105 indicating one or more hardware functions required by microsystem 200. The hardware function can be directly indicated by specifying one or more specific hardware resources 112.

[0103] Method 500 further comprises instantiating 520 a microsystem 200 in accordance with the request obtained. Instantiation 520 may further comprise selecting 522 one or more hardware resources 112 meeting the hardware requirement indicated by the request and obtaining 524 the assigned scheduling data associated with the selected hardware resources 112. Advantageously, the request (e.g., resource recipe 105) further comprises program instructions. These program instructions can be adapted to at least one of the one or more indicated hardware resources 112 (hardware functions), and configured so that, when executed by the hardware resource(s) 112, they instantiate the microsystem 200. For this purpose, instantiation 520 further comprises deploying 526 the microsystem 200 by executing the program instructions by the hardware resource(s) 112.

[0104] As previously indicated, the control plane 300 and chiplet arrangement 100 of this disclosure allow unparalleled flexibility in instantiating microsystems 200 and associated microservices 400. Instantiation of microsystems 200 and / or microservices 400 can be based on availability and / or hardware resource utilization 112. This makes it possible that Petition 870250095042, dated 10 / 17 / 2025, page 37 / 57 31 / 39 The control plane 300 of the chiplet array 100 optimizes the utilization of hardware resources 112 based on any measurable parameter. For example, the control plane 300 might comprise a reward-driven agent that can control the instantiation, reconfiguration, and / or decommissioning of microsystems 200 and / or microservices 400. The ability of the chiplet array 100 to be reconfigured allows the chiplet array 100 to adapt and change in response to new information or changes in its environment. This can be called adaptable hardware, flexible hardware, reconfigurable hardware, or a plastic system. A plastic system is capable of modifying its behavior, structure, or function to accommodate new inputs or demands, without necessarily undergoing permanent changes.Plasticity is often associated with systems that have a high degree of flexibility and adaptability, such as biological systems, cognitive systems, or neural networks. These systems are able to learn from experience, reorganize their structure, and modify their behavior in response to new inputs or stimuli. In general, the plasticity of a system is an essential factor in its ability to cope with changes in conditions or demands and can be a critical determinant of its functionality and overall success. The 100 chiplet arrangement of the present disclosure provides plasticity to the hardware.

[0105] The following description is a general analysis of the architecture presented in this document. The proposed architecture presented in the previous sections can be considered a theoretical framework for the design and development of future electronic systems. To demonstrate its feasibility, the following sections analyze the most relevant aspects of its implementation and present solutions based on currently available technologies. The service request triggers the instantiation of a microsystem 200. This is an advantageous part of the integration of hardware resources 112, as it includes the information Petition 870250095042, dated 10 / 17 / 2025, page 38 / 57 32 / 39 instructions needed to assemble, configure, and test the microsystem 200. The request can be sent through an interface outside the chiplet array 100 to the resource orchestrator 410, which initiates the instantiation. The request comprises the resource recipe 105 as presented in this document. The request may additionally comprise the code (program instructions, software, software code) and instructions needed to configure the microsystem 200 and provide the necessary computation. The code is adapted to the CPU type indicated in the resource recipe 105. The request may additionally comprise configuration parameters. Hardware resources 112 generally require configuration parameters. The request may include a list of parameters associated with each hardware resource 112. Examples of parameters are sampling rate, timing, precision, etc. The request may additionally comprise one or more policies.In addition to configuration parameters, other types of generic policies that need to be met can be included in the request. Policies govern the operation of the 110 chiplets. These policies can be defined by a system administrator, other authorized personnel, or a system developer. The architecture presented in this document is exemplified based on the use of policies to address orchestration, composability, security, quality of service (QoS), prioritization, and resource management. Policies can be communicated to the monitoring system to ensure their application over time. The request may also include tests. Tests are a valuable part of dynamic instantiation. They are provided to ensure that the microsystem operation has the desired capabilities and functionalities. More details on the types of tests that need to be included are in the following sections.The same service request can be reused to configure multiple 110 chiplets or 100 chiplet arrays.

[0106] To achieve successful dynamic instantiation, the dispo Petition 870250095042, dated 10 / 17 / 2025, pp. 39 / 57 33 / 39 Resource availability is advantageously considered carefully. During the early stages of instantiation, the resource register 430 can be used to determine if composability is possible based on the requirements indicated in the resource recipe 105 and the availability of hardware resources 112 in the chiplet array 100. The resource register 430 advantageously includes the hardware resources 112 available at a specific time, the type of hardware resources 112, and their technical characteristics. This information can be cross-referenced, and the necessary resources are selected. If some of the resources are not available, several options can be configured. If the resource type is not available, the microsystem 200 cannot be instantiated. There are at least two solutions to this problem: (i) termination of microsystems 200 based on predefined criteria, such as priority configuration, data usability, etc.or (ii) use of queues. Instantiation can be placed on hold until hardware resources 112 are released. Resource scheduler 420 can be consulted to obtain the life expectancy of microsystems 200 and make an informed decision. Information about hardware resources can be stored in resource register 430 when the chiplet array 100 is built (produced, manufactured, marketed, installed). The internal components of the chiplet array 100 remain the same over time, only their configuration and composability change with the use of microsystems 200. Therefore, resource register 430 can contain all the information necessary to determine if composability between hardware resources 112 is possible and if it fits an expected serviceability.

[0107] Network management is one aspect of the presented architecture. The microservices architecture is designed to operate on an open wireless network, where all-to-all connections are possible. However, in a 100-chiplet array, the network faces numerous restrictions and limitations. In addition, Petition 870250095042, dated 10 / 17 / 2025, pp. 40 / 57 34 / 39 So, the nature of the 100-chiplet array involves managing the network between the 110-chiplets to provide integration of smaller independent chips into a larger 100-chiplet array. To demonstrate the feasibility of the approach and analyze the potential limitations of current technologies, two approaches are presented.

[0108] A first approach involves the interconnection of peripheral components (PCI). The PCI bus is a standard bus architecture that provides a high-speed communication channel between the processor and other peripherals. The PCI bus can be used as a communication network between the chiplets 110 and other system components. The network manager 400 would consequently act as a PCI bus master, initiating transactions on the bus and managing data transfers between the chiplets and other components.

[0109] A second approach involves Universal Chiplet Interconnect (UCPI). UCPI is a high-speed, low-latency interconnect technology designed specifically for 110 chiplets. The 440 network manager would act in this approach as the UCPI controller, managing communication between the 110 chiplets and other system components.

[0110] Regardless of the specific technology used, the 440 network manager advantageously ensures that communications between the 110 chiplets and other components are efficient, reliable, and secure. This may involve implementing error correction and flow control mechanisms, prioritizing different types of data, and handling issues such as congestion or network failures.

[0111] In the context of the proposed architecture, during the instantiation of the microsystem, the integration and testing of 200 microsystems and individual 110 chiplets into a larger system will generally occur. Therefore, in order to ensure Petition 870250095042, dated 10 / 17 / 2025, pp. 41 / 57 35 / 39 For the entire system to function correctly, it is advantageous to have a robust system testing strategy in place. The most commonly incorporated system testing strategies that can be employed for microsystem instantiation in chiplet technology are software code unit testing, integrated self-testing (BIST), boundary scan, error correction codes (ECC), and post-silicon validation.

[0112] With regard to software code unit testing, in this case, the microsystem code introduced in the service request is tested in order to ensure the correct operation of the microsystem. These tests may be included in the service request in the form of unit tests.

[0113] BIST involves the design of self-test circuits and mechanisms that can perform diagnostic tests and identify any defects or problems in a chiplet 110. BIST can be useful in detecting faults in various parts of the chiplet array 100, such as memory arrays or logic blocks.

[0114] Boundary scanning involves incorporating boundary scan cells into the chiplet design. These cells can be used to perform structural tests on the chiplet array 100 and can help identify any faults in the interconnections between the chiplets 110.

[0115] ECC can be incorporated into the chiplet design to detect and correct errors that may occur in the chiplet's memory or data paths.

[0116] Once the 110 chiplets are integrated into the larger system, extensive post-silicon validation testing can be performed to ensure the system is functioning as expected. This may include running a suite of functional tests, performance tests, and stress tests to verify the system's reliability and robustness.

[0117] When a microsystem 200 or all of its associated microservices 400 are no longer requested or needed, the microsystem can be released. This means that the hardware resources 112 are released (disassociated) Petition 870250095042, dated 10 / 17 / 2025, pp. 42 / 57 36 / 39 of microsystem 200 and control plane 300 is updated to reflect the release of microsystem 200.

[0118] The lifecycle of a microsystem 200 can be divided into four phases: (1) microsystem instantiation, (2) service integration, (3) operation, and (4) release. Resource utilization in these phases varies. Computation and communication between the components of the control plane 300 can result in overhead and delays; however, the heaviest load is located in the first two phases. Instantiation and integration are transient phases necessary only when the chiplet array 100 is updated or reused for other functions. Therefore, operation remains unchanged by the new architecture, since once the microsystems 200 are instantiated and the chiplets 110 communicate through the microservices 400, the electronic systems begin to function as a monolithic architecture.

[0119] The microservice-based chiplet implementation presented in this document can be employed in a large number of fields.

[0120] In the telecommunications field, the microservice-based chiplet 100 arrangement presented in this document can be used in telecommunications systems to provide different functionalities such as network processors / processes, communication blocks and RF systems, routing, switching, security, etc. This allows the industry to easily exchange or replace newer versions, as they are designed to be independent of the overall system.

[0121] In the automotive sector, the microservice-based chiplet array 100 can be used in automotive systems to provide different functionalities such as driver assistance, navigation, entertainment, health monitoring, infotainment systems, autonomous driving systems, maintenance systems, energy / power management systems, etc. As Petition 870250095042, dated 10 / 17 / 2025, pp. 43 / 57 37 / 39 implementations can be easily integrated into the system as services, making the overall design process more modular and flexible.

[0122] Within industrial automation, the microservice-based 100 chiplet array can be used in industrial automation systems to provide different functionalities such as control (internal and remote), monitoring, data analysis, machine vision, condition monitoring, predictive maintenance, etc. As mentioned earlier, the microservice-based 100 chiplet array can be easily integrated into the system as services, making the overall design process more modular and flexible, thus helping to meet the Industry 4.0 concept.

[0123] Within high-performance computing, a microservice-based 100 chiplet array can be used to build high-performance computing systems that can handle large volumes of data and perform complex calculations, system management, fault tolerance, AI / hardware acceleration, memory management, power management, among others.

[0124] Within artificial intelligence (AI), the microservice-based chiplet array 100 can contribute to building AI-based systems that will be able to perform complex tasks such as image and speech recognition, natural language processing, federated learning, security, explainability, edge computing, optimization, etc.

[0125] Within robotics, a microservice-based 100 chiplet array would facilitate the adaptability of robotics to changing environments and requirements, due to the modular and flexible construction offered by the concept presented in this document, providing motor control, sensor fusion, computer vision, edge intelligence, power management, etc.

[0126] Within consumer electronics, an arrangement of 100 ba chiplets Petition 870250095042, dated 10 / 17 / 2025, pp. 44 / 57 38 / 39 microservice technology offers the ability to transfer system control to consumers. This allows consumers to design and reuse the device according to their needs.

[0127] It should be mentioned that the examples above represent only some of the fields in which microservice-based chiplet 100 layouts are of great importance. There are many other possible use cases in different domains. All of this is made possible due to the essential aspect of the microservice-based chiplet 100 layout of providing a way to manage communication and interactions between different chiplets and microsystems in a more modular, flexible, and scalable manner.

[0128] The modalities, examples, resources, and concepts presented in this document enable an architecture in which a control plane 300 can organize and instantiate (e.g., orchestrate) any suitable hardware and / or software resources in the form of microsystems 200. These microsystems 200 can be configured to consume one or more microservices 400 and / or produce one or more microservices 400.

[0129] Modifications and other variants of the described embodiments will become apparent to those skilled in the art, benefiting from the teachings presented in the preceding description and the associated drawings. Therefore, it should be understood that the embodiments are not limited to the specific examples described in this disclosure and that modifications and other variants are intended to be included within the scope of this disclosure. For example, although the embodiments of the invention have been described with reference to chiplets and chiplet arrangements, those skilled in the art will understand that the embodiments of the invention can be applied equivalently to any suitable computer system and not specifically to chiplets.

[0130] As a mere example, it is conceivable to provide a computer system controllable by an external communication interface. The computer system Petition 870250095042, dated 10 / 17 / 2025, pp. 45 / 57 39 / 39 The system comprises a plurality of hardware resources, each providing at least one dedicated hardware functionality. The hardware resources are connected by a hardware network. The computer system has a control plane configured to orchestrate one or more microsystems, each microsystem comprising at least one hardware resource and an addressable connection on the network. The control plane is further configured to expose one or more microsystems as microservices on the external communication interface.

[0131] Furthermore, although specific terms may be employed in this document, they are used only in a generic and descriptive sense and not for purposes of limitation. Therefore, one skilled in the art will recognize numerous variations of the embodiments described that would still be included within the scope of the appended claims. Furthermore, although individual features may be included in different claims (or embodiments), they may possibly be advantageously combined, and the inclusion of different claims (or embodiments) does not imply that a combination of features is not feasible and / or advantageous. Furthermore, singular references do not preclude plurality. Finally, reference signs in the claims are provided merely as an explanatory example and should not be interpreted in any way as limiting the scope of the claims. Petition 870250095042, dated 10 / 17 / 2025, pp. 46 / 57

Claims

1 / 5 CLAIMS 1. Chiplet arrangement (100) controllable by an external communication interface (150), wherein the chiplet arrangement (100) CHARACTERIZED in that it comprises at least one chiplet (110) connected to a chiplet network (120), and wherein the at least one chiplet (110) comprises at least one hardware resource (112); and wherein the chiplet arrangement (100) is endowed with a chiplet control plane (300) configured to: orchestrate one or more microsystems (200), wherein each microsystem (200) comprises at least one hardware resource (112) and an addressable connection in the chiplet network (120), and expose one or more microsystems (200) as microservices (400) in the external communication interface (150).

2. Arrangement of chiplets (100), according to claim 1, CHARACTERIZED in that it comprises two or more chiplets (110) connected by the chiplet network (120).

3. Arrangement of chiplets (100), according to claim 1 or 2, CHARACTERIZED in that the chiplet control plane (300) is configured to set up the instantiation of microsystems (200) based on the availability and / or utilization of hardware resource(s) (112).

4. Arrangement of chiplets (100), according to any of the preceding claims, CHARACTERIZED in that the chiplet control plane (300) is configured to set up the instantiation of microservices (400) based on the availability and / or utilization of hardware resource(s) (112).

5. Chiplet arrangement (100), according to any of the preceding claims, CHARACTERIZED in that the chiplet control plane (300) comprises: a resource orchestrator (410) configurable to instantiate microsystem Petition 870250095042, dated 10 / 17 / 2025, page 47 / 57 2 / 5 but (200) of the chiplet arrangement (100).

6. Chiplet arrangement (100), according to claim 5, CHARACTERIZED in that the resource orchestrator (410) comprises a pre-configured microsystem (200) of the chiplet arrangement (100) associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

7. Arrangement of chiplets (100), according to claim 5 or 6, CHARACTERIZED in that the resource orchestrator (410) is additionally configurable to instantiate microservices (400) associated with specific microsystems (200).

8. Arrangement of chiplets (100), according to any of the preceding claims, CHARACTERIZED in that at least one microsystem (200) is configured to consume or produce one or more microservices (400) associated with at least one microsystem (200).

9. Chiplet arrangement (100), according to any of the preceding claims, CHARACTERIZED in that the chiplet control plane (300) comprises: a network manager (440) configured to control communication between the microsystems (200) and the external communication interface (150) of the chiplet arrangement (100).

10. Chiplet arrangement (100), according to claim 9, CHARACTERIZED in that the network manager (440) is a pre-configured microsystem (200) of the chiplet arrangement (100) associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

11. Chiplet arrangement (100), according to any of the preceding claims, CHARACTERIZED in that the control plane (300) comprises a resource register (430) comprising data indicating at least some hardware resources (112) of the chiplet arrangement (100), preferably the resource register (430) comprising data indicating all hardware resources (112) of all chiplets (110) of the chiplet arrangement (100).

12. Arrangement of chiplets (100), according to any of the preceding claims, CHARACTERIZED in that the control plane (300) comprises a resource scheduler (420) configured to schedule the utilization of hardware resources (112).

13. Chiplet arrangement (100), according to claim 12, CHARACTERIZED in that the resource scheduler (420) is a pre-configured microsystem (200) of the chiplet arrangement (100) associated with one or more pre-configured microservices (400) of the chiplet arrangement (100).

14. Arrangement of chiplets (100), according to any of the preceding claims, CHARACTERIZED in that at least one hardware feature (112) is a network interface configured to connect the chiplet (110) to the chiplet network (120).

15. Chiplet arrangement (100), according to any of the preceding claims, CHARACTERIZED in that at least one hardware feature (112) is a computational hardware feature such as a CPU, a GPU or a microcontroller and / or at least one hardware feature (112) is a memory hardware feature such as volatile memory or non-volatile memory, and / or at least one hardware feature (112) is a sensor hardware feature (112) such as a temperature sensor, a pressure sensor, a light sensor, an optical sensor or a fingerprint sensor, and / or at least one hardware feature (112) is a peripheral hardware feature (112) such as an interrupt controller, a DMA controller, a digital I / O, a DAC, an ADC or a clock, and / or at least one hardware feature (112) is a communication hardware feature (112) such as an I2C interface, an interface PCIe or a UCIe interface,and / or provided that at least one Petition 870250095042, of 10 / 17 / 2025, page 49 / 57 4 / 5 hardware resource (112) is an actuator hardware resource (112) such as a loudspeaker, a sound signal, a light source or a screen., 16. Arrangement of chiplets (100), according to any of the preceding claims, CHARACTERIZED in that each hardware feature (112) provides at least one dedicated hardware functionality.

17. Chiplet arrangement (100), according to any of the preceding claims, CHARACTERIZED in that the chiplet arrangement (100) is a chiplet package that is part of an integrated circuit, IC.

18. Method (500) for configuring a chiplet array (100), according to any of the preceding claims, wherein the method (500) is CHARACTERIZED in that it is executed by the control plane (300) of the chiplet array (100) and comprises: obtaining (510) a request indicating that a microsystem (200) is to be instantiated, and instantiating (520) a microsystem (200) in accordance with the obtained request.

19. Method (500), according to claim 18, CHARACTERIZED in that the request comprises a resource recipe (105) indicating one or more hardware requirements of the microsystem (200) to be instantiated and the instantiation (520) further comprises: selecting (522) hardware resources (112) that meet the hardware requirements, and obtaining (524) assigned scheduling data associated with the selected hardware resources (112).

20. Method (500), according to claim 19, CHARACTERIZED in that at least one of the hardware resources (112) is selected as a computational hardware resource, the application further comprises program instructions which, when executed by the selected computational hardware resource, instantiate the microsystem (200) indicated by the application; the instantiation (510) further comprises: deploying (526) the microsystem by executing the program instructions by the selected computational hardware resource.

21. Method (500), according to any one of claims 18 to 20, CHARACTERIZED in that the instantiation (520) of the microsystem (200) is based on the availability and / or use of hardware resources (112). Petition 870250095042, dated 10 / 17 / 2025, pp. 51 / 57

Images