Display panel and display device

Description

1 / 26 DISPLAY PANEL AND DISPLAY DEVICE TECHNICAL FIELD

[0001] This application relates to a technical field of display and, in particular, to a display panel and a display device. BACKGROUND

[0002] In a manufacturing process for an organic light-emitting diode (OLED) display panel, layers of organic film in a non-display area of ​​the display panel need to be excavated to form a barrier groove to level an organic encapsulation layer, and a conductive structure at the bottom of the barrier groove is exposed. Affected by the precision of the film-forming process and considering the requirements of a narrow structure, the boundary of a cathode often extends to the barrier groove, so that the cathode has easy contact with the exposed conductive structure, resulting in a short-circuit risk. In related technology, a passivation (PV) layer is placed between the cathode and the conductive structure to block the cathode and the conductive structure, so as to reduce the short-circuit risk. However, the manufacturing of the PV layer requires at least one process, which does not contribute to cost reduction. SUMMARY

[0003] A display panel and a display device are provided to solve a technical problem where a passivation (PV) layer is placed between a cathode and a conductive structure to reduce the risk of short-circuiting between them in the existing display panel and display device, resulting in a more time-consuming manufacturing process, which does not contribute to cost reduction.

[0004] To resolve the problem mentioned above, the technical solutions provided by this application are as follows: A display panel provided by this application includes Petition 870250095189, dated 10 / 17 / 2025, page 47 / 108 2 / 26 a display area and a non-display area located on at least one side of the display area and further includes: a substrate; a conductive structure located on one side of the substrate and extending from the display area to the non-display area; a first layer of planarization covering the conductive structure and extending from the display area to the non-display area; a second planarization layer located on one side of the first planarization layer, away from the substrate and located in the display area and the non-display area; A pixel definition layer located on one side of the second planarization layer, away from the substrate and located in both the display and non-display areas; and a cathode layer located on one side of the pixel definition layer, away from the substrate.

[0005] The display panel also includes a first spacing slot located in the non-display area, the first spacing slot penetrates through the second planarization layer and the pixel definition layer, and a cathode layer boundary falls into the first spacing slot.

[0006] According to the display panel provided by the present application, the display panel further includes a first barrier dam and a second barrier dam located in the non-display area at intervals, the second barrier dam is located on one side of the first barrier dam away from the first spacing slot, and a second spacing slot is defined between the first barrier dam and the second barrier dam.

[0007] the first barrier includes the second planarization layer and the pixel definition layer, and the second barrier includes the pixel definition layer and does not include the second planarization layer. Petition 870250095189, dated 10 / 17 / 2025, page 48 / 108 3 / 26

[0008] According to the display panel provided by the present application, the display panel further includes a chemical attack barrier layer located on the side of the first planarization layer, away from the substrate and located in the non-display area, and an orthographic projection of the chemical attack barrier layer onto the substrate covers at least one orthographic projection of the first spacing groove on the substrate.

[0009] According to the display panel provided by the present application, an orthographic projection of a boundary of the chemical attack barrier layer away from the display area on the substrate is within an orthographic projection of the second barrier on the substrate.

[0010] According to the display panel provided with this application, the chemical attack barrier layer is made of metal.

[0011] According to the display panel provided by the present application, the chemical attack barrier layer is provided with a plurality of exhaust holes in the first spacing groove, and the first planar layer is exposed by the plurality of exhaust holes.

[0012] According to the display panel provided by the present application, a plurality of planarization blocks corresponding to the plurality of exhaust holes are arranged in the first spacing slot and are arranged in the same layer as the second planarization layer, and an orthographic projection of each of the plurality of planarization blocks on the substrate covers an orthographic projection of a corresponding plurality of exhaust holes on the substrate.

[0013] According to the display panel provided by this application, an opening of each of the plurality of exhaust holes ranges from 12 microns to 18 microns, and a Petition 870250095189, dated 10 / 17 / 2025, page 49 / 108 4 / 26 The width of each of the planarization plurality blocks varies from 12 microns to 18 microns.

[0014] According to the display panel provided by the present application, the cathode layer contacts the chemical attack barrier layer at the first spacing groove.

[0015] According to the display panel provided by the present application, the display panel includes an encapsulation layer arranged on one side of the cathode layer, away from the substrate. In a thickness direction of the display panel, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer arranged in a stacked configuration and extending from the display area to the non-display area.

[0016] the first inorganic encapsulation layer comes into contact with the chemical attack barrier layer in the first spacing groove.

[0017] According to the display panel provided by the present application, in a thickness direction of the display panel, the conductive structure includes a first conductive layer and a second conductive layer arranged in a stacked configuration.

[0018] The display panel further includes a third planarization layer located in the display area and covering part of the first conductive layer and the substrate located in the display area, and part of the second conductive layer in the display area is located on one side of the third planarization layer away from the substrate.

[0019] According to the display panel provided by the present application, in a case where the first planarization layer, the second planarization layer, and the pixel definition layer undergo chemical etching with the same chemical etching liquid, a chemical etching rate of the first layer of Petition 870250095189, dated 10 / 17 / 2025, pp. 50 / 108 5 / 26 planarization is lower than the chemical attack rate of the second planarization layer and the chemical attack rate of the pixel definition layer.

[0020] A display device provided by this application includes the display panel mentioned above. The display panel includes a display area and a non-display area located on at least one side of the display area and further includes: a substrate; a conductive structure located on one side of the substrate and extending from the display area to the non-display area; a first layer of planarization covering the conductive structure and extending from the display area to the non-display area; a second planarization layer located on one side of the first planarization layer, away from the substrate and located in the display area and the non-display area; A pixel definition layer located on one side of the second planarization layer, away from the substrate and located in both the display and non-display areas; and a cathode layer located on one side of the pixel definition layer, away from the substrate.

[0021] The display panel also includes a first spacing slot located in the non-display area, the first spacing slot penetrates through the second planarization layer and the pixel definition layer, and a cathode layer boundary falls into the first spacing slot.

[0022] According to the display device provided by the present application, the display panel further includes a first barrier dam and a second barrier dam located in the non-display area at intervals, the second barrier dam is located on one side of the first barrier dam away from the first spacing slot, Petition 870250095189, dated 10 / 17 / 2025, page 51 / 108 6 / 26 and a second spacing groove is defined between the first barrier dam and the second barrier dam.

[0023] the first barrier includes the second planarization layer and the pixel definition layer, and the second barrier includes the pixel definition layer and does not include the second planarization layer.

[0024] According to the display device provided by the present application, the display panel further includes a chemical attack barrier layer located on the side of the first planarization layer, away from the substrate and located in the non-display area, and an orthographic projection of the chemical attack barrier layer onto the substrate covers at least one orthographic projection of the first spacing groove on the substrate.

[0025] According to the display device provided by the present application, an orthographic projection of a boundary of the chemical attack barrier layer away from the display area on the substrate is within an orthographic projection of the second barrier on the substrate.

[0026] According to the display device provided by this application, the chemical attack barrier layer is made of metal.

[0027] According to the display device provided by this application, the chemical attack barrier layer is provided with a plurality of exhaust holes in the first spacing groove, and the first planarization layer is exposed by the plurality of exhaust holes.

[0028] According to the display device provided by the present application, a plurality of planarization blocks corresponding to the plurality of exhaust holes are arranged in the first spacing slot and are arranged in the same layer as the second planarization layer, and a projection Petition 870250095189, dated 10 / 17 / 2025, p. 52 / 108 7 / 26 The orthographic projection of each of the plurality of planarization blocks in the substrate covers an orthographic projection of a corresponding plurality of exhaust holes in the substrate.

[0029] According to the display device provided by the present application, in a thickness direction of the display panel, the conductive structure includes a first conductive layer and a second conductive layer arranged in a stacked configuration.

[0030] The display panel further includes a third planarization layer located in the display area and covering part of the first conductive layer and the substrate in the display area, and part of the second conductive layer in the display area is located on one side of the third planarization layer away from the substrate.

[0031] The beneficial effects of the present application are illustrated below. A flexible display device is provided by the present application, a replaceable cover window structure is provided, so that the cover window structure is thinned to the maximum, and the bending performance is improved and other functional layers are thinned. There is a large space in the selection of materials, and expensive materials can be replaced by cheaper film layers. A hardened layer can be manufactured through more process routes. The replaceable cover window structure has strong replaceability, a simple process and low production cost. The embodiments of the present application provide the display panel and the display device. A first planar layer covering the conductive structure extends from the display area to the non-display area.When the cathode layer is manufactured, even if a cathode material falls into the first spacing groove due to the precision of the process, since the first planar layer can protect the cathode material, a short circuit can be avoided after the process. Petition 870250095189, dated 10 / 17 / 2025, page 53 / 108 8 / 26 cathode and the conductive structure are superimposed in the non-display area, which is beneficial for improving the display panel yield. Meanwhile, compared with the previous technique, a passivation layer between the cathode layer and the conductive structure does not need to be fabricated, which is beneficial for saving on the manufacturing process and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To describe the technical solutions of the embodiments of the present application more clearly, the attached drawings used in the description of the embodiments of the present application are briefly presented below. The attached drawings described below illustrate only some exemplary embodiments of the present application, and persons skilled in the art can derive other designs from the drawings without creative effort.

[0033] FIG. 1 is a schematic plan structural view of a display panel according to an embodiment of the present application.

[0034] FIG. 2 is a schematic structural cross-sectional view along an AA in FIG. 1.

[0035] FIG. 3 is another schematic structural view in cross-section along AA in FIG. 1.

[0036] FIG. 4 is a schematic top structural view of an area not shown in FIG. 3. Description of reference numbers: AA, display area; NAA, non-display area; 10, substrate; 11, conductive structure; 111, first conductive layer; 112, second conductive layer; 12, first planarization layer; 13, chemical attack barrier layer; 131, exhaust hole; 14, second planarization layer; 141, planarization block; 15, pixel definition layer; 16, cathode layer; 17, encapsulation layer; 18, third planarization layer; 21, first spacing groove; 22, first barrier dam; 23, second barrier dam; 24, Petition 870250095189, dated 10 / 17 / 2025, pp. 54 / 108 9 / 26 second barrier dam. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of this application will be described clearly and completely below with reference to the accompanying drawings. Apparently, the embodiments described are only a part, but not all, of the embodiments of this application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of this application, without creative effort, will be within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described in this document are used only to illustrate and explain this application, but not to limit this application. In this present application, unless otherwise indicated, the directional words used, such as top and bottom, generally refer to the top and bottom parts of the device in actual use or operating state, specifically the direction of the drawing in the drawings; while inside and outside refer to the outline of the device.

[0038] The specific embodiments of the present application are described in more detail below with reference to the accompanying drawings and embodiments. The following embodiments are used to illustrate the present application, but are not intended to limit the scope of the present application.

[0039] With reference to FIG. 1 and FIG. 2, the present application provides a display panel. The display panel includes a display area AA and a non-display area NAA located on at least one side of the display area AA.

[0040] The display panel also includes a substrate 10, a conductive structure 11, a first planarization layer 12, a second planarization layer 14, a pixel definition layer 15 and a cathode layer 16.

[0041] Conducting structure 11 is located on one side Petition 870250095189, dated 10 / 17 / 2025, page 55 / 108 10 / 26 of substrate 10 and extends from display area AA to non-display area NAA. The first planarization layer 12 covers the conductive structure 11 and extends from display area AA to non-display area NAA. The second planarization layer 14 is located on one side of the first planarization layer 12 away from substrate 10 and is located in both display area AA and non-display area NAA. The pixel definition layer 15 is located on one side of the second planarization layer 14, away from substrate 10 and located in both display area AA and non-display area NAA. The cathode layer 16 is located on one side of the pixel definition layer 15, away from substrate 10.

[0042] In the embodiments of the present application, the display panel further includes a first 21-spacing slot located in the non-display NAA area. The first 21-spacing slot penetrates through the second planarization layer 14 and the pixel definition layer 15. A cathode layer boundary 16 falls into the first 21-spacing slot.

[0043] It can be understood that the first planarization layer 12 covers the conductive structure 11 and extends from the display area AA to the non-display area NAA in the embodiments of the present application. When the cathode layer 16 is fabricated, due to a shadowing effect, even if a cathode material falls into the first spacing groove 21 due to process precision, the first planarization layer 12 can block the cathode material, thus preventing the cathode material from overlapping the conductive structure 11 located in the non-display area NAA, which results in a short circuit, which is beneficial for improving the performance of the display panel. Compared to the previous technique, a passivation layer that also performs a barrier function does not need to be fabricated between the cathode layer 16 and the conductive structure 11, which is beneficial for saving the manufacturing process and reducing cost. Petition 870250095189, dated 10 / 17 / 2025, pp. 56 / 108 11 / 26

[0044] In the present embodiments, the non-display area NAA is located below the display area AA, that is, the non-display area NAA is a lower edge of the display panel.

[0045] Specifically, a substrate material 10 is a flexible material, so that the substrate 10 can be bent to form a curved screen. Optionally, the substrate material 10 can be polyimide (PI). The conductive structure 11 can be a single-layer metallic wiring structure, a double-layer metallic wiring structure, or a multi-layer metallic wiring structure. The conductive structure 11 can be electrically connected with a VDD power signal or a Vinit startup signal.

[0046] Specifically, a first planarization layer material 12 and a second planarization layer material 14 are organic film layers for performing planarization. The first planarization layer 12 and the second planarization layer 14 may be the same or different. Optionally, both the first planarization layer material 12 and the second planarization layer material 14 may include an organic material such as acrylic, PI, or benzocyclobutene (BCB). Specifically, the Pixel Definition Layer 15 may be formed from organic materials such as PI, polyamide, BCB, acrylic resin, or phenolic resin.

[0047] In the embodiments of the present application, the display panel further includes a matrix layer (not shown in the figures) disposed on the substrate 10. The matrix layer includes a plurality of thin-film transistors located in the display area AA. The thin-film transistors include film layers such as a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode. The display area AA is further provided with a light-emitting layer located in a plurality of pixel apertures defined by the pixel definition layer 15 in the area of Petition 870250095189, dated 10 / 17 / 2025, pp. 57 / 108 12 / 26 AA display. The cathode layer 16 covers the pixel definition layer 15 and the light-emitting layer. The light-emitting layer includes a hole injection layer, a hole transport layer, a light-emitting organic material layer, an electron transport layer, and an electron injection layer, which is prior art and not a key point of this present application, and will not be described in detail in this document.

[0048] In the embodiments of the present application, at least one conductive film layer of the conductive structure 11 is in the same layer as a film layer where the source electrode and the drain electrode are located, and the first planarization layer 12 covers the matrix layer. It should be noted that the passivation layer is arranged in the matrix layer in the prior art, and the first planarization layer 12 covers the passivation layer. In contrast, the passivation layer is omitted in the present application, which is beneficial for saving the manufacturing process and reducing cost.

[0049] In the embodiments of this application, continue to refer to FIG. 2, the display panel further includes a first barrier dam 22 and a second barrier dam 23 located in the non-display NAA area at intervals. The second barrier dam 23 is located on one side of the first barrier dam 22, away from the first spacing slot 21. A second spacing slot 24 is defined between the first barrier dam 22 and the second barrier dam 23. The first barrier dam 22 includes the second planarization layer 14 and the pixel definition layer 15, and the second barrier dam 23 includes the pixel definition layer 15 and does not include the second planarization layer 14.

[0050] It can be understood that the first barrier dam 22 and the second barrier dam 23 are formed by opening the first slot with spacing 21 and the second slot with Petition 870250095189, dated 10 / 17 / 2025, pp. 58 / 108 13 / 26 spacing 24. The first barrier dam 22 is located between the first spacing groove 21 and the second spacing groove 24. A height difference is formed between the first barrier dam 22 and the first spacing groove 21, which mainly serves to block the overflow of organic encapsulation materials. The greater the height difference formed between the first barrier dam 22 and the first spacing groove 21, the better the blocking capacity of the first barrier dam 22 against the organic encapsulation materials. The first planarization layer 12 extends from the display area AA to the non-display area NAA, i.e., the non-display area NAA is provided with the first planarization layer 12, and the thickness of the film layers below the first spacing groove 21 increases.That is, compared with the previous technique, the depth of the first spacing groove 21 that can be opened in the present application decreases, and the height difference between the first barrier dam 22 and the first spacing groove 21 decreases, resulting in a deterioration of the barrier capacity of the first barrier dam 22 against the organic encapsulation materials.

[0051] In view of this, in order not to affect the barrier capacity of the first barrier dam 22 against organic encapsulation materials, a stacked structure of the first barrier dam 22 also includes the second planarization layer 14 and the pixel definition layer 15 compared with the previous technique. That is, the height difference formed between the first barrier dam 22 and the first spacing groove 21 in the present application remains unchanged, so that the barrier capacity of the first barrier dam 22 against organic encapsulation materials is not reduced.

[0052] In addition, the height of the first barrier dam Petition 870250095189, dated 10 / 17 / 2025, pp. 59 / 108 The heights of the first barrier dam 22 and the second barrier dam 23 in the prior art are the same. Both the first barrier dam 22 and the second barrier dam 23 include two film layers, which are the second planarization layer 14 and the pixel definition layer 15. Both the first barrier dam 22 and the second barrier dam 23 serve to block the organic encapsulation materials. In contrast, the first barrier dam 22 and the second barrier dam 23 have different heights in the present application, and the height of the first barrier dam 22 is greater than the height of the second barrier dam 23. Specifically, the first barrier dam 22 includes at least two film layers, including the second planarization layer 14 and the pixel definition layer 15, and the second barrier dam 23 does not include the second planarization layer 14.In other words, the height difference between the second barrier dam 23 and the first barrier dam is the height of the second planarization layer 14, at which point the first barrier dam 22 plays the role of blocking the organic encapsulation materials.

[0053] One reason why the height of the second barrier dam 23 is reduced in this present application is that the display panel also includes a touch layer located on the side of the second planarization layer 14, away from the substrate 10. The touch layer can adopt a direct touch-on-cell (DOT) mode. The touch layer includes a plurality of touch wires extending from the display area AA to the non-display area NAA. The plurality of touch wires are metal wires, which are easily broken when climbing slopes, thus affecting the touch performance. Compared to the prior art, the height of the second barrier dam 23 in the embodiments of the present application is reduced, thus preventing the touch wires from being broken when climbing slopes in the second barrier dam 23. It should be noted that the height here is Petition 870250095189, dated 10 / 17 / 2025, pp. 60 / 108 15 / 26 refers to the film thickness of the first barrier dam 22 and the second barrier dam 23 projecting from the first spacing slot 21 in the direction of the display panel thickness.

[0054] It should be noted that the number of barrier dams in the embodiments of the present application is two, but this is only an example, and in other embodiments, the number of barrier dams may be multiple, which is not limited in the present application.

[0055] Furthermore, in one embodiment, continue to refer to FIG. 2, the display panel further includes a chemical attack barrier layer 13 located on the side of the first planarization layer 12, away from the substrate 10 and located in the non-display NAA area. An orthographic projection of the chemical attack barrier layer 13 onto the substrate 10 covers at least one orthographic projection of the first spacing groove 21 on the substrate 10. One reason for this arrangement is that, after the formation of the first planarization layer 12, the organic film layers located above the first planarization layer 12 and located in the non-display NAA area need to be patterned. For example, the second planarization layer 14 and the pixel definition layer 15 are patterned to form the first spacing groove 21 and the second spacing groove 24.The first planarization layer 12, the second planarization layer 14, and the pixel definition layer 15 are generally made of organic materials. If there is no shielding above the first planarization layer 12, a chemical etching liquid to chemically attack the second planarization layer 14 and the pixel definition layer 15 flows easily to a surface of the first planarization layer 12 through the first spacing groove 21 and the second spacing groove 24, so that the first planarization layer 12 undergoes chemical etching and a thickness. Petition 870250095189, dated 10 / 17 / 2025, pp. 61 / 108 16 / 26 of the first planarization layer 12 is reduced or even completely removed by chemical etching. Generally, when the cathode layer 16 is manufactured, the cathode material falls into the first spacing groove 21 due to the precision of the process. If the first planarization layer 12 at the position of the first spacing groove 21 is thinned or chemically etched, and the cathode layer 16 cannot be protected by the first planarization layer 12, a short circuit between the chemical etching barrier layer 13 and the conductive structure 11 may not be avoided.

[0056] In view of this, by disposing of the chemical attack barrier layer 13 on the side of the first planarization layer 12, away from the substrate 10 in the embodiments of the present application, and the orthographic projection of the chemical attack barrier layer 13 on the substrate 10 covers at least one orthographic projection of the first spacing groove 21 on the substrate 10, so that the chemical attack barrier layer 13 can prevent the chemical attacking liquid for chemical attack of the organic film layers above from coming into contact with the first planarization layer 12 through the first spacing groove 21, thus preventing the first planarization layer 12 from being chemically attacked and further reducing the risk of short circuit between the cathode layer 16 and the conductive structure 11.Furthermore, the chemical attack barrier layer 13 is located between the cathode layer 16 and the first planarization layer 12 and has a certain thickness, like the first planarization layer 12, the chemical attack barrier layer 13 can also play the role of shielding the cathode material that falls into the first spacing groove 21, further reducing the risk of short-circuit between the cathode layer 16 and the conductive structure 11.

[0057] Furthermore, the orthographic projection of the chemical attack barrier layer 13 onto the substrate 10 covers a projection Petition 870250095189, dated 10 / 17 / 2025, pp. 62 / 108 17 / 26 orthographic of the first spacing groove 21 and the second spacing groove 24 on the substrate 10, in order to prevent a part of the first planarization layer 12 in the position of the second spacing groove 24 from being thinned or removed by chemical attack.

[0058] In the embodiments of the present application, a chemical attack barrier layer material 13 is a non-organic material. Specifically, the chemical attack barrier layer material 13 is a metallic material. Furthermore, the chemical attack barrier layer material 13 may be the same as the conductive structure material 11. Optionally, the chemical attack barrier layer material 13 includes copper, molybdenum, or an alloy thereof. Additionally, the planarization layer is an organic film layer, which can absorb water in a matrix cleaning process, so that the planarization layer contains a lot of water vapor, and the light-emitting layer and other films in the AA display area may be damaged by the accumulation of water vapor. For example, with reference to FIG. 3 and FIG. 4, the chemical attack barrier layer 13 in the present application is made of metal.If the first planarization layer 12 is shielded by the chemical attack barrier layer 13, especially if the first planarization layer 12 located in the non-display area NAA is protected by the chemical attack barrier layer 13, water vapor may not be released outwards along a longitudinal direction of the display panel, but may simply diffuse laterally into the display area AA within the first planarization layer 12, so that the light-emitting pixels located on an edge of the display area AA absorb water and shrink inwards, thus generating a red edge line. Therefore, in the embodiments of the present application, referring to FIG. 3, FIG. 3 differs from FIG. 2 in that the chemical attack barrier layer 13 is provided with a plurality of holes. Petition 870250095189, dated 10 / 17 / 2025, pp. 63 / 108 18 / 26 exhaust 131 in the first spacing groove 21, and the first planarization layer 14 is exposed by the plurality of exhaust holes 131.

[0059] It can be understood that, by opening holes in the chemical attack barrier layer 13 in the present application, water vapor within the first planarization layer 12 can be released outwards through the exhaust holes 131, so as to prevent the light-emitting layer and other films in the display area AA from being damaged by the accumulation of water vapor, which is beneficial for improving the display effects of the display panel. Furthermore, the exhaust holes 131 can further reduce the overlap area of ​​the cathode layer 16 and the conductive structure 11 in a top view, which is beneficial for further reducing the risk of short-circuit between them.

[0060] Furthermore, as the first planarization layer 12 is partially exposed by the exhaust holes 131, when the organic film layers undergo chemical attack, the chemical attacking liquid can easily enter the surface of the first planarization layer 12 through the exhaust holes 131, so that the first planarization layer 12 is corroded, and the first planarization layer 12 is thinned or chemically attacked, which is not able to prevent the cathode material from contracting the conductive structure 11, resulting in a short circuit between the cathode layer 16 and the conductive structure 11. Therefore, in the embodiments of the present application, a plurality of planarization blocks 141 corresponding to the plurality of exhaust holes 131 are arranged in the first spacing groove 21 and are arranged in the same layer as the second planarization layer 14.An orthographic projection of each of the plurality of planarization blocks 141 on substrate 10 covers an orthographic projection of a corresponding plurality of exhaust holes 131 on substrate 10. Or. Petition 870250095189, dated 10 / 17 / 2025, pp. 64 / 108 19 / 26, that is, each of the plurality of planarization blocks 141 can cover the entire corresponding plurality of exhaust holes 131, so that the exhaust holes 131 can be protected, the surface of the first planarization layer 12 can be prevented from being exposed, and the chemical attack liquid cannot enter the surface of the first planarization layer 12 through the exhaust holes 131 to corrode the first planarization layer 12, thus playing a role in protecting the first planarization layer 12. Furthermore, the planarization blocks 141 in the embodiments of the present application can also play a role in blocking the flow of organic encapsulation materials.

[0061] Furthermore, referring to FIG. 4, the chemical attack barrier layer 13 is further provided with the plurality of exhaust holes 131 in the second spacing groove 24. The second planarization layer 14 is exposed by the plurality of exhaust holes 131 to further release water vapor within the first planarization layer 12. It can be understood that the first barrier dam 22 covers the plurality of exhaust holes 131 opened in the second spacing groove 24 of the planarization block 141, the planarization blocks 141 need not be provided above the exhaust holes 131.

[0062] Specifically, the opening of each of the plurality of exhaust holes 131 varies from 12 microns to 18 microns, and the width of each of the plurality of planarization blocks 141 varies from 12 microns to 18 microns. For example, in the present application, the opening of each of the plurality of exhaust holes 131 is 12x12 microns, and the width of each of the plurality of planarization blocks 41 is 18x18 microns.

[0063] Optionally, the cross-sectional shape of each of the plurality of exhaust holes 131 can be any Petition 870250095189, dated 10 / 17 / 2025, pp. 65 / 108 20 / 26 one of the following: square, rectangular, circular, elliptical, or polygonal, which is not limited in this document. For example, the cross-sectional shape of each of the plurality of exhaust holes 131 in the figure is square. Specifically, the cross-sectional shape of each of the plurality of planarization blocks 141 and the cross-sectional shape of each of the plurality of exhaust holes 131 may be the same or different, provided that each of the plurality of planarization blocks 141 may fill a corresponding plurality of exhaust holes 131 and cover an edge of the exhaust hole 131. Consequently, the cross-sectional shape of each of the plurality of planarization blocks 141 may be any of the following: square, rectangle, circle, ellipse, and polygon. For example, the cross-sectional shape of each of the plurality of planarization blocks 141 in FIG. 3 is square.

[0064] Optionally, the plurality of planarization blocks 141 can be arranged in a plurality of rows and columns, and the planarization blocks 141 located in the same row / column are arranged uniformly, which is beneficial for improving the uniformity of water vapor release within the first planarization layer 12 and ensuring that all water vapor is released. Specifically, planarization blocks 141 located in adjacent rows / columns can be arranged directly or can be interleaved.

[0065] Specifically, planarization blocks 141 are arranged in the same layer as the second planarization layer 14, and planarization blocks 141 are formed in the same process as the first spacing groove 21 and the second spacing groove 24, which is beneficial for reducing the process and reducing the cost.

[0066] In other modes, the planarization blocks 141 can also be arranged in the same layer as the Layer of Petition 870250095189, dated 10 / 17 / 2025, pp. 66 / 108 21 / 26 pixel definition 15. Similarly, the planarization blocks 141 are formed in the same process as the first 21-spacing groove and the second 24-spacing groove, which is beneficial for reducing the process and reducing the cost.

[0067] In one embodiment, in a case where the first planarization layer 12, the second planarization layer 14, and the pixel definition layer 15 undergo chemical etching with the same chemical etching liquid, the chemical etching rate of the first planarization layer 12 is less than the chemical etching rate of the second planarization layer 14 and the chemical etching rate of the pixel definition layer 15. By limiting the chemical etching rate, the degree of chemical etching of the chemical etching solution of the second planarization layer 14 and the pixel definition layer 15 on the first planarization layer 12 can be reduced to further reduce the risk of short-circuiting between the cathode layer 16 and the conductive structure 11.

[0068] In embodiments of the present application, the display panel further includes an encapsulation layer 17 disposed on one side of the cathode layer 16, away from the substrate 10. In the direction of the thickness of the display panel, the encapsulation layer 17 includes a first inorganic encapsulation layer, an organic encapsulation layer (not shown in the figures) and a second inorganic encapsulation layer (not shown in the figures) arranged in a stacked configuration and extending from the display area AA to the non-display area NAA. The first inorganic encapsulation layer contacts the chemical attack barrier layer 13 in the first spacing groove 21 to prevent the first inorganic encapsulation layer from peeling off. It should be noted that the touch layer is located on one side of the encapsulation layer 17, away from the substrate 10.Specifically, the touch layer is located on one side of the second inorganic encapsulation layer, away from the substrate 10. Petition 870250095189, dated 10 / 17 / 2025, pp. 67 / 108 22 / 26

[0069] Optionally, the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by coating. The organic encapsulation layer material is made of fluid material, and the organic encapsulation layer is generally formed by inkjet printing. Therefore, a first 21-gauge spacing is provided in the embodiments of the present application, so that there is a height difference between the organic film layers on both sides of the first 21-gauge spacing and the first 21-gauge spacing, thus preventing the organic encapsulation material from overflowing.

[0070] Specifically, the width of the first 21-spacing groove is greater than 100 microns. Generally, when the 16-cathode layer is manufactured, a shadow is formed by the cathode material in the non-display area NAA due to process precision. That is, the distance between the boundary of the 16-cathode layer located in the non-display area NAA and the display area AA is generally less than 100 microns. Therefore, it is guaranteed that the boundary of the 16-cathode layer falls only within the first 21-spacing groove and does not extend to one side of the first 21-spacing groove away from the display area.

[0071] Furthermore, in embodiments of the present application, an orthographic projection of an edge of the chemical attack barrier layer 13 away from the cathode layer 16 on the substrate 10 covers at least the orthographic projection of the first spacing groove 21 on the substrate 10. One reason for this arrangement is that a chemical etching process is required during the formation of the chemical attack barrier layer 13 and the second planarization layer 14. Since the chemical attack barrier layer 13 is made of metal and the first planarization layer 12 and the second planarization layer 14 are both organic layers, the chemical etching solution used in the chemical etching process of the chemical attack barrier layer 13 is different from the solution Petition 870250095189, dated 10 / 17 / 2025, pp. 68 / 108 The chemical attack solution used in the chemical attack process of the first planarization layer 12 and the second planarization layer 14 is the same type of chemical attack solution. When the second planarization layer 14 undergoes chemical attack, the degree of corrosion of the chemical attack solution on the first planarization layer 12 is greater than the degree of corrosion of the chemical attack on the chemical attack barrier layer 13, so as to prevent the first planarization layer 12 in the first spacing groove 21 from being corroded or slightly corroded, and the first planarization layer 12 in the first spacing groove 21 is prevented from becoming thinner and not playing the role of blocking the cathode layer 16 and the conductive structure 11.Therefore, in the embodiments of the present application, the chemical attack barrier layer 13 is provided with an area as large as possible, at least over the entire first spacing groove 21.

[0072] Furthermore, the orthographic projection of the edge of the chemical attack barrier layer 13 away from the cathode layer 16 on the substrate 10 is within an orthographic projection of the second barrier barrier 23 on the substrate 10. One reason for this arrangement is that the unexposed NAA area includes an effective encapsulation area on one side of the second barrier barrier 23, away from the display area AA. Organic film layers in the effective encapsulation area are grooved to expose inorganic insulating layers below (e.g., several intercalated inorganic insulating layers below the conductive structure 11), so that the first inorganic encapsulation layer of the encapsulation layer 17 is in direct contact with an upper surface of the exposed inorganic insulating layers, a complete inorganic-inorganic encapsulation closed loop is formed to protect the encapsulation layer. Petition 870250095189, dated 10 / 17 / 2025, pp. 69 / 108 24 / 26 organic in the same. Therefore, if the chemical attack barrier layer 13 extends to the effective encapsulation area, the chemical attack barrier layer 13 will easily come into contact with the conductive structure 11 that extends to the outside of the second planarization area. Since the conductive structure 11 and the chemical attack barrier layer 13 are connected with different electrical signals, the conductive structure 11 comes into contact with the chemical attack barrier layer 13, resulting in signal disorder and affecting the yield.

[0073] In embodiments of the present application, the conductive structure 11 includes a VDD signal line for transmitting a high-level voltage signal. The cathode layer 16 contacts the chemical attack barrier layer 13 in the first spacing slot 21 to electrically connect to a low-level power supply signal line (VSS) for transmitting a low-level voltage signal.

[0074] In the embodiments of the present application, the conductive structure 11 may be a double-layer or multi-layer structure to reduce the impedance of the conductive structure 11. For example, in FIG. 2 and FIG. 3, in a thickness direction of the display panel, the conductive structure 11 includes a first conductive layer 111 and a second conductive layer 112 arranged in a stacked configuration. The first conductive layer 111 and the second conductive layer 112 are electrically connected, and the first conductive layer 111 and the source electrode and drain electrode of the thin-film transistor are arranged in the same layer.

[0075] In addition, the display panel further includes a third planarization layer 18 located in the display area AA and covering at least part of one side of the first conductive layer 111 and the substrate 10 located in the display area, and at least part of the second conductive layer 112 located Petition 870250095189, dated 10 / 17 / 2025, pp. 70 / 108 25 / 26 in the display area is located on one side of the third planarization layer 18, away from substrate 10. A portion of the third planarization layer 18 in the non-display NAA area undergoes chemical attack.

[0076] In the embodiments of the present application, the display panel may adopt a fan-out technology in the display area (FIAA), which can effectively reduce the bottom edge of the panel. In FIAA technology, a multi-layer twist connection design is introduced to reduce the twist space for fan-out twists. Specifically, the display area AA includes a normal display area and a fan-out display area, and the fan-out display area is located between the normal display area and the non-display area NAA.

[0077] The embodiment of the present application further provides a display device including a display panel in the embodiments mentioned above. The display device may be a computer, a television, a vehicle-mounted display device, and other display devices with display functions, which are not specifically limited in this present application. The display device provided by the embodiments of the present application has beneficial effects of the display panel provided by the embodiments of the present application. For details, please refer to the specific description of the display panel in the embodiments mentioned above, and this embodiment will not be repeated here.

[0078] The beneficial effects are that: the embodiments of the present application provide the display panel and the display device. A first planar layer covering the conductive structure extends from the display area to the non-display area. When the cathode layer is manufactured, even if the cathode material falls into the first spacing groove due to process precision, since the first planar layer can protect the cathode material, so that the Petition 870250095189, dated 10 / 17 / 2025, pp. 71 / 108 26 / 26 short circuits can be avoided after the cathode comes into contact with the conductive structure in the non-display area, which is beneficial for improving the performance of the display panel. Meanwhile, compared with the previous technique, the passivation layer between the cathode layer and the conductive structure does not need to be manufactured, which is beneficial for saving the manufacturing process and reducing costs.

[0079] In summary, although the present application has been disclosed in the above preferred embodiments, the above preferred embodiments are not intended to limit the present application. Various modifications and alterations may be made by ordinary persons skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this application is subject to the scope defined by the claims. Petition 870250095189, dated 10 / 17 / 2025, pp. 72 / 108

Claims

1 / 4 CLAIMS 1. Display panel, CHARACTERIZED in that it comprises a display area and a non-display area located on one side of the display area, and further comprising: a substrate; a conductive structure located on one side of the substrate and extending from the display area to the non-display area; a first planarization layer covering the conductive structure and extending from the display area to the non-display area; a second planarization layer located on one side of the first planarization layer away from the substrate, wherein the second planarization layer is located in the display area and the non-display area; a pixel definition layer located on one side of the second planarization layer away from the substrate, wherein the pixel definition layer is located in the display area and the non-display area; and a cathode layer located on one side of the pixel definition layer, away from the substrate;wherein the display panel further comprises a first spacing slot located in the non-display area, the first spacing slot penetrates through the second planarization layer and the pixel definition layer, and a cathode layer boundary falls into the first spacing slot.

2. Display panel, according to claim 1, CHARACTERIZED in that the display panel further comprises a first barrier dam and a second barrier dam located in the non-display area at intervals, the second barrier dam being located on one side of the first barrier dam away from the first spacing slot, and a second spacing slot being provided between the first barrier dam and the second barrier dam; and wherein the first barrier comprises the second planarization layer and the pixel definition layer, and the second barrier comprises the pixel definition layer and does not comprise the second planarization layer.

3. Display panel, according to claim 2, CHARACTERIZED in that the display panel further comprises a chemical attack barrier layer, the chemical attack barrier layer being located on the side of the first planarization layer, away from the substrate and located in the non-display area, and an orthographic projection of the chemical attack barrier layer onto the substrate covering at least one orthographic projection of the first spacing groove on the substrate.

4. Display panel, according to claim 3, CHARACTERIZED in that an orthographic projection of a boundary of the chemical attack barrier layer away from the display area on the substrate is within an orthographic projection of the second barrier on the substrate.

5. Display panel, according to claim 3 or 4, CHARACTERIZED in that the chemical attack barrier layer is made of metal.

6. Display panel, according to claim 5, CHARACTERIZED in that the chemical attack barrier layer is provided with a plurality of exhaust holes in the first spacing groove, and the first planar layer is exposed by the plurality of exhaust holes.

7. Display panel, according to claim 6, CHARACTERIZED in that a plurality of planarization blocks corresponding to a plurality of exhaust holes are arranged in the first spacing groove, the plurality of planarization blocks are arranged in the same layer as the second planarization layer, and an orthographic projection of each of the plurality of planarization blocks Petition 870250095189, dated 10 / 17 / 2025, page 74 / 108 3 / 4 on the substrate covers an orthographic projection of a corresponding plurality of exhaust holes on the substrate; preferably, wherein an aperture of each of the plurality of exhaust holes varies from 12 microns to 18 microns, and a width of each of the plurality of planarization blocks varies from 12 microns to 18 microns.

8. Display panel, according to any one of claims 3 to 7, CHARACTERIZED in that the cathode layer contacts the chemical attack barrier layer in the first spacing groove; and / or in that the display panel further comprises an encapsulation layer disposed on one side of the cathode layer, away from the substrate, and in a thickness direction of the display panel, the encapsulation layer comprising a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer arranged in a stacked configuration and extending from the display area to the non-display area; and in that the first inorganic encapsulation layer contacts the chemical attack barrier layer in the first spacing groove.

9. Display panel, according to any one of claims 1 to 8, CHARACTERIZED in that in one direction of thickness of the display panel, the conductive structure comprises a first conductive layer and a second conductive layer arranged in a stacked configuration; and wherein the display panel further comprises a third planar layer located in the display area, the third planar layer covering at least part of the first conductive layer and the substrate located in the display area, and at least part of the second conductive layer in the display area is located on one side of the third planar layer away from the substrate; and / or wherein, in a case where the first planar layer, Petition 870250095189, dated 10 / 17 / 2025, p.75 / 108 4 / 4 the second planarization layer and the pixel definition layer undergo chemical etching with the same chemical etching liquid, the chemical etching rate of the first planarization layer is lower than the chemical etching rate of the second planarization layer and the chemical etching rate of the pixel definition layer.

10. Display device, CHARACTERIZED in that it comprises the display panel as defined in any one of claims 1 to 9. Petition 870250095189, dated 10 / 17 / 2025, pp. 76 / 108

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