High power radio frequency (RF) amplifiers

Abstract

A power amplifier (10) having: a plurality of N amplifier modules, where N is an integer greater than one; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; a plurality of M delay lines, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the power amplifier.

Description

HIGH POWER RADIO FREQUENCY (RF) AMPLIFIERS TECHNICAL FIELD

[0001] This disclosure relates generally to high power radio frequency (RF) amplifiers and more particularly, to high power RF amplifiers having a plurality of amplifier modules coupled to a common input. BACKGROUND OF THE INVENTION

[0002] As is known in the art, many high power radio frequency (RF) amplifiers include a plurality of amplifier modules coupled to a common input through a power splitter; each one of the amplifier modules producing a corresponding one of a plurality of outputs. One such power amplifier is shown in FIG. 1, here in this example, having sixteen amplifier modules 1-16 producing outputs at a corresponding one of 16 outputs 1-16, as shown. The power RF amplifier includes a one to sixteen power splitter for dividing power of an RF signal at the input equally among the sixteen amplifier modules. Each one of the amplifier modules includes an adjustable phase shifter coupled between an output of a corresponding one of the power splitter and the input to such one of the amplifier modules, as shown. Since each one of the amplifier modules typically, when fabricated, will have a different phase shift through it, the phase shifters are adjusted during manufacture of the RF power amplifier so that the output signal from all of the sixteen amplifier modules are all in- phase with one another. That is, the signals at the outputs <com:Math><semantics>1−16<annotation encoding="application / x-tex">1 - 16< / annotation>< / semantics>< / com:Math> are all in-phase. However, tuning each one of the plurality of phase shifters is time consuming. SUMMARY OF THE INVENTION

[0003] In accordance with the present disclosure, a power amplifier is provided having a plurality of N amplifiers, where N is an integer greater than one; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N amplifiers; and, a plurality of M delay lines, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the plurality of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the power amplifier.

[0004] In one embodiment, the M:N power splitter and the M delay lines are disposed on a common printed circuit board.

[0005] In one embodiment, the amplifier includes a 1:M power splitter having M outputs, each one of the M outputs being coupled to an input of a corresponding one of the M delay lines.

[0006] In one embodiment, the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the amplifiers, each one of the N / M amplifiers in a corresponding one of the M amplifier module sections having a phase shift <com:Math><semantics>(Δ1+ / −δ)<annotation encoding="application / x-tex">(\Delta_1 + / - \delta)< / annotation>< / semantics>< / com:Math> degrees through <com:Math><semantics>(ΔM+ / −δ)<annotation encoding="application / x-tex">(\Delta_M + / - \delta)< / annotation>< / semantics>< / com:Math> degrees, respectively, and where each one of the M delay lines has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively.

[0007] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a schematic diagram of a high power RF power amplifier according to the PRIOR ART;

[0008] FIG. 2 is a is a schematic diagram of a high power RF power amplifier according to the disclosure; and

[0009] FIGS. 3A-3E are plan views of an upper surface of a printed circuit board having a 1:M power splitter, M:N power splitter, M delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>4< / com:Sub>, and resistors for use with the high RF power amplifier of FIG. 2 at various stages in the fabrications thereof.

[0010] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0011] Referring now to FIG. 2, a high power RF amplifier 10 is shown having; a plurality of N amplifiers 12<com:Sub>1-< / com:Sub>12<com:Sub>N< / com:Sub>, where N is an integer greater than one, here in this example N is sixteen; an M:N power splitter 14 having M inputs 14<com:Sub>1< / com:Sub>-14<com:Sub>M< / com:Sub>, where M is an integer less than N, here in this example, M is four, and N outputs 16<com:Sub>1< / com:Sub>-16<com:Sub>M< / com:Sub>, each one of the N outputs 16<com:Sub>1< / com:Sub>-16<com:Sub>M< / com:Sub> being coupled to an input 14<com:Sub>1< / com:Sub>-14<com:Sub>M< / com:Sub> of a corresponding one of the plurality of N amplifiers 12<com:Sub>1< / com:Sub>-12<com:Sub>N< / com:Sub>; and, a plurality of M delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>M< / com:Sub>, each one the M delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>M< / com:Sub> having an output T2, T4, T6, and T8, respectively, coupled to a corresponding one of the M inputs 14<com:Sub>1< / com:Sub>-14<com:Sub>M< / com:Sub> of the plurality of the M:N power splitter 14, each one of the plurality of M delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>M< / com:Sub> having an input T1, T3, T5 and T7, respectively, being coupled to a common input 20 of the power amplifier 10; here though a 1:N power splitter 22. It is noted that the 1:N power splitter and the M:N power splitter 14 are of conventional design and include conventional matched termination resistors R, here 50 ohms; the microwave transmission lines used to form the power splitters 14 and 22 as well as the and the delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>M< / com:Sub> here being in this example, 50 ohm microstrip transmission lines. Thus, there are, in this example, sixteen channels from the input 20 to a corresponding one of the sixteen outputs OUTPUT 1-OUTPUT 16.

[0012] Here, in this example, a plurality of amplifiers is fabricated and the phase shift through each one at the nominal operating frequently is measured and recorded. A predetermined tolerance <com:Math><semantics>±<annotation encoding="application / x-tex">\pm< / annotation>< / semantics>< / com:Math> from a predetermined phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> is selected for each one of the M amplifier module sections <com:Math><semantics>241<annotation encoding="application / x-tex">24_{1}< / annotation>< / semantics>< / com:Math>-<com:Math><semantics>24M<annotation encoding="application / x-tex">24_{M}< / annotation>< / semantics>< / com:Math>. Here for example, the predetermined tolerance <com:Math><semantics>δ<annotation encoding="application / x-tex">\delta< / annotation>< / semantics>< / com:Math> is selected as five degrees and the predetermined phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> are in this example selected as: <com:Math><semantics>Δ1=20<annotation encoding="application / x-tex">\Delta_1 = 20< / annotation>< / semantics>< / com:Math> degrees, <com:Math><semantics>Δ1+10<annotation encoding="application / x-tex">\Delta_1 + 10< / annotation>< / semantics>< / com:Math> =30 degrees, <com:Math><semantics>Δ1+20=40<annotation encoding="application / x-tex">\Delta_1 + 20 = 40< / annotation>< / semantics>< / com:Math> degrees and <com:Math><semantics>Δ1+30=50<annotation encoding="application / x-tex">\Delta_1 + 30 = 50< / annotation>< / semantics>< / com:Math> degrees, for the M amplifier module sections 24<com:Sub>1< / com:Sub>- 24<com:Sub>M< / com:Sub> respectively.

[0013] In this example, sixteen of the fabricated amplifiers are selected having the following phase shifts, in degrees: 16, 17, 22, 24, 26, 31, 34, 35, 36, 37, 42, 44, 48, 49, 52 and 53.

[0014] The selected amplifiers are arranged in the M amplifier module sections 24<com:Sub>1< / com:Sub>-24<com:Sub>M< / com:Sub> as follows: [Image disponible dans le document PDF, Image available in the PDF document]

[0015] It is noted that the N amplifiers 12<com:Sub>1< / com:Sub>-12<com:Sub>16< / com:Sub> are arranged in M amplifier module sections 24<com:Sub>1< / com:Sub>- 24<com:Sub>M< / com:Sub>, each one of the M amplifier module sections 24<com:Sub>1< / com:Sub>-24<com:Sub>M< / com:Sub> having N / M (here 4) of the amplifiers 12<com:Sub>1< / com:Sub>-12<com:Sub>N< / com:Sub>, each one of the N / M amplifiers 12<com:Sub>1< / com:Sub>-12<com:Sub>N< / com:Sub> in a corresponding one of the M amplifier module sections <com:Math><semantics>241<annotation encoding="application / x-tex">24_1< / annotation>< / semantics>< / com:Math>-<com:Math><semantics>24M<annotation encoding="application / x-tex">24_M< / annotation>< / semantics>< / com:Math> having a phase shift (<com:Math><semantics>Δ1+ / −δ<annotation encoding="application / x-tex">\Delta_1 + / -\delta< / annotation>< / semantics>< / com:Math>) degrees through (<com:Math><semantics>ΔM+ / −δ<annotation encoding="application / x-tex">\Delta_M + / -\delta< / annotation>< / semantics>< / com:Math>) degrees, respectively, and where each one of the M delay lines <com:Math><semantics>181<annotation encoding="application / x-tex">18_1< / annotation>< / semantics>< / com:Math>-<com:Math><semantics>18M<annotation encoding="application / x-tex">18_M< / annotation>< / semantics>< / com:Math> has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively.

[0016] It should be noted that the 1:M power splitter 22 and M:N power splitter 14 and the M delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>4< / com:Sub> are disposed on a common printed circuit board 30 as microstrip microwave transmission lines and also formed on the printed circuit board 30 are the resistors R.

[0017] Referring now to FIGS. 3A-3E plan views of various stages in the fabrications of the printed circuit 30 portion of the high RF power amplifier 10 are shown. Thus, shows the 1:M power splitter 22, M:N power splitter 14 and the resistors R. Here the 1:M power splitter 22 and the M:N power splitter 14 are microstrip transmission lines formed by strip conductors 31 formed on the upper surface 33 of a dielectric board 35 and a ground plane conductor, not shown, formed on the bottom surface of the dielectric board 35. One end of the resistors R is connected to the strip conductors 31, as shown, and the other end of the resistors is connected to the ground plane conductor (not shown) through conductive vias VIA, as indicated.

[0018] After forming the printed circuit board 30 as in FIG. 3A, the delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>4< / com:Sub> are formed as microstrip transmission lines; the ground plane being provided by the ground plane (not shown) formed on the back of the dielectric board 35. The strip conductor of the microstrip transmission line for the first delay line 18<com:Sub>1< / com:Sub> is printed using additive manufacturing or 3D printing as shown in FIG 3B.

[0019] Next, the strip conductor of the microstrip transmission line for the second delay line 18<com:Sub>2< / com:Sub> is printed using additive manufacturing or 3D printing as shown in FIG 3C.

[0020] Next the strip conductor of the microstrip transmission line for the third delay line 18<com:Sub>3< / com:Sub> is printed using additive manufacturing or 3D printing as shown in FIG 3D.

[0021] Finally, the strip conductor of the microstrip transmission line for the fourth delay line 184 is printed using additive manufacturing or 3D printing as shown in FIG 3D.

[0022] It should be understood that while in the example above the strip conductors of the microstrip transmission line for delay lines 18<com:Sub>1< / com:Sub>-18<com:Sub>4< / com:Sub> have been printed sequentially, they may be printed concurrently using for example a raster type motion for the 3D printing head.

[0023] It should now be appreciated, a power amplifier according to the disclosure includes: a plurality of N amplifier modules, where N is an integer greater than one; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; and a plurality of M delay lines, each one the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the power amplifier. The power amplifier may include one or more of the following features, individually or in combination, to include: wherein the M;N power splitter and the M delay lines are disposed on a common printed circuit board; a 1:M power splitter having M output each one of the M outputs being coupled to an input of a corresponding one of the M delay lines; wherein the M;N power splitter, the M delay lines, and the 1:M power splitter are disposed on a common printed circuit board; wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the amplifiers, each one of the N / M amplifiers in a corresponding one of the M amplifier module sections having a phase shift <com:Math><semantics>(Δ1+ / −δ)<annotation encoding="application / x-tex">(\Delta_1 + / - \delta)< / annotation>< / semantics>< / com:Math> degrees through <com:Math><semantics>(ΔM+ / −δ)<annotation encoding="application / x-tex">(\Delta_M + / - \delta)< / annotation>< / semantics>< / com:Math> degrees, respectively, and where each one of the M delay lines has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively; wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the amplifiers, each one of the N / M amplifiers in a corresponding one of the M amplifier module sections having a phase shift <com:Math><semantics>(Δ1+ / −δ)<annotation encoding="application / x-tex">(\Delta_1 + / - \delta)< / annotation>< / semantics>< / com:Math> degrees through <com:Math><semantics>(ΔM+ / −δ)<annotation encoding="application / x-tex">(\Delta_M + / - \delta)< / annotation>< / semantics>< / com:Math> degrees, respectively, and where each one of the M delay lines has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively; wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the amplifiers, each one of the N / M amplifiers in a corresponding one of the M amplifier module sections having a phase shift <com:Math><semantics>(Δ1+ / −δ)<annotation encoding="application / x-tex">(\Delta_1 + / - \delta)< / annotation>< / semantics>< / com:Math> degrees through <com:Math><semantics>(ΔM+ / −δ)<annotation encoding="application / x-tex">(\Delta_M + / - \delta)< / annotation>< / semantics>< / com:Math> degrees, respectively, and where each one of the M delay lines has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively; and wherein the N amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the amplifiers, each one of the N / M amplifiers in a corresponding one of the M amplifier module sections having a phase shift <com:Math><semantics>(Δ1+ / −δ)<annotation encoding="application / x-tex">(\Delta_1 + / -\delta)< / annotation>< / semantics>< / com:Math> degrees through <com:Math><semantics>(ΔM+ / −δ)<annotation encoding="application / x-tex">(\Delta_M + / -\delta)< / annotation>< / semantics>< / com:Math> degrees, respectively, and where each one of the M delay lines has a phase shift <com:Math><semantics>Δ1<annotation encoding="application / x-tex">\Delta_1< / annotation>< / semantics>< / com:Math> through <com:Math><semantics>ΔM<annotation encoding="application / x-tex">\Delta_M< / annotation>< / semantics>< / com:Math> respectively.

[0024] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A high power Radio-Frequency (RF) amplifier circuit comprising: a plurality of N power amplifiers, where N is an integer greater than one, each one of the power amplifiers having a predetermined phase shift; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; and a plurality of M delay lines, each one of the M delay lines having a predetermined phase shift selected from minus 20 degrees to minus 50 degrees, each one of the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the high power RF amplifier circuit, wherein a combination of the predetermined phase shift of each power amplifier combined with the predetermined phase shift of each one of the M delay lines provides a desired phase shift at an output for each one of the power amplifiers.

2. The high power RF amplifier circuit recited in claim 1 wherein N is equal to 16 and M is equal to 4.

3. The high power RF amplifier circuit recited in claim 1 wherein the M:N power splitter and the M delay lines are disposed on a common printed circuit board.

4. The high power RF amplifier circuit recited in claim 1 including a 1:M power splitter having M outputs, each one of the M outputs being coupled to an input of a corresponding one of the M delay lines.

5. The high power RF amplifier circuit recited in claim 4 wherein the M:N power splitter, the M delay lines, and the 1:M power splitter are disposed on a common printed circuit board.

6. The high power RF amplifier circuit recited in claim 1 wherein the N power amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the power amplifiers, each one of the N / M power amplifiers in a corresponding one of the M amplifier module sections having a phase shift ( Δ 1 + / − δ ) (\Delta_1 + / - \delta) degrees through ( Δ M + / − δ ) (\Delta_M + / - \delta) degrees, respectively, and wherein each one of the M delay lines has a phase shift Δ 1 \Delta_1 through Δ M \Delta_M , respectively.

7. The high power RF amplifier circuit recited in claim 6 wherein Δ 1 \Delta_1 is equal to minus 20 degrees, Δ 2 \Delta_2 is equal to minus 30 degrees, Δ 3 \Delta_3 is equal to minus 40 degrees, and Δ M \Delta_M is equal to minus 50 degrees.

8. The high power RF amplifier circuit recited in any one of claims 3 to 5 wherein the N power amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the power amplifiers, each one of the N / M power amplifiers in a corresponding one of the M amplifier module sections having a phase shift ( Δ 1 + / − δ ) (\Delta_1 + / - \delta) degrees through ( Δ M + / − δ ) (\Delta_M + / - \delta) degrees, respectively, and wherein each one of the M delay lines has a phase shift Δ 1 \Delta_1 through Δ M \Delta_M , respectively.

9. A high power Radio-Frequency (RF) amplifier circuit comprising: a plurality of N power amplifiers, where N is an integer greater than one, each one of the power amplifiers having a predetermined phase shift, wherein the N power amplifiers are arranged in M amplifier module sections, each one of the M amplifier module sections having N / M of the power amplifiers, each one of the N / M power amplifiers in a corresponding one of the M amplifier module sections having a phase shift ( Δ 1 + / − δ ) (\Delta_1 + / - \delta) degrees through ( Δ M + / − δ ) (\Delta_M + / - \delta) degrees, respectively; an M:N power splitter having M inputs, where M is an integer less than N, and N outputs, each one of the N outputs being coupled to an input of a corresponding one of the plurality of N power amplifiers; and a plurality of M delay lines, wherein each one of the M delay lines has a phase shift Δ 1 \Delta_1 through Δ M \Delta_{M} , respectively, selected from minus 20 degrees to minus 50 degrees, each one of the M delay lines having an output coupled to a corresponding one of the M inputs of the M:N power splitter, each one of the plurality of M delay lines being coupled to a common input of the high power RF amplifier circuit, wherein a combination of the predetermined phase shift of each power amplifier combined with the predetermined phase shift of each one of the M delay lines provides a desired phase shift at an output for each one of the power amplifiers.