Diode-less electrostatic discharge protection circuit

Abstract

An integrated circuit (IC) and a system for providing electrostatic discharge (ESD) protection is disclosed comprising a circuit (e.g., an ESD protection circuit) electrically connected to a circuit board. The circuit may comprise: a functional component; a gate pad connected to the functional component; and a FET pair connected to the gate pad and forming a low impedance discharge path from the gate pad to ground to protect the functional component against an ESD event. An ESD protection method is disclosed comprising: manufacturing a wafer comprising multiple circuits; dicing the wafer to form a IC; packaging the IC to form a chip; attaching the chip to a printed circuit board; and applying, from the printed circuit board, a DC voltage, exceeding a fusing voltage threshold level, to a gate pad of the IC to blow the fuse to disconnect the ESD protection circuit from the gate pad.

Description

DIODE-LESS ELECTROSTATIC DISCHARGE PROTECTION CIRCUITTechnical Field

[0001] The disclosure relates generally to the field of circuits, and more particularly to systems and methods for protecting circuits from electrostatic discharge (ESD) damage during manufacturing and / or testing processes.Background

[0002] Electrostatic discharge (ESD) can damage circuits. In particular, during the process of manufacturing and / or testing a circuit, ESD can cause damage to one or more components of the circuit. Common ESD protection solutions include protecting the circuit with a diode or diode stack. But it would be desirable to have an ESD protection solution that does not require a diode.Summary

[0003] An integrated circuit (IC) is disclosed. The IC may comprise: a gate pad connected to functional components of the IC; and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may comprise: a first FET having a first drain connected to the gate pad and a first source connected to a ground; a second FET having a second drain connected to the ground and a second source connected to the gate pad, the first FET and the second FET forming a FET pair, wherein the FET pair is configured to provide a low impedance discharge path from the gate pad to the ground to protect the functional components against an electrostatic discharge event.

[0004] A system for providing electrostatic discharge (ESD) protection is disclosed. The system may comprise: a circuit board; and a circuit electrically connected to the circuit board. The circuit may comprise: a functional component; a gate pad connected to the functional component; and a FET pair connected to the gate pad and forming a low impedance discharge path from the gate pad to ground to protect the functional component against an ESD event.

[0005] An electrostatic discharge (ESD) protection method, for protecting an integrated circuit (IC) from ESD events through a portion of a manufacturing process, is disclosed. The method may comprise: manufacturing a wafer comprising multiple circuits, wherein each circuit of the multiple circuits comprises: a functional component; a gate pad connected to the functional component; and an ESD protection circuit electricallyconnected to the gate pad. The ESD protection circuit may comprise: a FET pair forming a low impedance discharge path between the gate pad and ground for protecting the IC from an ESD event; and a fuse. The method may further comprise: dicing the wafer to form an IC; packaging the IC to form a chip; attaching the chip to a printed circuit board; and applying, from the printed circuit board, a DC voltage, exceeding a fusing voltage threshold level, to the gate pad of the IC to blow the fuse to disconnect the ESD protection circuit from the gate pad.Brief Description of the Drawings

[0006] The foregoing and other features of the present invention will become apparent to those skilled in the art to which the present invention relates upon reading the following description with reference to the accompanying drawings, in which:

[0007] FIG. 1 illustrates a diode-less integrated circuit IC with an example ESD protection circuit thereon, in accordance with example embodiments;

[0008] FIGS. 2A and 2B illustrate an IC with a more detailed example ESD protection circuit thereon, in accordance with example embodiments;

[0009] FIG. 3 illustrates a system comprising a circuit board and a circuit having an example ESD protection circuit thereon, in accordance with example embodiments; and

[0010] FIG. 4 illustrates a method for protecting a IC from ESD events through a portion of a manufacturing process, in accordance with example embodiments.Detailed Description

[0011] While exemplary embodiments are described herein in sufficient detail to enable those skilled in the art to practice the invention, it should be understood that other embodiments may be realized and that logical electrical and mechanical changes may be made without departing from the spirit and scope of the invention. Thus, the following detailed description is presented for purposes of illustration only.

[0012] With reference to FIG. 1 , an integrated circuit (IC) 100 comprises: a gate pad 120 connected to functional components 110 of the IC; and an electrostatic discharge (ESD) protection circuit 130. In an example embodiment, the IC is a diode-less IC. In an example embodiment, the ESD protection circuit 130 comprises a field effect transistor (FET) pair connected between the gate pad 120 and ground 131 for protecting the functional components 1 10 against an electrostatic discharge event. In particular, theESD protection circuit 130 may be configured to protect the functional components 1 10 against an ESD event. The ESD event may be caused by or originate from: any component on the integrated circuit 100, or from external sources via, for example the gate pad 120 or an RF input pad. In on example embodiment, the gate pad 120 may be electrically connected (e.g., via wire-bond) to an RF input on a circuit board. However, the disclosure is not so limited to such ESD events / causes.

[0013] In an example embodiment, the functional components 110 may comprise active and / or passive components, circuits, transistors, field effect transistors, and / or the like, that operate at any suitable frequencies. These functional components 1 10 may be configured to perform functions such as mixing, power amplification, low-noise amplification, high-frequency switching, and so forth. The IC 100 may be used in applications ranging from phased arrays to mobile phones and home satellite receivers, or any other suitable application. The IC 100 may be fabricated using Gallium Arsenide (GaAs), Silicon Germanium (SiGe), Indium Phosphide (InP), Gallium Nitride (GaN) or other suitable integrated circuit materials.

[0014] With reference now to FIGS. 2A and 2B, in an example embodiment, the integrated circuit 200 comprises a gate pad 220, functional components 210, and an ESD protection circuit 230. In an example embodiment, the ESD protection circuit 230 comprises: a first FET 231 having a first drain connected to the gate pad 220 and a first source connected to a ground 251 ; and a second FET 232 having a second drain connected to the ground 251 and a second source connected to the gate pad 220. In an example embodiment, the first FET 231 and the second FET 232 form a FET pair 238, wherein the FET pair 238 is configured to provide a low impedance discharge path from the gate pad 220 to the ground 251 to protect the functional components 210 against an ESD event regardless of whether the ESD event has a positive or negative voltage.

[0015] In accordance with various embodiments, the first FET 231 is configured to provide a low impedance discharge path to ground 251 for a positive voltage electrostatic discharge event, and the second FET 232 is configured to provide a low impedance discharge path to ground 251 for a negative voltage electrostatic discharge event. Specifically, the first FET 231 and the second FET 232 may pull the gate pad 220 towards 0 V via the ground 251 , thereby providing the ESD protection.

[0016] In accordance with a further example embodiment, the IC 100 may further comprise a fuse 240 connected between the gate pad 220 and the FET pair 238, for permanently disconnecting the FET pair 238 from the gate pad 220. It is noted thatbecause the FET pair 238 provides a low impedance discharge path for ESD threats, it also could prevent application of proper bias voltage for normal operation of the IC. Thus, the fuse 240 may be configured to disconnect the FET pair 238 from the gate pad 220 at the appropriate time. For example, it may be appropriate to disconnect the FET pair 238 and stop providing ESD protection after manufacturing steps are complete, after a portion of manufacturing steps are complete, after certain testing is complete, and / or the like.

[0017] Thus, in an example embodiment, the FET pair 238 may be disconnected after testing is complete and before normal operation of the IC. In another example embodiment, the fuse 240 may be fused open after the IC goes through the automated manufacturing process steps that typically are associated with more severe ESD threats, but opened before package testing or circuit board testing. In this manner, the functional components 210 of the IC are protected during manufacture / manufacturing. In this regard, the fuse may be configured to be strong enough to withstand the ESD threats, but to fuse open with DC voltage at the desired time, allowing package testing or board testing. In an example embodiment, the fuse is a 20 ohm resistor or 40 ohm resistor with a 7.5mA max DC rating, though any suitable resistor may be used to fuse out the ESD protection circuit.

[0018] In this example embodiment, the fuse 240 may be blown by applying a negative DC voltage to the gate pad 220 (or to whatever pad this ESD protection circuit is connected to), thus activating the ESD protection circuit to draw a sufficient DC current (from a fusing source) to blow the fuse, disconnecting the FET pair 238 from the gate pad 220. In an example embodiment, the first FET 231 and the second FET 232 are each a depletion mode FET. Moreover any suitable FETs may be used.

[0019] With reference now to FIG. 2B, in an example embodiment, the IC further comprises a disable pad 270. The ESD protection circuit 130 / 230 further comprises a first resistor R1 connected between the first source and a first gate of the first FET 231 . The ESD protection circuit 130 / 230 may further comprise a second resistor connected between the second source and a second gate of the second FET 232. In an example embodiment, the disable pad 270 is connected to a first gate of the first FET 231 , a first resistor (R1 ), a second gate of the second FET 232, and a second resistor (R2).

[0020] The disable pad 270 may be configured to temporarily disable the FET pair. In this example embodiment, the disable pad 270 may be configured to provide a bias voltage to the gates of the FET pair to temporarily disable the FET pair. The first resistor R1 may be configured for biasing the first FET 231 sufficient to disable the low impedancedischarge path to ground through the first FET 231 . The second resistor R2 may be configured for biasing the second FET 232 sufficient to disable the low impedance discharge path to ground 251 through the second FET 232. In general, R1 and R2 may be sized to achieve disabling of the FETS with an appropriate disable voltage applied to the disable pad, and yet to facilitate ESD protection when a disable voltage is not applied to the disable pad. In this manner, the disable pad 270 can be used to temporarily disable the ESD protection. In an example embodiment, this may be done to permit testing during manufacturing without interference from the ESD protection circuit 130. The FET pair can be disabled and enabled selectively by varying the bias voltage provided to the disable pad 270. Moreover, any suitable resistor network or other method of biasing the FET pair to selectively disable and enable the FET pair may be used.

[0021] Although shown here as a single disable pad, separate disable pads may be used for each FET.

[0022] In some example embodiments, not shown here, no fuse 240 is provided on IC 100, and the disable pad 270 may be used both during manufacture and during normal operation to disable the FET pair. This later option provides flexibility by never permanently fusing out the ESD protection circuit, but it also may increase reliance on the disable pad throughout the life of the IC. It is noted that the phase of particular risk of ESD damaging the IC is during certain automated manufacture processes, and that thereafter the ESD protection circuit 130 can be electrically isolated from the functional components.

[0023] In this manner, in an example embodiment the electrostatic discharge protection circuit provides diode-less ESD event protection. Stated another way, in an example embodiment the ESD protection circuit comprises no diodes. This is particularly important because some IC fabrication processes do not support use of diodes or diode stacks. Moreover, in an example embodiment, the ESD protection circuit does not comprise a resistor network to ground for discharging the ESD threat because such would result in the loss of too much power.

[0024] With reference now to FIG. 3, in accordance with an example embodiment, a system 301 is disclosed with ESD protection for the functional components 310. The system may comprise a circuit board 302 and a circuit 300 electrically connected to the circuit board 302. In this example embodiment, the circuit 300 may comprise an IC or the like. In an example embodiment, the circuit 300 may further comprise: a functional component 310, a gate pad 320 connected to the functional component 310, and a FETpair 330 connected to the gate pad and forming a low impedance discharge path from the gate pad to the ground 331 to protect the functional components against an ESD event.

[0025] In this embodiment, the low impedance discharge path is configured to discharge from the gate pad 320 if a charge begins to build up at the gate pad 320. This effectively provides a way to discharge all circuits connected to the gate pad 320, and therefor protects against an ESD event.

[0026] In an example embodiment, the circuit 300 further comprises a fuse 340. The fuse 340 is configured such that it will not fuse out when protecting against an ESD event, but is configured such that it can be selectively fused out when the ESD protection is no longer needed, such as when manufacturing is complete, when the circuit has been tested, or when the circuit is ready for normal operation. To disconnect the FET pair 330, a negative voltage is applied to the gate pad 320 to cause a current to flow through fuse 340 to ground, fusing out the fuse 340 and disconnecting the FET pair 330 from the gate pad 320. The negative voltage can be applied to the gate pad 320 from a corresponding bond pad on circuit board 302 (as illustrated in FIG. 3), via a probe placed in contact with gate pad 320 (not shown), or via any other suitable connection. The voltage level that is sufficient to cause the fuse to blow is described herein as the fusing voltage threshold level. This may be a negative voltage level in various example embodiments.

[0027] In an example embodiment, the circuit further comprises a disable pad 370. In an example embodiment, the circuit board 302 is configured to apply a DC voltage to the disable pad 370. The voltage level that is sufficient to cause the FET pair 330 to be disabled is described herein as the disable voltage threshold level. In an example embodiment, a DC voltage may be applied that exceeds a disabling voltage threshold level (e.g. -8V, though any suitable disabling voltage threshold level may be used). The disable pad 370 may be connected to the FET pair 330 and configured to apply the DC voltage to disable the FET pair 330. In an example embodiment, the circuit board 302 is connected to the disable pad 370 via a wire bond, as illustrated. However, a disable control from the circuit board can be electrically connected to the disable pad 370 using any suitable connection method. Moreover, any suitable device for applying a voltage to the disable pad (such as a probe) may be used.

[0028] In an example embodiment, the gate pad of the IC is electrically coupled to DC bias, any input / output pads on the circuit board, or to any suitable connection on the circuit board 302. The ESD protection circuit is configured to provide protection against an ESDevent to any component on the circuit board, pad . Moreover, the gate pad of the IC can be electrically coupled to any suitable portion of the circuit board.

[0029] In this regard, it is noted that the ESD protection circuit may protect functional components regardless of where they are located so long as they are in electrical connection with the gate pad 320. Thus, it is noted that the functional components 310 may be on the same substrate as the ESD protection circuit, on the circuit board 302, and / or part of other devices attached to the circuit board 302. The functional components may be any components susceptible to an ESD event that are connected electrically to the gate pad 320.

[0030] With reference now to FIG. 4, an ESD protection method 400, is disclosed. The method 400 may be configured to protect the IC from ESD events through a portion of a manufacturing process. In an example embodiment, the method 400 comprises: manufacturing (410) a wafer comprising multiple circuits, wherein each circuit of the multiple circuits comprises: a functional component; a gate pad connected to the functional component; and an ESD protection circuit electrically connected to the gate pad. In an example embodiment, the ESD protection circuit may comprise: a FET pair forming a low impedance discharge path between the gate pad and ground for protecting the IC from an ESD event; a disable pad; and a fuse.

[0031] The method may further comprise dicing (420) the wafer to form a IC. The method may further comprise packaging (430) the IC to form a chip. The method may further comprise attaching (440) the chip to a printed circuit board. The method may optionally include the step of disabling the ESD protection circuit by application of a voltage exceeding a disabling voltage threshold level, to a disable pad connected to the gates of the FET pair, to temporarily disable the ESD protection circuit. The method may further comprise applying (450), from the printed circuit board, a DC voltage, exceeding a fusing voltage threshold level, to the gate pad of the IC to blow the fuse to disconnect the ESD protection circuit from the gate pad.

[0032] The method may further comprise testing one or more of the printed circuit board and the chip prior to disconnecting the ESD protection circuit from the gate pad. Thus, the method may comprise iterations of disabling the ESD protection circuit when testing the functional components and reenabling the ESD protection circuit during additional manufacturing steps, until no further ESD protection is needed.

[0033] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutionsto problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as critical, required, or essential features or elements of any or all the claims. As used herein, the terms “includes,” “including,” “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, no element described herein is required for the practice of the invention unless expressly described as “essential” or “critical.”

Claims

CLAIMSWhat is claimed is:1 . An integrated circuit (IC) comprising: a gate pad connected to functional components of the IC; and an electrostatic discharge (ESD) protection circuit comprising: a first FET having a first drain connected to the gate pad and a first source connected to a ground; a second FET having a second drain connected to the ground and a second source connected to the gate pad, the first FET and the second FET forming a FET pair, wherein the FET pair is configured to provide a low impedance discharge path from the gate pad to the ground to protect the functional components against an electrostatic discharge event.

2. The IC of claim 1 , wherein the first FET is configured to provide a low impedance discharge path to the ground for a positive voltage electrostatic discharge event, and wherein the second FET is configured to provide a low impedance discharge path to the ground for a negative voltage electrostatic discharge event.

3. The IC of claim 2, further comprising a disable pad connected to a first gate of the first FET and to a second gate of the second FET for providing a disable biasing voltage to the FET pair; a first resistor connected between the first source and the first gate of the first FET, for biasing with the disable biasing voltage the first FET sufficient to disable the low impedance discharge path to ground through the first FET; and a second resistor connected between the second source and the second gate of the second FET, for biasing with the disable biasing voltage the second FET sufficient to disable the low impedance discharge path to ground through the second FET.

4. The IC of claim 1 , further comprising a fuse connected between the gate pad and the FET pair, for disconnecting the FET pair from the gate pad after testing.

5. The IC of claim 1 , further comprising a fuse connected between the gate pad and the FET pair, the fuse configured such that a negative voltage applied greater than a disabling voltage threshold level will blow the fuse and disconnect the ESD protection circuit from the gate pad.

6. The IC of claim 1 , further comprising a disable pad for selectively biasing the gates of the FET pair to selectively disable the FET pair.

7. The IC of claim 2, further comprising: a fuse connected between the gate pad and the FET pair for permantently disconnecting the ESD protection circuit from the gate pad based on application of a fusing voltage level to the gate pad; and a disable pad connected to a first gate of the first FET and to a second gate of the second FET for providing a disable biasing voltage to the FET pair; a first resistor connected between the first source and the first gate of the first FET, for biasing with the disable biasing voltage the first FET sufficient to disable the low impedance discharge path to ground through the first FET; and a second resistor connected between the second source and the second gate of the second FET, for biasing with the disable biasing voltage the second FET sufficient to disable the low impedance discharge path to ground through the second FET.

8. The IC of claim 1 , wherein the electrostatic discharge protection circuit provides diode-less ESD event protection.

9. The IC of claim 1 , wherein the first FET and the second FET are each a depletion mode FET.

10. A system for providing electrostatic discharge (ESD) protection, the system comprising: a circuit board; and a circuit electrically connected to the circuit board, the circuit comprising: a functional component; a gate pad connected to the functional component; anda FET pair connected to the gate pad and forming a low impedance discharge path from the gate pad to a ground to protect the functional component against an ESD event.11 . The system of claim 10, wherein the FET pair comprises: a first FET configured to provide a low impedance discharge path to ground for a positive voltage electrostatic discharge event; and a second FET configured to provide a low impedance discharge path to ground for a negative voltage electrostatic discharge event.

12. The system of claim 1 1 , further comprising: a disable pad connected to a first gate of the first FET and to a second gate of the second FET for providing a disable biasing voltage to the FET pair; a first resistor connected between a first source and the first gate of the first FET, for biasing with the disable biasing voltage the first FET sufficient to disable the low impedance discharge path to ground through the first FET; and a second resistor connected between a second source and the second gate of the second FET, for biasing with the disable biasing voltage the second FET sufficient to disable the low impedance discharge path to ground through the second FET.

13. The system of claim 10, wherein the circuit further comprises a fuse connected between the gate pad and the FET pair, for disconnecting the FET pair from the gate pad.

14. The system of claim 10, further comprising a disable pad for selectively biasing the gates of the FET pair to selectively disable the FET pair.

15. The system of claim 13, further comprising a fusing source for applying a DC voltage, exceeding a negative fusing voltage threshold level, to the gate pad to blow the fuse to disconnect the FET pair from the gate pad.

16. The system of claim 14, wherein the disable pad is wirebonded to the circuit board.

17. An electrostatic discharge (ESD) protection method, for protecting an integrated circuit (IC) from ESD events through a portion of a manufacturing process, the method comprising: manufacturing a wafer comprising multiple circuits, wherein each circuit of the multiple circuits comprises: a functional component; a gate pad connected to the functional component; and an ESD protection circuit electrically connected to the gate pad, the ESD protection circuit comprising: a FET pair forming a low impedance discharge path between the gate pad and ground for protecting the IC from an ESD event; and a fuse; dicing the wafer to form an IC; packaging the IC to form a chip; attaching the chip to a printed circuit board; and applying, from the printed circuit board, a DC voltage, exceeding a fusing voltage threshold level, to the gate pad of the IC to blow the fuse to disconnect the ESD protection circuit from the gate pad.

18. The method of claim 17, further comprising testing one or more of the printed circuit board and the chip after disconnecting the ESD protection circuit from the gate pad.

19. The method of claim 17, further comprising applying, from the printed circuit board, a DC voltage, exceeding a disabling voltage threshold level, to a disable pad of the IC to temporarily disable the ESD protection circuit.