Laminated isotope battery

Abstract

Disclosed herein relates to a stack-type isotope battery including: a plurality of stacked isotope electrode sheets; and a first outer electrode having a first polarity and a second outer electrode having a second polarity, electrically connected to the plurality of isotope electrode sheets to deliver electrical energy generated from the plurality of stacked isotope electrode sheets to an external load, wherein each of the plurality of isotope electrode sheets includes: a substrate; an isotope battery unit provided within the substrate; and a reflector provided near the edge of the substrate.

Description

Layered isotope battery

[0001] The present invention provides a layered isotope battery capable of generating electrical energy with high energy density.

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0111677, dated August 21, 2024, and Korean Patent Application No. 10-2025-0115528, dated August 20, 2025, the entire contents of which are incorporated herein by reference.

[0003] Radiation emitted by radioactive isotopes can be absorbed through the surface of a pn junction semiconductor and converted into electrical energy. The radiation generates electron-hole pairs in the space charge region within the pn junction semiconductor, and the resulting carriers exhibit voltage-current characteristics.

[0004] The present invention provides a layered isotope battery capable of generating electrical energy with high energy density.

[0005] In order to achieve the above technical problem, the present invention provides a stacked isotope battery comprising a plurality of stacked isotope electrode sheets, and a first external electrode of a first polarity and a second external electrode of a second polarity electrically connected to the plurality of isotope electrode sheets to transmit electric energy generated from the plurality of stacked isotope electrode sheets to an external load, wherein each of the plurality of isotope electrode sheets comprises: a substrate; an isotope battery unit provided within the substrate; and a reflector provided close to an edge of the substrate.

[0006] In some embodiments, the isotope battery unit may include a radiation source extending in the thickness direction of the substrate; and a first conductive semiconductor layer provided between the radiation source and the substrate.

[0007] In some embodiments, the first conductive semiconductor layer is configured to surround a side surface of the radiation source, and the isotope cell unit may further include a second conductive semiconductor layer on a side surface of the first conductive semiconductor layer. In some embodiments, the reflector may have substantially the same conductive type as the first conductive semiconductor layer.

[0008] In some embodiments, the reflector may have substantially the same composition as the first conductive semiconductor layer.

[0009] In some embodiments, the reflector may extend in the thickness direction of the substrate and be configured to reflect minority carriers.

[0010] In some embodiments, the reflector may comprise InAlP, InGaP, InAlGaP, ZnSe, AlAs, or AlAsP doped with a first conductive type dopant.

[0011] In some embodiments, the reflector may include fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), or silver (Ag) doped with a first conductive dopant.

[0012] In some embodiments, the reflector may comprise a layer lattice-matched to the substrate.

[0013] In some embodiments, the substrate may include a III-V semiconductor material.

[0014] In some embodiments, the substrate is a semiconductor substrate, and the first conductive semiconductor layer may include AMO3 (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0015] In some embodiments, the first conductive semiconductor layer is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x and may include at least one selected from the group consisting of LaAlO3.

[0016] In some embodiments, the semiconductor substrate may include a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, a sapphire substrate, or a combination thereof.

[0017] In some embodiments, the radiation source may be positioned within a through-hole penetrating the substrate.

[0018] In some embodiments, the substrate includes a plurality of through-holes, and the radiation source may be provided within each of the plurality of through-holes.

[0019] In some embodiments, the plurality of through-holes may be arranged in the substrate such that each center is located at a vertex of an imaginary equilateral triangle.

[0020] In some embodiments, the radiation source may be positioned within a slit penetrating the substrate.

[0021] In some embodiments, the substrate may include a plurality of slits, and the radiation source may be provided within each of the plurality of slits.

[0022] In some embodiments, the first conductive semiconductor layer may be positioned to face an elongated side of the radiation source, and the substrate may be positioned to face an elongated side of the first conductive semiconductor layer.

[0023] In some embodiments, the plurality of stacked isotope electrode sheets may be identical dies.

[0024] In some embodiments, the plurality of stacked isotope electrode sheets can be electrically connected to each other by solder balls.

[0025] In some embodiments, the plurality of stacked isotope electrode sheets may be molded by a molding resin.

[0026] In some embodiments, the radiation source may include a first portion provided within a trench extending along one surface of the substrate; and a second portion extending from a bottom surface of the trench to the other surface of the semiconductor substrate.

[0027] The layered isotope battery of the present invention has the effect of generating electric energy with high energy density.

[0028] The effects that can be obtained from the exemplary embodiments of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure pertain from the following description. In other words, unintended effects resulting from practicing the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

[0029] FIGS. 1A and 1B are cross-sectional side views showing a layered isotope battery according to embodiments of the present invention.

[0030] FIGS. 2A to 2C are plan views each showing a form in which the radiation source is placed within a through-hole according to embodiments of the present invention.

[0031] FIGS. 3A and 3B are plan views each showing a form in which the radiation source is placed within a slit according to embodiments of the present invention.

[0032] FIGS. 4 to 6A are cross-sectional side views each showing a stacked isotope battery according to different embodiments of the present invention.

[0033] Figure 6b is a plan view of the isotope electrode sheet of the laminated capacitor of Figure 6a.

[0034] Figure 6c is a cross-sectional view taken along line XX of Figure 6b.

[0035] Figure 7 is a cross-sectional side view showing a layered isotope battery according to one embodiment of the present invention.

[0036] FIG. 8a is a cross-sectional side view showing a stacked isotope battery according to another embodiment of the present invention.

[0037] Figure 8b is a partially enlarged perspective view showing the first region, radiation source, and insulating layer of the stacked isotope cell of Figure 8a.

[0038] FIG. 9 is a cross-sectional side view showing a stacked isotope battery according to another embodiment of the present invention.

[0039] FIGS. 10A to 10H are side views illustrating a method for manufacturing a layered isotope battery according to one embodiment of the present invention.

[0040] FIGS. 11A to 11H are side views illustrating a method for manufacturing a layered isotope battery according to another embodiment of the present invention.

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention may be modified in various different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. It is preferable to interpret that the embodiments of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art. Like numbers refer to like elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the present invention is not limited by the relative sizes or spacings depicted in the accompanying drawings.

[0042] While terms like "first" and "second" may be used to describe various components, these components are not limited by these terms. These terms are used solely to distinguish one component from another. For example, a first component could be referred to as a "second component," and vice versa, without departing from the scope of the present invention.

[0043] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the inventive concept. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the expressions “comprises” or “has” indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, operations, components, parts, or combinations thereof.

[0044] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains. Furthermore, it is to be understood that commonly used terms, such as those defined in dictionaries, should be interpreted to have a meaning consistent with their meaning within the relevant technical context, and should not be interpreted in an overly formal sense unless explicitly defined herein.

[0045] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0046] In the accompanying drawings, variations in the shapes depicted may be expected, for example, depending on manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be construed as being limited to the specific shapes of the regions depicted herein, but should include, for example, changes in shapes resulting from the manufacturing process. All terms "and / or" used herein include each and every combination of one or more of the mentioned components. In addition, the term "substrate" used herein may mean the substrate itself, or a laminated structure including the substrate and a predetermined layer or film formed on the surface thereof. In addition, the "surface of the substrate" in this specification may mean the exposed surface of the substrate itself, or the outer surface of a predetermined layer or film formed on the substrate.

[0047]

[0048] FIG. 1a is a cross-sectional side view showing a layered isotope battery (1) according to one embodiment of the present invention.

[0049] Referring to FIG. 1a, the stacked isotope battery (1) may include a plurality of stacked isotope electrode sheets (10).

[0050] Each of the plurality of isotope electrode sheets (10) includes a substrate (100), an isotope battery unit (10u) provided within the substrate (100), and a reflector (115) provided close to an edge of the substrate (100).

[0051] The above isotope battery unit (10u) may include a radiation source (200) extending in the thickness direction of the substrate (100), and a first conductive semiconductor layer (110) provided between the radiation source (200) and the substrate (100).

[0052] The above-mentioned material (100) may be an insulator or a semiconductor.

[0053] In some embodiments, the substrate (100) may include a III-V group semiconductor material. The III-V group semiconductor material may include InAlP, InGaP, InAlGaP, ZnSe, AlAs, AlAsP, or yttria-stabilized zirconia (YSZ).

[0054] In some embodiments, the substrate (100) may include a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, a sapphire substrate, or a combination thereof, which may be undoped substrates.

[0055] In some other embodiments, the substrate (100) may include a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, a sapphire substrate, or a combination thereof, which may be substrates doped with a dopant.

[0056] In some other embodiments, the substrate (100) may have a chemical formula of AMO3 (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0057] Specifically, the above-described (100) is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12, Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x and may include at least one selected from the group consisting of LaAlO3 (wherein 0 <x<1).

[0058] In some embodiments, the substrate (100) may include a non-conductive substrate. In some embodiments, the substrate (100) may include a semiconductor substrate.

[0059] The substrate (100) may include a recess. In some embodiments, the recess may be a hole or a trench. The recess may have a shape extending inward between the major surfaces of the substrate (100). The recess may completely penetrate the substrate (100) or may partially penetrate it.

[0060] In some embodiments, the first conductive semiconductor layer (110) may be disposed so as to form an interface with the substrate (100). The first conductive semiconductor layer (110) may be disposed at least partially within the concave portion. In some embodiments, the first conductive semiconductor layer (110) may be disposed within the concave portion.

[0061] The first conductive semiconductor layer (110) may be a material having higher electrical conductivity than the substrate (100). In some embodiments, the first conductive semiconductor layer (110) may include a material having a smaller band gap than the substrate (100). In some embodiments, the first conductive semiconductor layer (110) may include a material having a band gap of about 2.7 eV or more, about 3.0 eV or more, or about 3.5 eV or more.

[0062] The radiation source (200) may be positioned within the substrate (100). In some embodiments, the radiation source (200) may be positioned within the recessed portion, spaced apart from the interface. In some embodiments, the radiation source (200) may be positioned within the substrate (100), spaced apart from the interface.

[0063] In some embodiments, the first conductive semiconductor layer (110) may be provided conformally within the recess. In this case, the first conductive semiconductor layer (110) may have a recess space inheriting the recess. In some embodiments, the radiation source (200) may be disposed within the recess space.

[0064] In some embodiments, the radiation source (200) may be arranged to penetrate the first conductive semiconductor layer (110). The first conductive semiconductor layer (110) may be interposed between the second conductive semiconductor layer (120) and the radiation source (200). Specifically, the first conductive semiconductor layer (110) may be arranged on a side surface of the radiation source (200), and the second conductive semiconductor layer (120) may be arranged on a side surface of the first conductive semiconductor layer (110). In some embodiments, the second conductive semiconductor layer (120) may be a doped region in which an impurity is doped in the substrate (100) and may face the first conductive semiconductor layer (110) across the interface.

[0065] In some embodiments, the first conductive semiconductor layer (110) may include a metal oxide having a band gap energy of 2.7 eV or more. In some embodiments, the metal oxide may have a chemical formula of AMO3 (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr).

[0066] Specifically, the metal oxide is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x and may include at least one selected from the group consisting of LaAlO3 (wherein 0 <x<1).

[0067] The above metal oxide is not only stable in high temperature and high humidity environments, but also has high carrier mobility, so it can efficiently absorb radiation emitted from a radiation source (200) and provide high energy conversion efficiency. In addition, there is no inelastic collision in the carrier movement, so there is no energy loss and it is advantageous for heat dissipation. For example, the above metal oxide is 45 cm 2 / (V·s) or more, 80 cm 2 / (V·s) or more, 120 cm 2 / (V·s) or more, further 300 cm 2 / (V·s) or higher carrier mobility can be achieved.

[0068] These metal oxides are bidirectionally doped materials and have the advantage of being able to provide high current or high voltage depending on the direction of the applied bias.

[0069] The first conductive semiconductor layer (110) may be doped with a first conductive dopant. The second conductive semiconductor layer (110) may be doped with a second conductive dopant. The first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may generate electron-hole pairs by radiation emitted from a radiation source (200).

[0070] In some embodiments, the first conductivity type dopant may be an n-type dopant and the second conductivity type dopant may be a p-type dopant. In some other embodiments, the first conductivity type dopant may be a p-type dopant and the second conductivity type dopant may be an n-type dopant. Those skilled in the art will understand that, depending on the conductivity type of the dopant doped in each region, one of the first conductivity type semiconductor layer (110) and the second conductivity type semiconductor layer (120) may operate as a cathode and the other may operate as an anode. That is, if the first conductivity type dopant is an n-type dopant and the second conductivity type dopant is a p-type dopant, the first conductivity type semiconductor layer (110) may operate as an anode and the second conductivity type semiconductor layer (120) may operate as a cathode. Conversely, if the first conductive type dopant is a p-type dopant and the second conductive type dopant is an n-type dopant, the first conductive type semiconductor layer (110) can act as a cathode and the second conductive type semiconductor layer (120) can act as an anode.

[0071] The region doped with the above n-type dopant may be, for example, a semiconductor region doped with nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which are elements of Group 15 of the periodic table, or may be a compound semiconductor doped with nitrogen (N), phosphorus (P), arsenic (As), or antimony, which are elements of Group 15 of the periodic table. In the present specification, a compound semiconductor means a semiconductor composed of two or more elements, and may be, for example, silicon carbide, silicon oxide, aluminum phosphide (AlP), aluminum arsenide (AlAs), gallium arsenide (GaAs), or gallium nitride (GaN).

[0072] The region doped with the above p-type dopant may be, for example, a semiconductor region doped with elements of Group 13 of the periodic table, such as boron (B), aluminum (Al), gallium (Ga), or indium (In), or may be a compound semiconductor doped with elements of Group 13 of the periodic table, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0073] In some embodiments, the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may include an organic material used in an organic layer that receives light and generates electricity in the field of solar cells, etc. For example, the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may include a thiophene compound. Meanwhile, the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may be an organic-inorganic hybrid type by appropriately mixing the aforementioned inorganic material and organic material.

[0074] In some embodiments, a depletion region may be formed near the interface where the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) contact each other.

[0075] A reflector (115) may be placed close to the edge of the substrate (100). The reflector (115) may have substantially the same conductivity type as the first conductive semiconductor layer (110). That is, if the first conductive semiconductor layer (110) is p-type, the reflector (115) may also have p-type, and if the first conductive semiconductor layer (110) is n-type, the reflector (115) may also have n-type.

[0076] The above reflector (115) serves to increase the electrical efficiency of the isotope battery sheet (10). Some of the radiation emitted from the radiation source (200) contributes to the generation of electron-hole pairs (EHP) in the isotope battery unit (10u), but some of the radiation may be emitted to the outside of the isotope battery sheet (10) without contributing to the generation of EHP. The radiation emitted to the outside is not only one of the causes of the decrease in the energy efficiency of the isotope battery sheet (10), but may also impede radiation safety.

[0077] If there were no reflector (115), the radiation that would have been emitted to the outside can form an EHP at the pn junction between the reflector (115) and the second conductive semiconductor layer (120), thereby improving electrical efficiency and radiation safety.

[0078] The reflector (115) may have substantially the same composition as the first conductive semiconductor layer (110). The reflector (115) may form a pn junction with the second conductive semiconductor layer (120) adjacent thereto. In some embodiments, the reflector (115) may include a layer lattice-matched with the substrate (100). In other words, the reflector (115) may have substantially the same lattice constant as the substrate (100).

[0079] The above reflector (115) forms a pn junction with the second conductive semiconductor layer (120), thereby generating EHP from radiation incident thereon. Furthermore, the reflector (115) reduces electron-hole recombination by reflecting minority carriers, thereby improving the electrical conversion efficiency of the EHP.

[0080] In some embodiments, the reflector (115) may include InAlP, InGaP, InAlGaP, ZnSe, AlAs, or AlAsP doped with a first conductive type dopant. The doping concentration of the first conductive type dopant in the reflector (115) is about 1E16 cm -3 About 5E19 cm -3 It could be.

[0081] In some other embodiments, the reflector (115) may include fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), or silver (Ag) doped with a first conductive dopant.

[0082] In some embodiments, the reflector (115) may have substantially the same dimensions as the first conductive semiconductor layer (110) in the vertical direction (i.e., the thickness direction of the substrate (100)). In some embodiments, the reflector (115) may have a smaller dimension than the overall width of the radiation source (200) and the first conductive semiconductor layer (110) in the horizontal direction (i.e., the direction parallel to the major surface of the substrate (100). In some other embodiments, the reflector (115) may have substantially the same dimensions as the overall width of the radiation source (200) and the first conductive semiconductor layer (110) in the horizontal direction (i.e., the direction parallel to the major surface of the substrate (100).

[0083] In some embodiments, the radiation source (200) may be provided within a through-hole penetrating the substrate (100). FIGS. 2A to 2C are plan views each showing a form in which the radiation source (200) is placed within a through-hole (101) according to embodiments of the present invention.

[0084] Referring to FIG. 2a, the substrate (100) is provided with a plurality of through-holes (101) penetrating the substrate (100), and the radiation source (200) can be placed within the through-holes (101).

[0085] The through-holes (101) may be formed by any method known to those skilled in the art. For example, the through-holes (101) may be formed by anisotropic etching, isotropic etching, laser irradiation, or the like. In some embodiments, the through-holes (101) may be formed by irradiating the substrate (100) with laser light. In some embodiments, the through-holes (101) may be formed by reactive ion etching (RIE).

[0086] In some embodiments, the through-holes (101) may be arranged according to a predetermined rule. In some embodiments, the through-holes (101) may be arranged so that each center is located at a vertex of a series of virtual equilateral triangles.

[0087] By arranging the centers of the above through holes (101) to be located at the vertices of virtual equilateral triangles, the number of radiation sources (200) that can be accommodated per unit area can be maximized.

[0088] In some embodiments, the first conductive semiconductor layer (110) may be arranged to surround a side surface of the radiation source (200). In some embodiments, the second conductive semiconductor layer (120) may be arranged to surround a side surface of the first conductive semiconductor layer (110).

[0089] Referring to FIG. 2B, the side walls of the through-holes (101) may have a roughness. That is, the through-holes (101) may have concave and convex portions. The interface between the radiation source (200) and the first conductive semiconductor layer (110) may have a roughness. In some embodiments, the interface between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may have a roughness.

[0090] The first conductive semiconductor layer (110) may have a substantially constant lateral thickness as illustrated in FIG. 2B. Accordingly, the interface between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) may have a shape corresponding to the interface between the radiation source (200) and the first conductive semiconductor layer (110).

[0091] Since the side walls of the above through-holes (101) have an uneven shape, the contact area between the radiation source (200) and the first conductive semiconductor layer (110) can be increased, thereby improving the efficiency of the radiation source (200). In addition, since the interface between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) has an uneven shape, the contact area between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120) can be increased, thereby improving the efficiency of the isotope cell (1).

[0092] Referring to Fig. 2c, each center of the through-holes (101) may be arranged to be located at the vertices of continuously arranged virtual isosceles triangles. As in Fig. 2a, each center of the through-holes (101) may not necessarily be located at the vertices of continuously arranged virtual equilateral triangles.

[0093] In some embodiments, the triangles in which the centers of the through-holes (101) are arranged may have different shapes. Accordingly, the through-holes (101) may be arranged somewhat irregularly.

[0094] In some embodiments, the radiation source (200) may be positioned within a slit penetrating the substrate (100). FIGS. 3A and 3B are plan views each showing a form in which the radiation source (200) is positioned within a slit (102) according to embodiments of the present invention.

[0095] Referring to FIG. 3A, the substrate (100) may include a plurality of slits (102) extending parallel to one direction. In addition, a radiation source (200) may be provided within the slits (102). As illustrated in FIG. 3A, the slits (102) may extend long in a first direction (R1), and the extended length is greater than a width of the slits (102) in a second direction (R2). The first direction (R1) is perpendicular to a thickness direction (T) of the substrate (100), and the second direction (R2) is perpendicular to the first direction (R1) and the thickness direction (T).

[0096] In some embodiments, the side of the radiation source (200) may contact the side of the slits (102). The radiation source (200) may contact the outer edge of the slits (102).

[0097] In some embodiments, the first conductive semiconductor layer (110) may be arranged to face the elongated side surfaces of the radiation source (200). The first conductive semiconductor layer (110) may face both elongated side surfaces of the radiation source (200). For example, the first conductive semiconductor layer (110) may extend along two longitudinal side surfaces of the slit (102) extending in the first direction (R1). More preferably, as illustrated in FIG. 3A, the first conductive semiconductor layer (110) may laterally completely surround the slit (102) extending in the longitudinal direction. In general, the first conductive semiconductor layer (110) may be arranged to completely or at least partially surround the radiation source (200).

[0098] In some embodiments, the second conductive semiconductor layer (120) may be positioned to face an elongated side surface of the first conductive semiconductor layer (110). For example, the second conductive semiconductor layer (120) may extend along a portion of the first conductive semiconductor layer (110) that extends along the longitudinal side surface of the slit (102).

[0099] In some embodiments, the first conductive semiconductor layer (110) may be arranged to surround a side surface of the radiation source (200). In some embodiments, the second conductive semiconductor layer (120) may be arranged to at least partially surround a side surface of the first conductive semiconductor layer (110). In some embodiments, as exemplarily illustrated in FIG. 3A, the second conductive semiconductor layer (120) may completely surround the first conductive semiconductor layer (110) in a lateral direction.

[0100] Referring to FIG. 3b, the side walls of the slits (102) may have a roughness. That is, the slits (102) may have concave and convex portions. The interface between the radiation source (200) and the second material layer (110) may have a roughness.

[0101] By having the side walls of the above slits (102) uneven, the contact area between the radiation source (200) and the second material layer (110) can be increased, thereby improving the efficiency of the radiation source (200).

[0102] Although the entire substrate (100) is illustrated as a second conductive semiconductor layer (120) in FIGS. 1A to 3B , the present invention is not limited thereto. In FIGS. 1A to 3B , regions of different conductive types or dopant concentrations may exist within the substrate (100), or regions that are not doped with a specific conductive type may exist. In some embodiments, the substrate (100) may not be doped with a dopant. In this case, the substrate (100) may be an electrical insulator.

[0103] Referring again to FIG. 1a, the plurality of isotope electrode sheets (10) may be formed by stacking identical semiconductor dies.

[0104] As exemplarily shown in FIG. 1A, each of the isotope electrode sheets (10) may include a first upper electrode (132) on the first conductive semiconductor layer (110), for example, on the first major surface of the substrate (100). Additionally or alternatively, each of the isotope electrode sheets (10) may include a first lower electrode (152) on the lower side of the first conductive semiconductor layer (110), for example, on the second major surface of the substrate (100). The first upper electrode (132) may be in electrical contact with the first conductive semiconductor layer (110) at the first surface, and the first lower electrode (152) may be in electrical contact with the first conductive semiconductor layer (110) at the second surface.

[0105] In addition, each of the isotope electrode sheets (10) may include a second upper electrode (134) on the second conductive semiconductor layer (120) and a second lower electrode (154) on the lower side of the second conductive semiconductor layer (120). The second upper electrode (134) may be in electrical contact with the second conductive semiconductor layer (120) at the first surface, and the second lower electrode (154) may be in electrical contact with the second conductive semiconductor layer (120) at the second surface.

[0106] Each of the first upper electrode (132), the first lower electrode (152), the second upper electrode (134), and the second lower electrode (154) can substantially function as a current collector. Each of the first upper electrode (132), the first lower electrode (152), the second upper electrode (134), and the second lower electrode (154) is not particularly limited in type, size, shape, etc., as long as it has electrical conductivity without causing physical and chemical changes in the isotope electrode sheet (10). For example, each of the first upper electrode (132), the first lower electrode (152), the second upper electrode (134), and the second lower electrode (154) can have a cylindrical shape, a tetrahedral shape, a hexahedral shape, a torus shape, or a pad shape. Additionally, each of the first upper electrode (132), the first lower electrode (152), the second upper electrode (134), and the second lower electrode (154) may have a form in which the central portion is empty.

[0107] In some embodiments, the second upper electrode (134) on the first surface may be a continuous layer including openings arranged to correspond to the first conductive semiconductor layer (110), for example, and the first upper electrodes (132) may be arranged within the openings. Similarly, on the second surface, the second lower electrode (154) may be a continuous layer including openings arranged to correspond to the first conductive semiconductor layer (110), for example, and the first lower electrodes (152) may be arranged within the openings.

[0108] In addition, for example, each of the first upper electrode (132), the first lower electrode (152), the second upper electrode (134), and the second lower electrode (154) may include a metal material such as gold (Au), silver (Ag), platinum (Pt), stainless steel, copper (Cu), aluminum (Al), nickel (Ni), or titanium (Ti), or may include a transparent oxide such as fluorine (F)-doped tin oxide (FTO) or indium oxide (ITO, In2O3), or may include a carbon-based compound such as carbon nanotubes, graphene, or graphene oxide.

[0109] The above radiation source (200) may include a radioactive isotope. The radioactive isotope is not particularly limited when it decays and emits radiation, but includes tritium ( 3 H, tritium), Calcium-45( 45 Ca), nickel-63( 63 Ni), copper-67( 67 Cu), strontium-90( 90 Sr), promethium-147( 147 Pm), osmium-194( 194 OS), thulium-171( 171 Tm), tantalum-182( 182 Ta), cadmium-115( 115 Cd), germanium-75( 75 Ge), cerium-141( 141 Ce), cerium-144( 144 Ce) and tungsten-185( 185 W) may include one or more selected from the group consisting of; however, the present invention is not limited thereto.

[0110] In some embodiments, the radiation source (200) may include a radioisotope that emits alpha rays. For example, the radiation source (200) may include americium-241( 241 Am), americium-243( 243 Am), polonium-209( 209 Po), polonium-210( 210 Po), plutonium-238( 238 Pu), plutonium-239( 239 Pu), curium-242( 242 Cm), curium-244( 244 Cm), curium-249( 249 Cm), promethium-147( 147 Pm), uranium-238( 238 U), thorium-232( 232 Th), radium-226( 226 Ra), bismuth-210( 210 Bi), neptunium-237( 237 Np), europium-152( 152 Eu), francium-223( 223 Fr), astatine-210( 210 At), protactinium-231( 231 Pa), einsteinium-253( 253 Es), californium-252( 2520 Cf), and berkelium-249( 249 Bk) may include one or more selected from the group consisting of; however, the present invention is not limited thereto.

[0111] The above radiation source (200) can be formed by any method known to those skilled in the art. For example, the above radiation source (200) can be formed by various methods such as plating, vapor deposition, and atomic layer deposition (ALD).

[0112] In some embodiments, the radiation source (200) may be formed by plating. When the radiation source (200) is formed by plating, the radiation source (200) may be formed by forming a seed layer and then performing electrolytic plating. Alternatively, the radiation source (200) may be formed by electroless plating.

[0113] The first lower electrode (152) of the isotope electrode sheet (10) positioned above may be electrically connected to the first upper electrode (132) of the isotope electrode sheet (10) positioned below it. In some embodiments, the first lower electrode (152) of the isotope electrode sheet (10) positioned above and the first upper electrode (132) of the isotope electrode sheet (10) positioned below it may be connected by a connector (140) such as a solder ball.

[0114] In one example, the connector (140) may include a conductive material. Here, the conductive material may include one or more selected from the group consisting of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and lead (Pb), for example. The number, spacing, arrangement, shape, etc. of the connectors (140) are not limited to those illustrated and may be changed according to the design. Referring to FIG. 1, the connector (140) may have a solder ball or solder bump shape.

[0115] The space between two vertically adjacent isotope electrode sheets (10) can be filled with an insulator (160). The insulating layer (160) is not particularly limited as long as it is a material having electrical insulating properties, but may include, for example, one or more selected from the group consisting of silicate (e.g., TEOS), silicon nitride (SiN), hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, and aluminum oxide.

[0116] The isotope battery (1) illustrated in Fig. 1a can be obtained by manufacturing individual isotope battery sheets (10) and then stacking them. By manufacturing individual isotope battery sheets (10) and then stacking them, only defective isotope battery sheets (10) can be selected and excluded from the stacking process, thereby increasing the manufacturing yield of the isotope battery (1) and reducing the manufacturing cost.

[0117] The plurality of isotope electrode sheets (10) can be housed within a housing (190). In addition, the plurality of isotope electrode sheets (10) can be electrically connected to an external load by a conductor that passes through the housing (190) and is drawn outward.

[0118] In some embodiments, the housing (190) may further include an electromagnetic interference (EMI) shield (not shown) capable of shielding electromagnetic waves. The EMI shield may be formed on at least a portion of the inner surface and / or the outer surface of the housing (190). The EMI shield may include, for example, a metal such as copper or aluminum, a conductive polymer such as polyaniline, or a magnetic material such as iron oxide. In addition, the EMI shield may be provided in the form of a sheet, a mesh, a coating layer, a spray coating, a non-woven fabric, a tape, or a fabric layer. By faithfully providing the EMI shield in the housing (190), the electromagnetic compatibility (EMC) of the stacked isotope battery (1) can be secured.

[0119] The first upper electrodes (132) of the isotope electrode sheet (10) arranged at the top of Fig. 1a may be electrically connected to each other and electrically connected to the first external electrode (15a) of the first polarity. In addition, the second lower electrode (132) of the isotope electrode sheet (10) arranged at the bottom of Fig. 1a may be electrically connected to the second external electrode (15b) of the second polarity. The first external electrode (15a) and the second external electrode (15b) may be exposed to the outside of the housing (190) so as to be connected to an external load.

[0120] In some embodiments, the second lower electrodes (154) of the isotope electrode sheet (10) disposed at the bottom in FIG. 1A may surround the first lower electrode (152) and be electrically connected to each other. In some embodiments, the second lower electrodes (154) may be electrically connected to each other by a separate conductive line (not shown) and may be connected to the second external electrode (15b) exposed to the outside of the housing (190). The external load to which the first external electrode (15a) and the second external electrode (15b) are connected may include an electronic device, an electrochemical battery, an energy storage device, or other devices. During operation, the isotope cell according to the present invention has a plurality of pn junctions connected in parallel, whereby the output current flowing through the first external electrode (15a) and the second external electrode (15b) may be the sum of the individual currents of the individual pn junctions.

[0121] Figure 1b is a cross-sectional side view showing a layered isotope battery (1a) according to another embodiment of the present invention.

[0122] Referring to FIG. 1b, the laminated isotope battery (1a) may have a first isotope electrode sheet (11) and a second isotope electrode sheet (12) alternately and repeatedly laminated.

[0123] The above first isotope electrode sheet (11) is generally the same as the isotope electrode sheet (10) described with reference to Fig. 1a, so a detailed description thereof is omitted here.

[0124] The second isotope electrode sheet (12) is substantially identical to each component of the first isotope electrode sheet (11), but differs in that the conductivity type of the dopant is opposite. That is, if the first conductivity type semiconductor layer (110) of the first isotope electrode sheet (11) is doped with p-type, the corresponding region of the second isotope electrode sheet (12) may be doped with n-type. Conversely, if the first conductivity type semiconductor layer (110) of the first isotope electrode sheet (11) is doped with n-type, the corresponding region of the second isotope electrode sheet (12) may be doped with p-type.

[0125] Likewise, if the second conductive semiconductor layer (120) of the first isotope electrode sheet (11) is doped with p-type, the corresponding region of the second isotope electrode sheet (12) may be doped with n-type. Conversely, if the second conductive semiconductor layer (120) of the first isotope electrode sheet (11) is doped with n-type, the corresponding region of the second isotope electrode sheet (12) may be doped with p-type.

[0126] The stacked isotope cell (1a) illustrated in Fig. 1b can obtain higher voltage electrical energy because the number of unit cells corresponding to individual radiation sources (200) connected in series increases. Since the pn junctions in Fig. 1b are connected in series so that the total output voltage becomes the sum of the voltages generated at the individual pn junctions, the first external electrode (15a) and the second external electrode (15b) can have a higher operating voltage than in the isotope cell (1) of Fig. 1.

[0127]

[0128] Figure 4 is a cross-sectional side view showing a layered isotope battery (1b) according to one embodiment of the present invention.

[0129] The stacked isotope battery (1b) illustrated in FIG. 4 is generally the same as the stacked isotope battery (1) described with reference to FIGS. 1a to 3, but differs in that a plurality of isotope electrode sheets (10a) are encapsulated by a molding member (192) and a plurality of isotope electrode sheets (10a) are mounted on a controller chip (300). Therefore, the following description will focus on these differences and omit descriptions of common parts.

[0130] Referring to FIG. 4, the plurality of isotope electrode sheets (10a) are mounted on a controller chip (300). In some embodiments, the controller chip (300) may include a power management integrated circuit (PMIC) that outputs electrical energy generated from the plurality of stacked isotope electrode sheets (10) to the outside according to a predetermined rule.

[0131] The above plurality of isotope electrode sheets (10a) can be molded by a molding member (192). The molding member (192) can include, for example, an epoxy molding compound (EMC).

[0132] When the plurality of isotope electrode sheets (10a) are electrically connected to the controller chip (300) through the first and second lower electrodes (152, 154) provided on the lowermost isotope battery sheet (10) as illustrated in FIG. 4, the first upper electrode (132) and the second upper electrode (134) of the uppermost isotope electrode sheet (10a) may act as dummy electrodes. In some embodiments, at least one of the first upper electrode (132) and the second upper electrode (134) disposed on the uppermost of the plurality of isotope electrode sheets (10a) may be exposed to the outside through the molding member (192).

[0133] In another embodiment, the first upper electrode (132) and the second upper electrode (134) disposed at the uppermost portion among the plurality of isotope electrode sheets (10a) may be completely covered by the molding member (192). In some embodiments, the upper surface of the isotope battery sheet (10a) disposed at the uppermost portion among the plurality of isotope battery sheets (10a) may be covered with the first upper electrode (132) and the second upper electrode (134) instead of the first upper electrode (132) and the second upper electrode (134), or with a passivation layer or a molding member (192), or with a passivation layer and a molding member (192).

[0134] The electric energy generated from the plurality of isotope electrode sheets (10a) can be supplied to an external load through an external terminal (310a, 310b) provided to the controller chip (300). In Fig. 4, the plurality of isotope electrode sheets (10a) are illustrated as being mounted on the upper portion of the controller chip (300), but the present invention is not limited thereto.

[0135]

[0136] Figure 5 is a cross-sectional side view showing a layered isotope battery (1c) according to another embodiment of the present invention.

[0137] Referring to FIG. 5, the stacked isotope battery (1c) may include a plurality of isotope electrode sheets (10b) stacked in a vertical direction (V), i.e., in the thickness direction of the substrate (100).

[0138] The above isotope electrode sheet (10b) differs from the isotope electrode sheet (10) of Fig. 1a in that the lower electrodes (152, 154) and the connector (140) are omitted. Therefore, the following description will focus on these differences, and the description of the common parts will be omitted.

[0139] The above isotope electrode sheet (10b) includes a first upper electrode (132) and a second upper electrode (134) on the upper surface. In some embodiments, the isotope electrode sheets (10b) of the plurality of stacked isotope electrode sheets (10b) may all be identical semiconductor dies.

[0140] The first upper electrode (132) and the second upper electrode (134) of the isotope electrode sheet (10b) positioned at the bottom can be in direct contact with the bottom surfaces of the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120), respectively, of the isotope electrode sheet (10b) positioned thereon. In other words, on each isotope battery sheet (10b), the first upper electrode (132) and the second upper electrode (134) are provided only on the first surface, which is the upper main surface, and the second surface, which is the lower main surface, can be in electrical contact with the first upper electrode (132) and the second upper electrode (134) of the isotope battery sheet (10b) positioned directly below it.

[0141] The stacked isotope battery (1c) described above can be configured more compactly since the lower electrodes (152, 154) and the connector (140) are omitted, thereby increasing the energy density. Optionally, the first conductive semiconductor layers (110) of the isotope battery sheet (10b) and the second conductive semiconductor layers (120) of the adjacent isotope battery sheet (10b) may be arranged to be in direct contact with each other. In this case, the electrodes between the adjacent isotope battery sheets within the stack may be omitted.

[0142]

[0143] Fig. 6a is a cross-sectional side view showing a stacked isotope battery (1d) according to another embodiment of the present invention. Fig. 6b is a plan view of an isotope electrode sheet (10c) of the stacked isotope battery (1d) of Fig. 6a. Fig. 6c is a cross-sectional view taken along line XX of Fig. 6b.

[0144] Referring to FIG. 6a, the stacked isotope battery (1d) may include a plurality of stacked isotope electrode sheets (10c).

[0145] The isotope electrode sheet (10c) illustrated in FIGS. 6A, 6B, and 6C has a major difference in the configuration of the cavity (105) compared to the isotope electrode sheet illustrated in FIG. 1A. As in the example illustrated in FIG. 6A, the cavity (105) has a recessed shape with a step. The cavity (105) may include a trench (103) formed on the first surface. Additionally, one or more through-holes (101) may extend from the bottom of the trench (103) to the second surface.

[0146] The above isotope electrode sheet (10c) may include a trench (103) extending along the upper surface of the substrate (100) and a through-hole (101) extending from the bottom surface of the trench (103) to the lower surface of the substrate (100). As illustrated in FIG. 6b, the trench (103) may extend long in the line of sight of FIG. 6a (i.e., the first direction R1), and the through-hole (101) may extend vertically from the bottom surface of the trench (103). In some embodiments, as exemplarily illustrated in FIGS. 6b and 6c, a plurality of through-holes (101) may be arranged along the first direction R1 for one trench (103).

[0147] An isotope source (200) may be provided inside the trench (103) and the plurality of through-holes (101). The isotope source (200) may include a first portion (210) extending in a first direction (R1) that is the longitudinal direction of the trench (103) inside the trench (103), which may be disposed within the trench (103). In addition, the isotope source (200) may include a second portion (220) extending from within the through-hole (101) to the lower surface of the substrate (100).

[0148] The width direction (i.e., the second direction (R2)) dimension w1 of the first portion (210) may be larger than the width direction dimension w2 of the second portion (220). Here, the width direction means a direction perpendicular to the first direction R1, which is the direction in which the trench (103) extends, and refers to the horizontal direction of FIG. 6. The width direction dimension w3 of the first portion (210) and the corresponding first conductive semiconductor layer (110) may be larger than the width direction dimension w4 of the second portion (220) and the corresponding first conductive semiconductor layer (110).

[0149] The first conductive semiconductor layer (110) of the substrate (100) may have a generally constant thickness from the surface of the radiation source (200).

[0150] Fig. 7 is a cross-sectional side view showing an isotope cell (1e) according to one embodiment of the present invention. The isotope cell (1e) of Fig. 7 differs from the isotope cell (1) shown in Fig. 1a in that it further includes a photon generation layer (250) around the radiation source (200), and the following description will focus on this difference.

[0151] Referring to FIG. 7, the photon generation layer (250) may be any material layer capable of emitting photons in response to radiation particles, such as alpha rays, emitted from the radiation source (200). In some embodiments, the radiation source (200) may be a material that emits alpha rays, and since such materials have been described with reference to FIG. 1A, a detailed description thereof will be omitted herein.

[0152] For example, the photon generation layer (250) may employ materials such as Ba2Ca(BO3)2, BaHfO3, BaI2:Ce, BeO, BaF2, BaMgF4, Cs2LiLuCi6:Ce, K2YF5, KCaF3, YI3:Ce, etc., but is not limited thereto. Various examples of the photon generation layer (250) are disclosed at https: / scintillator.lbl.gov / inorganic-scintillator-library / .

[0153] The photon generation layer (250) can emit photons in response to alpha rays incident from the radiation source (200). The photons generated in the photon generation layer (250) can be incident on the junction region between the first conductive semiconductor layer (110) and the second conductive semiconductor layer (120), and electrical energy can be generated by the photons.

[0154] Fig. 8a is a side cross-sectional view showing an isotope battery (1f) according to another embodiment of the present invention. Fig. 8b is a partially enlarged perspective view showing the first conductive semiconductor layer (110), the radiation source (200), and the insulating layer (162) of the isotope battery (1f). The isotope battery (1f) illustrated in Figs. 8a and 8b differs from the isotope battery (1) illustrated in Fig. 1a in that the radiation source (200) has a hollow (annular) shape, and the following description will focus on this difference.

[0155] Referring to FIGS. 8A and 8B, the radiation source (200) may have a hollow tube shape. In some embodiments, the hollow central portion of the radiation source (200) may be filled with an insulating layer (162). In some other embodiments, the central portion may be filled with the substrate (100) or a semiconductor layer derived therefrom. The radiation source (200) may extend along the interface with the first conductive semiconductor layer (110) while having a substantially constant thickness.

[0156] Since the interior of the above radiation source (200) is filled with an insulating layer (162), the amount of radiation source required to form the radiation source (200) can be reduced. Since the price of radiation sources is high, by forming a hollow radiation source (200) in this way, an isotope battery (1f) can be manufactured inexpensively.

[0157] Fig. 9 is a cross-sectional side view of an isotope battery (1g) according to another embodiment of the present invention. The isotope battery (1g) illustrated in Fig. 9 differs from the isotope battery (1) illustrated in Fig. 1a in that it further concretizes the external electrodes (15a, 15b), and the following description focuses on these differences.

[0158] Referring to FIG. 9, the isotope battery (1g) includes a first external electrode (15a) and a second external electrode (15b) to supply electrical energy to an external load.

[0159] It includes conductors (15) extending within an insulator (164) to connect the first external electrode (15a) to the first upper electrodes (132) of the isotope electrode sheet (10). The conductors (15) can be electrically connected only to the first upper electrodes (132).

[0160] In some embodiments, the conductors (15) may include a first conductor (15h) and a second conductor (15v) extending in different directions within the insulator (164). The second conductor (15v) may electrically connect the first conductor (15h) and the first upper electrode (132). The first conductor (15h) may be physically and / or electrically connected to the first external electrode (15a). In some embodiments, the first conductor (15h) may extend horizontally and the second conductor (15v) may extend vertically, but the present invention is not limited thereto.

[0161] In some embodiments, the second upper electrodes (134) of the isotope electrode sheet (10) closest to the first external electrode (15a) may be omitted.

[0162] The second external electrode (15b) may also be electrically connected to the isotope electrode sheets (10) in a similar manner to the first external electrode (15a). A person skilled in the art will be able to envision the wiring connection between the second external electrode (15b) and the isotope electrode sheets (10) with reference to the wiring connection between the first external electrode (15a) and the isotope electrode sheets (10) described above.

[0163] Figures 10a to 10h are side views showing a method for manufacturing a layered isotope battery (1) according to one embodiment of the present invention.

[0164] Referring to FIG. 10a, a substrate (100) is provided. The substrate (100) may include, for example, a material having an energy band gap of about 2.5 eV or more. In some embodiments, the material of the substrate (100) has been described with reference to FIG. 1a, and thus a detailed description thereof is omitted herein.

[0165] The above-described substrate (100) may be at least partially doped with a dopant. The dopant may be a dopant of a desired conductivity type and may have a conductivity type opposite to that of the dopant doped into the first conductivity type semiconductor material layer (110m) to be described later.

[0166] The dopant may be doped throughout the entire substrate (100) or may be locally doped to form a well. In some embodiments, there may be a region within the substrate (100) that is not doped with a specific conductive type. The region doped with the dopant forms a second conductive type semiconductor layer (120).

[0167] Referring to FIG. 10b, a plurality of first recesses (100r) and a plurality of second recesses (110re) can be formed in the substrate (100).

[0168] The first recess (100r) may be formed, for example, by deep reactive ion etching (DRIE). However, the present invention is not limited thereto. The first recess (100r) may be in the form of a hole or in the form of a trench extending in the viewing direction of FIG. 10b.

[0169] Second recesses (100re) may be formed near the edge of the above-described substrate (100). In some embodiments, the first recess (100r) and the second recess (100re) may be formed in the same process.

[0170] The second recesses (100re) may be arranged closer to the edge of the substrate (100) than the first recesses (100r). In some embodiments, the second recesses (100re) may have a smaller width than the first recesses (100r). That is, the width g2 of the second recess (100re) may be smaller than the width g1 of the first recess (100r).

[0171] In some embodiments, the first recess (100r) and the second recess (100re) may have substantially the same depth.

[0172] As previously described, the entire substrate (100) may be doped with a specific conductive type. In this case, the side walls of the first recess (100r) and the second recess (100re) themselves may constitute the second conductive type semiconductor layer (120).

[0173] Alternatively, the substrate (100) may have a well region doped with a specific conductivity type. In this case, the first recess (100r) and the second recess (100re) may be formed within the well region, and the sidewalls of the first recess (100r) and the second recess (100re) formed within the well region may themselves constitute the second conductivity type semiconductor layer (120).

[0174] The aspect ratio of the first recess (100r) can be determined by considering the thickness of the first conductive semiconductor layer (110) to be formed later, the film formation characteristics of the radiation source (200), etc.

[0175] Referring to FIG. 10c, a first conductive semiconductor material layer (110m) can be formed with a predetermined thickness on the inside of the first recess (100r) and the second recess (100re) and on the upper surface of the substrate (100).

[0176] The first conductive semiconductor material layer (110m) may be formed by any known method. For example, the first conductive semiconductor material layer (110m) may be formed by a method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). However, the present invention is not limited thereto. A person skilled in the art will be able to select an appropriate deposition method by considering the type of material to be deposited, the characteristics of the precursor or source, the required step coverage, etc.

[0177] The first conductive semiconductor material layer (110m) may be conformally formed within the first recess (110r). Here, the fact that the first conductive semiconductor material layer (110m) is conformally formed means that the first conductive semiconductor material layer (110m) is formed to conform to the shape of the surface of the substrate (100). That is, since the first conductive semiconductor material layer (110m) is formed with a substantially constant thickness, the shape of the first conductive semiconductor material layer (110m) may conform to the shape of the surface of the substrate (100) underneath. Therefore, an unfilled space exists in the first recess (110r) even after the first conductive semiconductor material layer (110m) is formed.

[0178] In some embodiments, a second recess (100re) having a smaller width than the first recess (100r) may have its upper end closed by the first conductive semiconductor material layer (110m). In some embodiments, the second recess (100re) may have its upper end closed by the first conductive semiconductor material layer (110m) and may have a void therein. In some embodiments, the second recess (100re) may be completely filled by the first conductive semiconductor material layer (110m).

[0179] The first conductive semiconductor material layer (110m) may be formed of the same material as the first conductive semiconductor layer (110) described above, and a detailed description thereof will be omitted herein. As described above, the first conductive semiconductor material layer (110m) may be doped with dopants of a desired conductive type. The second conductive semiconductor layer (120) and the first conductive semiconductor material layer (110m) may form a pn junction at least on the sidewalls of the first recess (110r) and the second recess (110re).

[0180] Referring to FIG. 10d, a radiation source material layer (200m) is formed on the unburied portion of the first recess (110r) and the upper surface of the first conductive semiconductor material layer (110m). For example, the radiation source material layer (200m) may be formed within the first recess (110r) so as to cover or bury at least a portion of the unburied portion of the first recess (110r). Although FIG. 10d illustrates that the unburied portion of the first recess (110r) is completely buried by the radiation source material layer (200m), the present invention is not limited thereto.

[0181] Optionally, the radiation source material layer (200m) may also be formed on the upper surface of the first conductive semiconductor material layer (110m). For example, the radiation source material layer (200m) may be formed along the first conductive semiconductor material layer (110m) so as to cover the upper surface of the first conductive semiconductor material layer (110m).

[0182] The above-described radiation source material layer (200 m) can be formed by any known method. For example, the above-described radiation source material layer (200 m) can be formed by a method such as PVD, CVD, or ALD. However, the present invention is not limited thereto. A person skilled in the art will be able to select an appropriate deposition method by considering the type of material to be deposited, the characteristics of the precursor or source, the required step coating, etc.

[0183] The above radiation source material layer (200 m) may be made of the same material as the radiation source (200) described above, and a detailed description thereof is omitted here.

[0184] The above radiation source material layer (200m) can fill the remaining space left after the first conductive semiconductor material layer (110m) is filled in the first recess (110r).

[0185] As described above, the second recess (110re) is completely filled or at least the entrance is closed by the first conductive semiconductor material layer (110m), so the radiation source material layer (200m) is not formed inside the second recess (110re).

[0186] Referring to FIG. 10e, the radiation source material layer (200m) and the first conductive semiconductor material layer (110m) are partially removed so that the upper surface of the substrate (100) is exposed.

[0187] In some embodiments, a portion of the radiation source material layer (200m) and the first conductive semiconductor material layer (110m) present on the upper surface of the substrate (100) may be removed.

[0188] The above radiation source material layer (200 m) and the first conductive semiconductor material layer (110 m) can be partially removed and planarized by dry etching, wet etching, and / or chemical mechanical polishing (CMP).

[0189] By the above flattening, the first conductive semiconductor material layer (110m) inside the second recess (110re) can become a preliminary reflector (115p).

[0190] Referring to FIG. 10f, the lower portion of the substrate (100) can be partially removed. The lower portion of the substrate (100) can be removed until the lower portion of the radiation source (200) is exposed.

[0191] The lower portion of the substrate (100) may be partially removed and planarized by dry etching, wet etching, and / or CMP. As the lower surface of the substrate (100) is removed, the lower portions of the first conductive semiconductor material layer (110m) and the radiation source material layer (200m) may be partially removed. By partially removing the lower portion of the substrate (100), the radiation source (200) penetrates the substrate (100).

[0192] By partially removing the lower portion of the above-described substrate (100), the first conductive semiconductor material layer (110m) inside the first recess (110r) can become the first conductive semiconductor layer (110), and the first conductive semiconductor material layer (110m) inside the second recess (110re) can become the reflector (115).

[0193] Referring to FIG. 10g, in order to form an isotope electrode sheet (10), a first upper electrode (132) and a first lower electrode (152) may be formed on the upper and lower portions of the first conductive semiconductor layer (110), respectively, and a second upper electrode (134) and a second lower electrode (154) may be formed on the upper and lower portions of the second conductive semiconductor layer (120), respectively.

[0194] The above electrodes (132, 152, 134, 154) may be formed, for example, through electrolytic plating or electroless plating. If necessary, only some of the electrodes (132, 152, 134, 154) may be formed.

[0195] Referring to FIG. 10h, the isotope electrode sheets (10) can be repeatedly stacked. The stacked isotope electrode sheets (10) can be electrically connected to each other by a connector (140).

[0196] In some embodiments, an insulator (160) may be provided between two adjacent isotope electrode sheets (10). The insulator (160) has been described above with reference to FIG. 1A, and thus a detailed description thereof is omitted here.

[0197] Afterwards, when the stacked plurality of isotope electrode sheets (10) are electrically connected and housed in a housing (190), a stacked isotope battery (1) as shown in FIG. 1a can be obtained.

[0198]

[0199] Figures 11a to 11h are side views showing a method for manufacturing a layered isotope battery (1) according to another embodiment of the present invention.

[0200] The layered isotope battery (1) described with reference to FIGS. 11a to 11h differs from the layered isotope battery (1) described with reference to FIGS. 10a to 10h in the configuration of the reflector (115), but the other configurations are generally the same. Therefore, the following description focuses on these differences.

[0201] Referring to Fig. 11a, a preliminary reflector (115p) is formed near the edge of the substrate (100).

[0202] The above preliminary reflector (115p) can be formed by first forming a second recess (110re) near the edge of the substrate (100), and then depositing and flattening a material layer of the preliminary reflector (115p) within the second recess (110re).

[0203] The above preliminary reflector (115p) may include fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), or silver (Ag) doped with a first conductive type dopant.

[0204] Referring to Fig. 11b, a plurality of first recesses (100r) can be formed in the substrate (100). The formation of the first recesses (110r) has been described with reference to Fig. 10b, so a detailed description thereof is omitted here.

[0205] Referring to FIG. 11c, a first conductive semiconductor material layer (110m) can be formed with a predetermined thickness on the inside of the first recess (100r) and the upper surface of the substrate (100) and the preliminary reflector (115p).

[0206] The first conductive semiconductor material layer (110m) may be formed by any known method. For example, the first conductive semiconductor material layer (110m) may be formed by a method such as PVD, CVD, or ALD. However, the present invention is not limited thereto. A person skilled in the art will be able to select an appropriate deposition method by considering the type of material to be deposited, the characteristics of the precursor or source, the required step coverage, etc.

[0207] Referring to FIG. 11d, a radiation source material layer (200m) is formed on the unburied portion of the first recess (110r) and the upper surface of the first conductive semiconductor material layer (110m).

[0208] The above-described radiation source material layer (200 m) can be formed by any known method. For example, the above-described radiation source material layer (200 m) can be formed by a method such as PVD, CVD, or ALD. However, the present invention is not limited thereto. A person skilled in the art will be able to select an appropriate deposition method by considering the type of material to be deposited, the characteristics of the precursor or source, the required step coating, etc.

[0209] Referring to FIG. 11e, the radiation source material layer (200m) and the first conductive semiconductor material layer (110m) are partially removed so that the upper surface of the substrate (100) is exposed.

[0210] The above radiation source material layer (200 m) and the first conductive semiconductor material layer (110 m) can be partially removed and planarized by dry etching, wet etching, and / or chemical mechanical polishing (CMP).

[0211] Referring to FIG. 11f, the lower portion of the substrate (100) can be partially removed. The lower surface of the substrate (100) can be removed until the lower surface of the radiation source (200) is exposed.

[0212] The lower portion of the substrate (100) may be partially removed and planarized by dry etching, wet etching, and / or CMP. As the lower portion of the substrate (100) is removed, the lower portions of the first conductive semiconductor material layer (110m) and the radiation source material layer (200m) may be partially removed.

[0213] Referring to FIG. 11g, in order to form an isotope electrode sheet (10), a first upper electrode (132) and a first lower electrode (152) may be formed on the upper and lower portions of the first conductive semiconductor layer (110), respectively, and a second upper electrode (134) and a second lower electrode (154) may be formed on the upper and lower portions of the second conductive semiconductor layer (120), respectively.

[0214] Referring to FIG. 11h, the isotope electrode sheets (10) can be repeatedly stacked. The stacked isotope electrode sheets (10) can be electrically connected to each other by a connector (140).

[0215] Afterwards, a plurality of stacked isotope electrode sheets (10) are electrically connected and housed in a housing (190), thereby obtaining a stacked isotope battery (1).

[0216] Since fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), or silver (Ag) doped with a first-challenge dopant are used as a reflector (115), they can be used to reflect electrons emitted from a radiation source and generate EHP again.

[0217] Fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), and silver (Ag) can be used as materials for optical devices such as Brewster's windows. These materials can effectively reflect electrons emitted from a radiation source and increase the efficiency of EHP generation.

[0218]

[0219] While the embodiments of the present invention have been described in detail above, those skilled in the art will appreciate that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention as defined in the appended claims. Therefore, modifications to future embodiments of the present invention will not depart from the scope of the invention.

Claims

1. A first external electrode of a first polarity and a second external electrode of a second polarity electrically connected to the plurality of isotope electrode sheets so as to transmit electric energy generated from the plurality of stacked isotope electrode sheets to an external load; Including, Each of the above multiple isotope electrode sheets: write; An isotope battery unit provided within the above description; and A reflector provided close to the edge of the above description; A layered isotope battery comprising:

2. In paragraph 1, The above isotope battery unit: A radiation source extending in the thickness direction of the above-described material; and A first conductive semiconductor layer provided between the radiation source and the substrate; A layered isotope battery characterized by including:

3. In paragraph 1, The first conductive semiconductor layer is configured to surround a side surface of the radiation source, A laminated isotope battery, characterized in that the above isotope battery unit further includes a second conductive semiconductor layer on a side of the first conductive semiconductor layer.

4. In paragraph 3, A layered isotope battery, characterized in that the reflector has substantially the same conductivity type as the first conductive semiconductor layer.

5. In paragraph 4, A layered isotope battery, characterized in that the reflector has substantially the same composition as the first conductive semiconductor layer.

6. In paragraph 3, A layered isotope cell characterized in that the reflector extends in the thickness direction of the substrate and is configured to reflect minority carriers.

7. In paragraph 6, A layered isotope cell characterized in that the reflector comprises InAlP, InGaP, InAlGaP, ZnSe, AlAs, or AlAsP doped with a first conductive type dopant.

8. In paragraph 6, A layered isotope cell characterized in that the reflector comprises fused silica, sapphire, calcium fluoride (CaF2), magnesium fluoride (MgF2), BK7 glass, zinc selenide (ZnSe), germanium telluride (GeTe), molybdenum (Mo), or silver (Ag) doped with a first conductive dopant.

9. In paragraph 6, A layered isotope cell characterized in that the reflector comprises a layer lattice-matched to the substrate.

10. In paragraph 3, The above description is a layered isotope battery characterized by including a III-V group semiconductor material.

11. In paragraph 2, The above description is a semiconductor description, A layered isotope battery characterized in that the first conductive semiconductor layer comprises AMO3. (wherein A is at least one selected from the group consisting of La, Ba, Sr, and K, and M is at least one selected from the group consisting of Al, In, Ga, Ti, Sn, Hf, Ta, and Zr) 12. In paragraph 11, The first conductive semiconductor layer is BaSnO3, BaHfO3, BaZrO3, BaHf 1-x Ti x O3 (where 0 <x<1), Ba 1-x La x SnO3 (where 0 <x<1), Bi4Ge3O 12 , Al2O3, Y2O3, La2O3, Ga2O3, Bi2O3, ZrO2, HfO2, Ta2O5, TiO2, LaInO3, LaGaO3, SrZrO3, SrHfO3, SrTaO7, LaIn 1-x Ga x O3 (where 0 <x<1), LaGaO3, SrTiO3, KTaO3, HfSiO4, Ta3Ti2O x A layered isotope battery characterized in that it comprises at least one selected from the group consisting of LaAlO3.

13. In paragraph 11, A layered isotope cell characterized in that the semiconductor substrate comprises a diamond substrate, a SiC substrate, a GaN substrate, a Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / GeO2 substrate, a Sm2O3 / Bi2O3 / B2O3 substrate, a Sm2O3 / Bi2O3 / GeO2 / B2O3 substrate, a sapphire substrate, or a combination thereof.

14. In paragraph 2, A layered isotope battery characterized in that the radiation source is arranged within a through-hole penetrating the substrate.

15. In paragraph 14, A layered isotope battery characterized in that the above-mentioned device includes a plurality of through-holes, and the radiation source is provided inside each of the plurality of through-holes.

16. In paragraph 15, A stacked isotope battery characterized in that the plurality of through-holes are arranged in the substrate so that each center is located at a vertex of an imaginary equilateral triangle.

17. In paragraph 2, A layered isotope cell characterized in that the radiation source is positioned within a slit penetrating the substrate.

18. In paragraph 17, A layered isotope cell characterized in that the above-mentioned substrate includes a plurality of slits, and the radiation source is provided inside each of the plurality of slits.

19. In paragraph 17, A layered isotope battery characterized in that the first conductive semiconductor layer is arranged to face the elongated side of the radiation source, and the substrate is arranged to face the elongated side of the first conductive semiconductor layer.

20. In paragraph 1, A laminated isotope battery characterized in that the plurality of laminated isotope electrode sheets are identical dies.

21. In paragraph 1, A laminated isotope battery characterized in that the above laminated plurality of isotope electrode sheets are electrically connected to each other by solder balls.

22. In paragraph 1, A laminated isotope battery characterized in that the above laminated plurality of isotope electrode sheets are molded using a molding resin.

23. In paragraph 1, The above radiation sources are: a first portion provided within a trench extending along one surface of the above-described substrate; and A second portion extending from the bottom surface of the trench to the other surface of the semiconductor substrate; A layered isotope battery characterized by including: