Alignment pitch quartering patterning for advance correction of lithographic edge placement error

Abstract

Alignment pitch quartering patterning approaches for optical lithography edge placement error pre-correction are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A separate diblock copolymer is formed on the first patterned hardmask and on the second hardmask layer. A second polymer block is removed from the separate diblock copolymer. A second patterned hardmask is formed from the second hardmask layer, and a plurality of semiconductor fins is formed in the semiconductor substrate using the first polymer block as a mask. A first fin of the plurality of semiconductor fins is removed. After the first fin is removed, a second fin of the plurality of semiconductor fins is removed.

Description

Technical Field

[0001] The embodiments of the present invention are in the field of semiconductor devices and processes, and more particularly in the field of nonplanar semiconductor devices and methods of manufacturing nonplanar semiconductor devices. Background Technology

[0002] Over the past few decades, scaling features in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling to increasingly smaller features enables increased density of functional units on a limited realate area of ​​a semiconductor chip. For example, shrinking transistor size allows for the combination of an increased number of memory or logic devices on a single chip, thus providing greater capacity for product fabrication. However, this push for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors (such as tri-gate transistors) have become more prevalent as device dimensions continue to shrink proportionally. Tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates in conventional processes. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-volume bulk silicon substrate infrastructure.

[0004] However, scaling multi-gate transistors has not been without results. As the size of these basic building blocks of microelectronic circuits is reduced and as the absolute number of basic building blocks fabricated in a given area increases, the limitations on the semiconductor processes used to fabricate these building blocks have become prominent. Attached Figure Description

[0005] Figure 1A-1N Cross-sectional views are shown of various operations in a method of fabricating a nonplanar semiconductor device according to an embodiment of the present invention, wherein:

[0006] Figure 1A This shows a bulk semiconductor substrate on which a first patterned hard mask is formed;

[0007] Figure 1B This is shown after the formation of a second hard mask layer between the first patterned hard masks. Figure 1A The structure;

[0008] Figure 1C This shows the effect after applying a selective brush material layer. Figure 1B The structure;

[0009] Figure 1D This illustrates the effect after applying the Direct Self-Assembly (DSA) block copolymer and polymer assembly process. Figure 1C The structure;

[0010] Figure 1E This shows the result after removing one of the blocks of the diblock copolymer. Figure 1D The structure;

[0011] Figure 1F This illustrates the process after the pattern of the remaining polymer portion is transferred onto a base robust crystalline semiconductor substrate. Figure 1E The structure;

[0012] Figure 1G This shows the result after removing the remaining polymer layer and any brush layers. Figure 1F The structure;

[0013] Figure 1H This illustrates the process after forming an interlayer dielectric (ILD) layer between multiple fins. Figure 1G The structure;

[0014] Figure 1I This illustrates the formation and patterning of a photoresist material applied to form a patterned mask. Figure 1H The structure;

[0015] Figure 1J This shows the result of etching selected fins from a plurality of fins. Figure 1I The structure;

[0016] Figure 1K This illustrates the formation and patterning of the photoresist material used to form the patterned mask. Figure 1J The structure;

[0017] Figure 1L This shows the result of etching a selected second fin among multiple fins. Figure 1K The structure;

[0018] Figure 1M This illustrates the process after removing the patterned mask and forming an interlayer dielectric (ILD) layer over and at the locations of the removed fins. Figure 1L The structure; and

[0019] Figure 1N This shows the result after planarizing the ILD layer and removing the first and second patterned hard masks. Figure 1M The structure.

[0020] Figure 2 The diagram illustrates the upper portion of multiple fins after exposure, according to an embodiment of the invention. Figure 1N The structure.

[0021] Figure 3A A cross-sectional view of a non-planar semiconductor device according to an embodiment of the present invention is shown.

[0022] Figure 3BThe following is illustrated according to an embodiment of the invention: along Figure 3A A plan view of the semiconductor device along the a-a' axis.

[0023] Figure 4 A computing device according to an embodiment of the present invention is shown.

[0024] Figure 5 An interpolator including one or more embodiments of the present invention is shown. Detailed Implementation

[0025] A patterning method for pre-correcting lithographic edge placement errors, involving four equal divisions of the alignment pitch, is described. In the following description, numerous specific details (e.g., particular integration and material systems) are set forth to provide a thorough understanding of embodiments of the invention. It will be apparent to those skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of the invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0026] One or more embodiments described herein pertain to processes and structures based on and generated from an aligned pitch quadrature patterning method for edge placement error (EPE) correction. One or more embodiments can be described as a differentiation or “shading” alternating hard mask method for semiconductor fin patterning. Embodiments may include one or more of the following: directional self-assembly (DSA), semiconductor material patterning, pitch division such as pitch quadrature, differentiation hard mask selectivity, and self-alignment for fin patterning. One or more embodiments are particularly suitable for the fabrication of non-planar semiconductor devices.

[0027] According to embodiments of the invention, a doubling of the permissible edge placement error and a doubling of the cut size for cutting small features at close pitches are implemented for ultra-fine fin patterning. In one embodiment, all features (e.g., fin lines) are transferred to the semiconductor substrate via a single population with varying critical dimensions (CD). This approach contrasts with prior art methods that rely on spacer-based pitch quadrating, which typically have three discrete populations of linewidth (e.g., backbone, complement, and spacer dimensions).

[0028] To provide context, bulk silicon may be used for fins or tri-gate based semiconductor devices. In embodiments, directional self-assembly (DSA) is implemented to achieve pitch division and “coloring” for each other feature in the desired pattern. In one such embodiment, the patterning approach is particularly suitable for patterning silicon fins in a tri-gate transition patterning process. In embodiments, advantages of implementing the approach described herein may include one or more of the following: (1) the ability to achieve a single group of feature widths, (2) doubling the edge placement error requirements for feature cutting, (3) doubling the size of the holes or openings required for cutting individual features (e.g., relaxing constraints on opening size), or (4) reducing the cost of the patterning process. In embodiments, the structural article of manufacture produced in this process comprises a single group of critical dimensions and is situated in a protective ring around the die of the chip, transitioning from one pitch to another and / or from one grid to another. Embodiments may enable the cutting of tight pitch lines without scaling edge placement error requirements.

[0029] In the demonstration treatment plan, Figure 1A-1N Cross-sectional views are shown of various operations in a method for fabricating a nonplanar semiconductor device according to an embodiment of the present invention.

[0030] Figure 1A This illustrates a bulk semiconductor substrate 102 on which a first patterned hard mask 104 has been formed. In an embodiment, the bulk semiconductor substrate 102 is a bulk single-crystal silicon substrate configured such that fins 102 have been etched therein. In one embodiment, the bulk semiconductor substrate 102 is undoped or lightly doped at this stage. For example, in a specific embodiment, the bulk semiconductor substrate 102 has a density of less than approximately 1E17 atom / cm². 3 Concentration of boron dopant impurity atoms.

[0031] In an embodiment, the first patterned hard mask 104 includes features having a pitch 106. In one such embodiment, the first patterned hard mask 104 represents half the possible number of fins that will eventually be formed in the substrate 102. That is, the pitch 106 is effectively widened to twice the pitch of the final pattern of the formed fins. In one embodiment, the first hard mask 104 is patterned directly using a photolithography process. However, in other embodiments, pitch division is applied (e.g., pitch bisection) and used to provide the pitch 106 for the patterned hard mask 104. It should be understood that in the embodiments, the first guide pattern can be formed using conventional patterning (photolithography / etching), photolithography only, spacer-based dual patterning, or other pitch division methods. In one embodiment, the guide pattern is separated from the DSA pattern by the use of two or more hard masks, such that the CD is formed from a single group (e.g., a single etching).

[0032] Figure 1B This shows the second hard mask layer 108 formed between the first patterned hard masks 104. Figure 1A The structure is as follows. In one embodiment, a cover hard mask layer is formed over a substrate 102 and a first patterned hard mask 104, and then the cover hard mask layer is planarized to form a second hard mask layer 108 (e.g., by chemical mechanical planarization (CMP)). In other embodiments, ALD or CVD techniques are applied along the contours of the wafer surface, and since fin cutting is used as an example, this point in the wafer process is "completely" flat.

[0033] In one embodiment, the second hard mask layer 108 has etch characteristics different from those of the first patterned hard mask 104. In one embodiment, one or both of the second hard mask layer 108 or the first patterned hard mask 104 are silicon nitride (e.g., silicon nitride) layers or silicon oxide layers, or both or combinations thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, the hard mask material includes metals. For example, the hard mask or another overlay material may include titanium nitride (e.g., titanium nitride) layers or another metal. Potentially, smaller amounts of other materials (e.g., oxygen) may be included in one or more of these layers. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0034] Figure 1C This shows the effect after applying the selective brush material layer 110. Figure 1B The structure. In an embodiment, the selective brush material layer 110 is attached only to the first patterned hard mask 104, such as... Figure 1C As depicted. However, in another embodiment, a selective brush material is instead applied to the second hard mask layer 108. In yet another embodiment, the selective brush material layer 110 is attached only to the first patterned hard mask 104, and a second, different selective brush material is formed on the second hard mask layer 108.

[0035] In one embodiment, the selective brush material layer 110 includes molecular types comprising polystyrene having a head group selected from groups composed of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3. In another embodiment, the selective brush material layer 110 includes molecular types comprising polymethyl methacrylate having a head group selected from groups composed of -SH, -PO3H2, -CO2H, -NRH, -NRR', and -Si(OR)3. In this embodiment, the selective brush material layer 110 is attracted to a component of a DSA block copolymer (e.g., polystyrene or polymethyl methacrylate).

[0036] Figure 1D This illustrates the application of Direct Self-Assembly (DSA) block copolymer 114 / 116 (A / B) and the polymer assembly process. Figure 1C The structure. In an embodiment, the DSA block copolymer is coated on the surface and annealed to separate the polymer into a first block 114 and a second block 116 ( Figure 1D (Identified as 116A and 116B). In one embodiment, polymer blocks 116 are preferably attached to the selective brush material layer 110 during the annealing process. Second polymer blocks 114 are attached to the second hard mask layer 108. However, in a particular embodiment, the assembly pitch is half the pitch of the first patterned hard mask 104. In this case, a portion 116A of the first block is attached to the selective brush material layer 110 of the first hard mask 104, while a second portion 116B of the first block is formed between the second block portions 114 on the second hard mask layer 108.

[0037] In the embodiments, block copolymer molecules 114 / 116 (A / B) are polymeric molecules formed from covalently bonded monomer chains. In a diblock copolymer, two different types of monomers are present, and these different types of monomers are primarily contained within two different blocks or adjacent sequences of the monomers. The block copolymer molecules shown include polymer blocks 114 and polymer blocks 116 (A / B). In the embodiments, polymer block 114 is most notably composed of chains covalently linked to monomer A (e.g., AAAAA…), while polymer block 116 (A / B) is most notably composed of chains covalently linked to monomer B (e.g., BBBBB…). Monomers A and B may represent any of the different types of monomers known in the art used in block copolymers. As an example, monomer A may represent a monomer that forms polystyrene, and monomer B may represent a monomer that forms polymethyl methacrylate (PMMA), or vice versa, but the scope of the invention is not limited thereto. In other embodiments, more than two blocks may be present. Furthermore, in other embodiments, each of the blocks may include a different type of monomer (e.g., each block itself may be a copolymer). In one embodiment, polymer blocks 114 and 116 (A / B) are covalently bonded together. Polymer blocks 114 and 116 (A / B) may be of approximately equal length, or one block may be significantly longer than the other.

[0038] Typically, the blocks of a block copolymer (e.g., polymer block 114 and polymer block 116 (A / B)) can each have different chemical properties. As an example, one block can be relatively more hydrophobic (e.g., waterproof), while the other can be relatively more hydrophilic (e.g., hygroscopic). At least conceptually, one block can be relatively more similar to oil, while the other block can be relatively more similar to water. Such differences in chemical properties between different polymer blocks (whether hydrophilic-hydrophobic or otherwise) can enable the block copolymer molecules to self-assemble. For example, self-assembly can be based on microphase separation of the polymer blocks. Conceptually, this can be similar to the phase separation of oil and water (which are generally immiscible). Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and the other is relatively hydrophilic) can cause roughly similar microphase separation, where different polymer blocks attempt to “separate” from each other due to chemical aversion to the other block.

[0039] However, in the embodiments, because the polymer blocks are covalently bonded to each other, they cannot be completely separated at the macroscopic level. Instead, a given type of polymer block tends to separate or aggregate with polymer blocks of other molecules of the same type in extremely small (e.g., nanoscale) regions or phases. The specific size and shape of the region or microphase generally depend, at least in part, on the relative lengths of the polymer blocks. In the embodiments, as an example, in two block copolymers, if the blocks are of approximately the same length, a grid-like pattern of alternating polymer 114 lines and polymer 116 (A / B) lines is generated.

[0040] In an embodiment, the polymer 114 / polymer 116 (A / B) grating is first applied as an unassembled block copolymer layer portion, which comprises block copolymer material applied, for example, by brushing or another coating process. The unassembled aspect refers to a situation where, at the deposition time, the block copolymer has not yet undergone substantial phase separation and / or self-assembly to form a nanostructure. In this unassembled form, the block polymer molecules are relatively highly randomized, with the different polymer blocks being relatively highly randomly oriented and positioned. The unassembled block copolymer layer portion can be applied in a variety of different ways. As an example, the block copolymer can be dissolved in a solvent and then spin-coated onto a surface. Alternatively, the unassembled block copolymer can be sprayed, dip-coated, impregnated, or otherwise coated or applied to a surface. Potentially, other methods of applying block copolymers, as well as other methods known in the art for applying similar organic coatings, can be used. The unassembled layer can then be assembled into an assembled block copolymer layer portion, for example, through microphase separation and / or self-assembly of the unassembled block copolymer layer portion. Microphase separation and / or self-assembly occur through the rearrangement and / or repositioning of block copolymer molecules, and more specifically, the rearrangement and / or repositioning of different polymer blocks of the block copolymer molecules.

[0041] In one such embodiment, annealing can be applied to unassembled block copolymers to initiate, accelerate, improve quality, or otherwise promote microphase separation and / or self-assembly. In some embodiments, annealing may include processing operable to increase the temperature of the block copolymer. An example of such processing is baking the layer, heating the layer in an oven or under a heat lamp, applying infrared radiation to the layer, or otherwise applying heat to the layer or increasing the temperature of the layer. The expected temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and / or self-assembly of the block polymer without damaging the block copolymer or any other critical material or structure of the integrated circuit substrate. Typically, heating can be in the range of about 50°C to about 300°C or about 75°C to about 250°C, but not exceeding the thermal degradation limit of the block copolymer or the integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules, making them more mobile / flexible, thereby increasing the rate of microphase separation and / or improving the quality of microphase separation. The rearrangement / repositioning of block copolymer molecules or this microphase separation can induce self-assembly to form extremely small (e.g., nanoscale) structures. Self-assembly can occur under the influence of surface energy, molecular affinity, and other surface-dependent and chemically dependent forces.

[0042] In any case, in some embodiments, the self-assembly of the block copolymer (whether based on hydrophobic-hydrophilic differences or otherwise) can be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures or lines). In some embodiments, they can be used to form nanoscale lines or other nanoscale structures that can ultimately be used to form semiconductor fin lines.

[0043] Figure 1E The diagram shows the result after removing one of the blocks of the diblock copolymer. Figure 1D The structure is as follows. In an embodiment, polymer portion 114 is selectively removed by a wet or dry etching process to leave portion 116 (A / B). The pitch of the remaining portion 116 (A / B) is approximately half the pitch of the first patterned hard mask 104.

[0044] Figure 1F This illustrates the process after the pattern of the remaining polymer portion is transferred onto the underlying robust crystalline semiconductor substrate. Figure 1E The structure is as follows. In an embodiment, the pattern of the remaining polymer portions 116 (A / B) (i.e., the pattern of the first patterned hard mask 104, which is bisected by pitch) is etched into the bulk semiconductor substrate 102. Patterning is performed on the second hard mask layer 108 to form a second patterned hard mask layer 124 corresponding to the polymer portion 116B. The first patterned hard mask 104 corresponds to the polymer portion 116A. In an embodiment, a plurality of fins 118 are formed directly in the bulk substrate 102, which becomes a patterned substrate 120, and is thus formed on a generally flat surface 122 in a manner continuous with the bulk substrate 102 / 120.

[0045] Figure 1G This shows the result after removing the remaining polymer layer and any brush layers. Figure 1F The structure is as follows. In one embodiment, the remaining polymer layers 116 (A / B) and brush layers 110 are removed to leave a plurality of alternating fins 118 having an alternatingly “colored” first patterned hard mask 104 and a second patterned hard mask 124 thereon. In one embodiment, an ashing and cleaning process is used to remove the remaining polymer layers 116 (A / B) and brush layers 110. The resulting pitch 126 of the fins is half the pitch 106 of the original first patterned hard mask 104.

[0046] Figure 1H This illustrates the process after forming an interlayer dielectric (ILD) layer 128 between multiple fins. Figure 1GThe structure is as follows. In this embodiment, the ILD layer 128 is composed of silicon dioxide (e.g., used in shallow trench isolation fabrication). However, other dielectrics, such as carbide nitrides, may be used instead. The ILD layer 128 may be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD) and may be planarized by chemical mechanical polishing (CMP) to reveal the uppermost surfaces of the hard mask layers 104 and 128.

[0047] Figure 1I This illustrates the process of forming and patterning photoresist material to create a patterned mask 130. Figure 1H The structure is as follows. In an embodiment, the patterned mask 130 has an opening 132 formed therein. The opening 132 exposes target fins of a plurality of fins 118 having a first patterned hard mask 104 on which final fin removal is applied. The opening 132 has a cut size 136. In an embodiment, the constraint on the cut size 136 is relaxed, and even portions of adjacent fins having a second patterned hard mask 124 thereon can be exposed. In an embodiment, the patterning operation prepares to use “shading” or hard mask material differentiation to cut away unwanted features, allowing the cut size to be twice the pitch 126 of the feature 118 (i.e., producing the original pitch 106). In one embodiment, the hard mask material allows selective differentiation by plasma or wet etching between two hard mask materials. Furthermore, the edge placement error (EPE) 134 is half the pitch. By comparison, in a standard patterning process without shading, the cut size is 1 x pitch, and the edge placement error (EPE) is 1 / 4 pitch. Therefore, in the embodiments, the process described herein doubles the edge placement error budget and doubles the size of the hole or opening required to cut a single feature.

[0048] In one embodiment, the patterned mask 130 is composed of a photoresist layer (as known in the art) and can be patterned by conventional photolithography and development processes. In a specific embodiment, portions of the photoresist layer exposed to the light source are removed during development of the photoresist layer. Therefore, the patterned photoresist layer is composed of a positive photoresist material. In a particular embodiment, the photoresist layer is composed of a positive photoresist material (such as, but not limited to, 248 nm, 193 nm, 157 nm, far-ultraviolet (EUV), electron beam, imprinted layers, or a phenolic resin matrix having a diazonaphthoquinone sensitizer). In another particular embodiment, portions of the photoresist layer exposed to the light source are retained during development of the photoresist layer. Therefore, the photoresist layer is composed of a negative photoresist material. In certain embodiments, the photoresist layer is composed of a negative photoresist material (such as, but not limited to, cis-polyisoprene or polyvinyl cinnamate). In embodiments, lithography is performed using 193 nm immersion lithography (193i), EUV and / or EBDW lithography, or similar methods. Positive or negative tint resists can be used. In one embodiment, the patterned mask 130 is a three-layer mask consisting of an x-ray topographic shielding portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the x-ray topographic shielding portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon-containing ARC layer. In one embodiment of this type, spun glass materials with added chromophores are used to help suppress reflectivity. Chemically, they are (siloxane) silicon-containing carbon polymers. Upon annealing, they form a mixture of silicon dioxide and carbon polymers.

[0049] Figure 1J This shows selected fins among multiple fins 118 etched and subsequently removed from the patterned mask 130. Figure 1IThe structure is described. In one embodiment, this process is referred to as a “fin cutting” or “feature selection” operation. In one embodiment, one of the plurality of fins 118 is removed at position 138 to form a patterned plurality of fins 118' with a first interruption pattern. In one such embodiment, the exposed first patterned hard mask 104 is first removed using an etching process that is optional for any exposed second patterned hard mask 124 and optional for the ILD layer 128. In another embodiment, a “fin holding” approach is used, where features are selected using opposite hues of a photoresist and are protected during the etching process while removing the background or unprotected fins. It is the opposite polarity of the photolithography process (e.g., negative versus positive hue imaging). It should be understood that either process can be used in this operation. The exposed fins are then removed at position 138 using an etching process that is optional for the exposed second patterned hard mask 124 and optional for the ILD layer 128. In a first embodiment, the fin is removed at position 138 to level 140, leaving a protrusion 146 above the flat surface 122. In a second embodiment, the fin is removed at position 138 to level 142, which is substantially coplanar with the flat surface 122. In a third embodiment, the fin is removed at position 138 to level 144, leaving a notch 148 below the flat surface 122.

[0050] Figure 1K This illustrates the formation and patterning of photoresist material to form a patterned mask 150. Figure 1J The structure is as follows. In an embodiment, the patterned mask 150 has an opening 152 formed therein. The opening 152 exposes a plurality of target second fins 118', on which a second patterned hard mask 124 is applied for final fin removal. In an embodiment, the patterning operation prepares to use "shading" or hard mask material differentiation to cut away unwanted features, allowing the cut size to be twice the pitch 126 of the features 118'. (As in combination...) Figure 1I The process described herein doubles the edge placement error budget and doubles the size of the hole or opening required to cut a single feature. In an embodiment, the patterned mask 150 is, for example, combined with... Figure 1I The materials described herein constitute the composition.

[0051] Figure 1L This shows the selected second fin after etching multiple fins 118'. Figure 1KThe structure. In an embodiment, the second fins of the plurality of fins 118' are removed at position 154 to form a patterned plurality of fins 118' with a second interruption pattern. In one such embodiment, the exposed second patterned hard mask 124 is first removed using an etching process that is optional for any exposed first patterned hard mask 104 and optional for the ILD layer 128. The exposed fins are then removed at position 154 using an etching process that is optional for exposed first patterned hard mask 104 and optional for the ILD layer 128. In a first embodiment, the fins are removed at position 154 into the water. In the first embodiment, the fin is removed at position 154 to level 158, leaving a protrusion 164 above the flat surface 122 at a height approximately the same as the surface 140 of the protrusion 146. In the second embodiment, the fin is removed at position 154 to level 160, which is approximately coplanar with the flat surface 122. In the fourth embodiment, the fin is removed at position 154 to level 162, leaving a notch 166 below the flat surface 122.

[0052] Figure 1M The diagram illustrates the removal of the patterned mask 150 and the formation of an interlayer dielectric (ILD) layer 168 on the plurality of fins 118” and at locations 138 and 154 of the removed fins. Figure 1L The structure is as follows. In this embodiment, the ILD layer 168 is composed of silicon dioxide (e.g., used in shallow trench isolation fabrication). However, other dielectrics, such as nitrides or carbides, can be used alternatively. The ILD layer 168 can be deposited by chemical vapor deposition (CVD) or other deposition processes (e.g., ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD). Spinning materials are another common option for these films. Many low-k dielectric materials can be spin-formed onto wafers and cured. These are commonly used in industry.

[0053] Figure 1N This illustrates the planarization of ILD layer 168 and the removal of the first and second patterned hard masks 104 and 124. Figure 1MThe structure is as follows. In an embodiment, chemical mechanical polishing (CMP) is used to remove the first patterned hard mask 104 and the second hard mask 124 to recess ILD layers 128 and 168 to form planarized ILD layers 128' and 168', respectively, and expose the surfaces of the plurality of fins 118'". In an embodiment, the planarized ILD layer 128' is composed of substantially the same material as the planarized ILD layer 168'. In another embodiment, the planarized ILD layer 128' is composed of a different material than the planarized ILD layer 168'. In either case, in the embodiment, a seam is formed between ILD layer 168' and ILD layer 128' (e.g., at location 138 or 154). It should be understood that, in the embodiment, the exposed surfaces of the plurality of fins 118' are capable of being used with the formed planar semiconductor device.

[0054] However, according to another embodiment, Figure 2 Showing the upper portion after exposing multiple fins 118” Figure 1N The structure. (Refer to...) Figure 2 ILD layers 168' and 128' are recessed to expose the protruding portion 172 of fin 118', and the recessed ILD layers 168' and 128' are provided with a notch height 176. The notch height 176 defines the position between the upper fin portion 172 and the lower fin portion 174. The recesses of ILD layers 168' and 128' can be performed by plasma, steam, or wet etching processes. In one embodiment, an optional dry etching process is used on the silicon fin 118', which is based on plasma generated from gases such as, but not limited to, NF3, CHF3, C4F8, HBr, and O2, and typically employs a pressure in the range of 30-100 mTorr and a plasma bias of 50-1000 watts.

[0055] In the exemplary embodiment, refer again Figure 1J , Figure 1L and Figure 2 The semiconductor structure includes a plurality of semiconductor fins 118” protruding from a generally flat surface 122 of a semiconductor substrate 120. The plurality of semiconductor fins 118” have a lattice pattern interrupted by a first position 138 having a first fin portion 146 (which has a first height). The lattice pattern of the semiconductor fins is also interrupted by a second position 154 having a second fin portion 164 (which has a second height). In one embodiment, the second height of the second fin portion 154 is different from the first height of the first fin portion 146. In another embodiment, the second height of the second fin portion 154 is the same as the first height of the first fin portion 146. In this embodiment, the lattice pattern has a constant pitch 126 when viewed without interruption.

[0056] In the exemplary embodiment, refer again Figure 1J , Figure 1L and Figure 2 The semiconductor structure includes a plurality of semiconductor fins 118” protruding from a generally flat surface 122 of a semiconductor substrate 120. The plurality of semiconductor fins 118” have a lattice pattern interrupted by a first location 138 (which has a first notch). In one embodiment, the lattice pattern of the semiconductor fins is also interrupted by a second location 154 (which has a second notch or one of the fin portions). In an embodiment, the lattice pattern has a constant pitch 126 when viewed without interruption. In an embodiment, a trench isolation layer 168” is disposed in and on the notch.

[0057] To understand, the structure arising from the above-described exemplary treatment scheme (e.g., from...) Figure 1N and Figure 2 The structure of these devices can be used in the same or similar forms for subsequent processing operations to complete device fabrication (e.g., PMOS and NMOS device fabrication). As an example of a completed device, Figure 3A and Figure 3B Cross-sectional and planar views (taken along the a-a' axis of the cross-section) of a non-planar semiconductor device according to an embodiment of the present invention are shown respectively.

[0058] Reference Figure 3A The semiconductor structure or device 300 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 304 and a sub-fin region 305) formed from a substrate 302 within an isolation region 306. A gate line 308 is disposed over the protruding portion 304 of the non-planar active region and over a portion of the isolation region 306. As shown, the gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, the gate line 308 may also include a dielectric protective layer 354. This perspective view also shows gate contacts 314 and superimposed gate contact vias 316, along with superimposed metal interconnects 360, all disposed within an interlayer dielectric stack or layer 370. Figure 3A The perspective view also shows that, in one embodiment, the gate contact 314 is disposed above the isolation region 306, but not above the non-planar active region.

[0059] like Figure 3A The text also describes an embodiment where, in some cases, the fins are chosen to be recessed and retained in the final structure. For example, in the illustrated embodiment, the residual protrusion 399 is retained. In other embodiments, the notch may be retained, as described above.

[0060] like Figure 3AThe text also describes an embodiment where an interface 380 exists between the protruding fin portion 304 and the sub-fin region 305. The interface 380 can be a transition region between the doped sub-fin region 305 and the lightly or undoped fin portion 304. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is provided at the sub-fin location from an adjacent solid-state doped layer.

[0061] Reference Figure 3B Gate line 308 is shown disposed above protruding fin portion 304. Source and drain regions 304A, 304B of protruding fin portion 304 can be seen from this perspective view. In one embodiment, source and drain regions 304A, 304B are doped portions of the original material of protruding fin portion 304. In another embodiment, the material of protruding fin portion 304 is removed and replaced with another semiconductor material, for example, by epitaxial deposition. In either case, source and drain regions 304A and 304B may extend below the height of dielectric layer 306, i.e., into sub-fin region 305. According to embodiments of the invention, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 380) prevents source-to-drain leakage through this portion of the bulk semiconductor fin.

[0062] In one embodiment, the semiconductor structure or device 300 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In this embodiment, the corresponding semiconducting channel region is composed of or formed within a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 308 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0063] Substrate 302 may be composed of a semiconductor material capable of withstanding the manufacturing process and in which charge can migrate. In an embodiment, substrate 302 is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof) to form active region 304. In one embodiment, the concentration of silicon atoms in bulk substrate 302 is greater than 97%. In another embodiment, bulk substrate 302 is composed of an epitaxial layer grown on top of a different crystalline substrate (e.g., a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). Bulk substrate 302 may alternatively be composed of a III-V material. In an embodiment, bulk substrate 302 is composed of a III-V material (such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof). In one embodiment, the bulk substrate 302 is composed of a III-V material, and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0064] The isolation region 306 may be composed of a material suitable for final electrical isolation or for isolating a portion of a permanent gate structure from the base substrate, or for isolating active regions formed within the base substrate (e.g., isolation fin active regions). For example, in one embodiment, the isolation region 306 is composed of a dielectric material (such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride).

[0065] Gate line 308 may be composed of a gate electrode stack (which includes a gate dielectric layer 352 and a gate electrode layer 350). In an embodiment, the gate electrodes of the gate electrode stack are composed of metal gates, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a metal (such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead strontium tantalum oxide, lead zinc niobate, or combinations thereof). Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed from the top layers of the substrate 302. In an embodiment, the gate dielectric layer consists of a top high-k portion and a bottom portion (composed of an oxide of a semiconductor material). In one embodiment, the gate dielectric layer consists of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure, which includes a bottom portion that is generally parallel to the surface of the substrate and two sidewall portions that are generally perpendicular to the top surface of the substrate.

[0066] In one embodiment, the gate electrode is composed of a metal layer (such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides). In a particular embodiment, the gate electrode is composed of a non-work function set filler material (which is formed over a metal work function set layer). The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor will be a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filler layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). A P-type metal layer will enable the formation of a PMOS gate electrode having a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between approximately 3.9 eV and approximately 4.2 eV. In some implementations, the gate electrode may consist of a U-shaped structure including a bottom portion generally parallel to the surface of the substrate and two sidewall portions (generally perpendicular to the top surface of the substrate). In another implementation, at least one of the metal layers forming the gate electrode may be a planar layer, generally parallel to the top surface of the substrate, and excluding the sidewall portions generally perpendicular to the top surface of the substrate. In other implementations of the invention, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers (formed on top of one or more planar non-U-shaped layers).

[0067] The spacers associated with the gate electrode stack may be composed of materials suitable for final electrical isolation or for facilitating the isolation of the permanent gate structure from adjacent conductive contacts (e.g., self-aligning contacts). For example, in one embodiment, the spacers are composed of dielectric materials such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0068] The gate contact 314 and the superimposed gate contact via 316 may be made of a conductive material. In an embodiment, one or more of the contacts or vias may be made of a metal. The metal may be a pure metal (e.g., tungsten, nickel, or cobalt) or an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0069] In one embodiment (though not shown), structure 300 relates to the formation of a contact pattern that is essentially perfectly aligned with an existing gate pattern, while eliminating the use of photolithography operations with very tight registration budgets. In one such embodiment, this approach enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to generate contact openings. In another embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with contact plug photolithography operations. In yet another embodiment, this approach eliminates the need for other critical photolithography operations (as used in conventional methods) for generating the contact pattern. In another embodiment, the trench contact mesh is not patterned individually but is formed between multiple (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after grid patterning but before grid cutting.

[0070] Furthermore, the gate stack structure 308 can be fabricated via a gate replacement process. In this approach, the dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed during this process, as reversed from the previous processing. In embodiments, the dummy gate is removed by a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etching process (including the use of SF6). In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etching process (including the use of NH4OH or tetramethylammonium hydroxide). In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etching process (including an aqueous phosphoric acid solution).

[0071] In embodiments, one or more of the methods described herein essentially envision combining pseudo-and substitution gate processes with pseudo-and substitution contact processes to arrive at structure 300. In one such embodiment, the substitution contact process is performed after the substitution gate process to allow for high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure, such as after the formation of the gate dielectric layer, is performed at a temperature greater than approximately 600°C. Annealing is performed prior to the formation of the permanent contacts.

[0072] Refer again Figure 3AThe arrangement of the semiconductor structure or device 300 places the gate contacts over an isolation region. This arrangement can be seen as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts portions of a gate electrode formed over an active region. Generally, one or more embodiments of the invention include a gate-aligned trench contact process before (or otherwise) forming the gate contact structure (e.g., a via) over the active portion of the gate and in the same layer as the trench contact via. This process can be implemented to form a trench contact structure for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In embodiments, the trench contact pattern is formed to align with an existing gate pattern. In contrast, conventional approaches typically involve an additional photolithography process with close registration of the photolithographic contact pattern to an existing gate pattern, along with selective contact etching. For example, conventional processes may include patterning of independently patterned multi (gate)grids with contact features.

[0073] It is important to understand that not all aspects of the above process need to be practiced to fall within the spirit and scope of the embodiments of the invention. For example, in one embodiment, the dummy gate need not always be formed before the gate contacts are fabricated on the active portion of the gate stack. The gate stack described herein can actually be a permanent gate stack as originally formed. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device can be a transistor or such a device. For example, in an embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Additionally, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, a separately connected dual-gate device, or a FIN-FET. One or more embodiments can be particularly useful for fabricating semiconductor devices at technology nodes of 10 nanometers (10 nm) or smaller.

[0074] Figure 4 A computing device 400 according to one implementation of the present invention is shown. The computing device 400 includes a board 402. The board 402 may include multiple components, including but not limited to a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the board 402. In some implementations, at least one communication chip 406 is also physically and electrically coupled to the board 402. In other implementations, the communication chip 406 is part of the processor 404.

[0075] Depending on its application, computing device 400 may include other components that may or may not be physically and electrically coupled to board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, CD, DVD, etc.).

[0076] Communication chip 406 implements wireless communication for transferring data to and from computing device 400. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can communicate data using electromagnetic radiation modulated via a non-solid-state medium. This term does not imply that associated devices do not contain any wires, although they may not in some embodiments. Communication chip 406 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, EDCT, Bluetooth and its derivatives, and any other wireless protocols represented as 3G, 4G, 5G, and beyond. Computing device 400 may include multiple communication chips 406. For example, the first communication chip 406 can be dedicated to shorter-range wireless communication (such as Wi-Fi and Bluetooth), and the second communication chip 406 can be dedicated to longer-range wireless communication (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.).

[0077] The processor 404 of the computing device 400 includes an integrated circuit die packaged within the processor 404. In some implementations of the embodiments of the present invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors constructed according to the embodiments of the present invention. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0078] The communication chip 406 also includes an integrated circuit die packaged within the communication chip 406. According to another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors constructed according to an implementation of the invention.

[0079] In other implementations, another component included within the computing device 400 may include an integrated circuit die comprising one or more devices, such as a MOS-FET transistor constructed according to an embodiment of the present invention.

[0080] In various embodiments, computing device 400 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, computing device 400 may be any other electronic device that processes data.

[0081] Figure 5 An inserter 500 is shown, comprising one or more embodiments of the present invention. The inserter 500 is an intermediate substrate used to bridge a first substrate 502 to a second substrate 504. The first substrate 502 may be, for example, an integrated circuit die. The second substrate 504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the inserter 500 is to extend a connection to a wider pitch or to rewire a connection to a different connection. For example, the inserter 500 may couple an integrated circuit die to a ball grid array (BGA) 506, which can then be coupled to the second substrate 504. In some embodiments, the first and second substrates 502 / 504 are attached to opposite sides of the inserter 500. In other embodiments, the first and second substrates 502 / 504 are attached to the same side of the inserter 500. And in other embodiments, three or more substrates are interconnected via the inserter 500.

[0082] The inserter 500 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (e.g., polyimide). In other implementations, the inserter may be formed of alternating rigid or flexible materials (which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials).

[0083] The inserter may include metal interconnects 508 and through-holes 510, including but not limited to through-silicon vias (TSVs) 512. The inserter 500 may also include embedded devices 514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices (e.g., radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices) may also be formed on the inserter 500. According to embodiments of the invention, the devices or processes disclosed herein can be used in the fabrication of the inserter 500.

[0084] Therefore, embodiments of the present invention include an alignment pitch quadrature patterning method for early correction of photolithographic edge placement errors.

[0085] In one embodiment, a semiconductor structure includes a plurality of semiconductor fins projecting from a generally flat surface of a semiconductor substrate. The plurality of semiconductor fins have a grid pattern interrupted by a first location having a first fin portion and a second location having a second fin portion, the first fin portion having a first height and the second fin portion having a second height different from the first height. A trench isolation layer is disposed between the plurality of semiconductor fins and adjacent to the lower portions of the plurality of semiconductor fins, but not adjacent to the upper portions of the plurality of semiconductor fins. The trench isolation layer is disposed over the first and second fin portions. One or more gate electrode stacks are disposed on the top surface and sidewalls of the upper portions of the plurality of semiconductor fins, and on portions of the trench isolation layer. Source and drain regions are disposed on either side of the one or more gate electrode stacks.

[0086] In one embodiment, the lattice pattern has a constant pitch.

[0087] In one embodiment, the source and drain regions are configured to be adjacent to the upper portion of the plurality of semiconductor fins and include a semiconductor material different from the semiconductor material of the semiconductor fins.

[0088] In one embodiment, the source and drain regions are disposed within the upper portion of the plurality of semiconductor fins.

[0089] In one embodiment, the one or more gate electrode stacks include a high-k gate dielectric layer and a metal gate electrode.

[0090] In one embodiment, a semiconductor structure includes a plurality of semiconductor fins projecting from a generally flat surface of a semiconductor substrate. The plurality of semiconductor fins have a lattice pattern interrupted by a first location having a first notch below the generally flat surface of the semiconductor substrate. A trench isolation layer is disposed between the plurality of semiconductor fins and adjacent to lower portions of the plurality of semiconductor fins, but not adjacent to upper portions of the plurality of semiconductor fins. The trench isolation layer is disposed within and above the first notch. One or more gate electrode stacks are disposed on the top surface and sidewalls of the upper portions of the plurality of semiconductor fins, and on portions of the trench isolation layer. Source and drain regions are disposed on either side of the one or more gate electrode stacks.

[0091] In one embodiment, the lattice pattern is further interrupted by a second location having a second notch, and the trench isolation layer is disposed in and above the second notch, which is below the generally flat surface of the semiconductor substrate.

[0092] In one embodiment, the lattice pattern is further interrupted by a second location having fin portions, and the trench isolation layer is disposed above the fin portions, which are below the generally flat surface of the semiconductor substrate.

[0093] In one embodiment, the lattice pattern has a constant pitch.

[0094] In one embodiment, the source and drain regions are positioned adjacent to the upper portion of the plurality of semiconductor fins and are composed of a semiconductor material different from the semiconductor material of the semiconductor fins.

[0095] In one embodiment, the source and drain regions are disposed within the upper portion of the plurality of semiconductor fins.

[0096] In one embodiment, the one or more gate electrode stacks include a high-k gate dielectric layer and a metal gate electrode.

[0097] In an embodiment, a method of fabricating a semiconductor structure includes: forming a first patterned hard mask on a semiconductor substrate, the first patterned hard mask having features spaced apart by a pitch; forming a second hard mask layer on the semiconductor substrate, between the features of the first patterned hard mask; forming separate diblock copolymers on the first patterned hard mask and on the second hard mask layer, the separate diblock copolymers comprising alternating first and second polymer blocks, the separate diblock copolymers having a pitch between the first blocks approximately equal to half the pitch of the features of the first patterned hard mask; removing the second polymer blocks from the separate diblock copolymers; after removing the second polymer blocks, forming a second patterned hard mask from the second hard mask layer; and forming a plurality of semiconductor fins in the semiconductor substrate using the first polymer blocks as a mask, the semiconductor fins having a pitch approximately equal to half the pitch of the features of the first patterned hard mask, wherein the alternating fins of the plurality of semiconductor fins each have corresponding alternating portions of the first patterned hard mask and the second patterned hard mask. Remove the first fin of the plurality of semiconductor fins, the first fin having a portion thereon of the first patterned hard mask. After removing the first fin, remove the second fin of the plurality of semiconductor fins, the second fin having a portion thereon of the second patterned hard mask.

[0098] In one embodiment, forming the second hard mask layer includes forming a cover hard mask material on the semiconductor substrate and on the first patterned hard mask, and planarizing the cover hard mask material.

[0099] In one embodiment, the method further includes selectively forming a first molecular brush layer on the first patterned hard mask prior to forming the separated diblock copolymer.

[0100] In one embodiment, the method further includes selectively forming a second molecular brush layer on the second hard mask layer prior to forming the separated diblock copolymer.

[0101] In one embodiment, forming the separated diblock copolymer includes forming a randomized diblock copolymer on the first patterned hard mask and on the second hard mask layer, and then annealing the randomized diblock copolymer.

[0102] In one embodiment, the method further includes forming an interlayer dielectric (ILD) layer on the plurality of semiconductor fins after forming the second patterned hard mask and forming the plurality of semiconductor fins and before removing the first and second fins.

[0103] In one embodiment, the method further includes: after removing the first and second fins, recessing the ILD layer below the top surface of the plurality of semiconductor fins to expose a protruding portion of each of the plurality of semiconductor fins above a sub-fin region of each of the plurality of semiconductor fins.

[0104] In one embodiment, the method further includes forming one or more gate electrode stacks on the exposed protrusions of each of the plurality of semiconductor fins.

[0105] In one embodiment, removing the first fin of the plurality of semiconductor fins includes optionally etching the exposed portion of the first patterned hard mask to the exposed portion of the second patterned hard mask.

[0106] In one embodiment, removing the first fin of the plurality of semiconductor fins includes optionally etching the exposed portion of the first patterned hard mask onto the portion of the second patterned hard mask.

Claims

1. A method for fabricating a semiconductor structure, the method comprising: A first patterned hard mask is formed on a semiconductor substrate, the first patterned hard mask having features spaced apart by pitch; A second hard mask layer is formed on the semiconductor substrate between the features of the first patterned hard mask; Separate diblock copolymers are formed on the first patterned hard mask and on the second hard mask layer. The separate diblock copolymers comprise alternating first polymer blocks and second polymer blocks. The separate diblock copolymers have a pitch between adjacent first polymer blocks that is approximately half the pitch of the feature of the first patterned hard mask. Remove the second polymer block from the separated diblock copolymer; After removing the second polymer block, a second patterned hard mask is formed from the second hard mask layer, and a plurality of semiconductor fins are formed in the semiconductor substrate using the first polymer block as a mask. The semiconductor fins have a pitch approximately equal to half the pitch of the feature of the first patterned hard mask, wherein adjacent fins of the plurality of semiconductor fins have corresponding portions of the first patterned hard mask and the second patterned hard mask, respectively. Remove the first fin of the plurality of semiconductor fins, the first fin having a portion thereon of the first patterned hard mask; as well as After removing the first fin, remove the second fin of the plurality of semiconductor fins, the second fin having a portion thereon of the second patterned hard mask. The method further includes: After forming the second patterned hard mask and forming the plurality of semiconductor fins and before removing the first fin and the second fin, a trench isolation layer is formed between the plurality of semiconductor fins; After removing the first and second fins, a dielectric layer is formed on the top surfaces of the first and second fins. This dielectric layer is laterally positioned between and in contact with the sides of the trench isolation layer. The dielectric layer has a composition different from that of the trench isolation layer. After removing the first fin and the second fin, the trench isolation layer is recessed, the trench isolation layer being adjacent to the lower portion of the plurality of semiconductor fins but not adjacent to the upper portion of the plurality of semiconductor fins, wherein the trench isolation layer has an uppermost surface, wherein the uppermost surface of the trench isolation layer is lower than the uppermost surface of the plurality of semiconductor fins, and wherein the uppermost surface of the trench isolation layer is higher than the uppermost surfaces of the first fin and the second fin.

2. The method as described in claim 1, wherein, Forming the second hard mask layer includes forming a cover hard mask material on the semiconductor substrate and on the first patterned hard mask, and planarizing the cover hard mask material.

3. The method of claim 1, further comprising: Prior to forming the separated diblock copolymer, a first molecular brush layer is selectively formed on the first patterned hard mask.

4. The method of claim 3, further comprising: Prior to forming the separated diblock copolymer, a second molecular brush layer is selectively formed on the second hard mask layer.

5. The method of claim 1, wherein, Forming the separated diblock copolymer includes forming a randomized diblock copolymer on the first patterned hard mask and on the second hard mask layer, and then annealing the randomized diblock copolymer.

6. The method of claim 1, further comprising: After removing the first fin and the second fin, the dielectric layer below the top surface of the plurality of semiconductor fins is recessed, thereby exposing the protrusion of each of the plurality of semiconductor fins above the sub-fin region of each of the plurality of semiconductor fins.

7. The method of claim 6, further comprising: One or more gate electrode stacks are formed on the exposed protrusions of each of the plurality of semiconductor fins.

8. The method of claim 1, wherein, Removing the first fin of the plurality of semiconductor fins includes selectively etching portions of the first patterned hard mask.

9. The method of claim 8, wherein, Removing the first fin of the plurality of semiconductor fins includes selectively etching portions of the second patterned hard mask.

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