Improved flash memory cell and associated decoder

Abstract

The present invention relates to flash memory cells having only four terminals and decoder circuitry for operating an array of such flash memory cells. The present invention allows for fewer terminals per flash memory cell than the prior art, which results in a simplification of the overall die space required for the decoder circuitry and each flash memory cell. The present invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and program operations despite the lower number of terminals compared to prior art flash memory cells.

Description

[0001] Related patent applications This application claims the benefit of U.S. Patent Application No. 15 / 158,460, filed May 18, 2016. Technical Field

[0002] This invention relates to flash memory cells and decoder circuitry, wherein the flash memory cell has only four terminals, and the decoder circuitry is used to operate an array of such flash memory cells. Compared to the prior art, the present invention allows for fewer terminals per flash memory cell, resulting in a simplification of the decoder circuitry and the overall die space required for each flash memory cell. The present invention also provides the use of high voltage on one or more of the four terminals to allow read, erase, and program operations, despite having fewer terminals compared to prior art flash memory cells. Background Technology

[0003] Non-volatile memory cells are well known in the art. Figure 1 The image illustrates a prior art non-volatile split-gate memory cell 10, which includes five terminals. The memory cell 10 includes a semiconductor substrate 12 of a first conductivity type, such as P-type. The substrate 12 has a surface on which a first region 14 (also called a source line SL) of a second conductivity type, such as N-type, is formed. A second region 16 (also called a drain line), also of N-type, is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned above and insulated from a first portion of the channel region 18. The word line 22 has little or no overlap with the second region 16. A floating gate FG 24 is above another portion of the channel region 18. The floating gate 24 is insulated from this other portion and adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. Floating gate 24 may overlap with first region 14 to provide coupling from first region 14 to floating gate 24. Coupling gate CG (also called control gate) 26 is located above and insulated from floating gate 24. Eraser gate EG 28 is above first region 14 and adjacent to floating gate 24 and coupling gate 26, and is insulated from both floating gate and coupling gate. The top corner of floating gate 24 may point to the inner corner of T-shaped erase gate 28 to enhance erasing efficiency. Eraser gate 28 is also insulated from first region 14. Memory cell 10 is described in more detail in U.S. Patent No. 7,868,375, the entire disclosure of which is incorporated herein by reference.

[0004] An exemplary operation for erasing and programming a prior art non-volatile memory cell 10 is as follows. The memory cell 10 is erased by applying a high voltage to the erase gate 28, making the other terminals equal to zero volts, using the Fowler-Nordheim tunneling mechanism. Electrons tunnel from the floating gate 24 into the erase gate 28, causing the floating gate 24 to become positively charged, thereby opening the cell 10 in a read state. The resulting cell erase state is referred to as the '1' state.

[0005] The memory cell 10 is programmed via a source-side hot-electron programming mechanism by applying a high voltage to the coupling gate 26, a high voltage to the source line 14, a medium voltage to the erase gate 28, and a programming current to the bit line 20. A portion of the electrons flowing through the gap between the word line 22 and the floating gate 24 gain sufficient energy to inject into the floating gate 24, causing it to become negatively charged, thereby turning off the cell 10 in the read state. The resulting programmed state of the cell is called the '0' state.

[0006] Memory cell 10 can be read in current-sensing mode as follows: a bias voltage is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage or zero voltage is applied to erase gate 28, and a ground potential is applied to source line 14. In the erase state, there is a cell current flowing from bit line 20 to source line 14, while in the programming state, there is a negligible cell current or zero cell current flowing from bit line 20 to source line 14. Alternatively, memory cell 10 can be read in reverse current-sensing mode, in which bit line 20 is grounded and a bias voltage is applied to source line 24. In this mode, the current flows in the reverse direction from source line 14 to bit line 20.

[0007] Alternatively, memory cell 10 can be read in voltage-sensing mode as follows: a bias current (ground) is applied to bit line 20, a bias voltage is applied to word line 22, a bias voltage is applied to coupling gate 26, a bias voltage is applied to erase gate 28, and a bias voltage is applied to source line 14. For the erase state, there is a cell output voltage (significantly >0V) on bit line 20, while for the programming state, there is a negligible or near-zero output voltage on bit line 20. Alternatively, memory cell 10 can be read in reverse voltage-sensing mode, in which bit line 20 is biased at a bias voltage, and a bias current (ground) is applied to source line 14. In this mode, the memory cell 10 output voltage is located on source line 14 instead of bit line 20.

[0008] In the prior art, various combinations of positive or zero voltage are applied to word line 22, coupling gate 26 and floating gate 24 to perform read, program and erase operations.

[0009] In response to read, erase, or program commands, logic circuit 270 (in) Figure 2 (in the middle) to supply various voltages to each part of both the selected memory cell 10 and the unselected memory cell 10 in a timely and interference-free manner.

[0010] For the selected and unselected memory cells 10, the applied voltages and currents are as follows. The abbreviations used below refer to: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).

[0011] Table 1: PEO (Positive Erase Operation) Table .

[0012] In the applicant's most recent application (U.S. Patent Application No. 14 / 602,262, filed January 21, 2015, incorporated by reference), the applicant discloses an invention by which a negative voltage can be applied to word line 22 and / or coupling gate 26 during read, program, and / or erase operations. In this embodiment, the voltage and current applied to selected and unselected memory cells 10 are as follows.

[0013] Table 2: PEO (Positive Erase Operation) Table .

[0014] In another embodiment of U.S. Patent Application No. 14 / 602,262, when memory cell 10 is not selected during read, erase, and program operations, a negative voltage may be applied to word line 22, and a negative voltage may be applied to coupling gate 26 during erase operations, such that the following voltages are applied: Table 3: PNEO (Positive and Negative Erase Operations) Table .

[0015] The CGINH signal listed above is a disable signal that is applied to the coupling gate 26 of the unselected cell, which shares the erase gate 28 with the selected cell.

[0016] Figure 2 An embodiment of an architecture for a flash memory system including a die 200, recently developed by the applicant, is shown. The die 200 includes a memory array 215 and a memory array 220 for storing data, the memory arrays 215 and 220 comprising the components described above. Figure 1The memory cells 10 in the memory array 215 and 220 are rows and columns of memory cells; pads 240 and 280 are used to enable electrical communication between other components of die 200 and bonding wires (not shown), which in turn connect to pins (not shown) or package bumps for accessing the integrated circuit from outside the package chip or macro interface pins (not shown) for interconnection to other macros on the SOC (System-on-Chip); high-voltage circuit 275 for providing positive and negative voltage sources for the system; control logic 270 for providing various control functions such as redundancy and built-in self-test; analog circuit 265; sensing circuits 260 and 261 for reading data from memory array 215 and memory array 220, respectively; row decoder circuit 245 and row decoder circuit 246, respectively. For accessing rows to be read or written in memory arrays 215 and 220; column decoder circuits 255 and 256, respectively, for accessing bytes to be read or written in memory arrays 215 and 220; charge pump circuits 250 and 251, respectively, for providing increased voltages for programming and erasing operations to memory arrays 215 and 220; negative voltage driver circuit 230, for read and write operations and shared by memory arrays 215 and 220; high voltage driver circuit 225 used by memory array 215 during read and write operations, and high voltage driver circuit 226 used by memory array 220 during read and write operations.

[0017] As flash memory systems become ubiquitous in various computing and electronic devices, it is increasingly important to create designs that reduce the amount of die space required per memory cell and decrease the overall complexity of the decoders used in flash memory systems. What is needed is a flash memory cell design that utilizes fewer terminals than existing technologies and simplified circuitry for operating flash memory cells that follow that design. Summary of the Invention

[0018] This invention relates to flash memory cells and decoder circuitry, wherein the flash memory cell has only four terminals, and the decoder circuitry is used to operate an array of such flash memory cells. Compared to the prior art, this invention allows for fewer terminals per flash memory cell, resulting in a simplification of the decoder circuitry and the overall die space required for each flash memory cell. This invention also provides the ability to use high voltages on one or more of the four terminals to allow read, erase, and program operations, despite having fewer terminals compared to prior art flash memory cells. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of a prior art non-volatile memory cell, to which the method of the present invention can be applied.

[0020] Figure 2 Is using Figure 1 The diagram shows a block diagram of a non-volatile memory device with prior art non-volatile memory cells.

[0021] Figure 3 This is a block diagram of an implementation scheme for a non-volatile memory cell.

[0022] Figure 4 yes Figure 3 A schematic diagram of a non-volatile memory cell.

[0023] Figure 5 Is using Figure 3 A block diagram of a non-volatile memory device with non-volatile memory cells.

[0024] Figure 6 An embodiment of a line decoder for use with a memory device according to an embodiment of this disclosure is shown.

[0025] Figure 7 This is a block diagram of a decoder circuit for use with a memory device according to embodiments of the present disclosure.

[0026] Figure 8 An embodiment of an erase gate decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0027] Figure 9 An embodiment of an erase gate decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0028] Figure 10 An embodiment of an erase gate decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0029] Figure 11 An embodiment of a source-line decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0030] Figure 12 An embodiment of a source-line decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 13 An embodiment of a source-line decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0032] Figure 14 An embodiment of a source-line decoder for use with a memory device according to an embodiment of the present disclosure is shown.

[0033] Figure 15 An implementation of a source line decoder with virtual flash memory cells for selectively pulling down to a low-voltage or ground source line is shown.

[0034] Figure 16 An implementation scheme for a virtual flash memory cell is shown for selectively pulling down to a low voltage or grounding coupled to the source line of a selected flash memory cell.

[0035] Figure 17 An embodiment of a control gate decoder for use with a memory device using a memory cell according to another embodiment of this disclosure is shown.

[0036] Figure 18 An embodiment of a control gate decoder for use with a memory device using a memory cell according to another embodiment of this disclosure is shown.

[0037] Figure 19 An embodiment of a gate decoder for use with a memory device using a memory cell according to another embodiment of the present disclosure is shown.

[0038] Figure 20 An embodiment of a latch voltage level shifter for use with a memory device according to an embodiment of the present disclosure is shown.

[0039] Figure 21 An embodiment of a latch voltage level shifter for use with a memory device according to an embodiment of the present disclosure is shown.

[0040] Figure 22 An embodiment of a high-voltage current limiter for use with a memory device according to an embodiment of the present disclosure is shown.

[0041] Figure 23 An embodiment of a latch voltage level shifter for use with a memory device according to an embodiment of the present disclosure is shown.

[0042] Figure 24 An embodiment of a flash memory cell array is shown, having a row of virtual memory cells for selectively pulling down to a low voltage or grounding a selected source line. Detailed Implementation

[0043] Figure 3An embodiment of an improved flash memory cell 300 is shown. Like the prior art flash memory cell 10, the flash memory cell 300 includes a substrate 12, a first region (source line) 14, a second region 16, a channel region 18, a bit line 20, a word line 22, a floating gate 24, and an erase gate 28. Unlike the prior art flash memory cell 10, the flash memory cell 300 does not include a coupling gate or a control gate, and includes only four terminals—the bit line 20, the word line 22, the erase gate 28, and the source line 14. This significantly reduces the complexity of the circuitry required to operate the flash memory cell array, such as decoder circuitry.

[0044] Except for the absence of a control gate bias, the erase operation (erasing via the erase gate) and the read operation are similar. Figure 1 The programming operation is also performed without a control gate bias, therefore the programming voltage on the source line is higher to compensate for the lack of control gate bias.

[0045] Table 4 shows the typical voltage range that can be applied to the four terminals to perform read, erase, and program operations: Table 4: Operation Table for Four-Terminal Flash Memory Devices .

[0046] Figure 4 The symbol 400 of the flash memory cell 300 is shown. The symbol 400 includes the symbols of the four terminals of the flash memory cell 300 (i.e., bit line 20, word line 22, erase gate 28, and source line 14).

[0047] Figure 5 An implementation scheme of a flash memory system architecture including die 500 is shown. Die 500 includes memory arrays 501, 511, 521, and 531 for storing data, each of memory arrays 501, 511, 521, and 531 including the previously described... Figure 3The die 500 includes rows and columns of memory cells of the type of flash memory cell 300. The die 500 also includes: a sensing circuit 543 for reading data from memory arrays 501, 511, 521, and 531; a row decoder circuit 541 for accessing selected rows in memory arrays 501 and 511; a row decoder circuit 542 for accessing selected rows in memory array 521 to be read or written; column decoder circuits 503, 513, 523, and 533 for accessing bytes to be read or written in memory arrays 501, 511, 521, and 531, respectively; and high-voltage row decoders WSHDR 502, 512, 522, and 532 for providing high voltage to one or more terminals of selected memory cells within memory arrays 501, 511, 521, and 531 according to the operation being performed.

[0048] Die 500 also includes the following functional structures and subsystems: a macro interface pin ITFC pin 548 for interconnecting to other macros on the SOC (System-on-Chip); a low-voltage generation circuit (including a low-voltage charge pump circuit) 547 and a high-voltage generation circuit (including a high-voltage charge pump circuit) 546 for providing increased voltages for programming and erasing operations of memory arrays 501, 511, 521, and 531; an analog circuit 544 used by the analog circuitry on die 500; and a digital logic circuit 545 used by the digital circuitry on die 500.

[0049] Figure 6 A row decoder 600 for eight word lines in sectors within a memory array (such as memory arrays 501, 511, 521, and 531) is shown. The row decoder 600 may be part of row decoder circuits 541 and 542 in die 500. The row decoder 600 includes a NAND gate 601 that receives pre-decoded address signals (shown here as lines XPA, XPB, XPC, and XPD) that select sectors within the memory array. When XPA, XPB, XPC, and XPD are all "high," the output of NAND gate 601 will be "low," and that particular sector will be selected.

[0050] The line decoder 600 also includes an inverter 602, a decoder circuit 610 for generating word line WL0, a decoder circuit 620 for generating WL7, and additional decoder circuitry (not shown) for generating word lines WL1, WL2, WL3, WL4, WL5, and WL6.

[0051] Decoder circuit 610 includes PMOS transistors 611, 612, and 614 and NMOS transistors 613 and 615, configured as shown. Decoder circuit 610 receives the output of NAND gate 601, the output of inverter 602, and the pre-decoded address signal XPZB0. WL0 is active when the specific sector is selected and XPZB0 is "low". WL0 is inactive when XPZB0 is "high".

[0052] Similarly, the decoder circuit 620 includes PMOS transistors 621, 622, and 624 and NMOS transistors 623 and 625, as configured as shown. The decoder circuit 620 receives the output of NAND gate 601, the output of inverter 602, and the pre-decoded address signal XPZ70. WL7 is active when the specific sector is selected and XPZB7 is "low". WL7 is inactive when XPZB7 is "high".

[0053] It should be understood that the decoder circuits for WL1, WL2 and WL3, WL4, WL5 and WL6 (shown now) will follow the same design as decoder circuits 610 and 620, except that they will receive inputs XPZB1, XPZB2, XPZB3, XPZB4, XPZB5 and XPZB6 respectively, instead of XPZB0 or ​​XPZB7.

[0054] When the sector is selected and WL0 is expected to be active, the output of NAND gate 601 will be "low," and the output of the inverter will be "high." PMOS transistor 611 will be turned on, and the node between PMOS transistor 612 and NMOS transistor 613 will receive the value of XPZB0, which will be "low" when word line WL0 is active. This will turn on PMOS transistor 614, which will "pull" WL0 high to ZVDD, indicating an active state. In this case, XPZB7 is "high," indicating that WL7 is not active. This will pull the node between PMOS transistor 622 and NMOS transistor 623 to the value of XPZB7 (which is "high"), which will turn on NMOS transistor 624 and make WL "low," indicating an inactive state. In this way, when the sector is selected, one of the word lines WL0...WL7 can be selected.

[0055] Figure 7 A high-voltage line decoder 700 is shown. It should be remembered that in embodiments of the invention, a high-voltage signal (e.g., 7-9V for the source lines during programming operations) is required to compensate for the lack of coupling gates in the flash memory cells. The high-voltage decoder 700 includes a high-voltage level shift enable circuit 710, an erase gate decoder 720, and a source line decoder 730.

[0056] The high-voltage level shift enable circuit 710 includes a high-voltage level shift circuit 711 and a low-voltage latch 712. The low-voltage latch 712 receives word lines (WL), enable (EN), and reset (RST) as input signals, and outputs a sector enable signal (SECEN) and a sector enable signal bar (SECEN_N). The sector enable signal (SECEN) is provided as input to the high-voltage level shift circuit 711, which outputs a high voltage sector enable signal (SECEN_HV0…SECEN_HVN for N sectors) and a high voltage sector enable signal bar (SECEN_HV0_N…SECEN_HVN_N for N sectors).

[0057] The erase gate decoder 720 includes an erase gate decoder 721 for row 0 of a sector, and similar erase gate decoders (not shown) for rows 1, ..., N of a sector. Here, the erase gate decoder 721 receives a sector enable signal high voltage (SECEN_HV0), its complement (SECEN_HV0_N), a voltage erase gate power supply (VEGSUP), a low voltage erase gate power supply (VEGSUP_LOW), a sector enable signal (SECEN), and its complement (SECEN_N) from a high voltage level shift circuit 711. Therefore, the output EG0 of the erase gate decoder 721 can be at one of three different voltage levels: SECEN_HV0 (high voltage), VEGSUP (normal voltage), or VEGSUP_LOW (low voltage).

[0058] Similarly, the source line decoder 730 includes a source line decoder 721 for the 0th row of a sector, and similar source line decoders (not shown) for the 1st, ..., Nth rows of a sector. Here, the source line decoder 731 receives the sector enable signal high voltage (SECEN_HV0), its complement (SECEN_HV0_N), voltage source line power supply (VSLSUP), low voltage source line power supply (VSLSUP_LOW), sector enable signal (SECEN), and its complement (SECEN_N) from the high voltage level shift circuit 711. Therefore, the output SL0 of the source line decoder 730 can be at one of three different voltage levels: SECEN_HV0 (high voltage), VSLSUP (normal voltage), or VSLSUP_LOW (low voltage).

[0059] Figure 8An erase gate decoder 800 is shown, which is an embodiment of the erase gate decoder 720. The erase gate decoder 800 includes an NMOS transistor 801 and PMOS transistors 802 and 803 configured as shown. PMOS transistor 803 is a current limiter with EGHV_BIAS as a current mirror bias level. When the erase gate signal (EG) is active, EN_HV_N will be low (e.g., 0V, 1.2V, or 2.5V), which will turn on PMOS transistor 802 and turn off NMOS transistor 801, causing the erase gate (EG) to be high (i.e., =VEGSUP, e.g., 11.5V). When the erase gate signal (EG) is not active, EN_HV_N will be high, which will turn off PMOS transistor 802 and turn on NMOS transistor 801, causing the erase gate (EG) to be low (i.e., =VEGSUP_LOW level, e.g., 0V, 1.2V, or 2.5V).

[0060] Figure 9 An erase gate decoder 900 is shown, which is another embodiment of the erase gate decoder 720. The erase gate decoder 900 includes an NMOS transistor 901 and a PMOS transistor 902. The erase gate decoder 900 in this example does not include a current limiter. When the erase gate signal (EG) is active, EN_HV_N will be low (e.g., 0V or 1.2V), which will turn on the PMOS transistor 902 and turn off the NMOS transistor 901, causing the erase gate (EG) to be high. When the erase gate signal (EG) is not active, EN_HV_N will be high, which will turn off the PMOS transistor 902 and turn on the NMOS transistor 901, causing the erase gate (EG) to be low (e.g., 0V, 1.2V, or 2.5V).

[0061] Figure 10 An erase gate decoder 1000 is shown, which is another embodiment of an erase gate decoder 720 using only PMOS transistors. The erase gate decoder 1000 includes PMOS transistors 1001 and 1002 that share a common well. The erase gate decoder 1000 in this example does not include a current limiter. When the erase gate signal (EG) is active, EN_HV_N will be low and EN_HV will be high, which will turn on PMOS transistor 1002 and turn off PMOS transistor 1001, causing the erase gate (EG) to be high. When the erase gate signal (EG) is not active, EN_HV_N will be low and EN_HV will be high, which will turn off PMOS transistor 1002 and turn on PMOS transistor 1001, causing the erase gate (EG) to be low (e.g., 0V, 1.2V, or 2.5V).

[0062] Figure 11A source line decoder 1100 is shown, which is an embodiment of the source line decoder 730. The source line decoder 1100 includes NMOS transistors 1101, 1102, 1103, and 1104 configured as shown. NMOS transistor 1101 pulls the source line (SL) low during a read operation in response to the SLRD_EN signal. NMOS transistor 1102 pulls the source line (SL) low during a programming operation in response to the SLP_EN signal. NMOS transistor 1103 performs a monitoring function through its output VSLMON. NMOS transistor 1104 provides a voltage to the source line (SL) in response to the EN_HV signal.

[0063] Figure 12 A source line decoder 1200 is shown, which is another embodiment of the source line decoder 730. The source line decoder 1200 includes NMOS transistors 1201, 1202, and 1203 configured as shown. NMOS transistor 1201 pulls the source line (SL) low in response to the SLP_EN signal during programming operation. NMOS transistor 1202 performs a monitoring function through its output VSLMON. NMOS transistor 1203 provides a voltage to the source line (SL) in response to the EN_HV signal.

[0064] Figure 13 A source line decoder 1300 is shown, which is another embodiment of the source line decoder 730. The source line decoder 730 includes NMOS transistors 1301 and 1302 configured as shown. NMOS transistor 1301 pulls the source line (SL) low in response to the SLP_EN signal during programming operation. NMOS transistor 1302 supplies a voltage to the source line (SL) in response to the EN_HV signal.

[0065] Figure 14 A source line decoder 1400 is shown, which is another embodiment of the source line decoder 730 using only PMOS transistors. The source line decoder 1400 includes PMOS transistors 1401, 1402, and 1403 configured as shown. PMOS transistor 1401 pulls the source line (SL) low in response to the EN_HV signal during programming operation. PMOS transistor 1402 performs a monitoring function through its output VSLMON. PMOS transistor 1403 provides a voltage to the source line (SL) in response to the EN_HV_N signal.

[0066] Figure 15 The source line decoder 1500 is shown, which serves as... Figure 14Another embodiment of the source line decoder 730 is a variant of the source line decoder 1400. The source line decoder includes source line decoder 1400. The source lines (SL) of source line decoder 1400 are connected during read operations to the source line 1620 of the selected memory cell 1620 and the source line 1520 of the virtual memory cell 1510. Virtual memory cell 1510 follows the same construction as the selected memory cell 1610, which can be based on the design of memory cell 300, except that virtual memory cell 1510 is not used to store data.

[0067] Figure 16 Additional details regarding the selected memory cell 1620 and the virtual memory cell 1520 are shown. When the selected memory cell 1620 is in read or erase mode, source lines 1620 and 1520 are coupled to ground via the virtual memory cell 1510 and a virtual bit line 1526 coupled to ground. Before a read operation, the virtual memory cell 1510 needs to be erased. This will pull source lines 1520 and 1620 to ground.

[0068] When the selected memory cell 1610 is in programming mode, bit line 1526 is coupled to a disable voltage, such as VDD. This places the virtual memory cell 1510 in a programming disable mode, which keeps the virtual memory cell 1520 in an erase state. Multiple virtual cells, such as virtual memory cell 1510, can be connected to memory cell 1610 via their source lines to strengthen the pull-down of source line 1620 to ground.

[0069] Figure 17 The control gate decoder 1700 is shown, which is compatible with... Figures 1-2 The existing technology design uses a control gate decoder, and it is in Figures 3-16 This is not required in the proposed implementation. The control gate decoder 1700 includes an NMOS transistor 1701 and a PMOS transistor 1702. The NMOS transistor 1701 will respond to the signal EN_HV_N to pull down the control gate signal (CG). The PMOS transistor 1702 will respond to the signal EN_HV_N to pull up the control gate signal (CG).

[0070] Figure 18 This illustrates a control gate decoder 1800 that uses only PMOS transistors, which is compatible with... Figures 1-2 Another implementation of the control gate decoder used in existing technology designs, and its... Figures 3-16This is not required in the proposed implementation. The control gate decoder 1800 includes PMOS transistors 1801 and 1802. PMOS transistor 1801 will respond to the signal EN_HV to pull down the control gate signal (CG). PMOS transistor 1802 will respond to the signal EN_HV_N to pull up the control gate signal (CG).

[0071] Figure 19 The EG / CG / SL gate decoder 1900 is shown, which can be used with... Figures 1-2 Used in conjunction with existing technology designs, and Figures 3-16 The implementation scheme is used to illustrate the amount of space saved by the present invention. The gate decoder 1900 includes a PMOS transistor 1901. The PMOS transistor 1901 pulls the gate signals (EG / CG / SL) high low in response to the signal EN_HV_N. If EN_HV_N is not active, the value of EG / CG / SL will float. The EG / CG / SL gate is first pre-charged to a low bias level before being enabled to a high voltage level.

[0072] Figure 20 A latched voltage level shifter 2000 with adaptive high voltage VH and low voltage VL power supplies is shown. In the illustrated configuration, the latched voltage level shifter includes latches comprising inverters 2001 and 2002 and NMOS transistors 2003, 2004, 2005, 2006, and 2007. The latched voltage level shifter receives input 2012 for reset (input RST_SECDEC) and input 2010 for set, meaning enabled (inputs WL0 and SET_SECDEC), and produces outputs 2020 and 2022. The latched voltage level shifter adaptively changes the magnitude of the "high" or "low" voltage to minimize voltage stress. Latch inverters 2001 and 2002 receive power supply high VH and power supply low VL. Initially, when enabled via inputs 2010 / 2012, VH is Vdd, for example 1.2V, and VL is gnd. Then VH begins to ramp up to the intermediate VH level, for example, 5V. At this VH level, VL then ramps up to the intermediate VL level, for example, 2.5V. After VL reaches the intermediate VL level, VH then ramps up to the final high-voltage supply level, VHVSUP, for example, 11.5V. At this point, the voltage across the inverter is only 11.5V - 2.5V = 9V, thus reducing the voltage stress on it.

[0073] Figure 21A latch voltage shifter 2100 is shown. In the illustrated configuration, the latch voltage shifter 2100 includes a low-voltage latch inverter 2109, NMOS transistors 2103, 2104, 2107, and 2108, and PMOS transistors 2101, 2102, 2105, and 2106. The latch voltage shifter 2100 receives EN_SEC as an input and outputs EN_HV and EN_HV_N, which have voltage swings larger than EN_SEC and ground.

[0074] Figure 22 A high-voltage current limiter 2200 is shown, which includes a PMOS transistor that receives VEGSUP_LOC with a limited current (acting as a current bias) and outputs VEGSUP. This circuit can be used with devices that do not have features such as... Figure 9 , Figure 10 , Figure 17 , Figure 18 , Figure 19 They are used together with the local current limiter circuit to limit the current.

[0075] Figure 23 A latch voltage shifter 2300 with a current limiter for read operations is shown. The latch voltage shifter 2300 includes... Figure 21 The latch voltage shifter 2100. The latch voltage shifter 2300 also includes a current limiter 2310, which comprises a PMOS transistor 2301 and a current source 2302. The current limiter 2310 is connected to the current limiter 2310 via a switch 2303. The latch voltage shifter 2100 is also connected to the signal HVSUP_GLB via a switch 2304. During read operations, the latch voltage level shifter 2100 is connected to the current limiter 2310 via switch 2303. The output of the latch voltage level shifter 2100 (e.g., approximately one Vt threshold voltage below Vdd 2.5V) controls the gates of the EG and CG decoders, such as... Figure 8 , Figure 9 , Figure 10 , Figure 17 , Figure 18 , Figure 19 As shown. When not in a read operation, latch voltage level shifter 2100 is connected to HVSUP_GLB via switch 2304.

[0076] Figure 24 An array 2400 with source line pull-down is shown, which utilizes Figure 15 and Figure 16The design includes an array 2400 with source line pull-down, comprising multiple memory cells organized into rows (indicated by word lines WL0, ... WL7) and columns (indicated by bit lines BL0, ... BL31). An exemplary memory cell pair is memory cell pair 2401, which includes one cell coupled to word line 2402 (WL0) and another cell coupled to word line 2404 (WL1). The two cells share erase gate 2403 (EG0) and source line 2406 (SL0). A column of virtual memory cells is also present, shown here attached to bit line BL_PWDN1. An exemplary virtual memory cell pair is virtual memory cell pair 2407, which includes one cell coupled to word line 2402 (WL0) and another cell coupled to word line 2404 (WL1). The two cells share erase gate 2403 (EG0) and source line 2406 (SL0). The selected memory cell and virtual memory cell can be accessed during a read operation as described above. Figure 15 and Figure 16 The configuration is discussed.

Claims

1. A non-volatile memory device, comprising: An array of flash memory cells (501, 511, 521, 531) organized by rows and columns, each flash memory cell including a bit line terminal (20), a word line terminal (22), an erase gate terminal (28), a source line terminal (14), and no other terminals; A high-voltage line decoder (700) includes an adaptive latch voltage level shifter comprising: a latch formed by a first inverter and a second inverter, the first inverter and the second inverter receiving a first voltage (VH) from a first voltage source and a second voltage (VL) less than the first voltage from a second voltage source; and a transistor that receives an input signal to enable, wherein after the latch voltage level shifter receives the enable signal, the first voltage ramps up from an initial positive voltage to an intermediate first level, at which the second voltage ramps up from ground to an intermediate second level, and then at which the first voltage ramps up to a final high-voltage power supply level, whereby the voltage difference across the inverter is 9.0 volts; and an output sector enable signal high voltage; Erasure gate decoder (720), the erase gate decoder is configured to receive the sector enable signal high voltage from the high voltage row decoder, select one of a plurality of different voltages to generate an erase gate voltage, and apply the erase gate voltage to an erase gate line, the erase gate line being connected to the erase gate terminals of a plurality of flash memory cells in the array; Source line decoder (730), the source line decoder is configured to receive the sector enable signal high voltage from the high voltage row decoder, select one of a plurality of different voltages to generate a source line voltage, and apply the source line voltage to a source line, the source line being connected to the source line terminals of a plurality of flash memory cells in the array.

2. The memory device of claim 1, wherein the erase gate decoder includes a current limiter for limiting the current generated by applying the erase gate voltage to the erase gate line.

3. The memory device of claim 1, wherein the erase gate decoder includes a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to an erase gate select signal.

4. The memory device of claim 1, wherein the erase gate decoder comprises a PMOS transistor and no NMOS transistor.

5. The memory device of claim 1, wherein the source line decoder includes a monitoring circuit for providing a monitoring line containing the output of the source line decoder.

6. The memory device of claim 1, wherein the source line decoder includes a read deselect circuit for pulling the output of the source line decoder to a low voltage during a read operation.

7. The memory device of claim 1, wherein the source line decoder includes a programming deselection circuit for pulling the output of the source line decoder to a low voltage during a programming operation.

8. The memory device of claim 1, wherein the source line decoder comprises an NMOS transistor and no PMOS transistor.

9. The memory device of claim 1, wherein the source line decoder comprises a PMOS transistor and no NMOS transistor.

10. The memory device of claim 1, comprising: A column of virtual flash memory cells, wherein each virtual flash memory cell is not used to store data, and one or more of the virtual flash memory cells are coupled to a source line during a read or erase operation to pull the source line to a low voltage or ground, wherein each source line is coupled to the source line terminal of two rows of flash memory cells in the array.

11. The memory device of claim 10, wherein the erase gate decoder includes a current limiter for limiting the current generated by applying the erase gate voltage to the erase gate line.

12. The memory device of claim 10, wherein the erase gate decoder includes a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to an erase gate select signal.

13. The memory device of claim 10, wherein the erase gate decoder comprises a PMOS transistor and no NMOS transistor.

14. The memory device of claim 10, wherein the source line decoder includes monitoring circuitry for providing a monitoring line that includes the output of the source line decoder.

15. The memory device of claim 10, wherein the source-line decoder includes a read deselect circuit for pulling the output of the source-line decoder to a low voltage during a read operation.

16. The memory device of claim 10, wherein the source line decoder includes a programming deselection circuit for pulling the output of the source line decoder to a low voltage during a programming operation.

17. The memory device of claim 10, wherein the source line decoder comprises an NMOS transistor and no PMOS transistor.

18. The memory device of claim 10, wherein the source line decoder comprises a PMOS transistor and no NMOS transistor.

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