Semiconductor device

Abstract

A semiconductor device includes a substrate including a field region defining an active region, source / drain regions in the active region, a channel region between the source / drain regions, a lightly doped drain (LDD) region between one of the source / drain regions and the channel region, and a gate structure on the channel region. An upper portion of the active region can include an epitaxially grown layer having a lattice constant greater than a lattice constant of silicon (Si), and the source / drain regions and the LDD region can be doped with gallium (Ga).

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2017-0104160, filed on August 17, 2017 with the Korean Intellectual Property Office, the full disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices for carriers having enhanced mobility characteristics in the channel region. Background Technology

[0004] With the rapid development of the electronics industry and increasing user demands, electronic devices are becoming smaller and lighter. Highly integrated semiconductor devices are essential in electronic devices, thus reducing the design constraints of semiconductor device components. Furthermore, the demand for high-speed semiconductor devices is steadily increasing. Various studies have been conducted to meet the requirements of high integration and high speed in semiconductor devices. Summary of the Invention

[0005] This disclosure provides a semiconductor device that can have carriers with improved mobility characteristics in its channel region.

[0006] According to one aspect of this disclosure, a semiconductor device is provided. The semiconductor device may include: a substrate including a field region defining an active region; a source / drain region located within the active region; a channel region located between the source / drain regions; a lightly doped drain (LDD) region located between one of the source / drain regions and the channel region; and a gate structure located on the channel region. The upper portion of the active region may include an epitaxial growth layer having a lattice constant greater than that of silicon (Si), and the source / drain regions and the lightly doped drain region may be doped with gallium (Ga).

[0007] According to another aspect of this disclosure, a semiconductor device is provided. The semiconductor device may include: a substrate having a first transistor region and a second transistor region and formed of a first material; a first active region formed in the first transistor region; and a second active region formed in the second transistor region and including a source / drain region and a channel region. An upper region of the first active region may include a first epitaxial growth layer comprising the first material, and an upper portion of the second active region may include a second epitaxial growth layer comprising more than 50 atomic percent (at%) of a second material. The second material may be different from the first material, the source / drain regions may be doped with gallium (Ga), and the top surface of each of the first and second active regions may be flat.

[0008] According to another aspect of this disclosure, a semiconductor device is provided. The semiconductor device may include: an active region having a channel region and a gallium (Ga)-doped source / drain region; a channel silicon-germanium (c-SiGe) layer constituting the upper portion of the active region and containing more than 50 atomic percent (at%) Ge; and a gate structure disposed on the channel silicon-germanium (c-SiGe) layer and including a high-dielectric-constant gate insulating layer and a metal gate electrode. Attached Figure Description

[0009] Various aspects of this disclosure will become clearer when viewed in conjunction with the accompanying drawings and the following detailed description, in which:

[0010] Figures 1 to 11 This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to aspects of this disclosure.

[0011] Figure 12 It is a graph showing the sheet resistance relative to the dose of impurities in a semiconductor device according to aspects of this disclosure.

[0012] Figure 13 This is a view of the configuration of a system including semiconductor devices according to aspects of this disclosure.

[0013] Explanation of icon numbers:

[0014] 10: Semiconductor devices

[0015] 101: Substrate

[0016] 111: First semiconductor layer

[0017] 111': n-type LDD region

[0018] 111": n-type source / drain region

[0019] 111T: Top surface

[0020] 120: P-type channel area

[0021] 121: Second semiconductor layer

[0022] 121': p-type lightly doped drain (LDD) region

[0023] 121": p-type source / drain region

[0024] 121T: Top surface

[0025] 131: Device isolation layer

[0026] 131T: Top surface

[0027] 210: Dummy gate structure

[0028] 211: Dummy Gate

[0029] 213: Gate Mask

[0030] 220: Spacer

[0031] 230: Gate structure

[0032] 231: Gate insulating layer

[0033] 233: Gate electrode

[0034] 310: Intermetallic insulation layer

[0035] 320: Contact plug

[0036] 330: Interlayer insulation layer

[0037] 340: Wire

[0038] 1000: System

[0039] 1010: Controller

[0040] 1020: Input / Output Device

[0041] 1030: Memory device

[0042] 1040: Interface

[0043] 1050: Bus

[0044] AR: Active Area

[0045] M1: First mask pattern

[0046] M2: Second mask pattern

[0047] M3: Third Mask Pattern

[0048] M4: Fourth Mask Pattern

[0049] Rs: Thin film resistance

[0050] TR1: n-type transistor

[0051] TR2: p-type transistor Detailed Implementation

[0052] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings.

[0053] Figures 1 to 11 This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to aspects of this disclosure.

[0054] See Figure 1The substrate 101 may include a first transistor region n-FET and a second transistor region p-FET.

[0055] Substrate 101 may comprise silicon (Si), such as crystalline silicon (Si), polycrystalline silicon (Si), or amorphous silicon (Si). In other embodiments, substrate 101 may comprise a compound semiconductor, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, substrate 101 may comprise conductive regions, such as impurity-doped wells or impurity-doped structures. Hereinafter, in the current example embodiment, substrate 101 is a Si substrate.

[0056] Substrate 101 may include a first transistor region n-FET and a second transistor region p-FET. Multiple semiconductor devices may be located in each of the first transistor region n-FET and the second transistor region p-FET. As will be described below, the semiconductor devices on substrate 101 may be isolated by a device isolation layer (e.g., Figure 4 The device is electrically separated from each other by an isolation layer 131.

[0057] The first transistor region and the second transistor region can be defined relative to each other. That is, when the first transistor region is an n-FET region, the second transistor region can be a p-FET region. Alternatively, when the first transistor region is a p-FET region, the second transistor region can be an n-FET region. In the present example embodiment, the second transistor region is a p-FET region.

[0058] See Figure 2 The first semiconductor layer 111 may be formed on the first transistor region n-FET. The first mask pattern M1 may be formed on the second transistor region p-FET.

[0059] The first semiconductor layer 111 may be formed on the first transistor region n-FET, and the first semiconductor layer 111 may be silicon (Si), silicon germanium (SiGe), or any material suitable for a semiconductor device, grown from the Si atoms constituting the substrate 101 using an epitaxial growth process. In the present example embodiment, the first semiconductor layer 111 is a Si layer.

[0060] Therefore, the lattice structure of the channel region of the semiconductor device in the first transistor region n-FET can be determined by the lattice structure of the substrate 101 and the lattice structure of the first semiconductor layer 111. Simultaneously, the epitaxial growth process allows the substrate 101 to be free of lattice defects or have minimal lattice defects.

[0061] Since the first mask pattern M1 is formed in the second transistor region p-FET, the epitaxial growth of Si in the second transistor region p-FET can be suppressed / prevented, so that Si epitaxial growth can be selectively performed in the first transistor region n-FET.

[0062] The first semiconductor layer 111 is grown to minimize defects and maximize strain. The first semiconductor layer 111 forms an active region (e.g., ...) in a subsequent process. Figure 4 The upper part of the active region (AR).

[0063] Considering subsequent processes, the top surface 111T of the first semiconductor layer 111 may be flush with or not flush with the top surface of the substrate 101. The position of the top surface 111T of the first semiconductor layer 111 can be adjusted according to the difficulty caused by the difference in topology between the first transistor region n-FET and the second transistor region p-FET to be performed in subsequent processes.

[0064] See Figure 3 Remove the first mask pattern (e.g., Figure 2 After the first mask pattern M1, the second semiconductor layer 121 can be formed in the second transistor region p-FET using the second mask pattern M2 formed on the first semiconductor layer 111.

[0065] The second semiconductor layer 121 may be formed in the second transistor region p-FET and may be Si, SiGe, or any material suitable for a semiconductor device, grown from the Si atoms constituting the substrate 101 using an epitaxial growth process. In the present example embodiment, the second semiconductor layer 121 is a SiGe layer.

[0066] Therefore, the lattice structure of the channel region of the semiconductor device in the second transistor region p-FET can be determined by the lattice structure of the substrate 101 and the second semiconductor layer 121. The channel region of the second transistor region p-FET may contain more than 50 atomic percent (referred to herein as at%) Ge atoms. Simultaneously, dangling bonds affecting the channel current characteristics may be present in the channel region of the second transistor region p-FET. Therefore, an epitaxial growth process can be performed such that the substrate 101 is free of lattice defects or has only minimal lattice defects.

[0067] Since the second mask pattern M2 is formed in the first transistor region n-FET, SiGe epitaxial growth in the first transistor region n-FET can be prevented, allowing SiGe epitaxial growth to be selectively performed in the second transistor region p-FET.

[0068] The second semiconductor layer 121 can be grown to minimize defects and maximize strain. The second semiconductor layer 121 forms the active region in subsequent processes (see...). Figure 4 The upper part of the AR). Since the mobility of holes, which are charge carriers in the channel region, affects the characteristics of the device in a p-type transistor, a method of applying strain to the channel region can be used.

[0069] SiGe has a larger lattice constant than Si. The stress caused by this lattice constant mismatch results in strain, such as tension strain, which can thus improve hole mobility. During subsequent processing, the strain can be fully retained or partially released.

[0070] Considering the above process, the top surface 121T of the second semiconductor layer 121 may be flush with or not flush with the top surface of the substrate 101. The position of the top surface 121T of the second semiconductor layer 121 can be adjusted according to the difficulty of the process caused by the difference in topology between the second transistor region p-FET and the first transistor region n-FET performed in the above process.

[0071] See Figure 4 When removing the second mask pattern (e.g., Figure 3 After the second mask pattern M2), the active regions AR of the substrate 101 can be electrically separated from each other through the device isolation layer 131.

[0072] Device isolation layer 131 may include an insulating layer, but may also include an outer insulating layer and an inner insulating layer. The outer and inner insulating layers may be formed of different materials. For example, the outer insulating layer may include an oxide layer, and the inner insulating layer may include a nitride layer. However, the configuration of device isolation layer 131 is not limited to the above description. For example, device isolation layer 131 may include multiple layers, which may include a combination of at least three types of insulating layers.

[0073] Each of the first transistor region n-FET and the second transistor region p-FET can be included therein to form an active region AR of a semiconductor device. A device isolation layer 131 can define each active region AR. The first transistor region n-FET and the second transistor region p-FET can be separated from each other by the device isolation layer 131. That is, the device isolation layer 131 can be referred to as a field region. Furthermore, the device isolation layer 131 can be a shallow trench isolation region.

[0074] According to this disclosure, the top surface 121T of the second semiconductor layer 121 constituting the upper portion of the active region AR of the second transistor region p-FET can be substantially flush with the top surface 131T of the device isolation layer 131. Furthermore, the top surface 111T of the first semiconductor layer 111 can be substantially flush with the top surface 131T of the device isolation layer 131. That is, the top surfaces 111T of the first semiconductor layer 111, the second semiconductor layer 121, and the device isolation layer 131 can be flush or substantially flush.

[0075] See Figure 5 Multiple dummy gate structures 210 can be formed to form an alternative metal gate for a gate lastscheme-applied device.

[0076] Multiple dummy gate structures 210 can be formed using a process for forming multiple dummy gates 211 and a process for forming a gate mask 213 on the top surface of the multiple dummy gates 211.

[0077] The method for forming multiple dummy gate structures 210 will now be described in more detail.

[0078] A dummy gate forming layer can be formed on the first semiconductor layer 111 and the second semiconductor layer 121, and a gate mask forming layer can be formed on the dummy gate forming layer. A mask pattern for forming a plurality of dummy gates 211 and gate masks 213 is formed on the gate mask forming layer. The mask pattern can be used as an etching mask to etch the gate mask forming layer and the dummy gate forming layer to form a plurality of dummy gate structures 210 including a plurality of dummy gates 211 and gate masks 213 on the first semiconductor layer 111 and the second semiconductor layer 121. A plurality of dummy gates 211 having the same width and height can be formed on the first semiconductor layer 111 and the second semiconductor layer 121. However, this disclosure is not limited to this, and a plurality of dummy gates 211 with different widths and heights can be formed.

[0079] For example, the dummy gate 211 may be formed of Si. More specifically, the dummy gate 211 may be formed of polysilicon, amorphous silicon, or a combination thereof. Polysilicon may be formed using chemical vapor deposition (CVD), and amorphous silicon may be formed using sputtering, CVD, plasma deposition, and similar processes. However, this disclosure is not limited thereto. In the present exemplary embodiment, the dummy gate 211 is formed of polysilicon.

[0080] The dummy gate 211 may have the same width in the same region. Alternatively, the dummy gate 211 may have different widths even in the same region, depending on its purpose. Although dummy gates 211 with the same width are formed on the first semiconductor layer 111 and the second semiconductor layer 121 in the drawings, this disclosure is not limited thereto.

[0081] For example, gate mask 213 may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. Gate mask 213 may be formed using CVD. In the present embodiment, each of gate masks 213 comprises a silicon nitride layer.

[0082] The width and height of each gate mask 213 can be changed according to the dummy gate 211. The larger the width of the dummy gate 211, the larger the width of the gate mask 213.

[0083] Gate masks 213 may have the same height in the same region. Alternatively, gate masks 213 may have different heights even in the same region. Although the figures show gate masks 213 with the same height formed on the first semiconductor layer 111 and the second semiconductor layer 121, this disclosure is not limited thereto.

[0084] See Figure 6 p-type lightly doped drain (LDD) regions 121' can be formed by ion implantation of gallium (Ga) with impurities.

[0085] As semiconductor devices become increasingly integrated, the size of the transistors that make up integrated circuits is gradually decreasing. Consequently, the channel length of transistors also decreases, potentially leading to short-channel effects that degrade transistor characteristics. These short-channel effects can be caused by drain-induced barrier lowering (DIBL), punch-through, or hot carrier effects.

[0086] The hot carrier effect refers to the phenomenon that as the distance between the source and drain decreases, carriers emitted from the source are rapidly accelerated by the high electric field near the drain edge, resulting in hot carriers, which degrade transistor characteristics. LDD regions can be used to mitigate transistor degradation caused by hot carriers.

[0087] The method for forming the p-type LDD region 121' will be described in more detail herein. First, a third mask pattern M3 covering the first transistor region n-FET can be formed. The third mask pattern M3 can be formed using an exposure and development process. Subsequently, the third mask pattern M3 and the dummy gate structure 210 on the second semiconductor layer 121 can be used as a blocking mask for ion implantation (IIP) to implant Ga as an impurity into the exposed region. The IIP can be performed using an ion implantation device, and the tilt angle of the IIP (the angle formed by it and the top surface of the substrate 101) can be in the range of about 30° to about 90°.

[0088] Although not shown, halo ion implantation of n-type impurities can be performed before or after the formation of the p-type LDD region 121'. Halo ion implantation uses impurities of the opposite type to those in the transistor. Halo ion implantation effectively prevents punch-through.

[0089] According to aspects of this disclosure, the Ga dose in the p-type LDD region 121' can be from about 1E13 to 2E15 atoms per square centimeter (atoms / cm²). 2 As the stoichiometry of Ge in the SiGe constituting the second semiconductor layer 121 increases, the p-type LDD region 121' is doped with Ga. Ga has a higher degree of electrical activation compared to boron (B), which improves the speed characteristics of the p-type transistor. When Ga with a relatively high degree of activation is used in the second semiconductor layer 121, lower resistance can be achieved compared to implanting the same amount of B as Ga, thus improving the speed characteristics of the p-type transistor. This will be referred to... Figure 12 Describe in detail.

[0090] See Figure 7 When removing the third mask pattern (e.g., Figure 6 After the third mask pattern M3, an n-type LDD region 111' can be formed by performing ion implantation of n-type impurities on the first transistor region n-FET, and spacers 220 can be formed at the two sidewalls of each of the plurality of dummy gate structures 210.

[0091] The process for forming the n-type LDD region 111' is similar to the process for forming the p-type LDD region 121' in the second transistor region p-FET. However, the difference lies in that an n-type impurity is implanted into the second transistor region p-FET. For example, the n-type impurity can be a Group V element. The process for forming the n-type LDD region 111' can be referenced by those skilled in the art. Figure 6 The description has been modified. Therefore, its detailed description will be omitted.

[0092] Although not shown, cyclic ion implantation can be performed using p-type impurities before or after the formation of the n-type LDD region 111'. Cyclic ion implantation uses impurities of the opposite type to those used in transistors.

[0093] After forming the n-type LDD region 111' and the p-type LDD region 121', spacers 220 may be formed on both sides of each of the plurality of dummy gate structures 210. Spacers 220 may be formed of at least one material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. In the present exemplary embodiment, spacers 220 comprise a single layer. However, this disclosure is not limited thereto, and spacers 220 may also comprise two or three layers.

[0094] See Figure 8 Ga can be implanted as an impurity ion into the second transistor region p-FET to form a p-type source / drain region 121".

[0095] The method for forming the p-type source / drain region 121" will now be described in more detail.

[0096] First, a fourth mask pattern M4 can be formed to cover the first transistor region n-FET. The fourth mask pattern M4 can be formed using an exposure and development process. Subsequently, the fourth mask pattern M4, the dummy gate structure 210 disposed on the second semiconductor layer 121, and the spacers 220 formed at the two sidewalls of each dummy gate structure 210 are used as a blocking mask for IIP to implant Ga (which is an impurity) into the exposed region. IIP can be performed using an ion implantation device, and the tilt angle of the IIP (the angle formed between it and the top surface of the substrate 101) can be in the range of about 70° to about 90°.

[0097] According to various aspects of this disclosure, the Ga dose in the p-type source / drain region 121" can be 5E13 to 5E15 atoms / cm². The Ga dose in the p-type source / drain region 121" can be higher than the Ga dose in the p-type LDD region 121'.

[0098] As the stoichiometry of Ge in the SiGe constituting the second semiconductor layer 121 increases, the p-type source / drain region 121" can be doped with Ga, which has a higher electroactivation degree than B, thereby improving the speed characteristics of the p-type transistor. The p-type source / drain region 121" can be formed not only on the second semiconductor layer 121, but also on a portion of the substrate 101. That is, the upper portion of the p-type source / drain region 121" can be an epitaxial growth layer of SiGe containing more than 50 atomic percent Ge, while the other portions of the p-type source / drain region 121" can be Si.

[0099] When Ga, which has a relatively high activation level, is used in the second semiconductor layer 121, for example, in the upper portion of the p-type source / drain region 121", lower resistance can be achieved compared to the case where the same dose of B is implanted therein, thereby improving the speed characteristics of the p-type transistor. This will be referred to below. Figure 12 Describe in detail.

[0100] The p-type source / drain region 121" can be formed in the substrate 101 on both sides of the spacer 220, and the p-type channel region 120 located between the p-type source / drain regions 121" can be defined below the dummy gate structure 210.

[0101] The p-type channel region 120 may be located within the second semiconductor layer 121. That is, the p-type channel region 120 may be an epitaxial growth layer of SiGe containing more than 50 atomic percent Ge. In other words, the p-type channel region 120 may be located within a channel silicon-germanium (c-SiGe) layer. Furthermore, p-type LDD regions 121' may be located on both sides of the p-type channel region 120. Since the region where the p-type LDD region 121' overlaps with the p-type source / drain region 121" is defined as the p-type source / drain region 121", the p-type LDD region 121' may only be located on both sides of the p-type channel region 120.

[0102] See Figure 9 When removing the fourth mask pattern (e.g., Figure 8 After the fourth mask pattern M4, n-type source / drain regions 111" can be formed by implanting n-type impurity ions into the first transistor region n-FET.

[0103] The process for forming the n-type source / drain region 111" is similar to the process for forming the p-type source / drain region 121" in the second transistor region p-FET. However, the only difference is that an n-type impurity is implanted in the second transistor region p-FET. The n-type impurity can be a Group V element. The process for forming the n-type source / drain region 111" can be referenced by those skilled in the art. Figure 8 The description has been modified, and therefore its detailed description will be omitted.

[0104] The n-type source / drain region 111" can be formed not only on the first semiconductor layer 111, but also on a portion of the substrate 101. That is, the upper portion of the n-type source / drain region 111" can be an epitaxial growth layer of Si, and the other portions of the n-type source / drain region 111" can also be Si.

[0105] The n-type source / drain region 111" can be formed in the substrate 101 on both sides of the spacer 220, and the n-type channel region 110 located between the n-type source / drain regions 111" can be defined below the dummy gate structure 210.

[0106] The n-type channel region 110 may be located within the first semiconductor layer 111. That is, the n-type channel region 110 may be an epitaxial growth layer of Si. In other words, the n-type channel region 110 may be located within a channel silicon (c-Si) layer. Furthermore, the n-type LDD region 111' may be located on both sides of the n-type channel region 110. The overlapping region between the n-type LDD region 111' and the n-type source / drain region 111" can be defined as the n-type source / drain region 111". That is, the n-type LDD region 111' may only be located on both sides of the n-type channel region 110.

[0107] After performing impurity doping on the n-type LDD region 111', p-type LDD region 121', n-type source / drain region 111", and p-type source / drain region 121", the substrate 101 can be annealed at a temperature of about 650°C to 1050°C for about 5 to 240 seconds to repair damage caused by impurity implantation. The time and temperature are not limited to the above values.

[0108] See Figure 10 Multiple dummy gate structures can be removed (see...) Figure 9 (210) to form multiple gate structures 230.

[0109] The method of forming multiple gate structures 230 will now be described in more detail in this paper.

[0110] First, for example, removing multiple dummy gate structures (see...) Figure 9 The etching process of (210) can be a wet etching process using ammonia, tetramethyl ammonium hydroxide (TMAH), and / or tetraethyl ammonium hydroxide (TEAH). However, this disclosure is not limited thereto.

[0111] An interface layer (not shown) and a gate insulating layer 231 may be formed in the trenches that expose the top surface of the n-type channel region 110 and the top surface of the p-type channel region 120.

[0112] The interface layer can prevent the gate insulating layer 231 formed thereon from contacting the underlying first semiconductor layer and second semiconductor layer (e.g. Figure 5 Interface defects between semiconductor layers 111 and 121. For example, the interface layer may be a silicon oxide layer, a silicon oxynitride layer, a silicate layer, or a combination thereof. In some embodiments, the process of forming the interface layer may be omitted or can be omitted.

[0113] The gate insulating layer 231 can be formed using atomic layer deposition (ALD) or chemical oxidation. The gate insulating layer 231 may contain a high-dielectric-constant dielectric material. The high-dielectric-constant dielectric material may be a material with a dielectric constant higher than that of the silicon oxide layer.

[0114] High dielectric constant dielectric materials may include at least one selected from the group consisting of: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate.

[0115] A gate electrode 233 may be formed on the gate insulating layer 231. The gate electrode 233 may comprise titanium, titanium nitride, tantalum, tantalum nitride, tungsten, copper, aluminum, or mixtures thereof. The gate electrode 233 may be formed using processes such as ALD, metal-organic ALD (MOALD), CVD, metal-organic CVD (MOCVD), or physical vapor deposition (PVD). However, this disclosure is not limited thereto.

[0116] In some embodiments, during the formation of the gate electrode 233, in order to improve the reliability of the high-dielectric-constant dielectric material constituting the gate insulating layer 231 and the metal layer stack structure constituting the gate electrode 233, after forming a portion of the metal layer stack structure constituting the gate electrode 233 on the gate insulating layer 231, a polysilicon sacrificial layer for heat treatment may be formed on the portion of the metal layer. The resulting structure can be heat-treated, and then the polysilicon sacrificial layer for heat treatment can be removed again. Subsequently, another metal layer may be formed on the heat-treated portion of the metal layer to form the gate electrode 233.

[0117] Each of the n-type transistor TR1 and the p-type transistor TR2, which includes multiple gate structures 230 and spacers 220, may have a planar structure. That is, the first semiconductor layer and the second semiconductor layer (e.g., ...) formed on the substrate 101 Figure 5 Semiconductor layers 111 and 121 can be generally formed as flat, and n-type transistor TR1 and p-type transistor TR2 can be formed on the first semiconductor layer and the second semiconductor layer.

[0118] See Figure 11 The semiconductor device 10 may include a contact plug 320 and a wire 340.

[0119] An intermetallic insulating layer 310 may be formed on multiple gate structures 230 and spacers 220. The intermetallic insulating layer 310 may comprise a silicon oxide layer, a silicon nitride layer, or a combination thereof. The contact plug 320 may penetrate the intermetallic insulating layer 310 and thus be in direct contact with the n-type source / drain region 111" and the p-type source / drain region 121".

[0120] The method of forming the contact plug 320 will now be described in more detail in this paper.

[0121] A mask pattern (not shown) may be formed on the intermetallic insulating layer 310. The mask pattern may cover a portion of the intermetallic insulating layer 310 except for the area where the contact hole will be formed. After the mask pattern (not shown) is formed on the intermetallic insulating layer 310, it may be used as an etching mask to etch a portion of the intermetallic insulating layer 310 to form the contact hole. The n-type source / drain region 111" and the p-type source / drain region 121" may be exposed through the contact hole.

[0122] A conductive barrier layer (not shown) can be formed covering the inner wall of the contact hole. Conductive material can be filled into the contact hole to form a contact plug 320.

[0123] Subsequently, an interlayer insulating layer 330 and a conductive line 340 may be formed on the top surfaces of the intermetallic insulating layer 310 and the contact plug 320. In some embodiments, the contact plug 320 and the conductive line 340 may be formed using a damascene process or a dual damascene process. These processes can be performed by those skilled in the art in the process of forming semiconductor devices, and therefore their detailed description will be omitted.

[0124] Through these processes, aspects of this disclosure provide a semiconductor device 10 having a p-type transistor TR2 with improved speed characteristics.

[0125] Figure 12 It is a graph showing the sheet resistance relative to the dose of impurities in a semiconductor device according to aspects of this disclosure.

[0126] See Figure 12 The sheet resistance Rs is plotted based on the dosage of B and Ga relative to SiGe containing approximately 55 at% Ge.

[0127] CMOS transistors require both n-type and p-type transistors. In this configuration, electrons and holes are used as charge carriers. When Si is used as the material in the active region, the mobility of holes is lower than that of electrons. Therefore, the performance of p-type transistors is relatively lower than that of n-type transistors.

[0128] To improve the performance of p-type transistors, a process was applied to the active region using SiGe instead of Si. In pure Si and pure Ge, the hole mobility is 450 cm⁻¹. 2 / V·s and 1900cm 2 / V·s, and SiGe has values ​​corresponding to its stoichiometry.

[0129] Furthermore, to configure p-type transistors, after SiGe is formed by epitaxial growth, ion implantation is used to implant the desired impurities at the required concentration and depth. It has been found that in p-type transistors, when p-type impurity ions are implanted into the LDD region and the source / drain region, and the Ge content in the SiGe constituting the active region is sufficiently high (e.g., when Ge exceeds 50 atomic percent), Ga exhibits a higher activation level than B, which is located in the same Group III element.

[0130] Therefore, when Ga, which has a relatively high activation level, is used as an impurity in a p-type transistor, a lower resistance can be achieved compared to implanting the same amount of B, thereby improving the speed characteristics of the p-type transistor and thus improving the characteristics of the semiconductor device.

[0131] To verify the results in the SiGe layer, the sheet resistance Rs was measured based on the doses of B and Ga in a SiGe layer containing approximately 55 at% Ge. The doses of B and Ga are expressed on a logarithmic scale.

[0132] like Figure 12 As explained, the Ga dosage is less than the B dosage to demonstrate the equivalent sheet resistance Rs. Specifically, to achieve a sheet resistance Rs of approximately 4100 Ω / sq, a B dosage of approximately 2E14 atoms / cm² is required, and when doped with the same Ga dosage, the sheet resistance Rs can be approximately 2000 Ω / sq.

[0133] In other words, when the Ga dosage is the same as the B dosage, their sheet resistance Rs values ​​can differ by a factor of two or more. A lower sheet resistance Rs is an index that indirectly represents an increase in hole mobility. Therefore, even when implanting impurities with the same dosage, Ga doping can improve the speed characteristics of p-type transistors.

[0134] Therefore, when using SiGe containing more than 50 atomic percent Ge in the active region of a p-type transistor, if Ga, a Group III element, is used as an impurity, it is expected that the same or better improved hole mobility can be obtained with a lower dosage compared to the case where B is used as an impurity. Thus, the speed characteristics of the p-type transistor can be improved, and consequently, the characteristics of the semiconductor device can be enhanced.

[0135] Figure 13 It is a view of the configuration of a system including semiconductor devices according to aspects of this disclosure.

[0136] See Figure 13 The system 1000 includes a controller 1010, an input / output device 1020, a memory device 1030, an interface 1040, and a bus 1050.

[0137] System 1000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, a memory card, or the like.

[0138] In the control system 1000, the controller 1010 used to control the execution program can be a microprocessor, digital signal processor, microcontroller or similar device.

[0139] Input / output device 1020 can be used to input or output data to system 1000. System 1000 can be connected to external devices, such as personal computers or networks, or data can be exchanged with external devices using input / output device 1020. Input / output device 1020 can be a touchpad, keyboard, or display device.

[0140] The memory device 1030 may store data for operating the controller 1010 or data processed by the controller 1010. The memory device 1030 may include the semiconductor device 10 of the above embodiments according to the inventive concepts provided herein.

[0141] Interface 1040 can be a data transmission path between system 1000 and external devices. Controller 1010, input / output device 1020, memory device 1030 and interface 1040 can be interconnected via bus 1050.

[0142] While the inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, characterized by comprising: include: Substrate, including the field region that defines the active region; Source / drain regions are located within the active region; The channel region is located between the source region and the drain region; A lightly doped drain region is located between one of the source / drain regions and the channel region; as well as The gate structure is located on the channel region. The upper portion of the active region includes a strained epitaxial growth layer, the epitaxial growth layer having a lattice constant greater than that of the substrate and comprising a silicon-germanium layer containing more than 50 atomic percent germanium, and The source / drain region and the lightly doped drain region are doped with gallium, wherein the gallium dose in the source / drain region is 5E13 atoms / cm² to 5E15 atoms / cm², and the gallium dose in the lightly doped drain region is 1E13 to 2E15 atoms / cm². The channel region is located in the silicon-germanium layer below the gate structure, the top surface of the field region and the top surface of the epitaxial growth layer are substantially coplanar, and the thickness of the epitaxial growth layer in the source / drain region, the thickness of the epitaxial growth layer in the lightly doped drain region and the thickness of the epitaxial growth layer in the channel region are substantially the same.

2. The semiconductor device according to claim 1, characterized in that, The top surface of the epitaxial growth layer is generally flat.

3. The semiconductor device according to claim 1, characterized in that, The gate structure is a planar structure.

4. The semiconductor device according to claim 3, characterized in that, The gate structure includes a high-dielectric-constant dielectric gate insulating layer and a metal gate electrode.

5. A semiconductor device, characterized in that, include: The substrate includes a first transistor region and a second transistor region defined by the field region and includes a first material; The first active region is located in the first transistor region; as well as The second active region is located in the second transistor region and includes a source / drain region, a lightly doped drain region, and a channel region. in: The upper region of the first active region includes a first epitaxial growth layer, and the first epitaxial growth layer includes the first material. The upper portion of the second active region includes a second epitaxial growth layer, which comprises a second material exceeding 50 atomic percent. The second material is different from the first material. The source / drain region and the lightly doped drain region are doped with gallium. The first dose of gallium in the lightly doped drain region is lower than the second dose of gallium in the source / drain region, and The top surface of each of the first active region and the second active region is flat. The lattice constant of the second epitaxial layer is greater than that of the substrate. The second epitaxial growth layer experiences strain due to lattice constant mismatch. The second epitaxial growth layer comprises tensile strained silicon-germanium, and the second material is germanium. The channel region is located in the second active region, the top surface of the field region and the top surface of the second epitaxial growth layer are substantially coplanar, and the thickness of the second epitaxial growth layer in the source / drain region, the thickness of the second epitaxial growth layer in the lightly doped drain region and the thickness of the second epitaxial growth layer in the channel region are substantially the same.

6. The semiconductor device according to claim 5, characterized in that, The lightly doped drain region is located between one of the source / drain regions and the channel region.

7. A semiconductor device, characterized in that, include: The active region is defined by the field region and includes the channel region and the gallium-doped source / drain region, wherein the gallium dose in the source / drain region is from 5E13 atoms / cm² to 5E15 atoms / cm². A lightly doped drain region, located between one of the source / drain regions and the channel region, and doped with gallium, wherein the gallium dose in the lightly doped drain region is 1E13 to 2E15 atoms / cm². A channel silicon-germanium layer forms the upper portion of the active region and includes more than 50 atomic percent germanium; as well as The gate structure is located on the channel silicon-germanium layer and includes a high-dielectric-constant gate insulating layer and a metal gate electrode. The channel silicon-germanium layer includes a tension-strain epitaxial growth layer that experiences strain due to lattice constant mismatch, and The top surface of the field region and the top surface of the tension strain epitaxial growth layer are substantially coplanar, and the thickness of the tension strain epitaxial growth layer in the source / drain region and the thickness of the tension strain epitaxial growth layer in the lightly doped drain region are substantially the same.

8. The semiconductor device according to claim 7, characterized in that, The gate structure is a planar structure.

9. The semiconductor device according to claim 7, characterized in that, The channel silicon-germanium layer extends to the lightly doped drain region and the source / drain region.

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