Field Effect Transistor with n-type Doped Diamond Field Plate Structure

Abstract

The invention discloses a field effect transistor with an n-type doped diamond field plate structure, comprising a diamond substrate, a table formed by an n-type doped single crystal diamond epitaxial film is laid on the diamond substrate, two strip-shaped dielectric layers are deposited on the table, a drain electrode and a source electrode are laid along the outer edges of each dielectric layer and the table, a gate electrode is laid between the two dielectric layers, the dielectric layer, the drain electrode, the source electrode and the gate electrode form a field plate structure, a source lead-out electrode, a drain lead-out electrode and a gate lead-out electrode are deposited on the source electrode, the drain electrode and the gate electrode, respectively, and the source lead-out electrode, the drain lead-out electrode and the gate lead-out electrode are completely separated from each other by a passivation layer; the invention introduces a field plate structure at the edges of the source, gate and drain electrodes of the diamond MESFET, effectively reduces the electric field concentration effect, increases the withstand voltage characteristics of the device, effectively weakens the electric field concentration phenomenon at the edges of the source, gate and drain of the device, and improves the breakdown voltage performance of the device.

Description

[Technical field]

[0001] The invention belongs to the field of semiconductor devices, and in particular relates to a field effect transistor with an n-type doped diamond field plate structure. [Background technology]

[0002] As one of the representatives of ultra-wide bandgap semiconductor materials, diamond has incomparable excellent properties in terms of heat, electricity, sound, light, mechanics, etc. that other semiconductor materials cannot match. In terms of thermals, diamond has high thermal conductivity, low thermal melting point, and its heat dissipation efficiency is more significant especially at high temperatures. It is a heat sink material with excellent heat dissipation. In recent years, the development of high thermal conductivity diamond film preparation technology has made the application of diamond thermal deposition in high-power lasers, microwave devices and integrated circuits a reality; in the field of acoustics, diamond has low density and high elastic modulus. These characteristics make diamond a diaphragm for the tweeter of high-fidelity speakers, thereby producing high-end audio speakers and substrate materials for surface acoustic wave (SAW) devices; in the field of optics, diamond is used in addition to about In addition to the tiny absorption peak at the 3-5um position (caused by phonon vibration), diamond has high transmittance in the entire band from ultraviolet (0.22um) to far infrared (millimeter wave band), which makes diamond an ideal window material for high-power infrared lasers and detectors; in terms of electricity, diamond has a high bandgap width, ultra-high breakdown voltage, high Johnson index, high Keyes index, high Baliga index, large electron mobility and hole mobility. Therefore, diamond materials can be used to make ultra-high frequency and ultra-high power electronic devices.

[0003] The rapid development of science, technology and economy in modern society is inseparable from the development of integrated circuits, and the field effect transistor, as the most basic unit in integrated circuits, plays a vital role. From the perspective of device structure, field effect transistors can be divided into metal oxide semiconductor field effect transistors (MOSFET) and metal semiconductor field effect transistors (MESFET). The former is more widely used in the high-power field, and the latter is more widely used in the high-frequency field. However, with the development of semiconductor technology and the increasing complexity of electronic circuits, high-frequency devices must also have high-power characteristics, that is, the requirements for the withstand voltage performance of high-frequency devices are also getting higher and higher.

[0004] At present, although the diamond doping technology is not very mature, different types of doping can be preliminarily achieved by doping with conventional dopants. For example, the doping of boron and phosphorus can achieve p- and n-type doped single crystal diamond. The use of doped diamond can preliminarily realize the preparation of electronic devices. Diamond has the advantages of large bandgap width, high electron-hole mobility, high thermal conductivity, etc., which makes diamond can be used in high-frequency and high-power fields. When using the MESFET structure, due to the electric field concentration effect, the edge of the source, gate and drain electrodes has a high electric field, which is easy to produce hard breakdown phenomenon in these parts. The hard breakdown of MESFET is irreversible, which can damage the normal function of a single device at the least and cause the huge integrated circuit to be paralyzed at the worst. In the field of semiconductor devices, the field plate structure can effectively expand the depletion region at the edge of the electrode, weaken the electric field concentration effect at the edge of the electrode, and increase the withstand voltage value. Therefore, the use of the field plate structure in the source, gate and drain electrodes of the doped diamond MESFET can effectively reduce the electric field concentration effect and increase the withstand voltage characteristics of the device, which is very necessary and urgent for the application of diamond devices in high frequency and high power. [Summary of the invention]

[0005] The purpose of the present invention is to provide a field effect transistor with an n-type doped diamond field plate structure to solve the problem that hard breakdown is easily generated at the edges of the existing source, gate and drain electrodes.

[0006] The present invention adopts the following technical scheme: a field effect transistor with an n-type doped diamond field plate structure comprises a diamond substrate, a table formed by an n-type doped single crystal diamond epitaxial film is laid on the diamond substrate, two strip-shaped dielectric layers are deposited on the table, a drain electrode and a source electrode are laid along the outer edges of each dielectric layer and the table, a gate electrode is laid between the two dielectric layers, the dielectric layer, the drain electrode, the source electrode and the gate electrode form a field plate structure, a source lead-out electrode, a drain lead-out electrode and a gate lead-out electrode are deposited on the source electrode, the drain electrode and the gate electrode, respectively, and the source lead-out electrode, the drain lead-out electrode and the gate lead-out electrode are completely separated from each other by a passivation layer.

[0007] Furthermore, the gate covers a portion of the dielectric layer and a portion of the mesa.

[0008] Furthermore, the outer edge of the short side of the gate exceeds the outer edge of the mesa, or is flush with the outer edge of the mesa.

[0009] Furthermore, the gate and the mesa are in Schottky contact.

[0010] Furthermore, the cross section of the source electrode is L-shaped, a portion of the L-shape is directly covered on the diamond substrate, and another portion of the L-shape is covered on the dielectric layer and a portion of the terrace.

[0011] Furthermore, the cross section of the drain is L-shaped, a portion of the L-shape is directly covered on the diamond substrate, and another portion of the L-shape is covered on the dielectric layer and a portion of the terrace.

[0012] Furthermore, the outer edges of the short sides of the source and the drain both exceed the outer edge of the mesa, or are flush with the outer edge of the mesa.

[0013] Furthermore, the source and the drain are in ohmic contact with the mesa.

[0014] Furthermore, the passivation layer also covers the exposed parts of the diamond substrate except the source lead-out electrode, the drain lead-out electrode and the gate lead-out electrode.

[0015] Furthermore, the outer edges of the short sides of the two dielectric layers are both beyond the outer edge of the mesa, or are flush with the outer edge of the mesa.

[0016] The beneficial effects of the present invention are as follows: a field plate structure is introduced at the edges of the source, gate and drain electrodes of the diamond MESFET, which effectively reduces the electric field concentration effect, increases the voltage resistance characteristics of the device, effectively weakens the electric field concentration phenomenon at the edges of the source, gate and drain of the device, and improves the breakdown voltage performance of the device; the breakdown voltage of the device can be increased by setting the field plate structure, because the field plate structure can evenly distribute the electric field under the field plate, eliminate the electric field concentration phenomenon, increase the breakdown voltage of the device, and make it less likely for the edges of the source, gate and drain electrodes to produce hard breakdown.

Brief Description of the Drawings

[0017] Figure 1 is a schematic diagram of the transistor structure in the present invention;

[0018] Figure 2 It is a top view and a side view of step 1 in the present invention;

[0019] Figure 3 It is a top view and a side view of step 2 in the present invention;

[0020] Figure 4 It is a top view and a side view of step 3 in the present invention;

[0021] Figure 5 It is a top view and a side view of step 4 in the present invention;

[0022] Figure 6 It is a top view and a side view of step 5 in the present invention;

[0023] Figure 7 It is a top view and a side view of step 6 in the present invention;

[0024] Figure 8 It is a top view and a side view of step 7 in the present invention;

[0025] Fig. 9It is a top view and a side view of step 8 in the present invention;

[0026] Fig.10 It is a top view and a side view of step 9 in the present invention.

[0027] Among them: 1. Diamond substrate; 2. n-type doped single crystal diamond epitaxial film; 3. table; 4. field plate structure; 5. source; 6. drain; 7. gate; 8. passivation layer; 9. source extraction electrode; 10. drain extraction electrode; 11. gate extraction electrode. [Specific implementation method]

[0028] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] The present invention discloses a field effect transistor with an n-type doped diamond field plate structure, such as Figure 1 As shown, it includes a diamond substrate 1, on which a table 3 formed by an n-type doped single crystal diamond epitaxial film 2 is laid, on which two strip-shaped dielectric layers 4 are laid, along the outer edges of each dielectric layer 4 and the table 3, respectively, a drain 6 and a source 5 are laid, and between the two dielectric layers 4, a gate 7 is laid, and the dielectric layer 4, the drain 6, the source 5 and the gate 7 form a field plate structure, and on the source 5, the drain 6 and the gate 7, a source lead-out electrode 9, a drain lead-out electrode 10 and a gate lead-out electrode 11 are deposited, respectively, and the source lead-out electrode 9, the drain lead-out electrode 10 and the gate lead-out electrode 11 are completely separated from each other by a passivation layer 8.

[0030] The gate 7 covers part of the dielectric layer 4 and part of the terrace 3, the outer edge of the short side of the gate 7 exceeds the outer edge of the terrace 3, or is flush with the outer edge of the terrace 3, the gate 7 is in Schottky contact with the terrace 3, and the cross-section of the drain 6 is L-shaped, a part of the L-shape is directly covered on the diamond substrate 1, and the other part of the L-shape is covered on the dielectric layer 4 and part of the terrace 3.

[0031] The cross section of the drain electrode 6 is L-shaped, a part of the L-shape directly covers the diamond substrate 1, and another part of the L-shape covers the dielectric layer 4 and part of the table 3. The outer edges of the short sides of the source electrode 5, the drain electrode 6 and the dielectric layer 4 all exceed the outer edge of the table 3, or are flush with the outer edge of the table 3; the source electrode 5 and the drain electrode 6 are in ohmic contact with the table 3. The passivation layer 8 also covers the exposed parts of the diamond substrate 1 except the source extraction electrode 9, the drain extraction electrode 10 and the gate extraction electrode 11.

[0032] The breakdown voltage of the device can be increased by providing a field plate structure, because the field plate structure can evenly distribute the electric field below the field plate, thereby eliminating the electric field concentration phenomenon and increasing the breakdown voltage of the device.

[0033] The method for preparing the field effect transistor of the n-type doped single crystal diamond field plate structure of the present invention is as follows:

[0034] Step 1: removing the non-diamond phase on the surface of the diamond substrate 1.

[0035] Step 2: growing a layer of n-type doped single crystal diamond epitaxial film 2 on the diamond substrate 1.

[0036] Step 3: Etching the n-type doped single crystal diamond epitaxial film 2 to form a mesa 3 .

[0037] Step 4: Deposit two strip-shaped dielectric layers 4 on the terrace 3 .

[0038] Step 5: forming a drain 6 and a source 5 along the outer edges of each dielectric layer 4 and the mesa 3 respectively.

[0039] Step 6: Form a gate 7 between the two dielectric layers 4 to finally form a field plate structure.

[0040] Step 7: Cover all structures with a passivation layer 8.

[0041] Step 8: remove part of the passivation layer 8 on the source electrode 5, the drain electrode 6 and the gate electrode 7 to form a through hole.

[0042] Step 9: depositing a source lead-out electrode 9 , a drain lead-out electrode 10 and a gate lead-out electrode 11 on the source electrode 5 , the drain electrode 6 and the gate electrode 7 along the through hole.

[0043] Wherein, in step 1, the diamond substrate 1 is an intrinsic diamond material, and the non-diamond phase on the surface of the diamond substrate 1 is removed; Figure 2 As shown, the diamond substrate 1 is cleaned using a standard acid-base cleaning process to remove the non-diamond phase on the surface, and then the diamond substrate 1 is cleaned using alcohol, acetone, and deionized water, and the diamond substrate 1 is dried using nitrogen.

[0044] The n-type doped single crystal diamond epitaxial film 2 in step 2 is a phosphorus-doped diamond material, and its conductivity is n-type. The thickness of the n-type doped single crystal diamond epitaxial film 2 is 0-100 μm. A layer of n-type doped single crystal diamond epitaxial film 2 is grown on a diamond substrate 1.

[0045] A 1 μm thick n-type doped single crystal diamond epitaxial film 2 is grown on a diamond substrate 1 using microwave plasma chemical vapor deposition technology. The growth conditions are: power 1 KW, chamber pressure 50 Torr, total gas flow 500 sccm, and phosphine 20 sccm.

[0046] The method for forming the mesa 3 in step 3 is to remove part of the n-type doped single crystal diamond epitaxial film, that is, to remove the edge of the n-type doped single crystal diamond epitaxial film to form the mesa 3, the surface area of ​​the mesa 3 is smaller than the surface area of ​​the n-type doped single crystal diamond epitaxial film 2 grown in step 2, the thickness of the mesa 3 is greater than the thickness of the n-type doped single crystal diamond epitaxial film 2 grown in step 2, and the n-type doped single crystal diamond epitaxial film 2 is etched to form the mesa 3;

[0047] like Figure 3 and Figure 4 As shown, a portion of the n-type doped single crystal diamond epitaxial film 2 is patterned and etched away using a photolithography process and an inductively coupled plasma etching technique to form a terrace 3 .

[0048] Photolithography process: Spin a layer of AZ5214 photoresist on the surface of the sample, then heat the sample on a 100℃ hot plate for 90 seconds, then use a UV exposure machine for 5 seconds, then immerse the sample in a developer for 60 seconds, and cover the unetched part with photoresist to leave only the part to be etched. The etching gas is a mixture of oxygen and argon.

[0049] The dielectric layer 4 in step 4 is formed by photolithography and magnetron sputtering, the dielectric constant of the selected target material is greater than 1, the thickness of the formed dielectric layer 4 is greater than 30 nm, and the outer edges of the short sides of the dielectric layer 4 are all beyond the outer edges of the table 3; two strip-shaped dielectric layers 4 are formed on the table 3;

[0050] Acetone, alcohol and deionized water are used to clean the photoresist and impurities on the sample surface. Then, a photolithography process and a magnetron sputtering process are used to deposit a dielectric layer 4. The photolithography process is as follows: Figure 5 shown.

[0051] Photolithography process: Spin a layer of AZ5214 photoresist on the surface of the sample, then heat the sample on a 100℃ hot plate for 90 seconds, then use a UV exposure machine for 5 seconds, then immerse the sample in a developer for 60 seconds, and cover the unetched part with photoresist to leave only the part to be etched. The etching gas is a mixture of oxygen and argon.

[0052] The magnetron sputtering process parameters are: power of 100 W, target material of aluminum oxide, thickness of 30 nm, and argon gas of 30 sccm.

[0053] Among them, the method for forming the source 5 and the drain 6 in step 5 adopts a photolithography process and an electron beam evaporation process. The cross-section of the source 5 and the drain 6 is L-shaped. The source 5 and the drain 6 both cover part of the dielectric layer 4 and part of the table 3. The outer edges of the short sides of the source 5 and the drain 6 both exceed the outer edge of the table 3. The source 5 and the drain 6 are in ohmic contact with the table 3.

[0054] A drain electrode 6 and a source electrode 5 are formed along the outer edges of each dielectric layer 4 and the mesa 3 respectively;

[0055] The device is stripped with acetone to remove excess aluminum oxide and photoresist. Then, the source 5 and drain 6 are deposited using photolithography and electron beam evaporation. The material selected for the electron beam evaporation process is metal titanium / gold. The thickness of titanium is 20nm and the thickness of gold is 100nm. The photolithography process is as follows: Figure 6 As shown, electron beam evaporation process: chamber pressure 5×10 -4 Pa, room temperature.

[0056] Photolithography process: Spin a layer of AZ5214 photoresist on the surface of the sample, then heat the sample on a 100℃ hot plate for 90 seconds, then use a UV exposure machine for 5 seconds, then immerse the sample in a developer for 60 seconds, and cover the unetched part with photoresist to leave only the part to be etched. The etching gas is a mixture of oxygen and argon.

[0057] The device was stripped using acetone to remove excess Ti / Au and photoresist, and then the sample was annealed at 500° C. for 30 minutes in nitrogen to form an ohmic contact between Ti / Au and the mesa 3.

[0058] Among them, the gate 7 formation method in step 6 adopts photolithography process and electron beam evaporation process, the gate 7 covers part of the dielectric layer 4 and part of the table 3, the outer edge of the short side of the gate 7 exceeds the outer edge of the table 3, and the gate 7 and the table 3 are Schottky contact.

[0059] A gate 7 is formed between the two dielectric layers 4; the gate 7 is deposited using a photolithography process and an electron beam evaporation process. The material of the gate 7 is aluminum and the thickness is 150 nm. Figure 3 As shown, the electron beam evaporation process is Figure 7 As shown, Al and the mesa 3 form a Schottky contact.

[0060] Photolithography process: Spin a layer of AZ5214 photoresist on the surface of the sample, then heat the sample on a 100℃ hot plate for 90 seconds, then use a UV exposure machine for 5 seconds, then immerse the sample in a developer for 60 seconds, and cover the unetched part with photoresist to leave only the part to be etched. The etching gas is a mixture of oxygen and argon.

[0061] In step 7, the passivation layer 8 is formed by magnetron sputtering process, the material is a dielectric layer, the dielectric constant of the passivation layer 8 is greater than 1, and the thickness of the passivation layer 8 is greater than 200 nm.

[0062] A passivation layer 8 is used to cover all structures; Figure 8As shown, the device is stripped using acetone to remove excess Al and photoresist, and then a 200 nm layer of silicon dioxide is deposited on the surface of the sample using magnetron sputtering as a passivation layer 8. Magnetron sputtering process parameters: power 120 W, target material silicon dioxide, argon 50 sccm.

[0063] The purpose of forming the through hole in step 8 is to remove the passivation layer 8 from a portion of the area above the source 5 and the gate 7, so that the source, drain and gate electrodes are partially exposed.

[0064] Step 8: removing part of the passivation layer 8 on the source electrode 5, the drain electrode 6 and the gate electrode 7 to form a through hole;

[0065] Use photolithography and wet etching technology to remove part of the silicon dioxide on the source 5, gate 7 and drain 6 to form a through hole. The photolithography process is as follows: Fig. 9 shown.

[0066] Wet etching process: hydrogen fluoride buffer, room temperature.

[0067] In step 9, a source lead electrode 9, a drain lead electrode 10 and a gate lead electrode 11 are deposited along the through hole, and the material used is a conductive material with a sheet resistance of less than 100 KΩ / □.

[0068] A source lead electrode 9, a drain lead electrode 10 and a gate lead electrode 11 are deposited along the through hole;

[0069] like Fig.10 As shown, acetone is used to strip the device to remove excess photoresist, and then a photolithography process and an electron beam evaporation process are used to deposit a source lead electrode 9, a drain lead electrode 10 and a gate lead electrode 11 along the through hole. The material is aluminum and the thickness is 300 nm.

Claims

1. A field effect transistor with an n-type doped diamond field plate structure, characterized in that: The present invention comprises a diamond substrate (1), on which a table (3) formed by an n-type doped single crystal diamond epitaxial film (2) is laid, on which two strip-shaped dielectric layers (4) are deposited, along the outer edges of each of the dielectric layers (4) and the table (3), a drain electrode (6) and a source electrode (5) are laid respectively, between the two dielectric layers (4), a gate electrode (7) is laid, the dielectric layer (4), the drain electrode (6), the source electrode (5) and the gate electrode (7) form a field plate structure, on which a source lead-out electrode (9), a drain lead-out electrode (10) and a gate lead-out electrode (11) are deposited respectively, and the source lead-out electrode (9), the drain lead-out electrode (10) and the gate lead-out electrode (11) are completely separated from each other by a passivation layer (8); The outer edges of the short sides of the two dielectric layers (4) both extend beyond the outer edge of the table top (3), or are flush with the outer edge of the table top (3); The gate (7) covers part of the dielectric layer (4) and part of the mesa (3), and the outer edge of the short side of the gate (7) exceeds the outer edge of the mesa (3) or is flush with the outer edge of the mesa (3); The gate (7) and the table (3) are in Schottky contact; The cross-sections of the source electrode (5) and the drain electrode (6) are both L-shaped, a portion of the L-shape directly covers the diamond substrate (1), and another portion of the L-shape covers the dielectric layer (4) and a portion of the table (3); The outer edges of the short sides of the source (5) and the drain (6) both extend beyond the outer edge of the table top (3), or are flush with the outer edge of the table top (3).

2. The field effect transistor with an n-type doped diamond field plate structure according to claim 1, characterized in that: The source electrode (5) and the drain electrode (6) are both in ohmic contact with the mesa (3).

3. The field effect transistor with an n-type doped diamond field plate structure according to claim 1, characterized in that: The passivation layer (8) also covers the exposed parts on the diamond substrate (1) except the source lead-out electrode (9), the drain lead-out electrode (10) and the gate lead-out electrode (11).

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