Semiconductor device and method for manufacturing semiconductor device

Abstract

This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device is provided that suppresses electromagnetic noise leakage to the outside and the influence of electromagnetic noise from the outside, while exhibiting minimal warping of the semiconductor substrate. It comprises: a lower insulating layer formed on a main surface of a semiconductor substrate; a bonding layer formed and grounded to the upper surface of the lower insulating layer; and a conductive member having a first conductive member having a first film thickness stacked on the bonding layer, and a second conductive member having a second film thickness thinner than the first film thickness and stacked on the bonding layer and grounded to a first conductive region.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] As a package for LSI chips, a wafer-level CSP (Chip Size Package) is used where the size of the semiconductor substrate is equal to the package size and the circuit elements formed on the main surface of the semiconductor substrate are connected to external components through rewiring.

[0003] In such a wafer-level CSP, in order to prevent electromagnetic noise from leaking to the outside from the circuit elements formed on the main surface of the semiconductor substrate, a technique has been proposed to cover the entire surface of the semiconductor substrate by rewiring connected to the ground of the circuit elements, thereby forming a shield (e.g., Patent Document 1).

[0004] Existing technical documents Patent documents Patent document 1: Japanese Patent Application Publication No. 2001-156209. Summary of the Invention

[0005] The problem that the invention aims to solve When thick redistribution films are formed on the surface of a semiconductor substrate by electroplating, warping occurs in the semiconductor substrate. The greater the area ratio (pattern ratio) of the thick redistribution films on the surface of the semiconductor substrate, the greater the amount of warping occurs in the semiconductor substrate.

[0006] As with the aforementioned conventional techniques, when a shielding against electromagnetic noise from circuit elements is formed on the entire surface of a semiconductor substrate by a very thick redistribution layer, the redistribution pattern ratio is very high. Therefore, there is a problem that the warpage generated on the semiconductor substrate exceeds the allowable range in the wafer-level CSP manufacturing process, resulting in failures in the manufacturing process.

[0007] For example, in a semiconductor substrate whose warpage is outside the permissible range in the wafer-level CSP manufacturing process, poor adhesion of the vacuum chuck or electrostatic chuck that holds the semiconductor substrate in the stage of the manufacturing apparatus can cause a failure such as processing stoppage within the manufacturing apparatus.

[0008] Furthermore, during the photolithography process of forming resist patterns on the surface of a semiconductor substrate, defocusing (focus deviation) occurs, preventing the resist patterns from forming at the desired dimensions. Because the resist patterns cannot be formed at the desired dimensions, the dimensions of insulating or conductive components formed based on the resist patterns differ from the specified dimensions, resulting in malfunctions such as semiconductor devices not meeting desired characteristics.

[0009] The present invention was made in view of the above-mentioned problems, and its object is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the warpage of the semiconductor substrate and prevent the leakage of electromagnetic noise to the outside and the influence of electromagnetic noise from the outside.

[0010] Solution for solving the problem The semiconductor device of the present invention is characterized by comprising: a lower insulating layer formed on the main surface of a semiconductor substrate; an adhesive layer formed to ground with the upper surface of the lower insulating layer; and a conductive member having a first conductive member having a first film thickness stacked on the adhesive layer, and a second conductive member having a second film thickness thinner than the first film thickness stacked on the adhesive layer and grounded with the first conductive member.

[0011] The semiconductor device of the present invention is characterized by comprising: a lower insulating layer formed on the main surface of a semiconductor substrate; a wiring layer formed on the lower insulating layer having a first film thickness; and a shielding portion approaching the lower insulating layer at a predetermined distance from at least two sides of the wiring layer, and having a second film thickness thinner than the first film thickness.

[0012] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized by comprising: a step of preparing a semiconductor substrate on which electrodes are formed; a first step of forming a lower insulating layer having an opening on the main surface of the semiconductor substrate having a portion of the surface of the electrodes exposed; a second step of forming a UBM film composed of an adhesive layer and a seed layer on the surface of the lower insulating layer and on the surface of the electrodes exposed from the opening; a third step of forming a first conductive member having a first film thickness in the region corresponding to the opening of the lower insulating layer; a fourth step of forming a resist in the region corresponding to the shielding portion on the seed layer; and a fifth step of removing the UBM film by using the resist and the first conductive member as a mask to form a barrier metal portion.

[0013] Invention Effects The semiconductor device according to the present invention can suppress warping of the semiconductor substrate and prevent leakage of electromagnetic noise to the outside and the influence of electromagnetic noise from the outside. Therefore, it is possible to suppress the occurrence of faults caused by warping of the semiconductor substrate during the manufacturing process of the semiconductor device. Attached Figure Description

[0014] Figure 1 This is a top view showing the upper surface of the semiconductor device 100.

[0015] Figure 2A It means to indicate Figure 1 A cross-sectional view of the XX line in the diagram.

[0016] Figure 2B It means to indicate Figure 1 A cross-sectional view of the YY line in the diagram.

[0017] Figure 2C It means to indicate Figure 1 A cross-sectional view of the ZZ line in the diagram.

[0018] Figure 3 This is a flowchart showing the manufacturing sequence of the semiconductor device 100.

[0019] Figure 4 This is a flowchart showing the manufacturing sequence of the semiconductor device 100.

[0020] Figure 5A It is a cross-sectional view showing the cross-section of the ZZ line in the wafer preparation process.

[0021] Figure 5B It is a cross-sectional view showing the cross-section of the ZZ line in the process of forming the lower insulating film.

[0022] Figure 5C It is a cross-sectional diagram showing the ZZ line section in the thermosetting process.

[0023] Figure 5D This is a cross-sectional view showing the ZZ line in the UBM film formation process.

[0024] Figure 6A This is a cross-sectional view showing the ZZ lines in the photolithography process of the wiring department.

[0025] Figure 6B This is a cross-sectional diagram showing the ZZ line in the electroplating process of the wiring department.

[0026] Figure 6C This is a cross-sectional view showing the ZZ line section in the photolithography process of the shielding part.

[0027] Figure 6D This is a cross-sectional view showing the ZZ line in the UBM membrane removal process.

[0028] Figure 7A It is a cross-sectional view showing the ZZ line in the upper insulating film formation process.

[0029] Figure 7B It is a cross-sectional diagram showing the ZZ line section in the thermosetting process.

[0030] Figure 7C This is a cross-sectional view showing the ZZ line in the UBM film formation process.

[0031] Figure 7DIt is a cross-sectional view showing the ZZ line cross-section in the photolithography process of the barrier metal part.

[0032] Figure 8A It is a cross-sectional diagram showing the ZZ line in the electroplating process of the barrier metal part.

[0033] Figure 8B This is a cross-sectional view showing the ZZ line in the UBM membrane removal process.

[0034] Figure 8C This is a cross-sectional view showing the ZZ line section in the external connection terminal forming process.

[0035] Figure 9A This is a diagram showing the etching pattern when connecting the electrode sheet and the shield in a comparative example.

[0036] Figure 9B This is a diagram showing the etching pattern when connecting the electrode sheet and the shield in a comparative example.

[0037] Figure 9C This is a diagram showing the etching pattern when connecting the electrode sheet and the shield in a comparative example.

[0038] Figure 9D This is a diagram showing the etching pattern when connecting the electrode sheet and the shield in a comparative example.

[0039] Figure 10A This diagram shows the etching pattern when connecting the electrode sheet and the shield in this embodiment.

[0040] Figure 10B This diagram shows the etching pattern when connecting the electrode sheet and the shield in this embodiment.

[0041] Figure 10C This diagram shows the etching pattern when connecting the electrode sheet and the shield in this embodiment.

[0042] Figure 10D This diagram shows the etching pattern when connecting the electrode sheet and the shield in this embodiment. Detailed Implementation

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following descriptions of the embodiments and the accompanying drawings, substantially identical or equivalent parts are labeled with the same reference numerals.

[0044] Figure 1 This is a top view of a portion of the semiconductor device 100 of the present invention, viewed from above the component forming surface. Figure 2A It is along Figure 1 A cross-sectional view of line XX in the diagram. Furthermore... Figure 2B It is along Figure 1 A cross-sectional view of the YY line. Furthermore... Figure 2C It is along Figure 1 A cross-sectional view of the ZZ line in the diagram.

[0045] The semiconductor device 100 has sidewalls that are cut off by slicing, such as Figure 1 As shown, it has a rectangular shape in planar view (top view).

[0046] like Figure 2A , Figure 2B and Figure 2C As shown, an interlayer insulating film 11 is formed on a semiconductor substrate 10 made of a first conductivity type (e.g., p-type) such as Si (silicon). Lower layer wiring 12 is formed in the interlayer insulating film 11.

[0047] Electrode sheets 13 and passivation films 14, serving as protective layers, are formed on the interlayer insulating film 11. Electrode sheets 13 are connected to the underlying wiring 12 via connection portions L, and are electrically connected to circuit elements (not shown) formed on the semiconductor substrate 10. The circuit elements are connected to a fixed potential or transmit / receive signals via the electrode sheets 13. In the following description, the electrode sheet connected to the fixed potential is referred to as electrode sheet 13a, and the electrode sheet that transmits / receives signals is referred to as electrode sheet 13b. The passivation film 14 is formed by exposing a portion of the electrode sheet 13 and covering the outer periphery and sides of the electrode sheet 13, as well as the interlayer insulating film 11.

[0048] A lower insulating layer 15 is formed on the passivation film 14. The lower insulating layer 15 covers the surface of the passivation film 14 and has an opening OP that exposes the surface of the electrode sheet 13 exposed from the passivation film 14. Figure 1 (As shown in the figure). The opening OP has sloping sidewalls. The lower insulating layer 15 is composed of a photosensitive organic insulating film such as polyimide or PBO (polybenzoxazole).

[0049] A rewiring 16 is formed on the lower insulating layer 15, with one end connected to the electrode plate 13b via an opening OP in the lower insulating layer 15 and the other end connected to an external connection terminal. Furthermore, if the external connection terminal is formed directly on top of the electrode plate 13, the bottom surface of the rewiring 16 is connected to the electrode plate 13 via the opening OP in the lower insulating layer 15, and the upper surface of the rewiring 16 is connected to the external connection terminal. The rewiring 16 is composed of an adhesive layer 17 and a conductive layer 18.

[0050] The bonding layer 17 is composed of a film with high adhesion to the underlying insulating layer 15, such as Ti or TiW, which is formed by sputtering. The conductive layer 18 is formed on the bonding layer 17 and is composed of Cu, which is formed by electroplating. The bonding layer 17 has a film thickness of approximately 150 nm, and the conductive layer 18 has a film thickness of approximately 5 μm.

[0051] Furthermore, a shield 19 is formed on the lower insulating layer 15. For example... Figure 1 and Figure 2B As shown, the shield 19 is formed by approaching the rewiring 16 at a predetermined distance from at least two sides, or by surrounding the rewiring 16 at a predetermined distance, and extending over the entire surface of the underlying insulating layer 15. It is preferable that the distance between the shield 19 and the rewiring 16 is 5 μm or more, determined by the overlap with the lithography resolution, and 10 μm or less, which is sufficient to suppress electromagnetic noise leakage to the outside. This suppresses the leakage of electromagnetic noise generated by circuit elements to the outside and the influence of electromagnetic noise from the outside.

[0052] In addition, such as Figure 2A and Figure 2C As shown, the shield 19 is composed of a shielding portion 20 that is thinner than the redistribution portion 16 and a wiring portion 21 that has the same thickness as the redistribution portion 16.

[0053] Wiring section 21 is formed in the opening OP and surrounding area P1 of the lower insulating layer 15. Figure 2A (as shown in the diagram), the opening AP of the upper insulating layer 23 and its surrounding area P2 (in Figure 2A (As shown in the diagram). The wiring portion 21 formed in the opening OP and its surrounding region P1 of the lower insulating layer 15 is separated from and includes the outer periphery of the surface side of the lower insulating layer 15 of the opening OP by a predetermined distance in plan view. Taking into account the dimensional deviation of photolithography and the amount of mask overlap, it is preferable that the distance between the end of the wiring portion 21 formed in the peripheral region P1 and the outer periphery of the surface side of the lower insulating layer 15 of the opening OP is about 2 to 5 μm.

[0054] A portion of the shield 19 is connected to the electrode plate 13a, and another portion is connected to the external connection terminal 25. Thus, the shield 19 is connected to the ground terminal of the circuit element via the electrode plate 13a, and to a fixed potential via the external connection terminal 25 and the mounting substrate.

[0055] The shield 19 is composed of an adhesive layer 17 and a conductive member 22. The conductive member 22 is composed of a first conductive member 22a formed by electroplating a Cu film and a second conductive member 22b formed by sputtering a Cu film. The first conductive member 22a has a film thickness of about 5 μm and together with the adhesive layer 17 forms a wiring portion 21. The second conductive member 22b has a film thickness of about 200 to 500 nm and together with the adhesive layer 17 forms a shield 20.

[0056] The upper insulating layer 23 is formed by covering the surface of the lower insulating layer 15, the rewiring 16, and the shield 19. The upper insulating layer 23 has an opening AP in the region including the portion connecting the other end of the rewiring 16 and the external connection terminal 25 of the shield 19. Figure 1 (As shown). The upper insulating layer 23 is composed of a photosensitive organic insulating film such as polyimide, PBO (polybenzoxazole), or a phenolic organic insulating film. Furthermore, the wiring portion 21 formed in the opening AP and its surrounding area P2 of the upper insulating layer 23 is formed to include the wiring portion 21 exposed at the opening AP in plan view, and is formed in the area included by the external connection terminal 25. It is preferable that the distance between the end of the wiring portion 21 and the rewiring area exposed at the opening AP is approximately 2 μm, taking into account dimensional deviations in photolithography and mask overlap.

[0057] A barrier metal portion 24 is formed on the surface of the upper insulating layer 23, which connects to the rewiring 16 and the shield 19 via an opening AP in the upper insulating layer 23. For example... Figure 2A As shown, the barrier metal portion 24 is formed by depositing a Ni layer 24c formed by electroplating on a laminated film consisting of a Ti layer 24a and a Cu layer 24b formed by sputtering.

[0058] An external connection terminal 25 is formed on the barrier metal portion 24. The external connection terminal 25 is connected to wiring formed on the substrate on which the semiconductor device 100 is mounted. The external connection terminal 25 is made of SnAg.

[0059] In this embodiment of the semiconductor device 100, a shield 19, consisting of a thick wiring portion 21 formed by electroplating and a thin shield 20 formed by sputtering, is formed over the entire surface of the lower insulating layer 15. Most of the area outside the formation regions of the opening OP of the lower insulating layer 15 and the opening AP of the upper insulating layer 23 is formed by the thin shield 20, resulting in a low area ratio of the thick wiring portion 21 relative to the semiconductor substrate surface. Therefore, compared to the case where the entire surface is covered by a rewiring 16 and a shield of equal thickness, the amount of warpage generated in the semiconductor substrate is very small. Thus, it is possible to suppress the occurrence of manufacturing defects caused by semiconductor substrate warpage during the manufacturing process.

[0060] Next, along Figure 3 and Figure 4 The manufacturing process shown illustrates the method for manufacturing the semiconductor device 100. Furthermore, in the description of each process, reference is made to... Figure 5A ~D、 Figure 6A ~D、 Figure 7A ~D and Figure 8A ~C is explained along the line. Each figure is accompanied by... Figure 1 The cross-sectional view of the ZZ line (i.e., Figure 2C )correspond.

[0061] First, such as Figure 5AAs shown, a semiconductor wafer is prepared (wafer preparation process: step 101). The semiconductor wafer includes a semiconductor substrate 10, a semiconductor element (not shown) formed on the semiconductor substrate 10, an interlayer insulating film 11 covering the semiconductor substrate 10 and the semiconductor element, an electrode sheet 13 formed on the interlayer insulating film 11 and connected to the semiconductor element, and a passivation film (protective layer) 14 having an opening that exposes a portion of the electrode sheet 13.

[0062] Next, regarding Figure 5A The wafer shown undergoes a lower insulating film formation process (step 102). Specifically, a photosensitive lower insulating film 31, such as polyimide or PBO, is coated onto the passivation film 14 and the electrode sheet 13 using a spin coating method or similar method. Then, a conventional photolithography technique (exposure, development) is used to form an opening exposing the electrode sheet 13. Thus, as... Figure 5B As shown, a lower insulating film 31 with an opening OP1 is formed.

[0063] Furthermore, the photolithography techniques used in the lower insulating film formation process and in each photolithography process described below can be either positive or negative. For example, in the case of positive photolithography, light is irradiated outside the formation location of the opening OP1 to perform development, thereby forming the opening OP1.

[0064] Next, regarding Figure 5B The wafer shown undergoes a thermal curing process (step 103). Specifically, the lower insulating film 31 is thermally cured (cured) in a curing oven, thereby forming the lower insulating layer 15. At this time, the sidewall of the opening OP1 formed in the lower insulating film formation process in step 102 changes from a vertical to a conical shape due to the thermal shrinkage of the lower insulating film 31. Thus, a wafer with... Figure 5C The lower insulating layer 15 has openings OP2 on the outer periphery of the surface side and the inner periphery of the lower surface side, as shown.

[0065] Next, regarding Figure 5C The wafer shown undergoes a UBM film formation process (step 104). Specifically, a UBM (Under Barrier Metal) film 32 is formed covering the entire surface of the sidewall of the opening OP2 of the lower insulating layer 15 and the surface of the electrode sheet 13. The UBM film 32 is formed by sputtering a laminate of Ti as a bonding layer and Cu as a seed layer. Figure 5D As shown, a UBM film 32 is formed, consisting of a Ti layer 32a (sealing layer) and a Cu layer 32b (seed layer).

[0066] Next, regarding Figure 5DThe wafer shown undergoes a wiring section photolithography process (step 105). Specifically, a resist mask 33 is formed, which exposes openings in the UBM film 32 where the wiring section 21 is formed. The resist mask 33 is formed by spin-coating a resist onto the wafer followed by exposure and development. Thus, a wafer is formed as shown... Figure 6A The etch-resistant mask 33 shown is shown.

[0067] Next, regarding Figure 6A The wafer shown undergoes a wiring section electroplating process (step 106). Specifically, the surface of the wafer is immersed in an electroplating solution, and a voltage is applied to the UBM film, thereby depositing Cu at the locations corresponding to the openings of the resist mask 33. Afterwards, the resist is removed by ashing using an ashing device or by immersion in an organic stripping solution. This forms a... Figure 6B The first conductive member 22a and the conductive layer 18 are shown as conductive member 22.

[0068] Next, regarding Figure 6B The wafer shown undergoes a shielding photolithography process (step 107). Specifically, a resist mask 34 is formed covering the formation area of ​​the shielding portion 20. In the subsequent UBM film removal process, the resist mask 34 and the first conductive member 22a of the conductive member 22 are used as a mask for etching; therefore, it is necessary to cover the entire first conductive member 22a of the conductive member 22 with the resist mask 34. Thus, a shielding photolithography process is formed. Figure 6C The etch-resistant mask 34 shown is shown.

[0069] Next, regarding Figure 6C The wafer shown undergoes a UBM film removal process (step 108). Specifically, the Cu layer 32b and Ti layer 32a are removed sequentially using wet etching. During the etching of the Cu layer 32b, the Cu of the first conductive member 22a of the conductive member 22 and the resist mask 34 function as an etching mask. During the etching of the Ti layer 32a, the Cu of the first conductive member 22a of the conductive member 22 and the resist mask 34 function as an etching mask. After the removal of the UBM film 32, the resist mask 34 is removed by ashing using an ashing device or by immersion in an organic stripping solution. Thus, as Figure 6D As shown, a rewiring 16 and a shield 19 consisting of a shielding portion 20 and a wiring portion 21 are formed.

[0070] Next, regarding Figure 6DThe wafer shown undergoes an upper insulating film formation process (step 109). Specifically, a polyimide, PBO, or phenolic-based upper insulating film 35 is coated onto the lower insulating layer 15, the rewiring 16, the wiring portion 21, and the shielding portion 20 using a spin coating method or similar technique. Then, a conventional photolithography technique (exposure, development) is used to form an opening exposing a portion of the rewiring 16 and a portion of the wiring portion 21. This forms an opening with… Figure 7A The upper insulating film 35 of the opening AP1 as shown.

[0071] Next, regarding Figure 7A The wafer shown undergoes a thermal curing process (step 110). Specifically, the upper insulating film 35 is thermally cured (cured) in a curing oven, thereby forming the upper insulating layer 23. At this time, the sidewall of the opening AP1 formed in the upper insulating film formation step 109 changes from a vertical to a conical shape due to the thermal shrinkage of the upper insulating film 35. Thus, a wafer with... Figure 7B The upper insulating layer 23 of the opening AP2 as shown.

[0072] Next, regarding Figure 7B The wafer shown undergoes a UBM film formation process (step 111). Specifically, a UBM film 36 is formed covering the entire surface of the sidewall of the opening AP2 of the upper insulating layer 23 and the surfaces of the rewiring 16 and wiring portion 21 exposed from the opening AP2. The UBM film 36 is formed by sputtering a laminate of Ti as a bonding layer and Cu as a seed layer. Figure 7C As shown, a UBM film 36 is formed, consisting of a Ti layer 36a (sealing layer) and a Cu layer 36b (seed layer).

[0073] Next, regarding Figure 7C The wafer shown undergoes a barrier metal lithography process (step 112). Specifically, a resist mask 37 is formed, having openings exposed in the regions where the barrier metal portion 24 is formed. The resist mask 37 is formed using conventional photolithography techniques. Thus, a barrier metal portion 24 is formed. Figure 7D The etch-resistant mask 37 shown is an example of this.

[0074] Next, regarding Figure 7D The wafer shown undergoes a barrier metal plating process (step 113). Specifically, the surface of the wafer is immersed in an electroplating solution, and a voltage is applied to the UBM film 36, thereby depositing Ni at the location corresponding to the opening of the resist mask 37. Afterwards, the resist is removed using an ashing or organic stripping solution utilizing an ashing device. This forms a... Figure 8A The Ni layer 24c shown is as shown.

[0075] Next, regarding Figure 8AThe wafer shown undergoes a UBM film removal process (step 114). Specifically, the Cu layer 36b and Ti layer 36a are sequentially removed using wet etching with the Ni layer 24c as a mask. Then, after the removal of the UBM film 36, the resist is removed by ashing using an ashing device or by immersion in an organic stripping solution. Thus, as... Figure 8B As shown, the UBM film 36 on the upper insulating layer 23 is removed to form a barrier metal portion 24 composed of a Ti layer 24a, a Cu layer 24b and a Ni layer 24c.

[0076] Next, regarding Figure 8B The wafer shown undergoes an external interconnect terminal formation process (step 115). Specifically, firstly, solder terminals with Sn-Ag as the main component are disposed on the barrier metal portion 24 by solder printing (screen printing) or solder ball mounting. Then, external interconnect terminals 25 are formed on the barrier metal portion 24 by reflowing after the solder terminals are disposed. Thus, as Figure 8C As shown, a wafer with external connection terminals 25 is formed.

[0077] Next, regarding Figure 8C The wafer shown undergoes a semiconductor substrate grinding process (step 116). Specifically, after a protective tape is attached to the surface of the wafer, the back side of the wafer is ground by a grinding machine to achieve thin film formation.

[0078] Next, a wafer monolithization process (step 117) is performed on the thin-film-coated wafer. Specifically, after peeling off the protective tape on the wafer surface and attaching a dicing tape to the back of the wafer, the wafer is monolithized into individual chips using a dicing machine.

[0079] Semiconductor device 100 is manufactured through the processes described above.

[0080] In the semiconductor device 100 of this embodiment, a shield 19, consisting of a thick wiring portion 21 formed by electroplating and a thin shield 20 formed by sputtering, is formed over the entire surface of the lower insulating layer 15. Then, a wide area other than the portions connected to the electrode sheet 13 and the external connection terminal 25 (the areas where the openings OP and AP of the lower insulating layer 15 and the upper insulating layer 23 are formed) is covered by the thin shield 20, resulting in a low area ratio of the thick wiring portion 21 relative to the semiconductor substrate surface. Therefore, compared to the case where the entire surface is covered by a rewiring 16 and a shield of equal thickness, the amount of warpage generated in the semiconductor substrate is very small.

[0081] Therefore, the semiconductor device 100 according to this embodiment can reduce the warping of the semiconductor substrate, suppress the occurrence of faults caused by its manufacturing process, and suppress the leakage of electromagnetic waves to the outside of the semiconductor device 100 and the influence of electromagnetic waves from the outside.

[0082] Furthermore, in the manufacturing method of the semiconductor device 100 of this embodiment, the electrode sheet 13 exposed from the opening OP of the lower insulating layer 15 is connected to the shielding portion 20 via the wiring portion 21. This suppresses malfunctions that occur when the shielding portion 20 and the electrode sheet 13 are connected via a sputtered film. (Refer to...) Figure 9A ~D (comparative example) and Figure 10A ~D (this embodiment) will be used to explain the occurrence of such a fault and the mechanism for its suppression.

[0083] When connecting electrode sheets and shielding portions using sputtered films, the sputtered film is typically patterned using wet etching with a photoresist as a mask. For example, as a comparative example... Figure 9A As shown, the resist film 42 is used as a mask to pattern the laminated film consisting of a bonding layer 40 (Ti) and a conductive film 41 (Cu) formed by sputtering.

[0084] Because the adhesion between the resist film 42 and the conductive film 41 is very low, therefore... Figure 9B As shown, the etching of the conductive film 41 continues until it reaches the sidewall of the opening of the lower insulating layer 15. Because the density of the sputtered film formed on the sidewall of the inclined opening is very low, it has the characteristic of a high etching rate. Therefore, in cases where, for example, the gap between the opening and the shielding portion decreases due to shrinkage, when there is misalignment in the photolithography process, or when the lower insulating film shrinks due to thermal curing and the upper part of the opening of the lower insulating film 15 widens, the resist pattern is close to the outer periphery of the surface side of the lower insulating layer 15 at the opening of the lower insulating layer 15, because the etching rate of the conductive film 41 formed on the sidewall of the opening of the lower insulating layer 15 is very high, the etching continues until the middle of the sidewall of the opening of the lower insulating layer 15.

[0085] Next, during the etching of the bonding layer 40, the conductive film 41, up to the sidewall of the opening of the lower insulating layer 15, is used as a mask for etching the bonding layer 40. The etching of the bonding layer 40 begins from the sidewall of the opening of the lower insulating layer 15. As described above, the density of the sputtered film formed on the inclined sidewall of the opening of the lower insulating layer 15 is very low, and the etching rate is very high. Therefore, as... Figure 9C As shown, the etching process continues until the electrode sheet 13 is exposed at the bottom of the opening. Therefore, Ti etchant from the sealing layer 40 can easily remain in the gap created between the lower insulating layer 15 and the conductive film 41.

[0086] The residual etchant RE remaining between the conductive film 41 and the lower insulating layer 15 is affected by the formation of the upper insulating layer 23. Figure 9D As shown, residual etchant RE remains inside the semiconductor device. Therefore, the adhesive layer 40 between the electrode 13 and the conductive film 41 is gradually eroded by the residual etchant RE, resulting in poor conductivity between the electrode 13 and the conductive film 41 during long-term use.

[0087] In this regard, in the manufacturing method of the semiconductor device 100 of this embodiment, as follows: Figure 10A As shown, the first conductive member 22a of the conductive member 22 formed by electroplating functions as a mask for the conductive film 41. When the first conductive member 22a of the conductive member 22 is formed by electroplating with the conductive film 41 as a seed layer, the conductive film 41 formed on the sidewall of the opening of the lower insulating layer 15 is introduced into the first conductive member 22a of the conductive member 22. The density of the conductive film 41 introduced into the first conductive member 22a of the conductive member 22 is the same as the density of the electroplated film, and the etching rate is about 1 / 10 of that of the conductive film 41 formed by sputtering. Therefore, even when the end of the wiring portion 21 is close to the outer periphery of the surface side of the lower insulating layer 15 at the opening of the lower insulating layer 15, no side etching due to etching will occur in the first conductive member 22a of the conductive member 22. Figure 10B As shown, the etching of the conductive film 41 formed by sputtering stops at the surface of the lower insulating layer 15 and does not proceed to the sidewall of the opening.

[0088] like Figure 10C As shown, the etching of the sealing layer 40 begins with the first conductive member 22a of the conductive member 22 on the surface of the opening as a mask. Therefore, the etching of the sealing layer 40 does not proceed to the portion of the opening formed on the sidewalls where the etching rate is very high. Figure 10D As shown, no gaps will be generated between the lower insulating layer 15 and the first conductive member 22a of the conductive member 22. Therefore, no residue of etching solution will be generated, and no faults such as poor conductivity due to long-term use will occur.

[0089] Furthermore, in the semiconductor device 100 of this embodiment, the area exposed by the opening AP in the upper insulating layer 23 is the wiring portion 21. This suppresses opening defects that occur when the opening AP is formed in the upper insulating layer 23. The effect of suppressing these opening defects will be explained below.

[0090] Regarding the upper insulating layer, a photosensitive organic insulating film is generally used. For example, when a negatively photosensitive organic insulating film is used as the upper insulating layer and the area exposed from the opening of the upper insulating layer is a sputtered film, the thickness of the upper insulating film during exposure is thicker compared to when the exposed area is a wiring section; therefore, a longer exposure time is required. Then, if the exposure is insufficient, residual organic insulating film is formed on the bottom surface of the opening due to post-exposure development.

[0091] On the other hand, when a positive photosensitive organic insulating film is used as the upper insulating layer and the area exposed from the opening of the upper insulating layer is a sputtered film, the thickness of the upper insulating film removed by development is thicker than when the exposed area is a wiring section, thus requiring a longer development time. Then, if the development time is insufficient, residual organic insulating film is formed on the bottom surface of the opening.

[0092] The film residue from these organic insulating films hinders the electrical connection between the external connection terminals formed on the upper insulating layer and the shielding portion, causing malfunctions in the semiconductor device. Furthermore, to avoid film residue, long exposure and development times are required; therefore, excessive exposure or development time can lead to malfunctions such as enlarged openings or abnormal shapes.

[0093] In this embodiment of the semiconductor device 100, the area exposed by the opening AP of the upper insulating layer 23 is composed of wiring portions, thus eliminating the need for excessive exposure and development time. Therefore, malfunctions such as semiconductor device malfunctions due to residual organic insulating film, enlarged opening size, or abnormal shape will not occur.

[0094] Furthermore, the present invention is not limited to the embodiments described above. For example, in the above embodiments, the case where the barrier metal portion 24 is composed of a Ti / Cu / Ni laminated film was described as an example. However, it is not limited to this, for example, the barrier metal portion 24 can also be composed of a Ti / Ni, TiW / Cu / Ni, TiW / Ni, or other laminated films. That is, the barrier metal portion 24 can be composed of a dense layer composed of Ti and TiW and Ni.

[0095] Furthermore, in this embodiment, an example of a material composed of a photosensitive organic insulating film has been described; however, it is not limited to this, for example, a non-photosensitive organic insulating film may also be used to form the lower insulating layer 15 and the upper insulating layer 23. In this case, after the openings OP1 and AP1 are formed by etching, the openings OP2 and AP2 are formed by a thermal curing process.

[0096] Explanation of reference numerals in the attached figures 100 Semiconductor Devices 10 Semiconductor substrate 11-layer interlayer insulating film 12 Lower layer wiring 13 Electrode sheets 14 Passivation film 15 Lower insulation layer 16 Rewiring 17. Sealing layer 18. Conductive layer 19 Shielding 20 Shielding section 21. Cabling Department 22 Conductive components 22a First conductive component 22b Second conductive component 23 Upper insulation layer 24 Barrier Metal Part 24a Ti layer 24b Cu layer 24c Ni layer 25 External connection terminals 31 Lower insulating film 32 UBM membrane 32a Ti layer 32b Cu layer 33 Anti-corrosion mask 34 Anti-corrosion mask 35 Upper insulating film 36 UBM membrane 36a Ti layer 36b Cu layer 37. Anti-corrosion mask 40 sealing layers 41 Conductive components 42 Anti-corrosion film OP and AP openings.

Claims

1. A semiconductor device, characterized in that, have: The lower insulating layer is formed on the main surface of the semiconductor substrate; A sealing layer is formed by grounding the upper surface of the lower insulating layer; The conductive component includes a first conductive component having a first film thickness stacked on the adhesive layer, and a second conductive component having a second film thickness that is thinner than the first film thickness and is stacked on the adhesive layer in contact with the first conductive component. An upper insulating layer is formed on the conductive member and has a first opening that exposes a portion of the surface of the first conductive member. as well as An external connection terminal is formed on the surface of the upper insulating layer and is connected to the first conductive member via the first opening. The external connection terminal is connected to the first conductive member via a barrier metal portion. The conductive member includes one first conductive member and another first conductive member separate from the first conductive member. The second conductive member is connected to both the first conductive member and the other first conductive member. One of the first conductive components is connected to the external connection terminal. The other of the first conductive components is connected to the electrode via an opening in the lower insulating layer.

2. The semiconductor device according to claim 1, characterized in that, In a planar view, the area corresponding to the surface of the upper insulating layer of the external connection terminal includes the area corresponding to the surface of the upper insulating layer of the first conductive member.

3. The semiconductor device according to claim 1, characterized in that, The lower insulating layer has a second opening, which is formed such that the lower surface opposite to the upper surface is in contact with the surface of the electrode, exposing a portion of the surface of the electrode. The second opening is composed of an outer periphery on the upper surface side, an inner periphery on the lower surface side of the lower insulating layer, and a tapered sidewall connecting the outer periphery and the inner periphery. The sealing layer extends on the upper surface of the lower insulating layer, on the sidewall of the second opening, and on the surface of the electrode exposed at the second opening. The other first conductive member is connected to the electrode via the second opening, and the area corresponding to the upper surface of the lower insulating layer of the other first conductive member in plan view includes the outer periphery of the second opening.

4. The semiconductor device according to claim 1, characterized in that, It also includes a conductive layer having the sealing layer and the first film thickness, and a wiring layer formed on the upper surface of the lower insulating layer. The second conductive member and the sealing layer corresponding to the second conductive member extend on the upper surface of the lower insulating layer and approach each other at a predetermined distance from at least two sides of the wiring layer.

5. The semiconductor device according to claim 4, characterized in that, The second conductive member and the sealing layer corresponding to the second conductive member surround the wiring layer at a predetermined distance from it.

6. The semiconductor device according to claim 1, characterized in that, The conductive component is connected to a fixed potential via the external connection terminal.

7. The semiconductor device according to claim 1, characterized in that, The first conductive component is formed by electroplating, and the second conductive component is formed by sputtering.

8. The semiconductor device according to claim 4, characterized in that, The wiring layer has a first film thickness.

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