Semiconductor Devices

Abstract

A semiconductor device with improved reliability and a method for manufacturing the same are provided. The semiconductor device comprises: a substrate; a first spacer defining a gate trench on the substrate; and a gate electrode in the gate trench, wherein the height of an upper surface of the gate electrode adjacent to the first spacer increases in a direction away from the first spacer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0159980 filed on November 28, 2017 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As one of scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor obtained by forming a fin-shaped silicon body on a substrate and forming a gate on a surface of the silicon body has been proposed.

[0005] Since the multi-gate transistor uses a three-dimensional channel, scaling can be easy. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0006] Meanwhile, as semiconductor devices become highly integrated, the influence of leakage current generated in the semiconductor devices gradually increases, which results in a decrease in the reliability of the semiconductor devices. Summary of the invention

[0007] According to exemplary embodiments, aspects of the inventive concept provide a semiconductor device having improved reliability.

[0008] Aspects of the inventive concept also provide a method for manufacturing a semiconductor device having improved reliability according to exemplary embodiments.

[0009] However, aspects of the inventive concept are not limited to those set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below.

[0010] According to aspects of the present inventive concept, a semiconductor device is provided, comprising: a substrate; a first spacer defining a gate trench on the substrate; and a gate electrode in the gate trench; wherein a height of an upper surface of the gate electrode adjacent to the first spacer increases in a direction away from the first spacer.

[0011] According to various aspects of the present invention, a semiconductor device is provided, comprising: a substrate; a gate structure on the substrate; and a spacer on a sidewall of the gate structure, wherein the gate structure comprises a raised upper surface relative to an upper surface of the substrate, and the spacer comprises a recessed upper surface relative to an upper surface of the substrate.

[0012] According to various aspects of the present invention, there is provided a semiconductor device, comprising: a substrate; a gate structure on the substrate; and a spacer on a side wall of the gate structure, wherein an upper surface of the spacer contacts the side wall of the gate structure at a first point, and wherein a height of a lowermost portion of an upper surface of the spacer in a direction perpendicular to an upper surface of the substrate is lower than a height of the first point in a direction perpendicular to the upper surface of the substrate.

[0013] According to various aspects of the present invention, there is provided a semiconductor device, comprising: a substrate, comprising a first region and a second region; a first gate structure, on the first region of the substrate; a first spacer, on a sidewall of the first gate structure; a second gate structure, on the second region of the substrate; and a second spacer, on a sidewall of the second gate structure, wherein an upper surface of the first spacer contacts the sidewall of the first gate structure at a first point, wherein an upper surface of the second spacer contacts the sidewall of the second gate structure at a second point, wherein, at the first point, an upper surface of the first spacer and the sidewall of the first spacer form a first acute angle, and wherein, at the second point, an upper surface of the second spacer and the sidewall of the second spacer form a second acute angle greater than the first acute angle.

[0014] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a spacer defining a gate trench on a substrate; forming a gate structure filling the gate trench on the substrate; performing a first etching process having an etching rate greater than that of the spacer relative to the gate structure; and after performing the first etching process, performing a second etching process having an etching rate greater than that of the gate structure relative to the spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects and features of the inventive concept will become more apparent by describing in detail example embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0016] Figure 1 are layout diagrams illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0017] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0018] Figure 3 yes Figure 2 An enlarged view of portion R1.

[0019] Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0020] Figure 5 are cross-sectional views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0021] Figure 6 yes Figure 5 An enlarged view of portion R2.

[0022] Figure 7 are cross-sectional views illustrating effects of semiconductor devices according to some exemplary embodiments of the inventive concept.

[0023] Figure 8 yes Figure 7 An enlarged view of portion R3.

[0024] Fig. 9 are cross-sectional views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0025] Fig.10 are cross-sectional views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0026] Fig.11 are cross-sectional views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0027] Fig.12 are layout diagrams illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0028] Fig.13 It is along Fig.12 A cross-sectional view taken along line AA' and line CC'.

[0029] Fig.14A yes Fig.13 An enlarged view of portion R4.

[0030] Fig. 14B yes Fig.13 An enlarged view of portion R5.

[0031] Figures 15 to 30 are views illustrating intermediate steps of a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept.

[0032] Fig.31 and Fig.32are views illustrating intermediate steps of a method of fabricating a semiconductor device according to some exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0033] In the following, reference will be made to Figures 1 to 14B Semiconductor devices according to some exemplary embodiments of the inventive concept are described.

[0034] Figure 1 are layout diagrams illustrating semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 yes Figure 2 An enlarged view of portion R1. Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0035] Although the drawings relating to semiconductor devices according to some exemplary embodiments of the present invention show fin-type transistors (finFETs) including fin-shaped channel regions as examples, the present disclosure is not limited thereto. In addition, semiconductor devices according to some exemplary embodiments of the present invention may include tunnel FETs, bipolar junction transistors, lateral double diffused transistors (LDMOS), etc. The semiconductor device may be in the form of a semiconductor chip or die formed, for example, from a semiconductor wafer. The term "semiconductor device" used herein may also refer to a semiconductor package, including a package substrate, one or more semiconductor chips, and a sealant.

[0036] Reference Figures 1 to 4 According to some exemplary embodiments, a semiconductor device includes a substrate 100, a field insulating film 110, a first gate structure G1, a first spacer 132, a second spacer 134, a first source / drain region 140, a first capping pattern 170, a first interlayer insulating film 150, and a second interlayer insulating film 250.

[0037] The substrate 100 may be, for example, bulk silicon or silicon on insulator (SOI). The substrate 100 may be a silicon substrate, or it may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may have an epitaxial layer formed on a base substrate.

[0038] The substrate 100 may include a first fin pattern F1. The first fin pattern F1 may protrude from the top of the substrate 100 and be elongated. The first fin pattern F1 may be a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100.

[0039] The first fin pattern F1 may include, for example, silicon or germanium as an elemental semiconductor material. In addition, the first fin pattern F1 may include a compound semiconductor, for example, a group IV-V compound semiconductor or a group III-V compound semiconductor.

[0040] For example, in an exemplary embodiment where the first fin pattern F1 includes a group IV-V compound semiconductor, the first fin pattern F1 may include a binary or ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping a group IV element with a compound. For example, in an exemplary embodiment where the first fin pattern F1 includes a group III-V compound semiconductor, the first fin pattern F1 may include a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements. In semiconductor devices according to some exemplary embodiments, the first fin pattern F1 is described as a silicon fin pattern including silicon.

[0041] The first fin pattern F1 may be included in a channel region of a transistor including the first gate structure G1. In this specification, the channel region of a transistor including the first gate structure G1 is described as including the first fin pattern F1, but the present disclosure is not limited thereto. For example, the channel region of a transistor including the first gate structure G1 may include a nanowire pattern, a nanosheet pattern, etc.

[0042] The field insulating film 110 may cover a portion of a sidewall of the first fin pattern F1 on the substrate 100 .

[0043] The field insulating film 110 may include at least one of an oxide film, a nitride film, an oxynitride film, and a combination thereof, but the present disclosure is not limited thereto.

[0044] The first gate structure G1 may be formed on the substrate 100. For example, the first gate structure G1 may cross the first fin pattern F1 on the first fin pattern F1.

[0045] The first spacer 132 may be formed on the sidewall of the first gate structure G1. Thus, the first spacer 132 may intersect the first fin pattern F1 on the first fin pattern F1. In addition, the first spacer 132 may contact the first gate structure G1. When an element is referred to as "contacting" another element or "contacting" another element, there is no intermediate element.

[0046] The first spacer 132 may define a gate trench T1 on the substrate 100. For example, a gate trench T1 defined by the sidewall of the first spacer 132 and the upper surface of the first fin pattern F1 may be formed. Since the first spacer 132 may intersect the first fin pattern F1, the gate trench T1 may also intersect the first fin pattern F1. In this exemplary embodiment, the first gate structure G1 may fill the gate trench T1.

[0047] The second spacer 134 may be formed on the sidewall of the first spacer 132. Therefore, the second spacer 134 may cross the first fin pattern F1 on the first fin pattern F1. In some exemplary embodiments, the upper surface of the second spacer 134 may be formed to be higher than the upper surface of the first gate structure G1 in a direction away from the upper surface of the substrate 100.

[0048] Although each of the first spacer 132 and the second spacer 134 is illustrated as a single-layer film, the present disclosure is not limited thereto, and each of the first spacer 132 and the second spacer 134 may be formed of a multi-layer film.

[0049] The first spacer 132 and the second spacer 134 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxynitride (SiOCN), and combinations thereof. In some exemplary embodiments, the first spacer 132 may include silicon oxide, and the second spacer 134 may include silicon nitride.

[0050] The first gate structure G1 may include a first interface film 162 , a first gate insulating film 164 , and a first gate electrode 166 .

[0051] The first interface film 162 may be formed on the upper surface of the first fin pattern F1. For example, the first interface film 162 may extend along the contour of the bottom surface of the gate trench T1. However, the present disclosure is not limited thereto, and the first interface film 162 may extend along the contour of the bottom surface and the sidewall of the gate trench T1. In addition, in some exemplary embodiments, the first interface film 162 may be omitted.

[0052] The first interface film 162 may include, for example, silicon oxide (SiO 2 ). However, the first interface film 162 may include other material compositions depending on the type of the substrate 100, the type of the first fin pattern F1, or the type of the first gate insulating film 164.

[0053] The first gate insulating film 1164 may be interposed between the substrate 100 and the first gate electrode 166. For example, the first gate insulating film 164 may be formed on the first interface film 162. For example, the first gate insulating film 164 may extend along the contour of the bottom surface and the sidewall of the gate trench T1 on the first interface film 162. However, the present disclosure is not limited thereto, and the first gate insulating film 164 may extend along the contour of the bottom surface of the gate trench T1.

[0054] The first gate insulating film 164 may include, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), and silicon oxide (SiO 2 ). The high dielectric constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0055] The first gate structure 166 may be formed in the first trench T1. For example, after forming the first interface film 162 and the first gate insulating film 164, the first gate electrode 166 may fill the remaining area of ​​the gate trench T1. Therefore, the first gate insulating film 164 may extend along the bottom surface and sidewalls of the first gate electrode 166. For example, the first sidewall of the first spacer 132 contacts the first sidewall of the first gate insulating film 164, the second sidewall of the first spacer 132 opposite to the first sidewall of the first spacer 132 contacts the first sidewall of the second spacer 134, the bottom surface of the first gate electrode 166 contacts the upper portion of the bottom surface of the first gate insulating film 164 and the upper surface of the first interface film 162 contacts the lower portion of the bottom surface of the first gate insulating film 164, and the uppermost surface of the first fin pattern F1 contacts the lower surface of the first interface film 162. In some embodiments, the lowermost surface of the first interface film 162, the lowermost surface of the first spacer 132, the lowermost surface of the second spacer 134, and the uppermost surface of the first fin pattern F1 are arranged on the same plane (i.e., at the same height away from the upper surface of the substrate 100). In some embodiments, when the first interface film 162 is not provided between the first fin pattern F1 and the first gate electrode 166, the lowermost surface of the first gate insulating film 164, the lowermost surface of the first spacer 132, the lowermost surface of the second spacer 134, and the uppermost surface of the first fin pattern F1 are arranged on the same plane (i.e., at the same height away from the upper surface of the substrate 100).

[0056] The first gate electrode 166 may include a conductive material. In addition, the first gate electrode 166 may be formed by stacking a plurality of conductive materials. For example, the first gate electrode 166 may include a metal layer. For example, the first gate electrode 166 may include at least one of Ti, Ta, W, Al, Co, and a combination thereof. In addition, for example, the first gate electrode 166 may be made of silicon or silicon germanium instead of metal.

[0057] For example, the first gate electrode 166 may be formed through a replacement process, but the present disclosure is not limited thereto.

[0058] The upper surface of the first gate structure G1 adjacent to the first spacer 132 may be convex. The term "convex" used herein refers to a protrusion relative to the upper surface of the substrate 100. For example, Figure 3 As shown, the first gate structure G1 may include a first raised upper surface G1-US. The first raised upper surface G1-US of the first gate structure G1 may be adjacent to a sidewall of the first spacer 132. In some exemplary embodiments, the height of the first raised upper surface G1-US of the first gate structure G1 may increase in a direction away from the first spacer 132.

[0059] Since the first gate electrode 166 is a portion of the first gate structure G1 filling the gate trench T1, the upper surface of the first gate electrode 166 adjacent to the first spacer 132 may be convex. Therefore, the height of the upper surface of the first gate electrode 166 adjacent to the first spacer 132 may increase in a direction away from the first spacer 132.

[0060] The upper surface of the first gate electrode 166 and the sidewall of the first gate electrode 166 may form a first angle A1 at a point where the upper surface of the first gate electrode 166 meets the sidewall of the first gate electrode 166. In some exemplary embodiments, Figure 3 As shown, the first angle A1 may be an obtuse angle.

[0061] In some exemplary embodiments, the first convex upper surface G1-US of the first gate structure G1 may be formed on the upper surface of the first gate electrode 166 and the upper surface of the first gate insulating film 164. For example, when the first gate insulating film 164 extends along the sidewall of the first gate electrode 166, the upper surface of the first gate insulating film 164 may also be convex.

[0062] exist Figure 2 and Figure 3, the upper surface of the first gate electrode 166 and the upper surface of the first gate insulating film 164 are shown to be continuous, but the present disclosure is not limited thereto. For example, due to the difference in etching resistance between the first gate electrode 166 and the first gate insulating film 164, the upper surface of the first gate electrode 166 and the upper surface of the first gate insulating film 164 may be discontinuous.

[0063] The upper surface of the first spacer 132 may contact the sidewall of the first gate structure G1. Figure 3 As shown, at a first point P1 on a sidewall of the first gate structure G1 , an upper surface of the first spacer 132 and the first gate structure G1 may contact each other.

[0064] In some exemplary embodiments, the height of the lowest portion of the upper surface of the first spacer 132 may be lower than the height of the first point P1. For example, the upper surface of the first spacer 132 may be concave. The term "concave" used herein refers to a concave relative to the upper surface of the substrate 100. For example, Figure 3 As shown, the first spacer 132 may include a first recessed upper surface 132 -US.

[0065] At the first point P1, the sidewall of the first spacer 132 and the upper surface of the first spacer 132 may form a second angle A2. In some exemplary embodiments, the second angle A2 may be an acute angle.

[0066] Throughout this disclosure, any reference to “height” refers to the height in a direction perpendicular to the upper surface of the substrate 100 .

[0067] In some exemplary embodiments, the height of the first gate structure G1 may be higher than the height of the first spacer 132. For example, the height of the uppermost portion of the first gate structure G1 may be higher than the height of the lowermost portion of the first spacer 132. Figure 2 and Figure 3 As shown, the first height H1 of the first gate structure G1 may be higher than the second height H2 of the first spacer 132. In addition, the first height H1 of the first gate structure G1 may be higher than the height of the first point P1.

[0068] Therefore, an uppermost portion of the first convex upper surface G1 -US of the first gate structure G1 may be higher than a lowermost portion of the first recessed upper surface 132 -US of the first spacer 132 .

[0069] The first capping pattern 170 may be formed on the first gate structure G1 and the first spacer 132. For example, the first capping pattern 170 may cover an upper surface of the first gate structure G1 and an upper surface of the first spacer 132. The first capping pattern 170 may fill a space formed by the second spacer 134.

[0070] The upper surface of the first gate structure G1 adjacent to the first spacer 132 may be convex, and the upper surface of the first spacer 132 may be concave. Therefore, the bottom surface of the first capping pattern 170 may have a wavy shape. Figure 2 As shown, a bottom surface of the first capping pattern 170 adjacent to the sidewall of the second spacer 134 may have a wavy shape.

[0071] The first capping pattern 170 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbonitride (SiCN), silicon oxynitride (SiOCN) and at least one of a combination thereof.

[0072] The first source / drain region 140 may be formed on the sidewall of the first gate structure G1 on the substrate 100. Figure 2 As shown, the first source / drain region 140 may be formed on the sidewall of the second spacer 134 on the substrate 100 .

[0073] The first source / drain region 140 may include an epitaxial layer formed on the first fin pattern F1. In addition, the first source / drain region 140 may be an elevated source region and drain region including an upper surface protruding above the upper surface of the substrate 100. For example, the uppermost surface of the first source / drain region 140 may be arranged at a position higher than the lowermost surface of the first interface film 162, the lowermost surface of the first spacer 132, the lowermost surface of the second spacer 134, and the uppermost surface of the first fin pattern F1, but lower than a recessed portion of the upper surface of the first spacer 132 in a direction perpendicular to the upper surface of the substrate 100. However, the present disclosure is not limited thereto, and the first source / drain region 140 may be an impurity region formed in the substrate 100.

[0074] The first interlayer insulating film 150 may be formed on the substrate 100 . In addition, the first interlayer insulating film 150 may cover the sidewalls of the second spacers 134 .

[0075] exist Figure 2 , it has been illustrated that the upper surface of the first capping pattern 170, the upper surface of the second spacer 134, and the upper surface of the first interlayer insulating film 150 are arranged on the same plane. However, the present disclosure is not limited thereto.

[0076] The second interlayer insulating film 250 may be formed on the first interlayer insulating film 150. For example, the second interlayer insulating film 250 may cover an upper surface of the first capping pattern 170, an upper surface of the second spacer 134, and an upper surface of the first interlayer insulating film 150.

[0077] The first interlayer insulating film 150 and the second interlayer insulating film 250 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and at least one of a low dielectric constant material. However, in some exemplary embodiments, the first interlayer insulating film 150 may include a material composition different from that of the first spacer 132.

[0078] Figure 5 are cross-sectional views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 6 yes Figure 5 In order to simplify the description, the following will be briefly described or omitted. Figures 1 to 4 A similar description is repeated.

[0079] refer to Figure 5 and Figure 6 , the semiconductor device according to some exemplary embodiments further includes a contact 180 .

[0080] The contact 180 may contact the first source / drain region 140 on the first source / drain region 140. In addition, the contact 180 may contact the first capping pattern 170 and the second spacer 134. However, in some exemplary embodiments, the contact 180 may not contact the first spacer 132.

[0081] The contact 180 may be formed by, for example, a self-aligned contact (SAC) process. Therefore, the sidewall of the contact 180 may be defined by the sidewall of the first capping pattern 170 or the sidewall of the second spacer 134. Fig.30 This is described in detail.

[0082] In some exemplary embodiments, the first spacer 132 may include a low-k material. Therefore, the first spacer 132 may reduce parasitic capacitance between the first gate electrode 166 and the contact 180 .

[0083] In the following, reference will be made to Figures 5 to 8 Effects of semiconductor devices according to some exemplary embodiments of the inventive concept are described.

[0084] Figure 7 are cross-sectional views illustrating effects of semiconductor devices according to some exemplary embodiments of the inventive concept. Figure 8 yes Figure 7 In order to simplify the description, the following will be briefly described or omitted. Figures 1 to 4 A similar description is repeated.

[0085] Reference Figure 7 and Figure 8, the upper surface of the first gate structure G1 adjacent to the first spacer 132 may include a tip. For example, the upper surface of the first gate structure G1 may be recessed. For example, the upper surface of the first gate electrode 166 adjacent to the first spacer 132 may include a tip.

[0086] A gate electrode including a sharp tip is prone to leakage current. Figure 7 The distance from the first gate electrode 166 to the contact 180 is narrowed, which is prone to leakage current. In addition, Figure 7 The tip of the first gate electrode 166 may form a strong magnetic field with the contact 180 due to the sharp shape. This results in reduced reliability of the semiconductor device.

[0087] However, in the semiconductor device according to some exemplary embodiments, since the upper surface of the gate electrode adjacent to the spacer is convex, the reliability of the semiconductor device may be improved.

[0088] For example, due to Figure 6 The first gate electrode 166 includes a first raised upper surface G1-US, so Figure 6 The first distance D1 between the first gate electrode 166 and the contact 180 may be greater than Figure 8 The second distance D2 between the first gate electrode 166 and the contact 180 in FIG. For example, the semiconductor device according to some exemplary embodiments may ensure a sufficient distance between the gate electrode and the contact, thereby reducing leakage current.

[0089] In addition, due to Figure 6 The first gate electrode 166 does not include a tip of a sharp shape, and thus a strong magnetic field may be prevented from being formed at the tip of the gate electrode.

[0090] Refer again Figure 7 and Figure 8 , the upper surface of the first spacer 132 may be higher than the upper surface of the first gate structure G1. In this exemplary embodiment, leakage current tends to be generated between the first gate electrode 166 and the contact 180.

[0091] For example, the first spacer 132 includes silicon oxide (SiO 2 ) and the second spacer 134 includes silicon nitride (SiN), the first spacer 132 may have a lower etching resistance than the second spacer 134. Therefore, for example, in forming the contact hole CH to be described later (see Fig.30 ), the first spacer 132 is more likely to be etched than the second spacer 134. This may cause the distance between the first gate electrode 166 and the contact 180 to be narrowed.

[0092] However, the upper surface of the first spacer 132 of the semiconductor device according to some exemplary embodiments may be lower than the upper surface of the first gate structure G1. Figure 5 and Figure 6 The upper surface of the first spacer 132 in the first gate structure G1 may be lower than the upper surface of the first gate structure G1. Fig.30 ), the first spacer 132 may not be etched.

[0093] Fig. 9 1 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present invention. Figures 1 to 4 A similar description is repeated.

[0094] Reference Fig. 9 , the first gate electrode 166 of the semiconductor device according to some exemplary embodiments may be formed of a multi-layer film.

[0095] For example, the first gate electrode 166 may include a first conductive film 167 and a second conductive film 168 .

[0096] The first conductive film 167 of the first gate electrode 166 may extend along the bottom surface and the sidewall of the gate trench T1 . For example, the first conductive film 167 may extend along the contour of the first gate insulating film 164 .

[0097] The first conductive film 167 may adjust a work function. The second conductive film 168 of the first gate electrode 166 may fill a space formed by the first conductive film 167 .

[0098] The first conductive film 167 may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof The second conductive film 168 may include, for example, W or Al.

[0099] Fig.10 1 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present invention. Figures 1 to 4 A similar description is repeated.

[0100] Reference Fig.10 In the semiconductor device according to some exemplary embodiments, the upper surface of the second spacer 134 may be recessed. In addition, the height of the second spacer 134 may be lower than the height of the first gate structure G1.

[0101] exist Fig.10, the upper surface of the first spacer 132 and the upper surface of the second spacer 134 are shown to be continuous, but the present disclosure is not limited thereto. For example, due to the difference in etching resistance between the first spacer 132 and the second spacer 134, the upper surface of the first spacer 132 and the upper surface of the second spacer 134 may be discontinuous. In addition, the upper surface of the second spacer 134 may be in contact with the side wall of the first interlayer insulating film 150.

[0102] In this exemplary embodiment, the first capping pattern 170 may cover not only upper surfaces of the first gate structure G1 and the first spacer 132 but also upper surfaces of the second spacer 134. Therefore, the first capping pattern 170 may fill a space formed by the first interlayer insulating film 150.

[0103] Fig.11 1 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present invention. Figures 1 to 4 A similar description is repeated.

[0104] Reference Fig.11 , the semiconductor device according to some exemplary embodiments does not include the first capping pattern 170 .

[0105] Therefore, the second interlayer insulating film 250 may cover the upper surface of the first gate structure G1 and the upper surface of the first spacer 132 .

[0106] The upper surface of the first gate structure G1 adjacent to the first spacer 132 may be convex, and the upper surface of the first spacer 132 may be concave. Therefore, the bottom surface of the second interlayer insulating film 250 may have a wavy shape. For example, as shown in the figure, the bottom surface of the second interlayer insulating film 250 adjacent to the sidewall of the second spacer 134 may have a wavy shape.

[0107] Fig.12 are layout diagrams illustrating semiconductor devices according to some exemplary embodiments of the inventive concept. Fig.13 It is along Fig.12 A cross-sectional view taken along line AA' and line CC'. Fig.14A yes Fig.13 An enlarged view of portion R4. Fig. 14B yes Fig.13 In order to simplify the description, the following will be briefly described or omitted. Figures 1 to 4 A similar description is repeated.

[0108] Reference Figures 12 to 14B , in the semiconductor device according to some exemplary embodiments, the substrate 100 includes a first region I and a second region II.

[0109] The first region I and the second region II may be separated from each other, or may be connected to each other. It will be understood that when referring to an element being "connected" or "coupled" to another element or being "on" another element, the element may be directly connected or coupled to the other element or directly on the other element, or there may be intervening elements.

[0110] In the semiconductor device according to some exemplary embodiments, transistors of different conductivity types may be formed in the first region I and the second region II. For example, the first region I may be a region where an NMOS transistor is formed, and the second region II may be a region where a PMOS transistor is formed. Conversely, the first region I may be a region where a PMOS transistor is formed, and the second region II may be a region where an NMOS transistor is formed.

[0111] Since the first region I of the substrate 100 is Figures 1 to 4 The areas described are basically the same, so a detailed description will be omitted below.

[0112] In the second region II of the substrate 100 , a second gate structure G2 , a third spacer 232 , a fourth spacer 234 , a second source / drain region 240 , a second capping pattern 270 , a third interlayer insulating film 350 , and a fourth interlayer insulating film 450 may be formed.

[0113] In the second region II, the substrate 100 may include a second fin pattern F2. The second fin pattern F2 may protrude and be elongated from the top of the substrate 100. The first fin pattern F1 and the second fin pattern F2 may extend in the same direction or in different directions.

[0114] The second gate structure G2 may be formed on the substrate 100. For example, the second gate structure G2 may cross the second fin pattern F2 on the second fin pattern F2.

[0115] The third spacer 232 may be formed on a sidewall of the second gate structure G2. In addition, the third spacer 232 may contact the second gate structure G2.

[0116] The fourth spacer 234 may be formed on the sidewalls of the third spacer 232 .

[0117] The second gate structure G2 may include a second interface film 262 , a second gate insulating film 264 , and a second gate electrode 266 .

[0118] The upper surface of the second gate structure G2 adjacent to the third spacer 232 may be convex. Fig. 14BAs shown, the second gate structure G2 may include a second raised upper surface G2-US. The second raised upper surface G2-US of the second gate structure G2 may be adjacent to the sidewall of the third spacer 232. In some exemplary embodiments, the height of the second raised upper surface G2-US of the second gate structure G2 may increase in a direction away from the third spacer 232 and then decrease.

[0119] The upper surface of the second gate electrode 266 and the sidewall of the second gate electrode 266 may form a third angle A3 at a point where the upper surface of the second gate electrode 266 meets the sidewall of the second gate electrode 266. In some exemplary embodiments, as shown in FIG. Fig. 14B As shown, the third angle A3 may be an acute angle. However, the present disclosure is not limited thereto, and the third angle A3 may be an obtuse angle.

[0120] However, in some exemplary embodiments, the third angle A3 may be smaller than the first angle A1. For example, the curvature radius of the second convex upper surface G2-US may be smaller than the curvature radius of the first convex upper surface G1-US.

[0121] In some exemplary embodiments, the second raised upper surface G2 -US of the second gate structure G2 may be formed over an upper surface of the second gate electrode 266 and an upper surface of the second gate insulating film 264 .

[0122] exist Fig.13 and Fig. 14B , an upper surface of the first gate electrode 166 and an upper surface of the first gate insulating film 164 are shown to be continuous, but the present disclosure is not limited thereto.

[0123] The upper surface of the third spacer 232 may contact the sidewall of the second gate structure G2. Fig. 14B As shown, at a second point P2 on the sidewall of the second gate structure G2, an upper surface of the third spacer 232 and the second gate structure G2 may contact each other.

[0124] In some exemplary embodiments, the height of the lowest portion of the upper surface of the third spacer 232 may be less than the height of the second point P2. For example, the upper surface of the third spacer 232 may be concave. Fig. 14B As shown, the third spacer 232 may include a second recessed upper surface 232 -US.

[0125] At the second point P2, the sidewall of the third spacer 232 and the upper surface of the third spacer 232 may form a fourth angle A4. In some exemplary embodiments, the fourth angle A4 may be an acute angle.

[0126] However, in some exemplary embodiments, the fourth angle A4 may be greater than the second angle A2. For example, the radius of curvature of the second concave upper surface 232-US may be greater than the radius of curvature of the first concave upper surface 132-US.

[0127] In some exemplary embodiments, the height of the second gate structure G2 may be higher than the height of the third spacer 232. For example, the height of the uppermost portion of the first gate structure G1 may be higher than the height of the lowermost portion of the first spacer 132. Fig.13 and Fig. 14B As shown, the third height H3 of the second gate structure G2 may be higher than the fourth height H4 of the third spacer 232. Also, the third height H3 of the second gate structure G2 may be higher than the height of the second point P2.

[0128] Therefore, an uppermost portion of the second convex upper surface G2 -US of the second gate structure G2 may be higher than a lowermost portion of the second recessed upper surface 232 -US of the third spacer 232 .

[0129] However, in some exemplary embodiments, the third height H3 of the second gate structure G2 may be higher than the first height H1 of the first gate structure G1. In addition, in some exemplary embodiments, the fourth height of the third spacer 232 may be higher than the second height H2 of the first spacer 132.

[0130] The second capping pattern 270 may be formed on the second gate structure G2 and the third spacer 232 .

[0131] Since the upper surface of the second gate structure G2 adjacent to the third spacer 232 may be convex, and the upper surface of the third spacer 232 may be concave, the bottom surface of the second capping pattern 270 may have a wavy shape. Fig.13 As shown, a bottom surface of the second capping pattern 270 adjacent to the sidewall of the third spacer 232 may have a wavy shape.

[0132] The second source / drain region 240 may be formed on a sidewall of the second gate structure G2 on the substrate 100 .

[0133] A third interlayer insulating film 350 may be formed on the substrate 100 . In addition, the third interlayer insulating film 350 may cover sidewalls of the fourth spacer 234 .

[0134] The fourth interlayer insulating film 450 may be formed on the third interlayer insulating film 350. For example, the fourth interlayer insulating film 450 may cover an upper surface of the second capping pattern 270, an upper surface of the third spacer 232, and an upper surface of the third interlayer insulating film 350.

[0135] In the following, reference will be made to Figure 5 and Figures 15 to 32 Methods of fabricating semiconductor devices according to some exemplary embodiments of the inventive concept are described.

[0136] Figures 15 to 30 1 is a diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Figures 1 to 14B A similar description is repeated.

[0137] refer to Fig.15 , a dummy gate structure DG is formed on the substrate 100 .

[0138] First, a first fin pattern F1 may be formed on a substrate 100 . The first fin pattern F1 may be a portion of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 .

[0139] Then, an insulating film and a conductive film are sequentially formed on the substrate 100 and the first fin pattern F1, and the insulating film and the conductive film may be patterned to form a dummy gate insulating film 122 and a dummy gate electrode 124 intersecting the first fin pattern F1. Thus, a dummy gate structure DG including the dummy gate insulating film 122 and the dummy gate electrode 124 may be formed.

[0140] Reference Fig.16 , a first spacer 132 and a second spacer 134 are formed on the sidewalls of the dummy gate structure DG.

[0141] The first spacer 132 may be formed on both sidewalls of the dummy gate structure DG. The second spacer 134 may be formed on the sidewalls of the first spacer 132 .

[0142] Although each of the first spacer 132 and the second spacer 134 is illustrated as a single-layer film, the present disclosure is not limited thereto, and each of the first spacer 132 and the second spacer 134 may be formed of a multi-layer film.

[0143] The first spacer 132 and the second spacer 134 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxynitride (SiOCN), and combinations thereof. In some exemplary embodiments, the first spacer 132 may include silicon oxide, and the second spacer 134 may include silicon nitride.

[0144] Reference Fig.17 , a first source / drain region 140 is formed on the substrate 100 .

[0145] The first source / drain region 140 may be formed on a sidewall of the first gate structure G1 on the substrate 100 .

[0146] For example, the first source / drain region 140 may include an epitaxial layer formed on the first fin pattern F1 . In addition, the first source / drain region 140 may be an elevated source and drain region including an upper surface protruding above an upper surface of the substrate 100 .

[0147] For example, a portion of the first fin pattern F1 may be etched by using an etching process using the first gate structure G1, the first spacer 132, and the second spacer 134 as an etching mask. Then, the first source / drain region 140 may be formed in the etched first fin pattern F1 by using epitaxial growth.

[0148] Reference Fig.18 , a first interlayer insulating film 150 is formed on the substrate 100.

[0149] The first interlayer insulating film 150 may be formed to surround the sidewalls of the second spacer 134. For example, Fig.17 A first interlayer insulating film 150 is formed on the resultant structure, and a planarization process may be performed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process.

[0150] Therefore, an upper surface of the dummy gate structure DG, an upper surface of the second spacer 134 , and an upper surface of the first interlayer insulating film 150 may be arranged on the same plane, but the present disclosure is not limited thereto.

[0151] refer to Fig.19 , remove the dummy gate structure DG.

[0152] Therefore, the gate trench T1 may be formed in the region where the dummy gate structure DG is removed. For example, the gate trench T1 defined by the sidewall of the first spacer 132 and the upper surface of the first fin pattern F1 may be formed.

[0153] Reference Fig. 20 , a first interface film 162 , a first gate insulating film 164 , and a first gate electrode 166 are sequentially formed in the gate trench T1 .

[0154] First, the first interface film 162 may be formed to extend along the bottom surface of the gate trench T1. Then, the first gate insulating film 164 may be formed to extend along the upper surface of the first interlayer insulating film 150, the upper surface of the second spacer 134, the upper surface of the first spacer 132, the sidewall of the first spacer 132, and the contour of the upper surface of the first interface film 162.

[0155] The first gate electrode 166 may be formed on the first gate insulating film 164. The first gate electrode 166 may fill a space formed by the first gate insulating film 164.

[0156] Reference Fig.21 and Fig. 22 , a first etching process having a greater etching rate relative to the first gate structure G1 than the first spacer 132 is performed.

[0157] The first etching process may be performed until an upper surface of the first gate structure G1 becomes lower than an upper surface of the first spacer 132. Therefore, as shown in the figure, a fifth height H11 of the first gate structure G1 may be lower than a height of the first spacer 132.

[0158] However, in some exemplary embodiments, when the first etching process is performed, the second spacer 134 and the first interlayer insulating film 150 may not be etched.

[0159] The first etching process may include, for example, a reactive ion etching (RIE) process or a wet etching process, but the present disclosure is not limited thereto.

[0160] However, due to the nature of the etching process, the upper surface of the first gate structure G1 adjacent to the first spacer 132 may include a tip. Fig. 22 As shown, after performing the first etching process, the upper surface of the first gate structure G1 may be recessed.

[0161] For example, an upper surface of the first gate electrode 166 adjacent to the first spacer 132 may include a tip. For example, an upper surface of the first gate electrode 166 and a sidewall of the first gate electrode 166 may form a fifth angle A11, which is an acute angle at a point where the upper surface of the first gate electrode 166 meets the sidewall of the first gate electrode 166.

[0162] Reference Fig.23 and Fig.24 After performing the first etching process, a second etching process having a greater etching rate with respect to the first spacer 132 than the first gate structure G1 is performed.

[0163] The second etching process may be performed until the upper surface of the first spacer 132 contacts the sidewall of the first gate structure G1. Therefore, as shown in the figure, the upper surface of the first spacer 132 may contact the first gate structure G1 at a third point P11 on the sidewall of the first gate structure G1.

[0164] The second etching process may include, for example, a reactive ion etching (RIE) process or a wet etching process, but the present disclosure is not limited thereto.

[0165] In some exemplary embodiments, the second etching process may be performed until an upper surface of the first spacer 132 becomes lower than an upper surface of the first gate structure G1 , but the present disclosure is not limited thereto.

[0166] Through the second etching process, the tip of the first gate electrode 166 may be gentle. For example, at the point where the upper surface of the first gate electrode 166 meets the sidewall of the first gate electrode 166, the upper surface of the first gate electrode 166 and the sidewall of the first gate electrode 166 may form a greater than Fig. 22 The fifth angle A11 is the sixth angle A12.

[0167] exist Fig.24 , although the sixth angle A12 is shown as an acute angle, the present disclosure is not limited thereto. For example, depending on the etching rate of the second etching process, the sixth angle A12 may be a right angle or an obtuse angle.

[0168] In addition, due to the nature of the etching process, the upper surface of the first spacer 132 may be recessed. Therefore, the height of the lowermost portion of the upper surface of the first spacer 132 may be lower than the height of the third point P11. Fig.24 As shown, the sixth height H21 of the first spacer 132 may be lower than the height of the third point P11. In addition, for example, at the third point P11, the sidewall of the first spacer 132 and the upper surface of the first spacer 132 may be formed at a seventh angle A21, which is an acute angle.

[0169] Reference Fig.25 and Fig.26 After performing the second etching process, a third etching process having a greater etching rate than the first spacer 132 with respect to the first gate structure G1 is performed.

[0170] The third etching process may be similar to the first etching process. Therefore, the seventh height H12 of the first gate structure G1 may be lower than Fig. 22 In addition, as shown in the figure, the seventh height H12 of the first gate structure G1 may be lower than the height of the first spacer 132 .

[0171] Due to the nature of the etching process, the upper surface of the first gate structure G1 adjacent to the first spacer 132 may include a tip. Fig.26 As shown, after performing the third etching process, the upper surface of the first gate structure G1 may be recessed.

[0172] However, the tip of the first gate electrode 166 may be gentle. For example, at the point where the upper surface of the first gate electrode 166 meets the sidewall of the first gate electrode 166, the upper surface of the first gate electrode 166 and the sidewall of the first gate electrode 166 may form a greater than Fig. 22 The eighth angle A13 of the fifth angle A11.

[0173] However, in some exemplary embodiments, the third etching process may be omitted.

[0174] Reference Fig. 27 and Fig.28 After the third etching process is performed, a fourth etching process having a greater etching rate with respect to the first spacer 132 than the first gate structure G1 is performed.

[0175] The fourth etching process may be similar to the second etching process. Therefore, the eighth height H22 of the first spacer 132 may be lower than Fig.24 The sixth height H21 of the first spacer 132 is denoted as H21. In addition, as shown in the figure, at a fourth point P12 on the sidewall of the first gate structure G1, the upper surface of the first spacer 132 and the first gate structure G1 may contact each other.

[0176] In some exemplary embodiments, the fourth etching process may be performed until an upper surface of the first spacer 132 becomes lower than an upper surface of the first gate structure G1 , but the present disclosure is not limited thereto.

[0177] Through the fourth etching process, the tip of the first gate electrode 166 can be more gentle. For example, at the point where the upper surface of the first gate electrode 166 meets the sidewall of the first gate electrode 166, the upper surface of the first gate electrode 166 and the sidewall of the first gate electrode 166 can form a greater than Fig.24 The ninth angle A14 may be an obtuse angle.

[0178] In addition, due to the nature of the etching process, the upper surface of the first spacer 132 may be recessed. Therefore, the height of the lowermost portion of the upper surface of the first spacer 132 may be lower than the height of the fourth point P12. Fig.28 As shown in FIG. 1 , the eighth height H22 of the first spacer 132 may be lower than the height of the fourth point P12. In addition, for example, at the fourth point P12, the sidewall of the first spacer 132 and the upper surface of the first spacer 132 may form a tenth angle A22, and the tenth angle A22 is an acute angle. In some exemplary embodiments, the tenth angle A22 may be less than Fig.24 The seventh angle A21.

[0179] However, in some exemplary embodiments, the fourth etching process may be omitted.

[0180] Reference Fig.29 , a first capping pattern 170 is formed on the first gate structure G1 and the first spacer 132 .

[0181] The first capping pattern 170 may fill the space formed by the second spacer 134. Fig. 27 and Fig.28 A first capping pattern 170 is formed on the resulting structure, and a planarization process may be performed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process. Thus, the first capping pattern 170 may be formed to cover the upper surface of the first gate structure G1 and the upper surface of the first spacer 132.

[0182] Then, a second interlayer insulating film 250 is formed on the first interlayer insulating film 150 .

[0183] For example, the second interlayer insulating film 250 may be formed to cover an upper surface of the first capping pattern 170 , an upper surface of the second spacer 134 , and an upper surface of the first interlayer insulating film 150 .

[0184] Reference Fig.30 , a contact hole CH is formed to expose a portion of the first source / drain region 140 .

[0185] For example, a portion of the first interlayer insulating film 150 and a portion of the second interlayer insulating film 250 may be etched to form a contact hole CH exposing a portion of the first source / drain region 140 .

[0186] In the process of forming the contact hole CH, as shown in the figure, a portion of the first capping pattern 170 and a portion of the second spacer 134 may be etched. A portion of the first capping pattern 170 and a portion of the second spacer 134 may be etched by, for example, misalignment of the etching process for forming the contact hole CH. However, in some exemplary embodiments, the first spacer 132 may be protected from being etched.

[0187] Therefore, in some exemplary embodiments, a contact hole CH defined by the sidewalls of the second interlayer insulating film 250 , the first capping pattern 170 , and the second spacer 134 may be formed.

[0188] Then, refer to Figure 5 , the contact 180 is formed in the contact hole CH.

[0189] Therefore, a contact 180 contacting the first source / drain region 140 may be formed on the first source / drain region 140 .

[0190] However, in some exemplary embodiments, the contact 180 may not be in contact with the first spacer 132 .

[0191] Fig.31 and Fig.321 is a diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some exemplary embodiments of the present invention. Figures 1 to 30 A similar description is repeated.

[0192] For reference, Fig.31 and Fig.32 It is shown Fig. 20 A view of step after step.

[0193] refer to Fig.31 , can be Fig. 20 For example, the planarization process may be performed until the upper surface of the first interlayer insulating film 150 is exposed.

[0194] The planarization process may include, for example, a chemical mechanical polishing (CMP) process.

[0195] Therefore, an upper surface of the first gate structure G1 , an upper surface of the second spacer 134 , an upper surface of the first spacer 132 , and an upper surface of the first interlayer insulating film 150 may be disposed on the same plane. However, the present disclosure is not limited thereto.

[0196] Reference Fig.32 , a fifth etching process having a greater etching rate with respect to the first spacer 132 than the first gate structure G1 is performed.

[0197] The fifth etching process may be similar to the second etching process.

[0198] Through the fifth etching process, the tip of the first gate electrode 166 may be gentle. In addition, the upper surface of the first spacer 132 may be lower than the upper surface of the first gate structure G1.

[0199] Furthermore, due to the nature of the etching process, the upper surface of the first spacer 132 may be recessed.

[0200] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, it is desired that the present embodiment be considered in all respects as illustrative rather than restrictive, and reference is made to the appended claims rather than the foregoing description to indicate the scope of the invention.

Claims

1. A semiconductor device, comprising: substrate; a first spacer defining a gate trench on the substrate, wherein an upper surface of the first spacer is recessed; a gate structure, wherein in the gate trench, the upper surface of the first spacer contacts a sidewall of the gate structure at a first point; a second spacer, on a sidewall of the first spacer, wherein the upper surface of the first spacer and the upper surface of the second spacer are located at different heights from the substrate; a source / drain region in the substrate on a sidewall of the gate structure; a capping pattern covering an upper surface of the gate structure and an upper surface of the first spacer; as well as A contact connected to the source / drain region on a sidewall of the second spacer, the second spacer being interposed between the first spacer and the contact, The upper surface of the gate structure is curved, so that the height of the upper surface of the gate structure adjacent to the first spacer increases in a direction away from the first spacer. The gate structure includes a gate electrode and a gate insulating film between the gate electrode and the substrate and between the gate electrode and the first spacer. A first distance from an uppermost portion of the gate electrode to an upper surface of the capping pattern is smaller than a second distance from an uppermost portion of the gate insulating film to the upper surface of the capping pattern, the second distance is smaller than a third distance from the first point to the upper surface of the capping pattern, The third distance is smaller than a fourth distance from a lowermost portion of the upper surface of the first spacer to the upper surface of the capping pattern, and The sidewalls of the contact are at least partially defined by the sidewalls of the second spacer.

2. The semiconductor device according to claim 1, wherein An upper surface of the gate electrode adjacent to the gate insulating film is convex, and An upper surface of the gate insulating film is convex.

3. The semiconductor device according to claim 1, wherein A height of the upper surface of the first spacer decreases in a direction away from the gate electrode and then increases.

4. The semiconductor device according to claim 1, wherein: A first thickness of the gate insulating film in a direction parallel to an upper surface of the substrate is smaller than a second thickness of the first spacer in the direction parallel to the upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein A first angle is formed at a point where an upper surface of the gate electrode meets a sidewall of the gate electrode, and The first angle is an obtuse angle.

6. The semiconductor device according to claim 1, wherein The height of the upper surface of the gate insulating film decreases in a direction away from the gate electrode.

7. The semiconductor device according to claim 1, wherein The upper surface of the second spacer is higher than an upper surface of the gate electrode in a direction perpendicular to an upper surface of the substrate.

8. The semiconductor device according to claim 1, wherein The upper surface of the second spacer is lower than an upper surface of the gate electrode in a direction perpendicular to an upper surface of the substrate.

9. The semiconductor device according to claim 1, wherein: The second spacer extends along the sidewalls of the first spacer and the sidewalls of the capping pattern.

10. The semiconductor device according to claim 1, wherein The first spacer includes silicon oxide, and the second spacer includes silicon nitride.

11. The semiconductor device according to claim 1, wherein The upper surface of the gate structure includes a first portion adjacent to the first spacer and a second portion spaced apart from the first spacer, The height of the first portion of the upper surface of the gate structure increases in a direction away from the first spacer, and A height of the second portion of the upper surface of the gate structure is substantially the same in a direction away from the first spacer.

12. The semiconductor device according to claim 11, wherein The first length of the second portion is greater than the second length of the first portion, and The first length and the second length are measured along the upper surface of the gate structure.

13. A semiconductor device comprising: substrate; a gate structure on the substrate, wherein the gate structure comprises a gate electrode and a gate insulating film extending along a bottom surface and a sidewall of the gate electrode; a first spacer, on a sidewall of the gate structure, a capping pattern covering an upper surface of the gate structure and an upper surface of the first spacer; a second spacer, on a sidewall of the first spacer and a sidewall of the capping pattern, wherein the upper surface of the first spacer and the upper surface of the second spacer are located at different heights from the substrate; source / drain regions in the substrate on sidewalls of the gate structure; and A contact connected to the source / drain region on a sidewall of the second spacer, the second spacer being interposed between the first spacer and the contact, wherein the upper surface of the gate structure and the upper surface of the first spacer are connected to each other to form a raised upper surface of the gate structure relative to the upper surface of the substrate, and the first spacer includes a recessed upper surface relative to the upper surface of the substrate, A first distance from an uppermost portion of the gate electrode to an upper surface of the capping pattern is smaller than a second distance from an uppermost portion of the gate insulating film to the upper surface of the capping pattern, the second distance is smaller than a third distance from an uppermost portion of the upper surface of the first spacer to the upper surface of the capping pattern, The third distance is smaller than a fourth distance from a lowermost portion of the upper surface of the first spacer to the upper surface of the capping pattern, and A sidewall of the contact is defined by at least one of a sidewall of the second spacer and a sidewall of the capping pattern.

14. The semiconductor device according to claim 13, wherein: A first thickness of the gate insulating film in a direction parallel to an upper surface of the substrate is smaller than a second thickness of the first spacer in the direction parallel to the upper surface of the substrate.

15. The semiconductor device according to claim 13, wherein: An uppermost portion of the raised upper surface of the gate structure is higher than a lowermost portion of the recessed upper surface of the first spacer in a direction perpendicular to the upper surface of the substrate.

16. The semiconductor device according to claim 13, wherein: The raised upper surface of the gate structure is adjacent to the sidewall of the first spacer.

17. The semiconductor device according to claim 13, wherein: A bottom surface of the capping pattern has a wave shape.

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