Semiconductor device and method for forming a semiconductor device

Abstract

The present invention discloses a semiconductor device and a method for forming the semiconductor device. A method for forming the semiconductor device includes incorporating a recombination center atom into a semiconductor substrate. The method further includes injecting inert gas atoms into a doping region of at least one of a diode structure and a transistor structure after incorporating the recombination center atom. The doping region is arranged at a surface of the semiconductor substrate.

Description

Technical Field

[0001] Examples relate to concepts for semiconductor structures, and in particular, to semiconductor devices, and methods for forming semiconductor devices. Background Art

[0002] In some semiconductor devices, a power transistor may be connected to an inductive load. In the case of a sudden shutdown and / or the switching on or off of a power transistor, a high induced voltage may be generated due to the inductive load. For example, a freewheeling diode may be implemented in some semiconductor devices to conduct the current flow driven by the inductor when the transistor is disconnected. When the transistor is turned on again, the current that may still flow through the diode may be commutated to the power transistor. However, some semiconductor devices may suffer from high switching losses and / or unstable forward voltages. Summary of the invention

[0003] Some embodiments relate to a method for forming a semiconductor device. The method includes incorporating a recombination center atom into a semiconductor substrate. The method further includes injecting noble gas atoms into a doping region of at least one of a diode structure and a transistor structure after incorporating the recombination center atom. The doping region is arranged at a surface of the semiconductor substrate.

[0004] Some embodiments relate to a semiconductor device. The semiconductor device includes a doped region of at least one of a diode structure and a transistor structure. The doped region is arranged at a surface of a semiconductor substrate. The maximum doping concentration of the doped region is at least 3 1*10 18 The maximum doping concentration of the recombination center atoms in the semiconductor substrate is at least 3 1*10 16 A composite central atom. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which:

[0006] Figure 1A A flow chart showing a method for forming a semiconductor device is shown;

[0007] Figure 1B A flow chart illustrating an additional method for forming a semiconductor device;

[0008] Figure 2 The Pt concentration (per cm 3 ) is a graphical representation of the profile relative to depth (μm);

[0009] Figure 3shows the simulated net doping concentration between the surface and a depth of 5000 nm;

[0010] Figure 4 Shows Figure 3 The simulated net doping concentration between the surface and a depth of 1200 nm;

[0011] Figure 5 shows the normalized simulated distribution of crystal defects between the surface and a depth of 5000 nm;

[0012] Figure 6 Shows Figure 5 Normalized simulated distribution of crystal defects between the surface and a depth of 1200 nm;

[0013] Figure 7 The Pt concentration (per cm) between the surface and a depth of 5000 nm is shown. 3 ) Graphical representation of the profile versus depth (μm);

[0014] Figure 8 Shows Figure 7 The Pt concentration (per cm 3 ) Graphical representation of the profile versus depth (μm);

[0015] Fig.9A A schematic diagram of a semiconductor device is shown;

[0016] Fig. 9B A schematic diagram showing a further semiconductor device; and

[0017] Fig. 9C A schematic diagram of a circuit representation of a semiconductor device is shown. DETAILED DESCRIPTION

[0018] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are illustrated.In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0019] Therefore, although other examples can have various modifications and alternative forms, some of its specific examples are shown in each figure and will be described in detail subsequently. However, this specific embodiment does not limit other examples to the described specific forms. Other examples can cover all modifications, equivalents and alternatives that fall within the scope of the present disclosure. Throughout the description of each figure, the same number refers to the same or similar element, and the same or similar element can be implemented in the same or modified form when compared with each other, and the same or similar functionality is provided at the same time.

[0020] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be connected or coupled directly, or via one or more intervening elements. If two elements A and B are combined using "or", this will be understood to disclose all possible combinations, i.e., only A, only B, and A and B. An alternative wording for the same combination is "at least one of A and B". The same applies to combinations of more than two elements.

[0021] The terminology used for the purpose of describing a particular example herein is not intended to be restrictive for other examples. Whenever a singular form such as "one", "an" and "the" is used and only a single element is neither explicitly nor implicitly limited to being mandatory, other examples can also use plural elements to realize the same functionality. Similarly, when functionality is subsequently described as being realized by using multiple elements, other examples can realize the same functionality by using a single element or processing entity. In addition, it will be understood that the term "includes", "comprising", "including" and / or "comprising" specifies the existence of stated features, integers, steps, operations, processes, actions, elements and / or components when used, but does not exclude the existence or addition of one or more other features, integers, steps, operations, processes, actions, elements, components and / or any groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) are used herein with their ordinary meanings in the art to which the examples belong.

[0023] Figure 1A A flow chart of a method 100 for forming a semiconductor device according to an example is shown.

[0024] The method 100 includes incorporating (in 101) a recombination center atom into a semiconductor substrate. The method 100 further includes implanting (in 102) noble gas atoms into a doping region of at least one of a diode structure and a transistor structure after incorporating (in 101) the recombination center atom. The doping region is arranged at a surface of the semiconductor substrate.

[0025] Since the noble gas atoms are implanted 102 into the doped region after the incorporation 101 of the recombination central atoms, any damage caused by the implantation 102 of the noble gas atoms can be decoupled from the incorporation of the recombination central atoms. For example, getters of the recombination central atoms into unwanted complexes, electrically active clusters, and / or electrically inactive clusters, which may be enhanced due to defects in the lattice of the doped region caused by the damage implantation 102, can be avoided and / or reduced because the implantation 102 of the noble gas atoms is performed after the incorporation 101 of the recombination central atoms.

[0026] Incorporating the recombination center atom (in 101) may include implanting the recombination center atom (e.g., by ion implantation) into the semiconductor substrate. After forming a doped region in the semiconductor substrate, the recombination center atom may be implanted into the semiconductor substrate from the back surface of the semiconductor substrate. Optionally, the recombination center atom may include at least one type of atom from the following atomic group, the atomic group including: platinum atoms, gold atoms, and palladium atoms.

[0027] Can be used less than per cm 2 5*10 13 The implantation dose of atoms is used to implant the recombination central atom.

[0028] Incorporating the recombination center atom (in 101) may further include annealing (e.g., heating) the semiconductor substrate after the recombination center atom is implanted so that the implanted recombination center atom diffuses in the semiconductor substrate. Annealing of the semiconductor substrate may be performed such that the annealing temperature is between 750° C. and 950° C. In addition to the ramp-up phase, the time period at the maximum temperature may be between 5 minutes and several hours (e.g., 2 hours).

[0029] The method 100 may further include forming a doped region before the composite central atom is incorporated. The doped region to be formed may include (or may be) an anode doped region (or a first anode or cathode doped region) of a diode structure, and the doped region may be formed at a surface (e.g., a front surface) of the semiconductor substrate. The doped region may be formed by incorporating a first type of dopant (e.g., a p-type dopant) into the semiconductor substrate to form a highly doped portion (e.g., a p+ portion) of a doped region having a first conductivity type, and a very highly doped portion (p++ portion) of a doped region having a first conductivity type.

[0030] Incorporating the first type of dopant may include implanting the first type of dopant into the semiconductor substrate from the front surface of the semiconductor substrate (e.g., by ion implantation) to form a highly doped portion (p+ portion) of the doped region. The highly doped portion of the doped region may, for example, be a p-well doped region. For example, the first type of dopant may be incorporated into the semiconductor substrate using a plurality of dopants per cm 2 1*10 12 dopant atoms per cm 2 1*10 14 doping atoms per cm 2 5*10 12 dopant atoms per cm 2 5*10 13 The first type of dopant may be boron, aluminum, gallium and / or indium dopant. These dopants of the first type may cause the doped region to have a first conductivity type (e.g., p-type conductivity).

[0031] Incorporating the first type of dopant to form the doped region may further include annealing the semiconductor substrate after the first type of dopant is implanted so that the implanted first type of dopant diffuses in the semiconductor substrate to form a highly doped portion (p-well portion) of the doped region. Annealing of the semiconductor substrate may be performed such that the annealing temperature is between 800°C and 1200°C. The thermal budget for forming the highly doped portion of the doped region may be 200 minutes at 1150°C to achieve a junction depth of 4 μm. This is equivalent to approximately 80 minutes at 1200°C: that is, the annealing time is more than 1 hour in total.

[0032] The first type of dopant may be incorporated into the semiconductor substrate such that the average doping concentration of the highly doped portion of the doped region after annealing the semiconductor substrate is at least 100 Å per cm 3 1*10 14 dopant (or for example per cm 3 1*10 14 The dopant and per cm 3 1*10 17 The average doping concentration can, for example, be the measured number of dopants per volume averaged over the highly doped part of the doped region, or can be determined by the integrated dose value and the penetration depth of the corresponding diffusion profile (e.g. for Figure 3 This results in 7.5E15 cm^-3 in the p+ case and more than 1E19 cm^-3 in the p++ case). The penetration depth for the highly doped region can be considered as the point at which the doping concentration of the highly doped part is equal to the doping concentration of the underlying substrate.

[0033] Forming the doped region may further include, after forming the highly doped portion (p+ portion) of the doped region, incorporating a first type of dopant to form a very highly doped portion (e.g., p++ portion) of the doped region at the surface of the semiconductor substrate. For example, the first type of dopant may be incorporated into the doped region at a concentration of 100 μm / cm. 2 1*10 12 dopant atoms per cm 2 1*10 16 Implant doses between the dopant atoms are incorporated into the semiconductor substrate to form very highly doped portions of the doped region.

[0034] The first type of dopant may be incorporated into the semiconductor substrate such that the average doping concentration of the very highly doped portion (p++ portion) of the doped region after annealing at least a portion of the semiconductor substrate is in the range of 1.0 to 2.0 ppm. 3 1*10 17 The dopant and per cm 3 1*10 20 dopant (e.g. at least every cm 3 1*10 18 of dopant, at least per cm 3 5*10 18 of dopant, or at least per cm 3 1*10 19 The average doping concentration may be, for example, the measured number of dopants per volume averaged over the very highly doped part of the doping region, i.e. determined by the integrated dose value and the penetration depth of the corresponding diffusion profile. The penetration depth for a very highly doped region may be considered to be the point at which the doping concentration of the highly doped part is equal to the doping concentration of the highly doped part of the doping region. Additionally, optionally or alternatively, the maximum doping concentration of the very highly doped part of the doping region may be at least 1 cm 3 1*10 18dopant. For example, the first type of dopant can be implanted with an implantation energy between 20keV and 50keV. Incorporating the first type of dopant to form a very highly doped portion of the doped region can further include annealing the semiconductor substrate after the first type of dopant has been implanted so that the implanted first type of dopant diffuses in the semiconductor substrate to form a very highly doped portion of the doped region. Annealing of the semiconductor substrate can be implemented so that the maximum annealing temperature is between 800°C and 1200°C. If a laser thermal annealing (LTA) process is used with an annealing temperature above T>1414°C (melting point of silicon), the annealing time can be very short in the nanosecond range. Alternatively, a furnace process can be used, which has an annealing time of several hours (e.g., between 750°C and 900°C, 2h). For example, the annealing process can be combined with a Pt diffusion (annealing) process.

[0035] After annealing the semiconductor substrate, a very highly doped portion (p++ portion) of the doped region may be formed between the front surface of the semiconductor substrate and the highly doped portion of the doped region. In addition, the very highly doped portion (p++ portion) of the doped region may be formed adjacent to (e.g., directly adjacent to) or overlapping with the highly doped portion (p+ portion) of the doped region.

[0036] Even before forming the doped regions in the semiconductor substrate, the semiconductor substrate may be lightly doped with the second conductivity type (e.g., n-doped regions). The lightly doped regions with the second conductivity type may be part of the bulk substrate of the semiconductor substrate. Thus, the lightly doped regions with the second conductivity type may have the same doping as the bulk semiconductor substrate. For example, the semiconductor substrate before forming any doped regions may be an n-doped semiconductor substrate. The average doping concentration of the lightly doped regions may be 100 Å / cm 3 1*10 11 The dopant and per cm 3 5*10 14 For example, the average doping concentration can be the measured number of dopants per volume averaged over a lightly doped region.

[0037] After forming the doped region in the semiconductor substrate, the doped region can be formed adjacent to the lightly doped region (e.g., n-doped region) having the second conductivity type. After forming the doped region, a pn junction of a diode structure or a transistor structure can be formed between the anode doped region having the first conductivity type and the lightly doped region having the second conductivity type.

[0038] After forming the doped regions, recombination center atoms may be incorporated (in 101) into the semiconductor substrate. After incorporating the recombination center atoms, noble gas atoms may be implanted (in 102) into the semiconductor at (or from) the front surface of the semiconductor substrate. For example, Ar implantation performed on the surface opposite to the Pt implantation may be used to form an emitter controlled (EC) diode (combined with Figure 3 ). In emitter controlled (EC) diodes, a weak anode emitter can reduce switching losses and, on the other hand, such an emitter can use an additional boron implant with high dose and low penetration depth for ohmic contact. However, in case of increasing dose, the latter can lead to an increase in emitter efficiency. Thus, it may be desirable to weaken such emitter efficiency by using a damage implant (e.g. by Ar ion bombardment) to avoid degradation of the contact behavior. Implantation of noble gas atoms can be used to create damage to the lattice of very highly doped parts of the doped region. For example, such a damage implant can weaken the emitter efficiency, which can lead to lower switching losses.

[0039] The noble gas atoms may include at least one type of atoms from the following atomic group, the atomic group including: argon atoms, helium atoms, neon atoms, krypton atoms, and xenon atoms. 2 5*10 13 The noble gas atoms may be implanted (e.g., by ion implantation) at a dose of 100 atoms. The noble gas atoms may be implanted with an implantation energy of less than 500 keV.

[0040] The implantation of the noble gas atoms can be controlled (e.g., by controlling the implantation dose and / or the implantation energy) so that after the noble gas atoms are implanted, more than 50% (or, for example, more than 60%, or, for example, more than 70%, or, for example, more than 90%) of the implanted noble gas atoms are arranged at a penetration depth equal to or less than the thickness of the very highly doped portion of the doped region after annealing (or within the penetration depth). For example, the highest (or maximum) penetration depth of more than 50% (or, for example, more than 60%, or, for example, more than 70%, or, for example, more than 90%) of the implanted noble gas atoms can be equal to or less than the highest (or maximum) thickness of the very highly doped portion of the doped region. The highest penetration depth can be the maximum distance range that the implanted noble gas atoms travel (or reach) from the entry (or injection) surface (e.g., front surface) of the semiconductor substrate. The distance can be measured in a direction substantially perpendicular or orthogonal to the lateral entry surface of the semiconductor substrate. For example, the thickness of the very highly doped portion of the doped region can be the distance measured orthogonally from the front surface of the semiconductor substrate.

[0041] The method 100 may further include thinning (e.g., grinding) the semiconductor substrate from a back surface of the semiconductor substrate after implanting the inert gas atoms. After thinning the semiconductor substrate, the thickness of the semiconductor substrate (measured in an orthogonal or vertical direction between the front surface and the back surface) may be between 30 μm and 700 μm. Thinning the semiconductor substrate may help remove excess platinum clusters in an end of range (EOR) depth at an implanted surface (e.g., back surface) of the semiconductor substrate.

[0042] Method 100 may further include incorporating a second type of dopant (e.g., hydrogen H atoms) to form a field stop zone (e.g., an n+ doped zone) of a diode structure (or transistor structure). The field stop zone may be formed between a lightly doped region having a second conductivity type and a back surface of the semiconductor substrate. Incorporating the second type of dopant to form the field stop zone may include implanting the second type of dopant into the semiconductor substrate from the back surface of the semiconductor substrate. Incorporating the second type of dopant to form the field stop zone may include annealing at least a portion of the semiconductor substrate. Annealing of the semiconductor substrate may be performed such that the annealing temperature is below 700° C. The second type of dopant may be incorporated such that the average doping concentration of the field stop zone after annealing may be at a concentration of 100 nm per cm 3 5*10 14 The dopant and per cm 3 1*10 17 between dopants (or for example per cm 3 1*10 15 The dopant and per cm 3 5*10 16 The integrated dose value on the field stop zone can be between 5E11 cm^-2 and 1e12 cm^-2.

[0043] The method 100 may further include forming a very highly doped region (e.g., an n++ doped region) having the second conductivity type at the back side of the semiconductor wafer after forming the field stop region having the second conductivity type. Forming the very highly doped region having the second conductivity type may include incorporating a dopant of the second type into the semiconductor substrate after forming the field stop region. The dopant of the second conductivity type may be incorporated into the semiconductor substrate such that an integrated dose value of the very highly doped region having the second conductivity type is at least 100 ppm per cm 2 5*10 14 or 5*10 15 of dopants.

[0044] A lightly doped region with the second conductivity type (n-doped region), a field stop region with the second conductivity type (n+ doped region) and a very highly doped region with the second conductivity type (n++ doped region) can be part of the cathode doped region (or second anode or cathode doped region) of the diode structure.

[0045] The method 100 may further include forming a backside contact metallization layer (electrode) at the back side of the semiconductor substrate (e.g., on its back surface) after forming the very highly doped region of the second conductivity type. For example, the backside contact metallization layer may be formed directly adjacent to the very highly doped region. For example, the method 100 may further include forming a frontside contact metallization layer at the front side of the semiconductor substrate (e.g., on its front surface), directly adjacent to the very highly doped region of the first conductivity type.

[0046] In the examples described herein, the doping region including the first conductivity type may be a p-doping region (e.g., caused by an incorporated dopant that is a boron, aluminum, gallium, and / or indium dopant). Thus, the second conductivity type indicates a relative n-doping region. Alternatively, it may be that the doping region including the first conductivity type may be an n-doping region (e.g., caused by an incorporated dopant that is a phosphorus ion, antimony, selenium, arsenic and / or sulfur, tellurium dopant), and therefore, the second conductivity type indicates a relative p-doping region. In other words, the first conductivity type may indicate p-doping, and the second conductivity type may indicate n-doping, or vice versa.

[0047] For example, a lateral surface or a lateral dimension (e.g. a diameter or a length) of a main surface (e.g. a front surface or a back surface) of the semiconductor wafer may be more than 100 times (or more than 1000 times or more than 10000 times) the distance between the front side of the semiconductor wafer and the back surface of the semiconductor wafer.

[0048] The front side surface of a semiconductor wafer may be the semiconductor surface of a semiconductor wafer facing a metal layer, an insulating layer, or a passivation layer on top of the semiconductor surface. Compared to the substantially vertical edge of a semiconductor wafer (e.g., resulting from the separation of chips from each other by dicing a semiconductor wafer), the surface of a semiconductor wafer may be a substantially horizontal surface extending laterally. The surface of a semiconductor wafer may be a substantially flat plane (e.g., ignoring the unevenness of the semiconductor structure due to the manufacturing process or the groove). For example, the front side surface of a semiconductor wafer may be an interface between a semiconductor material and an insulating layer, a metal layer, or a passivation layer on top of the semiconductor wafer. For example, a more complex structure may be located at the front side surface of a semiconductor wafer than at the back side of a semiconductor wafer. The back side surface of a semiconductor wafer may be a side or surface of a semiconductor wafer, where a back side metallization contact structure (e.g., an anode or cathode contact structure) covering more than 50% (or, for example, more than 80%) of the back side surface of the semiconductor wafer will be formed (or formed).

[0049] For example, the vertical direction may be perpendicular or orthogonal to the side of the semiconductor wafer (or the side of the amorphous semiconductor layer). The implantation surface or entry surface may be the surface (of the semiconductor wafer or layer) at which the implanted dopant ions enter the semiconductor wafer or layer. For example, the doped region formed by the implantation of dopant ions (e.g., at the range region of the implantation of dopant ions) may be located at a certain depth relative to the implantation surface used to implant the dopant ions into the semiconductor wafer.

[0050] The semiconductor substrate may be a silicon-based substrate (e.g., a silicon (Si) substrate or a silicon wafer). For example, alternatively, the semiconductor wafer of the semiconductor device may be a silicon carbide (SiC) wafer, a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer. For example, the semiconductor wafer may be an epitaxial semiconductor wafer, a CZ semiconductor wafer, a magnetic CZ semiconductor wafer, or a floating zone semiconductor wafer.

[0051] The example described in method 100 can illustrate the disconnection of two competing mechanisms. The first mechanism can be the setting of the emitter efficiency by Ar damage implantation. The second mechanism can be an increase in the recombination rate by reducing the recombination lifetime. In an example, the diffusion of the implanted platinum can be performed before the emitter efficiency is set. For example, the Ar damage implantation can be performed after the Pt process. Lower Pt implant dose and implantation energy and lower Ar damage dose and implantation energy can be achieved even due to the disconnection of the two competing mechanisms.

[0052] In an example, the diode structure can be configured as a freewheeling diode (e.g., a flyback diode) in a semiconductor device, which can be connected to a power transistor. The power transistor can also be connected to an inductive load. In the case of a sudden shutdown, or the turning on or off of the power transistor, a high induced voltage can be generated due to the inductive load. When the transistor is turned off, the freewheeling diode structure can conduct the current flow driven by the inductance. When the transistor is turned on again, the current flow is reversed until the reverse current drops to zero when the recombination of the stored charge is completed.

[0053] Thus, method 100 may include forming a power transistor structure and a diode structure. The diode structure may be connected to the power transistor structure such that the diode structure may be configured to conduct current from the power transistor if the power transistor is switched from a conducting state to a non-conducting state.

[0054] The semiconductor device to be formed by the method 100 may be capable of controlling an inductive load connected to a power transistor. Examples of such inductive loads may be electric motors in voltage source converters for variable speed transmissions, which may be used in consumer applications such as washing machines, and / or air conditioning systems, and / or in transmission technology for railway and industrial applications. The power transistor of the semiconductor device to be formed may include (or may be) a fast switching metal oxide semiconductor (MOS) power transistor, such as an insulated gate bipolar transistor (IGBT), which may be used in a higher voltage range. Depending on the field of application, the size of the semiconductor device to be formed may be determined for a blocking capability ranging from 600V to 6500V. By mutual connection and / or disconnection in the bridge circuit, a desired frequency (e.g., by pulse width modulation) may be generated at the output.

[0055] Method 100 can provide a concept for forming a semiconductor device with low switching losses and high switching speed. In order to keep the switching losses as low as possible, a high switching speed can be expected. However, due to the inductive load, a high induced voltage can be generated in the case of a sudden shutdown that destroys the active switch. A freewheeling diode (e.g., such as a diode structure formed by method 100) can be provided in the parallel branch, which can continue to guide the current flow driven by the inductance. When the transistor is turned on again, the current still flowing through the diode can be commutated to the IGBT. Here, the turn-on speed of the transistor can determine the steepness of the reduction of the current in the diode, the so-called dI / dt (I=current, t=time). In addition to the switching speed and the bias current, the stored charge can also be a factor. Its amount can be determined by the recombination speed of electrons and holes (which carry the current in the forward direction) during the depletion process in the diode. The corresponding characteristic time constant is the so-called minority charge carrier lifetime τ.

[0056] Switching losses can be reduced by reducing the minority charge carrier lifetime τ. The diffusion of heavy metal recombination center atoms (e.g., gold (Au) or platinum (Pt)) (in 101) into the drift region of the semiconductor device can be implemented to reduce τ. Heavy metal atoms that are alternatively incorporated on the lattice space can occupy vacancies in the host lattice forming center in the forbidden band with mid-band range energy levels, and can cause a corresponding increase in the recombination rate due to the associated higher capture rate for electrons and holes. However, during the blocking operation of the diode, the recombination center can in turn act as a generation center and can cause an increase in the leakage current. Compared to the gold (Au) center, the platinum (Pt) center can have a slightly more dispersed energy level relative to the band center. Thus, the Pt center can have a lower generation rate because the generation rate decreases exponentially with the distance from the band center. Therefore, Pt can be used in power semiconductor devices and can cause lower leakage current values ​​(compared to Au). This may be true in the case of higher operating temperatures, which may range from 125° C. to 175° C., depending on the application and voltage rating of the semiconductor device.

[0057] Method 100 may further provide a concept for controlling the minority carrier lifetime τ of a diode structure. Method 100 includes an implantation process (in 101) for implanting recombination central atoms. Instead of implanting recombination central atoms, the lifetime setting of the IGBT freewheeling diode, as well as the controllable setting of the anode emitter efficiency (e.g. in an EC diode), may alternatively be performed by diffusion of Pt from a platinum silicide (PtSi) layer. For example, a thin Pt layer (e.g. approximately 10 nm to 20 nm) may be deposited onto the semiconductor body by evaporation or sputtering. An intermetallic phase of platinum silicide (PtSi) may then be formed by an alloying process. In the PtSi process, after any excess metallic platinum has been removed in an aqua regia etch, the Pt from the silicide may be diffused into the semiconductor crystal using an additional oven process at a temperature between 750°C and 900°C to set the forward voltage (V F Setting). Silicide can be formed via contact holes, for which an intermediate oxide (IOX) can be used to mask the chip edge. Platinum can be used to set the lifetime τ, and silicide can be considered as a practically inexhaustible source. Temperature can determine the solid solubility and thus the surface concentration. In addition, the amount of platinum incorporated on the alternative lattice sites that form the desired recombination centers in the drift path of the device can also depend on the thermal budget of Pt diffusion (temperature x time). For example, the concentration of centers in the middle of the drift region can follow the following law: The law describes its growth proportional to the square root of time.

[0058] In serial production, V F The value can be used to monitor the effectiveness of lifetime limitation (e.g., τ reduction). An increase in the recombination rate can result in a diode forward voltage V F The increase in the steady decline in , which can lead to an increase in forward losses. However, this may only have a minor effect when the switching frequency increases.

[0059] Another parameter that can be considered during wafer testing is the leakage current (I R ). Pt doping generally provides low leakage current values. However, crystal defects may form during production, which may affect the electrical parameters. Such crystal defects may include slip lines, dislocation loops or other extended defects, which may lead to V F and I R For example, some other variable factors (segregation or absorption effects caused by highly doped edge regions or thermal oxides at the semiconductor surface) may also affect the desired Pt distribution.

[0060] Compared to Pt diffusion from a PtSi layer, the implantation process for incorporating platinum can provide better reproducibility in terms of dose due to its good controllability. Moreover, the manufacturing process can be less expensive. However, the limited Pt dose can face multiple competing processes during diffusion. For example, in the worst case, most of the incorporated platinum can be incorporated in unwanted complexes, electroactive and / or electroactive clusters, which can result in insufficient amounts of platinum available for alternative lattice incorporation. During Pt implantation, the scattering oxides used for implantation can therefore be removed before Pt diffusion. In addition, after the high temperature process (which is used for Pt diffusion), highly doped n-doped layers can be produced. + emitter (at the back surface). Otherwise, the presence of high phosphorus (P) concentration (from the n+ emitter) during Pt diffusion can absorb a portion of the platinum, which can lead to V F Strong variations in settings. For example, n can be formed (or made) by phosphorus P implantation after Pt diffusion + The emitter and activation can be performed by a laser process during which short laser pulses prevent interaction between platinum and phosphorus that could lead to "phosphorus diffusion absorption" of platinum. For example, since no PtSi layer is deposited, there is no interfering Pt silicide in the contact hole.

[0061] Figure 1BA flow chart of a method 150 for forming a semiconductor device is shown. The method 150 may be similar to the method 100. For example, the method 150 may include one or more or all of the features described with respect to the method 100. For example, the method 150 may be a manufacturing process for forming an IGBT freewheeling diode structure.

[0062] Method 150 may include forming a doped region in a semiconductor substrate. The doped region to be formed may be an anode doped region of a diode structure. Forming the doped region may include implanting (in 103) (e.g., by ion implantation II) a first type of dopant (e.g., boron B) atoms into the semiconductor substrate to form a p-well doped region (which may become a highly doped portion (p+ portion) of the doped region to be formed). Forming the doped region in the semiconductor substrate may further include annealing the semiconductor substrate (in 104) after implanting the first type of dopant to cause diffusion (e.g., a diffusion process) of the implanted first type of dopant in the semiconductor substrate to form the p-well doped region. Annealing the semiconductor substrate may be implemented so that there is a maximum annealing temperature of more than 900°C. The thermal budget for forming the highly doped portion of the doped region may be 200 minutes at 1150°C to achieve a junction depth of 4μm. This is equivalent to approximately 80 minutes at 1200°C: that is, the annealing time is more than 1 hour in total.

[0063] The first type of dopant may be incorporated into the semiconductor substrate such that the average doping concentration of the highly doped portion of the doped region after annealing the semiconductor substrate is at least 100 Å per cm 3 5*10 14 of dopant (or at least per cm 3 1*10 15 of dopant or at least per cm 3 5*10 15 From the ratio between the integrated dose and the depth as mentioned above, the average doping concentration can be determined.

[0064] For example, forming the doped regions may further include utilizing 2 1*10 15 The first type of dopant (e.g., boron B) is implanted (e.g., by ion implantation II) into the semiconductor substrate with an implantation dose of 10 dopant atoms and an implantation energy of 30 keV to form a very highly doped portion (p++ portion) of the doped region. For example, the very highly doped portion of the doped region can be formed after forming the highly doped portion of the doped region. The very highly doped portion can form a good ohmic contact to a front side contact metallization layer to be formed at the front side of the semiconductor wafer.

[0065] The method 150 may further include incorporating (in 101) the recombination center atom into the semiconductor substrate after forming the very highly doped portion of the doped region. Incorporating the recombination center atom 101 may include implanting (eg, by ion implantation) the recombination center atom (eg, platinum Pt) into the back surface of the semiconductor substrate. 2 1*10 13 The implantation dose of atoms is used to implant the recombination central atom.

[0066] Incorporating the recombination center atom (in 101) may further include annealing (eg, heating) the semiconductor substrate so that Pt diffusion in the semiconductor substrate occurs. The annealing temperature of the annealing period may be at least 750°C.

[0067] Method 150 may further include implanting noble gas atoms after incorporating the recombination center atom (at 102). 2 2*10 13 The implantation dose of the inert gas atoms (eg, argon Ar atoms) is 1000 keV and the implantation energy is less than 500 keV (or 285 keV, for example). For example, the implantation of the inert gas atoms may cause damage at the front surface of the semiconductor substrate.

[0068] Method 150 may further include incorporating a second type of dopant (e.g., hydrogen H atoms) to form a field stop FS region of the diode structure (or transistor structure). Incorporating the second type of dopant to form the field stop region may include implanting the second type of dopant into the semiconductor substrate from the back surface of the semiconductor substrate. Incorporating the second type of dopant to form the field stop region may further include annealing at least a portion of the semiconductor substrate after implanting the second type of dopant (in 107). For example, annealing the semiconductor substrate may be performed such that the annealing temperature is 400° C. to 500° C. for approximately 150 minutes.

[0069] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 1B The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figure 1A ) or less ( Figures 2 to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0070] Figure 2 The composite effective electroactive Pts concentration is 224 (per cm 3 ) versus depth 225 (μm). For example, Figure 2Shown is a U-shaped distribution of the concentration of substitutional Pt centers (named Pts) determined using DLTS measurements (deep level transient spectroscopy).

[0071] A strong challenge for the implanted platinum (compounding central atom) can be caused by the generation of lattice damage in the implanted edge region. For example, with increasing implantation dose, a decreasing fraction or part of the incorporated Pt amount can become electrically active. For example, for a 1200V diode, once the dose reaches approximately 1 cm 2 1*10 13 The threshold value of the dopant for V F The value can reach the saturation level. An alternative integrated dose value of incorporated platinum for setting the lifetime can be approximately 100 μm / cm 2 1*10 12 of dopants, or 90% of the Pt dose may exist as electrically inactive clusters. Figure 2 The diagram shows the amount of water injected per cm 2 5*10 13 The average doping concentration of the electroactive recombination center atoms can be less than 1 cm 3 1*10 15 For example, the integrated dose of Pts centers at 800°C can be about 2 6*10 11 of dopant and can increase to approximately 1 cm at 850°C. 2 1*10 12 The edge concentration can be per cm 3 3*10 14 atoms per cm 3 4*10 14 atoms, which can be, for example, Figure 7 and Figure 8 The edge concentration of inactive clustered platinum shown in the SIMS analysis in is several orders of magnitude smaller. The solubility of Pt at 800°C is approximately 1E14 cm^-3, and at 850°C approximately 5E14 cm^-3.

[0072] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 2 The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 1B ) or less ( Figures 3 to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0073] The formation of crystal damage through the implantation process leads to the formation of absorption centers, which effectively reduce the electrically activated Pt concentration.

[0074] Figure 3 The simulated net doping concentration |N between the surface and a depth of 5000 nm is shown. A -N D |, and Figure 4 Shows Figure 3 Simulated net doping concentration between the surface and a depth of 1200 nm.

[0075] Figure 3 A diagram of an anode cross-section of a diode structure that may be produced or formed by method 100 and / or method 150 is shown.

[0076] An exemplary diode structure (e.g., a diode doping region) may be formed with a high junction depth, which can sharply flatten the concentration gradient. Another boron implant may then be performed to ensure ohmic contact. Such a boron implant may have a value in the order of magnitude of the anode implant dose, but with lower implant energy and depth. Electrical activation may occur by a subsequent high temperature process, but with a much lower thermal budget than used for the formation of the diode doping region. Process control may result in a junction depth of approximately 4 μm, and approximately 4·10 16 cm -3 The surface concentration (e.g. Figure 3 as shown by the dotted line in the figure).

[0077] The surface concentration of the contact implant (e.g., the very highly doped p++ portion of the doped region formed in methods 100, 150) may be at least one order of magnitude greater than the surface concentration of the highly doped portion of the doped region to form a low ohmic contact region. This may result in an increase in emitter efficiency to the extent that the switching losses of the diode may become unacceptably high. Thus, an Ar damage implant (in 102 of methods 100, 150) may be performed to reduce the emitter efficiency to an appropriate level again.

[0078] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 3 and 4 The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 2 ) or less ( Figures 5 to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0079] Figure 5 shows the normalized simulated distribution of crystal defects created by Ar damage implantation between the surface and a depth of 5000 nm, and Figure 6 Shows Figure 5 Normalized simulated distribution of crystal defects between the surface and a depth of 1200 nm.

[0080] A sufficiently high implantation energy level can be used in order to obtain a penetration depth, which the radiation reaches by contacting the highly doped region of the implantation (the p++ doped part). The comparison shows the dependence of the implantation energy on the distribution of crystal defects over depth. This region can lead to a large absorption effect of the implanted platinum under these boundary conditions, even if an Ar implantation will be carried out at the side opposite to the Pt implantation. The desired V for obtaining the desired V at a constant Pt diffusion temperature is shown in Table 1. F One possible way to set this up could be a large increase in the implanted Pt dose. For example, by raising the Pt dose to 2 6*10 13 atoms, it is actually possible to F To each cm 2 1*10 13 However, this can also lead to a diffusion temperature being raised by about 5°C, which can lead to a stronger formation of Pt-decorated slip lines, which can lead to an increase in the leakage current of the device. Such a dose value can also be a threshold for the onset of saturation, since a further increase in the dose does not necessarily lead to a V F Under the specified boundary conditions, the carrier lifetime setting can be controlled by two competing mechanisms: Pt in-diffusion and simultaneous absorption in Ar damage, which can be related to the crystal defect annealing, which increases at higher Pt diffusion temperatures. Therefore, for V F The alternative Pt set may be the result of the subtraction of two large numbers: the two large numbers may naturally show significant fluctuations. In addition, such a large Pt implant dose may also be unattractive for process technology, as it may lead to long exposure times and additionally cause high costs. Thus, for a 1200V device, the Pt implant dose may be reduced to, for example, about 1 / cm 2 1*10 13 atoms.

[0081] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 5 and 6 The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 3 ) or less ( Figures 7 to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0082] Since the forward voltage of a diode includes the series resistance of the body resistance and the contact resistance, and since the body resistance increases with the number of electrically active recombination centers (e.g., Pts centers), the forward voltage is usually selected in semiconductor manufacturing to monitor both the contact resistance and the effective lifetime limit introduced. In the case when the absorption center introduced, such as by inert gas injection, exists before annealing the recombination center atoms, the latter species is dominantly present in the damaged region, and the measured forward voltage is low. In this case, the VF value is mainly determined by the knee voltage of the pn junction and the series resistance of the remaining substrate that does not include a considerable number of Pts centers. For example, for a 1200V Si diode with virtually no recombination centers, the forward voltage may be, for example, 1V, while the same device with an appropriate number of recombination centers and an emitter efficiency typical for applications such as freewheeling diodes may be, for example, 1.5V. If the contact resistance is now increased, for example by damaging the emitter too severely to reduce its efficiency, the forward voltage can rise to unreasonable values, for example above 2 V, and the IV characteristic also includes a region of negative differential resistance.

[0083] By avoiding Pt absorption during diffusion, it is possible to use 2 1*10 13 The Pt implant dose of the dopant and / or the dose for the Ar damage implant can be reduced by one order of magnitude to per cm 2 2*10 13 atoms.

[0084] It may be possible to reduce the Ar energy even further, which may further reduce leakage current.

[0085] SRP (spreading resistance method), SIMS (secondary ion mass spectrometry) analysis and DLTS measurements can be implemented to measure the distribution of donor, acceptor, total Pt and Pts concentrations in the diode structure. Although the solubility limit cannot be exceeded in the diffusion from silicide as Pt source, the Pt concentration in the projected range can increase by several orders of magnitude compared to the previous one during the implantation depending on the dose value used. In the case of diffusion from an inexhaustible source (such as a PtSi layer), the surface concentration due to solubility limitation can be calculated according to the following relationship:

[0086] .

[0087] With an in-diffusion temperature of 857 °C (after Pt implantation), approximately 3 6*10 14 The maximum Pt concentration of the dopant can be strictly monotonically decreased towards the middle of the wafer (e.g. Figure 2In contrast, for each cm at an energy of 80 keV 2 1*10 13 The Monte Carlo simulation can lead to a Pt dose of 4.5*10 18 cm -3 The maximum concentration of , which can exceed the solubility limit by 4 orders of magnitude. During implantation, the concentration maximum can be at a depth of 39 nm.

[0088] Figure 7 The Pt distribution (per cm 3 Atoms) versus depth (μm), which may result in the specified values ​​for implantation after diffusion at a temperature of 780°C. For example, a process without a thermal budget above 700°C may be provided after Ar ion implantation II to allow Pt diffusion (indicated by line 910), in contrast to a process providing a thermal budget above 700°C after Ar ion implantation II resulting in absorption of Pt at crystal defect centers (indicated by line 920), or a process with Ar implantation and PtSi diffusion (indicated by line 930). The profiles of Pt from the implanted side (e.g., back surface) and from the opposite side (e.g., front surface) are determined using SIMS analysis and plotted on top of each other. SIMS analysis is used to measure the distribution of Pt concentrations bound in "clusters." Figure 8 Shows Figure 7 The Pt concentration (per cm 3 ) versus depth (μm) profile.

[0089] For example, more than 10% of the electrically inactive Pt reaches the very highly doped region, about 10% is activated instead, and the main part remains in the EOR region at the back side that is removed during the thinning process. The surface concentration of electrically inactive Pt may correspond to 3 2*10 17 atoms and thus clearly above the concentration of alternatively incorporated platinum and / or above the values ​​that can be reached during diffusion from the silicide. The Pt concentration can drop to the detection limit of SIMS analysis within a distance of about 100 nm.

[0090] The expected Pt distribution at the surface may be different for high Pt doses. 2 6*10 13 With a high Pt dose of 1000 atoms, only a small fracture in the range of about 1% to 2% can be observed with V F efficient way is instead incorporated into the lattice spacing, and it may be possible to tune V FThe rest may travel into the Ar damaged regions during Pt diffusion and may precipitate out in the form of Pt clusters.

[0091] In contrast to the case where Pt diffusion is decoupled from Ar damage implantation, Pt concentration can reach high values ​​of the order of 100 nm per cm across the entire damage depth range of 600 nm corresponding to dose values ​​of approximately 10%. 3 1*10 18 atoms.

[0092] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Figure 7 and 8 The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 6 ) or less ( Figures 9A to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0093] Fig.9A A diagram of a cross-sectional side view of a semiconductor device 1100 is shown.

[0094] The semiconductor device 1100 includes a doping region 1171 of at least one of a diode structure and a transistor structure 1174. The doping region 1171 is arranged at a surface 1172 of a semiconductor substrate 1173. The maximum doping concentration of the doping region 1171 is at least 100 ppm per cm 3 1*10 18 The maximum doping concentration of the recombination center atoms in the semiconductor substrate 1173 is at least 3 1*10 16 A composite central atom.

[0095] Since the maximum doping concentration of the doping region 1171 is at least 3 1*10 18 However, since the maximum doping concentration of the recombination center atoms in the semiconductor substrate 173 is at least 1 cm 3 1*10 16 The recombination rate of the diode structure can be increased, which can lead to a forward voltage V F increase.

[0096] The doping region 1171 may include (or may be) an anode (or first anode or cathode) doping region of the diode structure 1174. The doping region 1171 may be formed at the front surface 1172 of the semiconductor substrate 1173, and the doping region 1171 may have a first conductivity type (e.g., p-type doping). The doping region 1171 may include a highly doped portion (p+) and a very highly doped portion (p++). The very highly doped portion (p++) of the doping region 1171 may be arranged at the surface 1172 of the semiconductor substrate 1173. The very highly doped portion (p++ portion) of the doping region 1171 may be arranged between the front surface 1172 of the semiconductor substrate 1173 and the highly doped portion of the doping region 1171.

[0097] The average doping concentration of the very highly doped portion (p++ portion) of the doping region 1171 may be 100 Å per cm 3 1*10 17 The dopant and per cm 3 1*10 20 between the dopants.

[0098] The average doping concentration of the highly doped portion of the doped region 1171 (see above) may be at least 100 Å per cm 3 1*10 14 dopant (or for example per cm 3 1*10 14 The dopant and per cm 3 1*10 17 between dopants, or for example per cm 3 1*10 14 The dopant and per cm 3 1*10 16 between the dopants).

[0099] The composite central atom may include at least one type of atom from the following atomic group consisting of: a platinum atom, a gold atom, and a palladium atom.

[0100] The average doping concentration of the recombination central atoms in the very highly doped portion of the doping region 1171 may be at least 1 / cm 3 1*10 17 Recombination center atoms (or at least every cm 3 1*10 18 complex central atoms, or for example, in each cm 3 1*10 17 The number of complex central atoms and each cm 3 1*10 19 Between the composite center atoms, or for example, between each cm 3 2*1017 The number of complex central atoms and each cm 3 5*10 18 For example, the average doping concentration may be a measured number of recombination central atoms per volume averaged over the thickness of the very highly doped portion of the doped region 1171.

[0101] The doped region may be an anode (or cathode) doped region of a diode structure. The diode structure may be configured as a freewheeling diode (e.g., a flyback diode) in the semiconductor device 1100. For example, the semiconductor device 1100 may further include a power transistor structure (e.g., an IGBT) connected to an inductive load. The diode structure may be connected to (e.g., configured relative to) a power transistor structure such that the diode structure is configured to conduct current from the power transistor if the power transistor is switched from a conducting state to a non-conducting state.

[0102] However, the doped region is not limited to being an anode (or cathode) doped region of a diode structure. Alternatively or optionally, the doped region may be a collector or emitter doped region of a transistor structure. For example, the doped region may be an anode emitter (or cathode collector) of an IGBT structure, or a source region (or drain region) of a MOSFET structure (e.g., a coolMOS MOSFET).

[0103] For example, semiconductor device 1100 may be a power semiconductor device having a breakdown voltage or blocking voltage of more than 10 V (e.g., a breakdown voltage of 10 V, 20 V, or 50 V), more than 100 V (e.g., a breakdown voltage of 200 V, 300 V, 400 V, or 500 V), or more than 500 V (e.g., a breakdown voltage of 600 V, 700 V, 800 V, or 1000 V), or more than 1000 V (e.g., a breakdown voltage of 1200 V, 1500 V, 1700 V, 2000 V, 3300 V, or 6500 V).

[0104] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Fig.9A The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 8 ) or less ( Figures 9B to 9C ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0105] Fig. 9B A diagram of a cross-sectional side view of a semiconductor device 1110 is shown.

[0106] The semiconductor device 1110 may be similar to a combination of Fig.9AThe semiconductor device 1100 is described. For example, the semiconductor device 1110 may include Fig.9A One or more or all of the described features.

[0107] like Fig. 9B As shown in , the semiconductor device 1110 may include a diode structure 1174. The diode structure 1174 may include a doped region 1171 having a first conductivity type. The doped region 1171 may be formed at a front surface 1172 of a semiconductor substrate 1173. The doped region 1171 may include a highly doped portion (p+) 1175 and a very highly doped portion (p++) 1176. The very highly doped portion (p++) 1176 of the doped region 1171 may be arranged at the surface 1172 of the semiconductor substrate 1173. The very highly doped portion (p++ portion) 1176 of the doped region 1171 may be arranged between the front surface 1172 of the semiconductor substrate 1173 and the highly doped portion 1175 of the doped region 1171. The doped region 1171 may be an anode doped region (or, for example, a first anode or cathode doped region) of the diode structure 1174.

[0108] The diode structure 1174 may further include a cathode doped region 1178 (or, for example, a second anode or cathode doped region of the diode structure) arranged in the semiconductor substrate. The anode doped region 1171 may be arranged adjacent to the cathode doped region 1178 such that a pn junction exists between the anode doped region 1171 and the cathode doped region 1178. The cathode doped region may include a lightly doped portion 1177 (e.g., a drift portion) that may be arranged directly adjacent to a highly doped portion 1175 of the anode doped region 1171. The lightly doped region 1177 may have a second conductivity type (e.g., an n-doped region). The cathode doped region may further include a highly doped field stop portion (n+) 1179 and a very highly doped portion (n++) 1181 of the second conductivity type.

[0109] The average doping concentration of the field stop portion may be higher than the average doping concentration of the lightly doped portion 1177, but lower than the average doping concentration of the very highly doped portion 1181. The average doping concentration of the lightly doped region 1171 may be 100 Å per cm 3 1*10 11 The dopant and per cm 3 5*10 14 After annealing, the average doping concentration of the field stop region 1179 can be between 10 and 10 cm 3 5*10 14 The dopant and per cm 3 1*10 17After annealing at least a portion of the semiconductor substrate, the average doping concentration of the very highly doped portion 1181 of the cathode doped region 1178 is between 10 and 10 cm 3 1*10 17 The dopant and per cm 3 1*10 20 between the dopants.

[0110] The average doping concentration of the highly doped portion of the doped region 1171 may be at least 3 1*10 14 dopant (or for example per cm 3 1*10 14 The dopant and per cm 3 1*10 17 between the dopants).

[0111] The composite central atom may include at least one type of atom from the following atomic group consisting of: a platinum atom, a gold atom, and a palladium atom.

[0112] The average doping concentration of the recombination center atoms throughout the semiconductor substrate 1173 may be at least 3 1*10 16 composite central atoms, at least per cm 3 1*10 16 Recombination center atoms (or at least every cm 3 1*10 17 complex central atoms, or for example, in each cm 3 1*10 16 The number of complex central atoms and each cm 3 1*10 19 Between the composite center atoms, or for example, between each cm 3 5*10 16 The number of complex central atoms and each cm 3 5*10 17 Between the composite center atoms, or for example about every cm 3 1*10 16 For example, the average doping concentration can be a measured number of recombination central atoms per volume averaged over the thickness of the semiconductor substrate 1173 (between the front surface 1172 and the opposing back surface).

[0113] The average doping concentration of the recombination central atoms in the very highly doped portion of the doping region 1171 may be at least 1 / cm 3 1*10 17 Recombination center atoms (or at least every cm 3 1*1018 complex central atoms, or for example, in each cm 3 1*10 17 The number of complex central atoms and each cm 3 1*10 19 Between the composite center atoms, or for example, between each cm 3 5*10 17 The number of complex central atoms and each cm 3 5*10 18 Between the composite center atoms, or for example about every cm 3 1*10 18 For example, the average doping concentration may be a measured number of recombination central atoms per volume averaged over the thickness of a very highly doped portion of the doping region 1171.

[0114] Lattice defects 1182 caused by the damaging implantation of noble gas atoms may be present in the very highly doped portion 1176 of the doped region 1171 .

[0115] The semiconductor device 1110 may further include an edge termination structure 1183 arranged at (or on) the front surface 1172 of the semiconductor substrate 1173. The edge termination structure 1183 may be arranged in an edge termination region of the semiconductor device 100. For example, the edge termination region may laterally surround (or may be formed laterally around) an active device region in a top view, where a diode structure is arranged. The edge termination structure 1183 may include or may be an oxide layer.

[0116] The semiconductor device 1110 may further include a front side contact metallization layer 1184 arranged at the front side of the semiconductor substrate, for example on the front surface 1172. For example, the front side contact metallization layer 1184 may be arranged directly adjacent to the very highly doped portion 1182 of the anode doping region 1171 having the first conductivity type. The semiconductor device 1110 may further include a back side contact metallization layer 1185 (electrode) arranged at the back side of the semiconductor substrate 1173, for example on the back surface 1186. For example, the back side contact metallization layer 1185 may be arranged directly adjacent to the very highly doped portion 1181 of the cathode doping region 1178 having the second conductivity type.

[0117] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Fig. 9B The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 9A ) or less ( Fig. 9C) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0118] Fig. 9C A schematic diagram of a circuit representation of a semiconductor device 1120 is shown.

[0119] The semiconductor device 1120 may include a diode structure 1174. The diode structure 1174 may be configured as a freewheeling diode. The semiconductor device 1120 may further include a power transistor structure (e.g., an IGBT) 1187 connected to an inductive load 1188. The semiconductor device 1120 may include a gate terminal 1191 connected to a gate region 1189 of the IGBT structure 1187. The semiconductor device 1120 may further include a collector terminal 1192 connected to a collector region 1194 of the IGBT structure 1187. The semiconductor device 1120 may further include an emitter terminal 1193 connected to an emitter region 1195 of the IGBT structure 1187.

[0120] The emitter region 1195 of the IGBT structure 1187 may be connected to the inductive load 1188. For example, the inductive load 1188 may be arranged between the emitter region 1195 of the IGBT structure 1187 and the emitter terminal 1193 of the semiconductor device 1120.

[0121] For example, the gate region 1189 of the IGBT structure 1187 may be connected to a gate control circuit. For example, the gate control circuit may be arranged between the gate 1189 of the IGBT structure 1187 and a gate terminal 1191 of the semiconductor device 1120. For example, the gate control circuit may optionally include at least one voltage source, a resistor, and an inductor.

[0122] The diode structure 1174 may be connected to (e.g. configured relative to) the power transistor structure 1187 such that the diode structure 1174 is configured to conduct current from the power transistor 1187 if the power transistor 1187 is switched from a conducting state to a non-conducting state. For example, the diode structure 1174 may be connected to a collector region 1194 of the IGBT structure 1187. For example, the diode structure 1174 (and / or the inductor) may be connected in parallel between the collector terminal 1192 of the semiconductor device 1120 and the collector region 1194 of the IGBT structure 1187. Optionally, the diode structure 1174 (and / or the inductor) may be connected in parallel to a current source that is arranged between the collector terminal 1192 of the semiconductor device 1120 and the collector region 1194 of the IGBT structure 1187.

[0123] Further details and aspects are mentioned in conjunction with the embodiments described above or below. Fig. 9C The embodiments shown in the figure may include one or more optional additional features, which correspond to the combination of the proposed concept or the above (for example Figures 1A to 9B ) One or more aspects mentioned in connection with one or more embodiments described in the present invention.

[0124] For example, various examples relate to the optimization of the dynamic properties of the IGBT freewheeling diode. Various examples relate to Pt implantation technology, and relate to disconnecting the two competing processes for Pt inward diffusion and Pt absorption in Ar damage implantation. Various examples described herein provide concepts for forming semiconductor devices. Ar damage implantation, which can be used to set the emitter efficiency, can be performed after the Pt process, and the formation of Pt silicide can be omitted. This can allow a significant reduction in dose during implantation, and also significantly reduce energy in the case of argon. The level of scattering in the forward voltage and the leakage current can be significantly reduced, and a level comparable to that of a process using Pt diffusion from PtSi can be achieved.

[0125] The aspects and features mentioned and described (e.g., semiconductor substrates, doped regions, composite central atoms, noble gas atoms, diode structures, semiconductor devices) together with one or more of the previously detailed examples and figures may also be combined with one or more of the other examples to replace similar features of the other examples, or to additionally introduce features into the other examples.

[0126] Examples may also be or relate to a computer program having a program code for executing one or more of the above methods when the computer program is executed on a computer or processor. The steps, operations or processes of the various methods described above may be performed by a programmed computer or processor. Examples may also cover program storage devices, such as digital data storage media, which are machine, processor or computer readable, and encode the machine executable, processor executable or computer executable program of the instructions. The instructions execute or cause some or all of the actions of the methods described above to be performed. The program storage device may include or may be, for example, a digital memory, a magnetic storage medium, such as a disk and tape, a hard drive, or an optically readable digital data storage medium. Other examples may also cover a computer, a processor or a control unit programmed to perform the actions of the methods described above, or a (field) programmable logic array ((F) PLA) or a (field) programmable gate array ((F) PGA) programmed to perform the actions of the methods described above.

[0127] The description and drawings merely illustrate the principles of the disclosure. In addition, all examples recorded herein are primarily and explicitly intended to be used for teaching purposes only, to help the reader understand the principles of the disclosure and the concepts contributed by the inventor(s) to advance the art. All statements recording the principles, aspects and examples of the disclosure, and specific examples thereof, herein are intended to encompass their equivalents.

[0128] A block diagram may, for example, illustrate a high-level circuit diagram that implements the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, etc. may represent various processes, operations, or steps that may, for example, be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or in the claims may be implemented by an apparatus having means for performing each of the corresponding actions of these methods.

[0129] It will be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a specific order, unless otherwise explicitly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit these to a specific order, unless such actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or may be decomposed into a plurality of sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Such sub-actions may be included in the disclosure of this single action and may be the part of the disclosure of this single action, unless explicitly excluded.

[0130] In addition, the attached claims are hereby incorporated into the detailed description, where each claim can be independently used as a separate example. Although each claim can be independently used as a separate example, it is noted that - although the dependent claim can refer to a specific combination with one or more other claims in the claims - other examples can also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such a combination is explicitly proposed herein unless it is stated that a specific combination is not intended. In addition, it is intended to include the features of a claim to any other independent claim, even if the claim is not directly made dependent on the independent claim.

Claims

1. A method (100, 500) for forming a semiconductor device, the method comprising: Incorporating a composite central atom (101) into a semiconductor substrate; as well as implanting (102) noble gas atoms into a doped region of at least one of a diode structure and a transistor structure after incorporating the recombination center atoms, wherein the doped region is arranged at a surface of the semiconductor substrate; introducing (105) a first type of dopant into the semiconductor substrate prior to incorporating the recombination central atom to form a very highly doped portion of the doped region at the surface of the semiconductor substrate, wherein the maximum doping concentration of the very highly doped portion of the doped region is at least 1 cm 3 1*10 18 of dopants.

2. The method according to claim 1, wherein incorporating the recombination center atom comprises implanting the recombination center atom into the semiconductor substrate, and Before the inert gas atoms are implanted, the semiconductor substrate is annealed so that the recombination center atoms diffuse in the semiconductor substrate.

3. The method according to claim 1 or 2, wherein the composite central atom comprises at least one type of atom from the following atomic group, the atomic group comprising: Platinum atoms, gold atoms, and palladium atoms.

4. The method of claim 1 or 2, wherein incorporating (101) complexing central atoms comprises: 2 A dose of 1e14 atoms is used to implant the recombination central atom.

5. The method according to claim 1 or 2, wherein the noble gas atoms include at least one type of atoms from the following atomic group, the atomic group comprising: Argon atoms, helium atoms, neon atoms, xenon atoms, krypton atoms.

6. The method according to claim 1 or 2, wherein the 2 A dose of 2e14 atoms is used to implant noble gas atoms.

7. The method of claim 1 or 2, wherein the noble gas atoms are implanted at an implantation energy of less than 500 keV.

8. The method of claim 1, wherein the noble gas atoms are implanted such that a maximum concentration of created crystal defects is arranged within a very highly doped portion of the doped region.

9. The method according to claim 1, 2 or 8, wherein inert gas atoms are implanted at the front surface of the semiconductor substrate, and The incorporation of the recombination central atoms includes implanting the recombination central atoms from the back surface of the semiconductor substrate.

10. The method according to claim 1, 2 or 8, further comprising thinning the semiconductor substrate from a back surface of the semiconductor substrate after the implantation of the inert gas atoms.

11. The method of claim 1 or 2 or 8, further comprising incorporating a second type of dopant into the semiconductor substrate to form a field stop region of at least one of a diode structure and a transistor structure.

12. A semiconductor device (1100, 1110, 1120), comprising: a doped region (1171) of at least one of a diode structure (1174) and a transistor structure, wherein the doped region (1171) is arranged at a surface (1172) of a semiconductor substrate (1173), The maximum doping concentration of the doped region (1171) is at least 3 1*10 18 dopant; and The maximum doping concentration of the recombination center atoms in the semiconductor substrate (1173) is at least 3 1*10 16 The composite central atom The maximum doping concentration of the recombination central atom is located in the very highly doped region.

13. The semiconductor device according to claim 12, wherein the doped region (1171) comprises a very highly doped portion (1176) arranged at a surface (1172) of the semiconductor substrate (1173).

14. The semiconductor device of claim 13, wherein a maximum doping concentration of the very highly doped region is at least 10 times higher than a maximum doping concentration of doped regions (1171) outside the very highly doped region.

15. A semiconductor device according to claim 13 or 14, wherein the average doping concentration of the recombination central atoms in the very highly doped part of the doped region is at least 1.0 wt % per cm 3 1*10 17 A composite central atom.

16. The semiconductor device according to any one of claims 12 to 14, wherein the average doping concentration of the electrically active recombination center atoms is less than 1.04 N·m-1 / cm 3 1*10 15 A composite central atom.

17. The semiconductor device according to any one of claims 12 to 14, wherein the doped region (1171) comprises an anode or cathode doped region of a diode structure, or a collector or emitter doped region of a transistor structure.

18. A semiconductor device according to any one of claims 12 to 14, further comprising a power transistor structure (1187) connected to an inductive load (1188), and wherein the doped region (1171) comprises an anode or cathode doped region of a diode structure (1174), The diode structure (1174) is configured to conduct current from the power transistor structure (1187) if the power transistor structure (1187) is switched from a conducting state to a non-conducting state.

19. The semiconductor device according to any one of claims 12 to 14, wherein the recombination center atom comprises at least one type of atom from the following atomic group, the atomic group comprising: Platinum atoms, gold atoms, and palladium atoms.

20. The semiconductor device according to any one of claims 12 to 14, wherein a blocking voltage of the semiconductor device is at least 10V.

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