Semiconductor devices

Abstract

The present invention provides a semiconductor device, which is expected to prevent the FWD region of an RC-IGBT from being destroyed when a reverse recovery current flows in the FWD region. The semiconductor device has a plurality of transistor regions and a plurality of diode regions on a semiconductor substrate, and comprises: a plurality of transistor regions and a plurality of diode regions, each extending from one end edge to the other end edge of an active region; a first conductive type solder pad well region, which contacts a rectangular ring-shaped gate flow channel region and is arranged inside the gate flow channel region; a first conductive type collector region, which is arranged on the lower surface side of the semiconductor substrate and is at least arranged in the transistor region; and a second conductive type cathode region, which is arranged on the lower surface side of the semiconductor substrate and is arranged in the plurality of diode regions, the end of the solder pad well region in the arrangement direction orthogonal to the extension direction of the plurality of transistor regions and the plurality of diode regions extends along the extension direction, and a collector region is arranged below the end of the solder pad well region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a reverse conducting IGBT (RC (Reverse Conducting)-IGBT) in which an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Diode) are provided on a single semiconductor substrate (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2016 / 098199 Summary of the invention

[0006] Technical issues

[0007] It is desirable that when a reverse recovery current flows through the FWD region of the RC-IGBT, the FWD region is not destroyed.

[0008] Technical Solution

[0009] In a first embodiment of the present invention, a semiconductor device is provided, which has a plurality of transistor regions and a plurality of diode regions on a semiconductor substrate. The semiconductor device may include a plurality of transistor regions and a plurality of diode regions, a pad well region, and a cathode region. The plurality of transistor regions and the plurality of diode regions may extend from one end edge of the active region to the other end edge, respectively. The other end edge may be opposite to one end edge. The active region may be located inside the gate flow channel region. When the semiconductor substrate is viewed from above, the gate flow channel region may be a rectangular ring with four sides. The pad well region may be in contact with the rectangular ring-shaped gate flow channel region on the upper surface side of the semiconductor substrate and may be arranged inside the gate flow channel region. The pad well region may be of the first conductivity type. The collector region and the cathode region may be arranged on the lower surface side of the semiconductor substrate, respectively. The collector region may be arranged at least in each transistor region of the plurality of transistor regions. The collector region may be of the first conductivity type. The cathode region may be arranged in each diode region of the plurality of diode regions. The cathode region may be of the second conductivity type. The end of the pad well region in the arrangement direction may extend along the extension direction of the plurality of transistor regions and the plurality of diode regions. The arrangement direction of the plurality of transistor regions and the plurality of diode regions may be a direction orthogonal to the extension direction of the plurality of transistor regions and the plurality of diode regions. A collector region may be provided below the end of the pad well region.

[0010] The pad well region may have a plurality of ends extending in the extension direction. The plurality of ends of the pad well region may respectively contact one of the plurality of transistor regions. Collector regions may be provided below the plurality of ends of the pad well region.

[0011] The pad well region may contact two transistor regions and one diode region. One diode region may be located between the two transistor regions. A first end of the plurality of ends of the pad well region may contact the first transistor region of the two transistor regions. A second end of the plurality of ends of the pad well region may contact the second transistor region of the two transistor regions. The second transistor region may be located at a different position from the first transistor region.

[0012] The semiconductor device may include a diode region that is not in contact with the pad well region. A diode region that is not in contact with the pad well region may be located on the side opposite to the pad well region in the arrangement direction relative to a transistor region that is in contact with the pad well region. A portion of the end of the cathode region may have a receding end. A portion of the end of the cathode region may be an end of the cathode region of a diode region that is not in contact with the pad well region, which is opposite to the end of the pad well region in the arrangement direction and extends in the extension direction. The receding end is located on the side opposite to the end of the pad well region relative to the boundary of the transistor region that is in contact with the pad well region and the diode region that is not in contact with the pad well region, and may be receded in the direction from the pad well region toward the diode region that is not in contact with the pad well region in the arrangement direction.

[0013] The receding end portion of the end portion of the cathode region may be separated from the end portion of the pad well region by a thickness equal to or greater than the thickness of the semiconductor substrate.

[0014] The receding end portion of the end portion of the cathode region may be separated from the boundary by 90 μm or more.

[0015] The semiconductor substrate may include a lifetime control body region. The lifetime control body region may be provided between the collector region and the cathode region and the upper surface of the semiconductor substrate, and above the receding end of the cathode region.

[0016] The pad well region may be in contact with one edge of the active region and provided near the center of the one edge in the arrangement direction.

[0017] The rectangular ring-shaped gate flow channel region may include a gate flow channel well region. The gate flow channel well region may be provided on the upper surface side of the semiconductor substrate. The gate flow channel well region may be of the first conductivity type. The semiconductor substrate may include a lifetime control body region. When looking down at the semiconductor substrate, the lifetime control body region may be provided from the active region in the extension direction to a predetermined position of the gate flow channel well region.

[0018] At least one of the plurality of diode regions may have a plurality of contact portions. The plurality of contact portions may extend along the extension direction on the upper surface of the semiconductor substrate in the active region, respectively, and may be arranged spaced apart from each other in the arrangement direction. The rectangular ring-shaped gate runner region may include a gate runner well region. The gate runner well region may be provided on the upper surface side of the semiconductor substrate. The gate runner well region may be of the first conductivity type. The gate runner well region may contact at least one diode region in the extension direction. When the ends of the gate runner well regions that are opposite to each other in the extension direction and that contact the active region and the ends of the cathode regions of at least one diode region are virtually projected onto the upper surface of the semiconductor substrate, the first distance may be greater than the depth of the gate runner well region and less than the thickness of the semiconductor substrate. The first distance may be the shortest distance between the ends of the gate runner well region and the ends of the cathode region. The depth of the gate runner well region may be the depth from the upper surface of the semiconductor substrate to the bottom of the gate runner well region. The thickness of the semiconductor substrate may be the thickness from the upper surface to the lower surface of the semiconductor substrate.

[0019] When the ends of the gate runner well region and the ends of at least one of the plurality of contacts that are opposite to each other in the extension direction are virtually projected onto the upper surface of the semiconductor substrate, the first distance may be greater than the second distance. The second distance may be the shortest distance between the ends of the gate runner well region and the ends of at least one of the contacts.

[0020] When the semiconductor substrate is viewed in a plan view, the transistor regions may be provided at both ends of the active region in the arrangement direction of the pad well region. The pad well region may be in contact with the corner of the active region.

[0021] The plurality of diode regions may include other diode regions. The other diode regions may extend from the pad well region toward the other end edge in the extension direction. When the semiconductor substrate is viewed from above, the end of the cathode region in the other diode regions opposite to the pad well region in the extension direction may be separated from the pad well region.

[0022] It should be noted that the above invention summary does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also realize the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a top view of the semiconductor device 200 according to the first embodiment.

[0024] Figure 2 The diagram shows the range in which the collector region 22 and the cathode region 82 are provided in the semiconductor device 200 .

[0025] Figure 3 1 and 2 are diagrams showing the range in which the lifetime controlling body region 26 and the cathode region 82 are provided in the semiconductor device 200 .

[0026] Figure 4 yes Figure 3 AA cross-section diagram.

[0027] Figure 5 yes Figure 3 BB cross-section diagram.

[0028] Figure 6 yes Figure 3 CC cross-section diagram.

[0029] Figure 7 1 is a top view of a semiconductor device 800 according to a comparative example.

[0030] Figure 8 yes Figure 7 DD cross-sectional view.

[0031] Fig. 9 (a) and (b) are diagrams showing a semiconductor device 300 according to the second embodiment.

[0032] Fig.10 (a) and (b) are diagrams showing a semiconductor device 400 according to a first modification example of the second embodiment.

[0033] Fig.11 (a) and (b) are plan views of a semiconductor device 500 according to a second modification example of the second embodiment.

[0034] Fig.12 (a) and (b) are plan views of a semiconductor device 600 according to a third modification example of the second embodiment.

[0035] Fig.13 This is a diagram showing the range in which the collector region 22 and the cathode region 82 are provided in the semiconductor device 700 according to the third embodiment. DETAILED DESCRIPTION

[0036] The present invention will be described below by way of the embodiments of the invention, but the following embodiments do not limit the invention as defined in the claims. In addition, the entire combination of features described in the embodiments is not essential to the solution provided by the invention.

[0037] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, region, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions "upper" and "lower" are not limited to the direction of gravity or the mounting direction when the semiconductor device is mounted on a wiring substrate, etc.

[0038] In this specification, technical matters are sometimes described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, the X-axis, Y-axis, and Z-axis form a right-hand system. In this specification, a plane parallel to the upper surface or the lower surface of the semiconductor substrate is defined as an XY plane, and a depth direction of the semiconductor substrate perpendicular to the upper surface or the lower surface of the semiconductor substrate is defined as a Z axis.

[0039] In this specification, the first conductivity type is P type and the second conductivity type is N type, but the first conductivity type may be N type and the second conductivity type may be P type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are changed to opposite conductivity types. In addition, in this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than that of P type or N type.

[0040] In this specification, doping concentration refers to the concentration of donor- or acceptor-type impurities. In this specification, the difference between the concentrations of donors and acceptors is sometimes referred to as net doping concentration or simply as doping concentration. In addition, the peak value of the doping concentration distribution is sometimes referred to as doping concentration.

[0041] Figure 1 is a top view of the semiconductor device 200 according to the first embodiment. Figure 1 2 is a diagram showing the upper surface side of the semiconductor substrate 10 in the semiconductor device 200 viewed parallel to the Z axis. Figure 1 In order to facilitate understanding of the arrangement relationship of each region, components such as the emitter, the gate metal layer, and the passivation film are omitted. It should be noted that in this specification, the semiconductor substrate 10 is sometimes referred to as a chip.

[0042] The semiconductor device 200 has a semiconductor substrate 10. The semiconductor substrate 10 may have a rectangular shape. One side of the rectangular shape may be several mm to more than ten mm. For example, the semiconductor substrate 10 may be in the shape of a square of 10 mm×10 mm. The semiconductor substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a nitride semiconductor substrate such as gallium nitride (GaN). The semiconductor substrate 10 in the present embodiment is a silicon substrate. When a silicon substrate is used, the N-type dopant may be one or more elements of phosphorus (P) and arsenic (As), and the P-type dopant may be one or more elements of boron (B) and aluminum (Al).

[0043] The semiconductor device 200 includes an active region 100, a pad region 110, a gate runner region 130, and an edge termination region 140. The active region 100 may include a plurality of transistor regions where current flows between the upper surface and the lower surface of the semiconductor substrate 10 when a transistor (e.g., an IGBT) provided on the semiconductor device 200 is turned on, and a plurality of diode regions where current flows between the upper surface and the lower surface of the semiconductor substrate 10 in a direction opposite to the transistor. It should be noted that the active region 100 may be a region where an emitter is provided when viewed from above. The active region 100 of the present embodiment is surrounded by the gate runner region 130 when viewed from above, and is a region other than the pad region 110 in a region provided inside the gate runner region 130.

[0044] The semiconductor device 200 of the present embodiment is an RC-IGBT. The semiconductor device 200 of the present embodiment has an IGBT region 70 and a FWD (Free Wheeling Diode) region 80 in an active region 100 of a semiconductor substrate 10. The IGBT region 70 is an example of a transistor region, and the FWD region 80 is an example of a diode region. In the present embodiment, the IGBT region 70 and the FWD region 80 are alternately arranged in the X-axis direction. In the present embodiment, the arrangement direction of the IGBT region 70 and the FWD region 80 is parallel to the X-axis direction. In addition, when viewed from above, the IGBT region 70 is provided at both ends of the active region 100 in the X-axis direction.

[0045] In the present embodiment, for the sake of convenience, the IGBT region 70 located closest to the positive side of the X-axis is set as the IGBT region 70-1. As the IGBT region 70-1 moves toward the negative direction of the X-axis, the IGBT regions 70-2, 70-3, and 70-4 are set. Similarly, for the sake of convenience, the FWD region 80 located closest to the positive side of the X-axis is set as the FWD region 80-1, and as the FWD region 80-1 moves toward the negative direction of the X-axis, the FWD regions 80-2 and 80-3 are set. However, the number of IGBT regions 70 and FWD regions 80 in the present embodiment is an example. The number of IGBT regions 70 and FWD regions 80 may be less or more than the number shown in the present embodiment. The length of the IGBT region 70 in the X-axis direction may be greater than 500 μm and less than 1500 μm. In contrast, the length of the FWD region 80 in the X-axis direction may be greater than 100 μm and less than 600 μm.

[0046] The active region 100 has four edges 102, 104, 106 and 108. In the present embodiment, the edge 102 is opposite to the edge 104 in the Y-axis direction, and the edge 106 is opposite to the edge 108 in the X-axis direction. The IGBT region 70 and the FWD region 80 can extend along the Y-axis direction. Each IGBT region 70 and each FWD region 80 can extend from the edge 102 in the positive direction of the Y-axis of the active region 100 to the edge 104 in the negative direction of the Y-axis. In the present embodiment, the extension direction of the IGBT region 70 and the FWD region 80 is parallel to the Y-axis direction. In the present embodiment, the extension direction (Y-axis direction) is orthogonal to the arrangement direction (X-axis direction).

[0047] The pad region 110 of the present embodiment is a region formed by cutting off a portion of the active region 100. The pad region 110 of the present embodiment is not included in the active region 100. The pad region 110 of the present embodiment includes a P+ type pad well region 112, a polysilicon layer 120, a gate pad 116, and a gate resistance measurement pad 118. The gate pad 116 and the gate resistance measurement pad 118 may be metal layers formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper (Cu) alloy.

[0048] The pad well region 112 may be set to a wider range than the polysilicon layer 120, the gate pad 116, and the gate resistance measurement pad 118. The pad well region 112 of the present embodiment includes a pad well region 112-1 with the gate pad 116 disposed thereon, and a pad well region 112-2 with the gate resistance measurement pad 118 disposed thereon. The pad well region 112-1 and the pad well region 112-2 each have a rectangular shape that is longer in the X-axis direction than in the Y-axis direction. Therefore, the pad well region 112-1 and the pad well region 112-2 of the present embodiment have a convex shape that protrudes in the negative direction of the Y-axis when viewed from above.

[0049] The pad well region 112 may be provided on the upper surface side of the semiconductor substrate 10. The pad well region 112 of the present embodiment is provided from the upper surface of the semiconductor substrate 10 to a predetermined depth position. The bottom of the pad well region 112 may be deeper than the groove portion described later. The pad well region 112 of the present embodiment is in contact with the gate flow channel region 130 and is provided inside the gate flow channel region 130.

[0050] The length of the pad well region 112-1 in the X-axis direction may be greater than 1000 μm and less than 1800 μm. The pad well region 112-2 may be located within the range of the pad well region 112-1 in the X-axis direction. In addition, the length of the pad well region 112 in the Y-axis direction formed by combining the pad well region 112-1 and the pad well region 112-2 may be greater than 900 μm and less than 1500 μm. In the present embodiment, the pad well region 112-1 and the pad well region 112-2 are in contact with each other in the Y-axis direction. In addition, the pad well region 112-1 is provided between the pad well region 112-2 and the gate flow channel region 130.

[0051] The pad well region 112 may be in contact with one end edge 102 of the active region 100. Furthermore, the pad well region 112 may be provided near the center of the end edge 102 in the X-axis direction. Thus, the gate pad 116 and the gate resistance measurement pad 118 may also be provided near the center of one side of the gate flow channel region 130. Therefore, compared with the case where the gate pad 116 and the like are arranged at the four corners of the active region 100, the setting conditions when the gate wire is provided on the gate pad 116 can be relaxed. Thus, the semiconductor device 200 can be applied to more types of semiconductor packages, and the semiconductor device 200 can be made into a more versatile semiconductor device.

[0052] The pad well region 112 has a function of reducing the influence of the polysilicon layer 120, the gate pad 116, and the gate resistance measurement pad 118, which are respectively provided above the pad well region 112, on the base region and the drift region in the IGBT region 70 and the FWD region 80. The pad well region 112 and the polysilicon layer 120 can be electrically insulated by an insulating film provided therebetween.

[0053] The polysilicon layer 120 of this embodiment includes a first region 122 located below the gate pad 116, a third region 126 located below the gate resistance measurement pad 118, and a second region 124 that bridges the first region 122 and the third region 126. An interlayer insulating film may be provided on the polysilicon layer 120. The gate pad 116 and the first region 122 may be electrically connected through an opening of the interlayer insulating film. The gate resistance measurement pad 118 and the third region 126 may be electrically connected through another opening of the interlayer insulating film. The second region 124 may be entirely covered with an interlayer insulating film.

[0054] The second region 124 of the polysilicon layer 120 is located between the gate resistance measurement pad 118 and the gate conductive portion of the IGBT region 70 in the circuit. The second region 124 can be regarded as an additional gate resistor (Rg) for the IGBT region 70.

[0055] IGBTs sometimes use multiple chips in parallel. When multiple chips are used in parallel, the gates of each chip are also connected in parallel. At this time, there is a problem that the exchange of current between the gates of the chips causes oscillation of the gate voltage, resulting in chip damage. Therefore, by building an additional gate resistor (Rg) into each IGBT chip, the current exchange between the gates when connected in parallel is suppressed, and the effect of not easily causing gate voltage oscillation is highly expected. It should be noted that the gate can be regarded as equivalent to the gate conductive portion or the gate flow channel portion 134 described later.

[0056] The gate pad 116 and the gate resistance measurement pad 118 can be used to measure the additional gate resistance (Rg). For example, a test pin for current measurement and a test pin for voltage measurement are respectively contacted with the gate pad 116 and the gate resistance measurement pad 118, so that the additional gate resistance (Rg) is measured by measuring the voltage drop when a certain constant current flows between the gate pad 116 and the gate resistance measurement pad 118.

[0057] In this embodiment, the value of Rg is predetermined by the width of the second region 124 in the X-axis direction. The greater the width of the second region 124 in the X-axis direction, the smaller the value of Rg, or the smaller the width of the second region 124 in the X-axis direction, the larger the value of Rg.

[0058] The gate pad 116 may be electrically connected to the gate runner portion 134 of the gate runner region 130. A gate signal may be provided to the gate pad 116 from the outside of the semiconductor device 200 through a gate wire. The gate pad 116 may be electrically connected to the gate runner portion 134 through a gate metal layer. The gate pad 116 may be a metal layer formed in the same process as the gate metal layer.

[0059] The gate flow channel region 130 may be a rectangular ring region with four sides when viewed from above. The gate flow channel region 130 of this embodiment has four straight sides and four corners, and the four corners have curvature. The gate flow channel region 130 may be provided between the active region 100 and the edge termination region 140. The gate flow channel region 130 may include a P+ type well region, i.e., a gate flow channel well region 132, and a conductive gate flow channel portion 134.

[0060] The gate channel well region 132 may have a width wider than the gate channel portion 134. The gate channel portion 134 may be provided on the gate channel well region 132 within the width of the gate channel well region 132. The gate channel portion 134 may transmit a gate signal provided from the outside through the gate pad 116 to the gate conductive portion of the IGBT region 70. The gate channel portion 134 may be electrically connected to the gate conductive portion of the IGBT region 70 on each side in contact with the end edge 102 and the end edge 104. The gate channel portion 134 may have a stacked structure of a gate metal layer and a polysilicon layer. However, in Figure 1 In FIG. 1 , for ease of understanding, the gate metal layer is omitted and the outer shape of the polysilicon layer in the gate channel portion 134 is shown.

[0061] The gate metal layer of the gate flow channel portion 134 may be a metal layer formed of the same material as the gate pad 116 and the gate resistance measurement pad 118. The gate metal layer may be provided on the polysilicon layer in the gate flow channel portion 134. The gate metal layer of the gate flow channel portion 134 may be connected to the polysilicon layer through a predetermined contact portion (e.g., an opening portion of an interlayer insulating film).

[0062] The polysilicon layer of the gate flow channel portion 134 may be a polysilicon layer doped with impurities such as phosphorus. An insulating film may be provided between the polysilicon layer of the gate flow channel portion 134 and the upper surface of the semiconductor substrate 10. The gate flow channel portion 134 may be electrically separated from the semiconductor substrate 10 by the insulating film at a portion other than the portion connected to the gate trench portion.

[0063] The gate runner region 130 of this embodiment does not cross the active region 100, but only surrounds the periphery of the active region 100. Therefore, the length of contact between the active region 100 and the gate runner well region 132 can be reduced compared to the case where the gate runner region 130 crosses the active region 100. This is advantageous in reducing reverse recovery damage of the FWD region 80 as described later.

[0064] The edge termination region 140 may be provided between the active region 100 and the outer peripheral end of the semiconductor substrate 10 in a plan view. The edge termination region 140 may be configured to surround the active region 100 and the gate runner region 130 on the upper surface of the semiconductor substrate 10. The edge termination region 140 of the present embodiment is configured in a rectangular ring shape along the outer peripheral end of the semiconductor substrate 10. The edge termination region 140 may have a function of alleviating electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination region 140 has, for example, any one of a guard ring, a field plate, and a surface electric field reduction structure, or a structure in which two or more of these structures are combined.

[0065] Figure 2 The figure shows the range where the collector region 22 and the cathode region 82 are provided in the semiconductor device 200. In addition, in the gate flow channel region 130, the gate flow channel portion 134 is omitted and the gate flow channel well region 132 is shown.

[0066] The IGBT region 70 of the present embodiment has a P+ type collector region 22 provided on the lower surface side of the semiconductor substrate 10. The so-called lower surface side refers to, for example, a position lower than half of the semiconductor substrate 10. The range in which the collector region 22 is provided in the active region 100 is shaded. However, the collector region 22 may also be provided on the entire lower surface of the semiconductor substrate 10 outside the active region 100.

[0067] The IGBT region 70 of the present embodiment is a region that is located in the active region 100 and includes transistors such as a MOS gate structure. In addition, the IGBT region 70 is a region where the collector region 22 is provided on the lower surface side of the semiconductor substrate 10. In the IGBT region 70, a unit structure including an N+ type emitter region and a P+ type contact region can be periodically provided on the upper surface of the semiconductor substrate 10. For example, in the IGBT region 70, the emitter region and the contact region are alternately provided in the Y-axis direction.

[0068] In the present embodiment, the IGBT region 70 may be a region where transistors such as a MOS gate structure are periodically repeated on the upper surface side of the semiconductor substrate 10. In addition, in a structure where the IGBT region 70 and the FWD region 80 are alternately arranged in the X-axis direction, the IGBT region 70 may be a region where the collector region 22 is provided on the lower surface side of the semiconductor substrate 10.

[0069] The FWD region 80 of this embodiment includes an N+ type cathode region 82 provided on the lower surface side of the semiconductor substrate 10. The area in the active region 100 where the cathode region 82 is provided is shaded differently from the collector region 22. Figure 2 In the figure, the dashed line indicates the boundary 72 between the IGBT region 70 and the FWD region 80, which does not overlap with the shadow indicating the range of the cathode region 82. It should be noted that within the range of the FWD region 80, in the region on the lower surface side outside the range of the cathode region 82, the collector region 22 is provided in the same manner as the IGBT region 70.

[0070] The FWD region 80 of the present embodiment is a region that is located in the active region 100 and includes a diode such as a freewheel diode (FWD). In addition, the FWD region 80 is a region in which an N+ type cathode region 82 is provided on the lower surface side of the semiconductor substrate 10. However, the end 84 of the cathode region 82 in the Y-axis direction is near the gate flow channel region 130 and can be located inside the active region 100 in the Y-axis direction. In the present embodiment, the ends 84-b and 84-e of the cathode region 82 in the Y-axis direction are near the gate flow channel region 130 and retreat along the Y-axis direction.

[0071] Each end portion 84-b and 84-e may be retreated from the gate flow channel region 130 by more than the depth of the gate flow channel well region 132, preferably more than the thickness of the semiconductor substrate 10. For example, each end portion 84-b and 84-e may be retreated by about 100 μm from the edge 102 and the edge 104. As described above, the collector region 22 is provided in the region where the cathode region 82 is retreated in the FWD region 80.

[0072] However, in the present embodiment, no transistor such as a MOS gate structure is provided above the region where the cathode region 82 has retreated. Therefore, in the present specification, even when the ends 84-b and 84-e of the cathode region 82 in the Y-axis direction are located inside the active region 100, the entire length of the active region 100 in the Y-axis direction is regarded as the FWD region 80. That is, in the present specification, the FWD region 80 is continuous from the edge 102 to the edge 104.

[0073] In addition, the end 84 of the cathode region in the X-axis direction may be partially retreated from the boundary 72 between the IGBT region 70 and the FWD region 80. In the present embodiment, the end 84 of a portion of the cathode region 82 in the X-axis direction, i.e., the end 84-a, is located closer to the FWD region 80 than the boundary 72 between the IGBT region 70 and the FWD region 80. It should be noted that the end 84-a is an example of a retreated end. In the present embodiment, the end 84-a is retreated from the boundary 72 to the inner side of the FWD region 80 by a length L. d The end 84 in the Y-axis direction formed by the retreat of the end 84-a is set as the end 84-b1, and the remaining end 84-b is set as the end 84-b2. In the present embodiment, the ends 84-a, 84-b1 and 84-b2 are provided in the FWD region 80-1 and the FWD region 80-3 located on the left and right of the pad region 110. In the FWD region 80-1 and the FWD region 80-3, the Y-axis length of the retreated end 84-a can be smaller than the Y-axis length of the non-retreating end 84-c.

[0074] In the present embodiment, the FWD region 80 may be a region where a diode such as a freewheeling diode is provided on the upper surface side of the semiconductor substrate 10. In addition, in a structure where the IGBT region 70 and the FWD region 80 are alternately arranged in the X-axis direction, the FWD region 80 may be a region where a cathode region 82 is provided on the lower surface side of the semiconductor substrate 10.

[0075] In addition, a boundary region for preventing mutual interference may also be provided between the IGBT region 70 and the FWD region 80. For example, the boundary region may have a device structure that is different from the device structure of the IGBT region 70 and the device structure of diodes such as the freewheeling diode of the FWD region 80. The length of the boundary region in the X-axis direction may be greater than 10 μm and less than 100 μm, or may be greater than 50 μm and less than 100 μm. In addition, the boundary region may have a plurality of mesa portions. More preferably, the boundary region has more than four and less than ten mesa portions. The width of a mesa portion in the X-axis direction may be approximately 10 μm.

[0076] The pad well region 112 may have a plurality of ends 113 located at the ends in the X-axis direction and extending in the Y-axis direction. In this embodiment, the pad well region 112-1 has an end 113-1 and an end 113-2. In addition, the pad well region 112-2 has an end 113-3 and an end 113-4.

[0077] The pad well region 112 may be in contact with two IGBT regions 70 and one FWD region 80 located between the two IGBT regions 70. The pad well region 112 of this embodiment is in contact with the IGBT region 70-2, the IGBT region 70-3, and the FWD region 80-2. In this embodiment, the end portion 113-1 and the end portion 113-3 are in contact with the IGBT region 70-3. Similarly, the end portions 113-2 and 113-4 are in contact with the IGBT region 70-2.

[0078] It should be noted that the end portion 113-1 is an example of a first end portion of the pad well region 112, and the IGBT region 70-3 is an example of a first transistor region. Similarly, the end portion 113-2 is an example of a second end portion of the pad well region 112, and the IGBT region 70-2 is an example of a second transistor region provided at a position different from the first transistor region. Since the pad well region 112-1 has a wider width than the pad well region 112-2, the end portions 113-1 and 113-2 protrude in the X-axis direction compared to the end portions 113-3 and 113-4.

[0079] The X-axis direction end 113 of the pad well region 112 may contact the IGBT region 70. Since the collector region 22 is provided on the lower surface side of the IGBT region 70, the collector region 22 may be located below the ends 113-1, 113-2, 113-3, and 113-4 of the pad well region 112.

[0080] In the present embodiment, the FWD region 80-1 and the FWD region 80-3 are not in contact with the pad well region 112. The FWD region 80-1 and the FWD region 80-3 are provided on the side opposite to the pad well region 112 in the X-axis direction with respect to the IGBT regions 70-2 and 70-3 in contact with the pad well region 112. Each end 84-a is opposite to the end 113 of the pad well region 112 in the X-axis direction and extends in the Y-axis direction. The end 84-a of the FWD region 80-1 is located on the side opposite to the end 113 of the pad well region 112 with respect to the boundary 72 between the IGBT region 70-2 and the FWD region 80-1, and the end 84-a of the FWD region 80-3 is located on the side opposite to the end 113 of the pad well region 112 with respect to the boundary 72 between the IGBT region 70-3 and the FWD region 80-3.

[0081] The cathode region 82 of the present embodiment includes a pair of ends 84 in the Y-axis direction (a group of ends 84-b1 and 84-b2 and an end 84-e), and a pair of ends 84 in the X-axis direction (a group of ends 84-c and an end 84-d). However, the cathode region 82 of the FWD region 80-2 that contacts the pad region 110 in the Y-axis direction includes a pair of ends 84-c1 and 84-c2 in the X-axis direction. In the present embodiment, the end 84-b1 of the cathode region 82 of the FWD region 80-1 and the end 84-b1 of the cathode region 82 of the FWD region 80-3 are arranged at the same position in the Y-axis direction. In addition, the end 84-b2 of the cathode region 82 of the FWD region 80-1, the end 84-b2 of the cathode region 82 of the FWD region 80-2, and the end 84-b2 of the cathode region 82 of the FWD region 80-3 are all arranged at the same position in the Y-axis direction. Likewise, each end portion 84 - e of the cathode region 82 in the FWD region 80 - 1 , the FWD region 80 - 2 , and the FWD region 80 - 3 is provided at the same position in the Y-axis direction.

[0082] During the period when the gate conductive portion of the IGBT region 70 of the RC-IGBT in another chip set as the opposing arm of the chip is applied with an on-voltage (i.e., the IGBT region 70 of the opposing arm is in the on-state), no current flows in the FWD region 80 of the chip. However, during the period when the IGBT region 70 of the RC-IGBT in another chip is in the off-state, current can flow in the FWD region 80 of the chip. For example, a return current flows from the emitter to the collector in the FWD region 80 of the chip. Then, a reverse recovery current flows from the collector to the emitter (i.e., the direction of flow of the return current becomes opposite). Further, the return current then decreases to gradually approach zero.

[0083] In the vicinity of the pad well region 112, carriers (in this example, holes) can be accumulated due to the return current of the FWD region 80. When the reverse recovery current flows, the holes accumulated in the vicinity of the pad well region 112 flow from the pad well region 112 to the FWD region 80. As a result, holes are particularly concentrated in the FWD region 80 located near the pad well region 112, and electric field concentration is easily generated. Therefore, reverse recovery damage that damages the FWD region 80 near the pad well region 112 may occur during reverse recovery.

[0084] Therefore, in the present embodiment, as described above, the collector region 22 is provided below the end 113 of the pad well region 112. That is, the pad well region 112 is separated from the FWD region by at least the width in the X-axis direction of the IGBT region 70. Thus, compared with the case where the end 113 of the pad well region 112 is in contact with the FWD region 80, the electric field concentration in the FWD region 80 can be reduced, and the risk of reverse recovery destruction in the FWD region 80 can be reduced.

[0085] In addition, in the present embodiment, the cathode region 82 is separated from the pad well region 112 by a distance greater than the width of the IGBT region 70 in the X-axis direction. In the present embodiment, the end 84-a of the cathode region 82 in the FWD region 80-1 is set back from the boundary 72 in the X-axis direction toward the FWD region 80-1 by a length L. d Similarly, the end 84 - a of the cathode region 82 in the FWD region 80 - 3 is also retreated from the boundary 72 in the X-axis direction toward the FWD region 80 - 3 by a length L. d Thus, compared to the case where the end 84 - a is set at the same position in the X-axis direction as the end 84 - c, the electric field concentration at the end 84 on the pad region 110 side of the FWD region 80 can be further reduced, further reducing the risk of reverse recovery damage in the FWD region 80 .

[0086] The end 84-a may be separated from the end 113 of the pad well region 112 by more than the thickness of the semiconductor substrate 10. The end 84-a may be separated from the end 113-1 by more than the thickness of the semiconductor substrate 10. Similarly, the end 84-a may be separated from the end 113-3 by more than the thickness of the semiconductor substrate 10. The separation distance between the end 84-a and the end 113-2 and the separation distance between the end 84-a and the end 113-4 may be more than the thickness of the semiconductor substrate 10. The end 84-a may be separated from the boundary 72 by more than 90 μm and less than 110 μm, and the boundary 72 exists at the same position in the X-axis direction as the end 84-c that does not retreat. For example, the end 84-a is separated from the boundary 72 by 100 μm. In this way, by retreating the end 84-a, the risk of reverse recovery destruction in the FWD region 80 can be further reduced, and the excessive reduction in the area of ​​the cathode region 82 can be suppressed.

[0087] Figure 3 2 is a diagram showing the range in which the lifetime control body region 26 and the cathode region 82 are provided in the semiconductor device 200. Figure 3In the figure, the lifetime control body region 26 is shaded, and the range of the cathode region 82 is indicated by a dotted line. It should be noted that, for ease of understanding, the gate pad 116 and the like are partially omitted, and the cathode region 82 is disposed at a position lower than the gate pad 116 and the like. The semiconductor substrate 10 may include the lifetime control body region 26 between the collector region 22 and the cathode region 82 and the upper surface of the semiconductor substrate 10. The lifetime control body region 26 may be disposed at a position closer to the upper surface side than the center position of the upper surface and the lower surface of the semiconductor substrate 10.

[0088] The lifetime control region 26 may have point defects (holes, double holes, dangling bonds, etc.) formed in the semiconductor substrate 10 by introducing impurities such as helium (He). In addition, the lifetime control region 26 may have the impurities themselves introduced to form point defects. The lifetime control region 26 may have a recombination center of carriers formed by at least any one of the point defects and impurities in the semiconductor substrate 10.

[0089] The lifetime control body region 26 can be provided corresponding to the FWD region 80. The lifetime control body region 26 of the present embodiment is provided at least in the entire FWD region 80 when viewed from above. Therefore, the lifetime control body region 26 is also provided above the end 84-a of the cathode region 82. By providing the lifetime control body region 26, the number of holes reaching the FWD region 80 can be reduced during reverse recovery. Thus, the reverse recovery damage of the FWD region 80 can be further reduced.

[0090] The semiconductor substrate 10 may include a lifetime control body region 26 at a predetermined position from the edge 102 and 104 to the gate runner well region 132 in a plan view. The lifetime control body region 26 of the present embodiment is provided to the center of the gate runner well region 132 in the Y-axis direction, beyond the FWD region 80 and even the end of the gate runner well region 132 in the Y-axis direction that contacts the FWD region 80 in a plan view. Thus, the number of holes that reach the FWD region 80 from the gate runner well region 132 during reverse recovery can be further reduced.

[0091] In addition, the lifetime control body region 26 of the present embodiment is provided in addition to the FWD region 80-2 in a plan view, and is also provided from the end of the pad well region 112-2 in the Y-axis direction that contacts the FWD region 80-2 to the pad well region 112-1. Thus, the number of holes that reach the FWD region 80-2 from the pad well region 112 during reverse recovery can be further reduced.

[0092] In other embodiments, the concentration of recombination centers in the lifetime control body region 26 in the region overlapping the gate runner well region 132 and the pad well region 112 may be higher than the concentration of recombination centers in the FWD region 80. Figure 3 After helium is introduced into the lifetime control body region 26 shown in the figure, helium is further additionally introduced only into the region overlapping with the gate channel well region 132 and the pad well region 112. In this way, by multi-stage injection of helium into a partial region, the concentration of the recombination center in the partial region can be increased. Thus, the number of holes reaching the FWD region 80 during reverse recovery can be further reduced.

[0093] Figure 4 yes Figure 3 AA cross-sectional view. The AA cross-sectional view passes through the pad region 110, the IGBT region 70-2 and the FWD region 80-1, and is parallel to the XZ plane. The semiconductor substrate 10 has an upper surface 62 and a lower surface 64. The semiconductor substrate 10 of the present embodiment includes a pad well region 112-1, an N+ type emitter region 12, a P- type base region 14, an N-type accumulation region 16, an N- type drift region 18, a dummy groove portion 30, a gate groove portion 40, a lifetime control body region 26, an N-type field stop region (hereinafter referred to as FS region 20), a P+ type collector region 22 and an N+ type cathode region 82.

[0094] In the AA cross section, the pad region 110 has an insulating film 36 on the upper surface 62 and a polysilicon layer 120 on the insulating film 36. The polysilicon layer 120 can be formed in the same manner as the polysilicon layer of the gate flow channel portion 134. The insulating film 36 can be silicon dioxide (SiO2) formed by thermally oxidizing a silicon substrate. The polysilicon layer 120 can be electrically connected to the gate pad 116 through the opening 54 of the interlayer insulating film 38. In the opening 54, a plug 56 formed of tungsten (W) or the like can be provided. The interlayer insulating film 36 can be formed of one or more materials selected from silicon dioxide, BPSG (Boro-Phospho Silicate Glass), PSG (Phosphorus Silicate Glass) and BSG (Borosilicate Glass).

[0095] In the AA cross section, the IGBT region 70-2 has an emitter region 12, a base region 14, an accumulation region 16, and a drift region 18 in order from the upper surface 62. The dummy trench portion 30 and the gate trench portion 40 are arranged at a predetermined interval in the X-axis direction. The dummy trench portion 30 and the gate trench portion 40 penetrate the base region 14 and the accumulation region 16 and reach the drift region 18. In this specification, the dummy trench portion 30 and the gate trench portion 40 are sometimes collectively referred to as a trench portion.

[0096] The dummy groove portion 30 includes a dummy groove 32, a dummy groove insulating film 33, and a dummy groove conductive portion 34. The dummy groove 32 can be formed by etching the semiconductor substrate 10 from the upper surface 62 to a predetermined depth. The dummy groove insulating film 33 can be provided in contact with the inner wall of the dummy groove 32. The dummy groove insulating film 33 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the dummy groove 32. The dummy groove conductive portion 34 can be in contact with the dummy groove insulating film 33 and be provided at a position closer to the inside than the dummy groove insulating film 33. The dummy groove insulating film 33 can insulate the dummy groove conductive portion 34 from the semiconductor substrate 10. In the present embodiment, the dummy groove insulating film 33 is silicon dioxide formed by thermal oxidation, and the dummy groove conductive portion 34 is a conductive material such as polysilicon.

[0097] The gate trench portion 40 includes a gate trench 42, a gate insulating film 43, and a gate conductive portion 44. The gate trench 42, the gate insulating film 43, and the gate conductive portion 44 can be formed by the same method as the dummy trench 32, the dummy trench insulating film 33, and the dummy trench conductive portion 34. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel can be formed in a region near the interface in contact with the gate trench 42 in the base region 14. As a result, the IGBT region 70 becomes conductive.

[0098] The accumulation region 16 may be located between the base region 14 and the bottom of the groove portion in the depth direction. The accumulation region 16 may have a function of temporarily accumulating holes introduced from the collector region 22 to the upper surface 62. Thus, since the carrier injection enhancement effect (IE effect) can be improved, the on-voltage (V) in the IGBT region 70 can be reduced compared to the case where the accumulation region 16 is not provided. on ).

[0099] The interlayer insulating film 38 may be provided on the upper surface 62. The interlayer insulating film 38 may have a plurality of openings 52 on the upper surface 62 in the active region 100. The plurality of openings 52 may extend in the Y-axis direction, respectively, and may be separated from each other in the X-axis direction. The emitter 50 may be electrically connected to the emitter region 12 (and the P+ type contact region 15 described below) through the opening 52. The material of the emitter 50 may be the same as that of the above-mentioned gate metal layer. The emitter 50 may have a barrier metal formed of titanium (Ti) or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. In addition, a plug formed of tungsten, etc. may be provided in the opening 52. It should be noted that the opening 52 of the interlayer insulating film 38 is an example of a contact portion.

[0100] In the AA cross section, the IGBT region 70-2 has the collector region 22 and the FS region 20 in order from the lower surface 64. The FS region 20 may be located between the drift region 18 and the collector region 22. The FS region 20 has a function of preventing the depletion layer extending from the bottom of the base region 14 to the lower surface 64 from reaching the collector region 22 when the semiconductor device 200 is turned off. The FS region 20 may have one or more peaks of the N-type doping concentration distribution in the Z-axis direction.

[0101] In the AA cross section, the FWD region 80-1 has the base region 14, the accumulation region 16, and the drift region 18 in order from the upper surface 62. In the FWD region 80-1, the gate trench portion 40 is not formed. In the FWD region 80-1, the dummy trench portions 30 are provided at predetermined intervals in the X-axis direction. In addition, as described above, the FWD region 80-1 includes the lifetime control body region 26 that reaches the boundary 72 between the IGBT region 70-2 and the FWD region 80-1 in the X-axis direction.

[0102] In the AA cross section, the FWD region 80-1 includes the cathode region 82, the collector region 22, and the FS region 20 in order from the lower surface 64. As described above, in this embodiment, the end 84-a of the cathode region 82 is set back from the boundary 72 by a length L. d The semiconductor device 200 includes a collector electrode 24 in contact with the lower surface 64. The collector electrode 24 may be in contact with the entire lower surface 64 of the semiconductor substrate 10. The collector electrode 24 may be formed of the same conductive material as the emitter, such as metal.

[0103] Figure 5 yes Figure 3BB cross-sectional view. The BB cross-sectional view passes through the IGBT region 70-2 and the FWD region 80-1 and is parallel to the XZ plane. The BB cross-sectional view passes through the emitter regions 12 and the contact regions 15 alternately arranged in the Y-axis direction in the IGBT region 70. In the BB cross-sectional view, the position of the end 84-c of the cathode region 82 coincides with the position of the boundary 72 in the X-axis direction.

[0104] Figure 6 yes Figure 3 The CC cross section passes through the opening 52 of the FWD region 80-3, the gate flow channel region 130, and the edge terminal region 140, and is parallel to the YZ plane. In particular, the CC cross section passes through the end 84-b1 of the cathode region 82 of the FWD region 80-3 (refer to Figure 2 The gate flow channel region 130 has a gate flow channel well region 132 provided to a predetermined depth position from the upper surface 62. In the present embodiment, the depth from the upper surface 62 to the bottom of the gate flow channel well region 132 is set to D pw In addition, the thickness from the upper surface 62 to the lower surface 64 of the semiconductor substrate 10 is denoted as T sub .

[0105] The gate flow channel region 130 includes an insulating film 36, a gate flow channel portion 134, and an interlayer insulating film 38. The gate flow channel portion 134 of the present embodiment includes a polysilicon layer 136 and a gate metal layer 138 provided with the interlayer insulating film 38 interposed therebetween. The polysilicon layer 136 can be formed by the same method as the polysilicon layer 120 in the pad region 110. The gate metal layer 138 can be formed by the same method as the gate pad 116 and the gate resistance measurement pad 118 in the pad region 110.

[0106] The polysilicon layer 136 and the gate metal layer 138 can be electrically connected through the opening 58 of the interlayer insulating film 38. The above-mentioned plug can be provided in the opening 58. Since the CC cross section passes through the FWD region 80-3, the gate groove portion 40 is not shown. In the case where the cross section parallel to the CC cross section passes through the gate groove portion 40 of the IGBT region 70, the gate metal layer 138 can be electrically connected to the gate conductive portion 44.

[0107] The gate flow channel well region 132 has an end 133 that contacts the FWD region 80 in the Y-axis direction. In the present embodiment, the end 133 is set as the boundary between the active region 100 and the gate flow channel region 130. When the end 133 of the gate flow channel well region 132 and the end 84-b1 of the cathode region 82 that are opposite to each other in the Y-axis direction are virtually projected onto the upper surface 62 of the semiconductor substrate 10, the shortest distance between the end 133 and the end 84-b1 is set as the first distance L1. It should be noted that in the CC cross section, the state of virtual projection through the extension line (dashed line) parallel to the Z-axis direction is shown.

[0108] In this embodiment, the end 84-b1 of the cathode region 82 is set back inwardly compared to the end 133 of the gate channel well region 132. Therefore, compared to the case where the Y-axis position of the end 84-b1 coincides with the end 133, the effective area of ​​the FWD region 80-3 operating as the FWD is reduced. The shortest distance between the end 133 and the end 84-b1, i.e., the first distance L1, may be greater than the depth D pw Thus, the number of holes introduced from the base region 14 to the drift region 18 can be reduced in accordance with the reduction in the effective area of ​​the FWD region 80-3 that works as the FWD when the return current flows. It should be noted that in the FWD region 80, the base region 14 works as the anode of the FWD. Therefore, the number of holes accumulated near the gate flow channel well region 132 can also be reduced.

[0109] In addition, in the present embodiment, the shortest distance between the end 133 of the gate channel well region 132 and the end 53 of at least one opening 52 is set to the second distance L2. When the end 133 and the end 53 facing each other in the Y-axis direction are virtually projected onto the upper surface 62 of the semiconductor substrate 10, the first distance L1 may be greater than the second distance L2.

[0110] However, if the first distance L1 is too large, the conduction loss in the FWD region 80 becomes large. Therefore, the first distance L1 may be smaller than the thickness T sub As a result, the number of holes accumulated in the vicinity of the gate runner well region 132 is also reduced, and the conduction loss in the FWD region 80 can be reduced by suppressing an excessive reduction in the area of ​​the cathode region 82 .

[0111] The holes accumulated near the gate channel well region 132 tend to concentrate near the end 53 of the opening 52 during reverse recovery. The distance L2 can be greater than 40% and less than 60% of the distance L1. For example, the distance L2 can be greater than 10 μm and less than 20 μm. In this way, by sufficiently setting the distance between the end 133 and the end 53, it is possible to suppress the injection of excessive carriers from the vicinity of the gate channel well region 132 compared to the case where the distance L2 = 0. In addition, since the electric field concentration near the end 53 of the opening 52 can be reduced, the destructive resistance of the semiconductor device 200 during reverse recovery action can be improved.

[0112] In this embodiment, the edge termination region 140 has a P+ type guard ring 142 and a metal layer 146 connected to the guard ring 142 through an opening 144 of the interlayer insulating film 38. The metal layer 146 can work as a field plate. The guard ring 142 and the metal layer 146 can be arranged in a rectangular ring shape similarly to the gate runner region 130.

[0113] Figure 7 1 is a top view of a semiconductor device 800 of a comparative example. The semiconductor device 800 has five IGBT regions 70 (70-1 to 70-5) and four FWD regions 80 (80-1 to 80-4). In addition, the pad well region 112 contacts the IGBT region 70-3 in the Y-axis direction. The end 113-1 of the pad well region 112-1 contacts the FWD region 80-3, and the end 113-2 contacts the FWD region 80-2. This is mainly different from the first embodiment.

[0114] Figure 8 yes Figure 7 DD cross-sectional view. The DD cross-sectional view passes through the pad region 110, the FWD region 80-2, and the IGBT region 70-2, and is parallel to the XZ plane. In the DD cross-sectional view, "h" represents a hole. When a return current flows from the base region 14 to the cathode region 82 in the FWD region 80, holes can be introduced into the drift region 18. In contrast, when a reverse recovery current flows from the cathode region 82 to the base region 14 in the FWD region 80, holes can be introduced into the base region 14 from the vicinity of the pad well region 112.

[0115] In this comparative example, the pad region 110 is in contact with the FWD region 80-2. Therefore, a higher electric field concentration than in the first embodiment occurs in the FWD region 80-2, and reverse recovery destruction of the FWD region 80-2 is more likely to occur.

[0116] Fig. 9 (a) and (b) are diagrams showing a semiconductor device 300 according to the second embodiment. Fig. 9 (a) and Figure 1The top view of the semiconductor device 300 is also shown. Fig. 9 (b) and Figure 2 The same shows the range where the collector region 22 and the cathode region 82 are provided in the semiconductor device 300. In the second embodiment, the pad region 110 contacts the corner of the active region 100. Accordingly, the pad well region 112 also contacts the corner of the active region 100. This is mainly different from the first embodiment.

[0117] In the first embodiment, the FWD region 80-2 is closest to the pad well region 112, and the FWD region 80-1 and the FWD region 80-3 are next closest. In the first embodiment, the distance between the FWD region 80-1 and the pad region 110 and the distance between the FWD region 80-3 and the pad region 110 are each smaller than the length (L) of one IGBT region 70 in the X-axis direction. X-IGBT ). In contrast, in the second embodiment, one FWD region 80-3 among the three FWD regions may be separated from the pad region 110 by L. X-IGBT In addition, the distance between the next closest FWD region 80 - 2 and the pad region 110 in the X-axis direction may be longer than in the first embodiment. This can further reduce the risk of reverse recovery destruction in the FWD region 80 .

[0118] The pad well region 112 of the present embodiment is in contact with the IGBT region 70-1, the IGBT region 70-2, and the FWD region 80-1. In addition, the end 84 of the cathode region in the X-axis direction provided corresponding to the FWD region 80-2 has an end 84-a as an example of a receding end. In the present embodiment, the end 84-a is also receded from the boundary 72 to the inside of the FWD region 80 by a length L. d .

[0119] In the present embodiment, the FWD region 80-2 and the FWD region 80-3 are not in contact with the pad well region 112. The FWD region 80-2 and the FWD region 80-3 are provided on the side opposite to the pad well region 112 in the X-axis direction with respect to the IGBT region 70-1 and the IGBT region 70-2 in contact with the pad well region 112. The end portion 84-a is opposite to the end portion 113 of the pad well region 112 in the X-axis direction and extends in the Y-axis direction. The end portion 84-a is located on the side opposite to the end portion 113 of the pad well region 112 with respect to the boundary 72 between the IGBT region 70-2 and the FWD region 80-1.

[0120] In addition, the end 84 - a of the cathode region 82 in the FWD region 80 - 2 may be retreated from the boundary 72 toward the FWD region 80 - 3 by a length L in the X-axis direction.d Length L d The thickness of the semiconductor substrate 10 may be greater than 90 μm. In this embodiment, the FWD region 80 - 3 and the pad region 110 may be separated by L. X-IGBT As described above, the area of ​​the cathode region 82 provided corresponding to the FWD region 80-3 can be increased compared to the first embodiment. As a result, since the area of ​​the cathode region 82 can be suppressed from being excessively reduced, the conduction loss in the FWD region 80 can be reduced compared to the first embodiment. It should be noted that the semiconductor device 300 of this embodiment can also be used in the same manner as that of the first embodiment. Figure 3 A lifetime control volume region 26 is also present.

[0121] Fig.10 (a) and (b) are diagrams showing a semiconductor device 400 according to a first modification example of the second embodiment. Fig.10 (a) and Figure 1 The top view of the semiconductor device 400 is also shown. Fig.10 (b) and Figure 2 Similarly, it shows the range where the collector region 22 and the cathode region 82 are provided in the semiconductor device 400. The position of the pad region 110 in the semiconductor device 300 and the position of the pad region 110 in the semiconductor device 400 are mirror images with respect to the Y axis. The first modification can also obtain the same advantageous effects as the second embodiment.

[0122] Fig.11 (a) and (b) are plan views of a semiconductor device 500 according to a second modification example of the second embodiment. Fig.11 The pad area 110 of (a) is Fig. 9 The pad area 110 of (a) is rotated 90 degrees clockwise on the XY plane. Fig.11 The configuration of the pad region 110 in the active region 100 is such that Fig.10 The arrangement of the pad region 110 in (a) in the active region 100 is obtained by rotating 90 degrees clockwise on the XY plane. Fig.11 (b) means Fig.11 The range of the collector region 22 and the cathode region 82 (hatched portion) in (a).

[0123] exist Fig.11 In (a), the FWD region 80-1 is closest to the pad region 110, and the FWD region 80-2 is second closest to the pad region 110. Fig.11In (a), since the pad region 110 does not exceed the FWD region 80-1 in the X-axis direction, the distance between the pad region 110 and the FWD region 80-2 can be increased compared to the second embodiment. Therefore, the damage resistance of the semiconductor device 500 during the reverse recovery operation can be further improved.

[0124] The end 84-b2 of the cathode region 82 corresponding to the FWD region 80-1 may be disposed at the same Y-axis direction position as the end 84-b1 of the cathode region 82 corresponding to the FWD region 80-2 and the FWD region 80-3, or may be disposed at the same Y-axis direction position as the end of the pad well region 112-2 in the negative direction of the Y axis, or may be disposed at a position closer to the negative direction of the Y axis than the end of the pad well region 112-2 in the negative direction of the Y axis. In the present embodiment, the end 84-b2 of the cathode region 82 is located between the end of the pad well region 112-1 in the negative direction of the Y axis and the end of the pad well region 112-2 in the negative direction of the Y axis.

[0125] Fig.12 (a) and (b) are plan views of a semiconductor device 600 according to a third modification example of the second embodiment. Fig.12 The pad area 110 of (a) is Fig.10 The pad area 110 of (a) is rotated 90 degrees counterclockwise on the XY plane. Fig.12 The configuration of the pad region 110 in the active region 100 is such that Fig. 9 The arrangement of the pad region 110 in the active region 100 in (a) is obtained by rotating 90 degrees counterclockwise on the XY plane. Fig.12 (b) means Fig.12 The range of the collector region 22 and the cathode region 82 (hatched portion) in (a).

[0126] exist Fig.12 In (a), the FWD region 80-3 is closest to the pad region 110, and the FWD region 80-2 is second closest to the pad region 110. Fig.12 In (a), since the pad region 110 does not exceed the FWD region 80-3 in the X-axis direction, the distance between the pad region 110 and the FWD region 80-2 can be increased compared to the second embodiment. In the third modification, the end 84-b2 of the cathode region 82 corresponding to the FWD region 80-3 can also be the same as the second modification ( Fig.11 ) has the same configuration as the end portion 84-b2 of the cathode region 82 corresponding to the FWD region 80-1.

[0127] Fig.13This is a diagram showing the range in which the collector region 22 and the cathode region 82 are provided in the semiconductor device 700 according to the third embodiment. Fig.13 Corresponding to Figure 2 The end 84 - b2 of the cathode region 82 of the FWD region 80 - 2 in the Y-axis direction is retreated by a length L Y The composition formed.

[0128] The end 84-b2 of the cathode region 82 in the FWD region 80-2 may be opposite to the pad well region 112 in the Y-axis direction, or may be close to the pad well region 112 in the Y-axis direction. In the present embodiment, the FWD region 80-2 is an example of another FWD region 80. The FWD region 80-2 extends from the pad well region 112 toward the edge 104 in the Y-axis direction. It should be noted that the edge 104 is an example of another edge.

[0129] In the present embodiment, the end 84-b2 of the cathode region 82 is separated from the pad well region 112 (particularly the pad well region 112-2). The end 84-b2 may be retreated by about 100 μm from the end of the pad well region 112-2 in the negative direction of the Y axis, or may be retreated by more than 100 μm. It should be noted that, as described above, the collector region 22 is provided in the region where the cathode region 82 is retreated in the FWD region 80. However, even when the end 84-b2 of the cathode region 82 is retreated, the region from the end of the pad well region 112-2 in the negative direction of the Y axis to the edge 104 is also regarded as the FWD region 80.

[0130] In the present embodiment, by separating the end 84-b2 of the cathode region 82 from the pad well region 112-2, the electric field concentration at the position corresponding to the end 84-b2 of the cathode region 82 in the FWD region 80 can be reduced. It should be noted that the end 84-b2 of the cathode region 82 of the FWD region 80-1 and 80-3 may be retreated to the same position in the Y-axis direction as the end 84-b2 of the cathode region 82 of the FWD region 80-2. In this case, the respective ends 84-a and 84-b2 of the FWD region 80-1 and the FWD region 80-3 may be provided at the positions indicated by the dotted lines of the respective cathode regions 82 of the FWD region 80-1 and the FWD region 80-3.

[0131] In addition, the present embodiment in which the end portion 84-b2 is separated from the pad well region 112 in the Y-axis direction can be applied to the second embodiment ( Fig. 9 )、The first modification example of the second embodiment ( Fig.10 )、Second modification example of the second embodiment ( Fig.11 ) and the third modification example of the second embodiment ( Fig.12In the second modification example ( Fig.11 ), the end 84-b1 of the cathode region 82 of the FWD region 80-1 closest to the pad well region 112 may be located at the end of the pad well region 112-2 in the negative direction of the Y axis, or may be retreated in the negative direction of the Y axis compared to the end of the pad well region 112-2 in the negative direction of the Y axis. Furthermore, the end 84-b1 of the cathode region 82 may be located at the end of the pad well region 112-1 in the negative direction of the Y axis, or may be retreated in the negative direction of the Y axis compared to the end of the pad well region 112-1 in the negative direction of the Y axis.

[0132] Similarly, in the third modification example ( Fig.12 ), the end 84-b1 of the cathode region 82 of the FWD region 80-3 may also be located at the end of the pad well region 112-2 in the negative direction of the Y axis, or may be retreated in the negative direction of the Y axis compared to the end of the pad well region 112-2 in the negative direction of the Y axis. Furthermore, the end 84-b1 of the cathode region 82 may be located at the end of the pad well region 112-1 in the negative direction of the Y axis, or may be retreated in the negative direction of the Y axis compared to the end of the pad well region 112-1 in the negative direction of the Y axis. The retreat length may be determined based on a comparison of the conduction loss in the FWD region 80 and the reduction of the electric field concentration.

[0133] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various changes and improvements can be made to the above embodiments. It can be seen from the description of the claims that the manner in which such changes and improvements are made is also included in the technical scope of the present invention.

[0134] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated as "before...", "prior to...", etc., and the output of the previous process is not used for the next process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: A semiconductor device having a plurality of transistor regions and a plurality of diode regions on a semiconductor substrate includes: The plurality of transistor regions and the plurality of diode regions extend from one end edge of the active region to another end edge opposite to the one end edge in the extension direction, and are alternately arranged in an arrangement direction perpendicular to the extension direction, and the active region is located inside a gate flow channel region which is a rectangular ring with four sides when the semiconductor substrate is viewed from above; a first conductive type pad well region, which is on the upper surface side of the semiconductor substrate, in contact with the rectangular ring-shaped gate flow channel region and is provided inside the gate flow channel region; a collector region of a first conductivity type, which is provided on the lower surface side of the semiconductor substrate and is provided at least in each transistor region of the plurality of transistor regions; as well as a cathode region of the second conductivity type, which is provided on the lower surface side of the semiconductor substrate and provided in each of the plurality of diode regions, The pad well region is located at an end of the arrangement direction and has a plurality of end portions extending along the extension direction. The plurality of end portions of the pad well region are respectively in contact with one of the plurality of transistor regions, The collector regions are respectively provided below the plurality of end portions of the pad well region. The pad well region is in contact with two transistor regions and a diode region located between the two transistor regions. A first end portion of the plurality of end portions of the pad well region is in contact with a first transistor region of the two transistor regions, A second end portion of the plurality of end portions of the pad well region is in contact with a second transistor region of the two transistor regions, and the second transistor region is provided at a position different from that of the first transistor region.

2. The semiconductor device according to claim 1, wherein: The semiconductor device includes a diode region that is not in contact with the pad well region, and the diode region is provided on the side opposite to the pad well region in the arrangement direction relative to a transistor region that is in contact with the pad well region. A portion of the end of the cathode region of the one diode region not in contact with the pad well region, which is opposite to the end of the pad well region in the arrangement direction and extends along the extension direction, has a receding end, and the receding end is located on the side opposite to the multiple ends of the pad well region relative to the boundary between the one transistor region in contact with the pad well region and the one diode region not in contact with the pad well region, and the receding end is receded in the direction from the pad well region toward the one diode region not in contact with the pad well region in the arrangement direction.

3. The semiconductor device according to claim 2, wherein: The retreated end portion of the end portions of the cathode region is separated from the plurality of end portions of the pad well region by an amount equal to or greater than the thickness of the semiconductor substrate.

4. The semiconductor device according to claim 2, wherein: The receding end portion of the end portions of the cathode region is spaced apart from the boundary by 90 μm or more.

5. The semiconductor device according to claim 3, wherein: The receding end portion of the end portions of the cathode region is spaced apart from the boundary by 90 μm or more.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that The semiconductor substrate includes a lifetime control body region, and the lifetime control body region is provided between the collector region and the cathode region and the upper surface of the semiconductor substrate, and above the receding end of the cathode region.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that The pad well region is in contact with the one edge of the active region and is provided near the center of the one edge in the arrangement direction.

8. The semiconductor device according to claim 6, wherein: The pad well region is in contact with the one edge of the active region and is provided near the center of the one edge in the arrangement direction.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that: The rectangular ring-shaped gate flow channel region includes a first conductivity type gate flow channel well region provided on the upper surface side of the semiconductor substrate. The semiconductor substrate includes a lifetime control body region from the active region to a predetermined position of the gate runner well region in the extending direction when the semiconductor substrate is viewed in plan.

10. The semiconductor device according to any one of claims 1 to 5, characterized in that At least one of the plurality of diode regions has a plurality of contact portions, and the plurality of contact portions extend along the extension direction on the upper surface of the semiconductor substrate in the active region, respectively, and are spaced apart from each other in the arrangement direction. The rectangular ring-shaped gate flow channel region includes a first conductivity type gate flow channel well region provided on the upper surface side of the semiconductor substrate. The gate channel well region is in contact with the at least one diode region in the extending direction, When the end of the gate runner well region that is opposite to each other in the extension direction and that contacts the active region and the end of the cathode region of the at least one diode region are virtually projected onto the upper surface of the semiconductor substrate, a first distance is greater than the depth of the semiconductor substrate from the upper surface to the bottom of the gate runner well region and is less than the thickness of the semiconductor substrate from the upper surface to the lower surface, and the first distance is the shortest distance between the end of the gate runner well region and the end of the cathode region.

11. The semiconductor device according to claim 10, wherein: When the ends of the gate channel well region and the ends of at least one of the multiple contact portions, which are opposite to each other in the extension direction, are virtually projected onto the upper surface of the semiconductor substrate, the first distance is greater than the second distance, and the second distance is the shortest distance between the ends of the gate channel well region and the ends of the at least one contact portion.

12. The semiconductor device according to any one of claims 1 to 5, characterized in that When the semiconductor substrate is viewed from above, transistor regions are provided at both ends of the active region in the arrangement direction of the pad well region. The pad well region is in contact with a corner of the active region.

13. The semiconductor device according to any one of claims 1 to 5, characterized in that The plurality of diode regions include another diode region extending from the pad well region toward the other end edge in the extending direction, In a plan view of the semiconductor substrate, an end portion of the cathode region in the other diode region that faces the pad well region in the extending direction is separated from the pad well region.

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