OLED display substrate, display panel and display device

Abstract

The embodiments of the present invention provide an OLED display substrate, a display panel and a display device, which relate to the field of display technology and can reduce the IR voltage drop caused by the difference in wiring resistance. An OLED display substrate comprises: a substrate, an anode layer and a cathode layer sequentially arranged on the substrate; the cathode layer comprises a plurality of mutually insulated first electrodes arranged in an array and wiring electrically connected to each first electrode; the resistance of the wiring is consistent; the substrate comprises a first area and a second area, the first area is located on the left side of the substrate, and the second area is located on the right side of the substrate; in the first electrode located in the first area, the width and length of the wiring electrically connected to the first electrode of the first column, the second column and the third column respectively in the order from left to right are equal; in the first electrode located in the second area, the width and length of the wiring electrically connected to the first electrode of the first column, the second column and the third column respectively in the order from right to left are equal.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an OLED display substrate, a display panel and a display device. Background Art

[0002] With the rapid development of display technology, the birth of touch panel (TP) makes people's life more convenient. Nowadays, embedded capacitive touch technology has been widely used in the display field. In particular, full in-cell (FIC) touch screen has gradually become the mainstream technology of embedded capacitive touch products due to its high integration, thinness and low cost. Summary of the invention

[0003] Embodiments of the present invention provide an OLED display substrate, a display panel and a display device, which can reduce the IR voltage drop caused by the difference in wiring resistance.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, an OLED display substrate is provided, comprising: a substrate, an anode layer and a cathode layer sequentially arranged on the substrate; the cathode layer comprises a plurality of first electrodes which are insulated from each other and arranged in an array, and a wiring electrically connected to each of the first electrodes; the resistance of the wiring is consistent; the substrate comprises a first area and a second area, the first area is located on the left side of the substrate, and the second area is located on the right side of the substrate; in the first electrode located in the first area, the width and length of the wiring electrically connected to the first electrodes in the first column, the second column and the third column respectively in order from left to right are both equal; in the first electrode located in the second area, the width and length of the wiring electrically connected to the first electrode in the first column, the second column and the third column respectively in order from right to left are both equal.

[0006] In some embodiments, any of the first electrodes and the wiring electrically connected thereto are an integrated structure.

[0007] In some embodiments, the first region includes at least four columns of the first electrodes; the second region includes at least four columns of the first electrodes. Among the first electrodes located in the first region, relative to the width and length of the routing electrically connected to the first electrodes in the third column, starting from the fourth column and as the number of columns increases successively, the width and length of the routing electrically connected to each column of the first electrodes increase successively. Among the first electrodes located in the second region, relative to the width and length of the routing electrically connected to the first electrodes in the third column, starting from the fourth column and as the number of columns increases successively, the width and length of the routing electrically connected to each column of the first electrodes increase successively.

[0008] In some embodiments, in the first electrodes located in the first region, in the order from left to right, the width of the wiring electrically connected to the first electrodes in the first column, the second column, and the third column respectively is equal to the width of one sub-pixel of the OLED display substrate. And / or, in the first electrodes located in the second region, in the order from right to left, the width of the wiring electrically connected to the first electrodes in the first column, the second column, and the third column respectively is equal to the width of one sub-pixel of the OLED display substrate.

[0009] In some embodiments, the widths of all the first electrodes are equal. Among the first electrodes located in the first region, the length of the routing lines electrically connected to the first electrodes in the first column, the second column, and the third column, respectively, from left to right, is equal to twice the width of the first electrode. And / or, among the first electrodes located in the second region, the length of the routing lines electrically connected to the first electrodes in the first column, the second column, and the third column, respectively, from right to left, is equal to twice the width of the first electrode.

[0010] In some embodiments, the routing line electrically connected to the first electrode in the first column on the leftmost side of the first region is in a mirror image of an L shape; the routing line electrically connected to the first electrode in the first column on the rightmost side of the second region is in an L shape.

[0011] In some embodiments, the OLED display substrate further includes a retaining wall disposed on the substrate; the retaining wall is disposed between adjacent first electrodes and between adjacent wirings; the cathode layer further includes a retaining pattern disposed on a side of the retaining wall away from the substrate, and the retaining pattern is disposed on the same layer as the first electrode and the wiring.

[0012] In some embodiments, the retaining wall includes a first retaining wall located in the first area and a second retaining wall located in the second area.

[0013] The first retaining wall includes a plurality of first strip-shaped sub-retaining walls extending in the column direction and a plurality of second strip-shaped sub-retaining walls extending in the horizontal direction, and the first strip-shaped sub-retaining walls correspond to and are connected to the second strip-shaped sub-retaining walls one by one. The first retaining wall also includes a plurality of third strip-shaped sub-retaining walls extending in the column direction. In the first region, in order from left to right, the second strip-shaped sub-retaining wall connected to the first first strip-shaped sub-retaining wall in each row is also connected to one of the third strip-shaped sub-retaining walls. The first first strip-shaped sub-retaining wall, the second strip-shaped sub-retaining wall connected to it, and the third strip-shaped sub-retaining wall connected to the second strip-shaped sub-retaining wall define the area of ​​the first electrode on the far left. The area of ​​the routing connected to the first electrode on the far left is defined between the third strip-shaped sub-retaining wall and the second first strip-shaped sub-retaining wall adjacent to it, and between the second strip-shaped sub-retaining wall connected to the third strip-shaped sub-retaining wall and the second strip-shaped sub-retaining wall adjacent to it. In each row, except for the first first strip-shaped sub-blocking wall, any adjacent first strip-shaped sub-blocking walls in the remaining first strip-shaped sub-blocking walls define a first electrode region. In the first region, the lengths of the first strip-shaped sub-blocking walls arranged from left to right increase sequentially, and the lengths of the second strip-shaped sub-blocking walls connected to the first strip-shaped sub-blocking walls increase sequentially.

[0014] The second retaining wall and the first retaining wall have symmetrical structures.

[0015] In some embodiments, in the first area, the second strip sub-retaining wall connected to any of the first strip sub-retaining walls located on the rightmost side is also connected to all of the first strip sub-retaining walls in the next row adjacent to the first strip sub-retaining wall.

[0016] In some embodiments, the longitudinal section of the retaining wall is in the shape of an inverted trapezoid; the longitudinal section is perpendicular to the base plate.

[0017] In some embodiments, the OLED display substrate further includes a spacer, and the spacer and the retaining wall are made of the same layer and the same material.

[0018] In some embodiments, the OLED display substrate further includes a pixel defining layer disposed between the substrate and the blocking wall; the blocking wall is disposed on a side of the pixel defining layer away from the substrate.

[0019] In some embodiments, the cathode layer is made of metal material.

[0020] In some embodiments, the substrate is a TFT backplane.

[0021] On the other hand, a display panel is also provided, comprising the above-mentioned OLED display substrate.

[0022] On the other hand, a display device is provided, comprising the display panel, an FPC on an OLED display substrate having one end bound to the display panel, and a mainboard connected to the other end of the FPC; an IC is also provided on the OLED display substrate and / or the FPC.

[0023] The embodiments of the present invention provide an OLED display substrate, a display panel and a display device. By making the cathode layer include a plurality of first electrodes that are insulated from each other and arranged in an array, the first electrodes can be reused as touch electrodes, thereby realizing fully embedded touch control with a simple structure. On this basis, by setting the resistance of the wirings electrically connected to different first electrodes to be consistent, the resistance value of the wiring itself can have the same effect on the signal input to the first electrode connected to it through each wiring, and the acquisition signal output to the TIC. Therefore, by designing the wiring with equal resistance, the influence of the IR voltage drop caused by the difference in wiring resistance on the display and touch performance is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic top view of an OLED display substrate provided in some embodiments of the present invention;

[0026] Figure 2 for Figure 1 An enlarged schematic diagram of one row of the first area in FIG.

[0027] Figure 3 A schematic cross-sectional view of an OLED display substrate provided in some embodiments of the present invention;

[0028] Figure 4 is a schematic diagram of the arrangement of touch electrodes and touch electrode lines in the related art;

[0029] Figure 5 Based on Figure 4 A configuration method, a schematic diagram of a structure of an organic material functional layer;

[0030] Figure 6 A schematic diagram of the structure of an organic material functional layer provided in some embodiments of the present invention;

[0031] Figure 7 A schematic top view of another OLED display substrate provided in some embodiments of the present invention;

[0032] Figure 8 A schematic cross-sectional view of another OLED display substrate provided for some embodiments of the present invention.

[0033] Reference numerals:

[0034] 1-display area; 2-non-display area; 3-first area; 4-second area; 10-substrate; 11-substrate; 12-thin film transistor; 21-first electrode; 22-routing; 23-anode; 24-retained pattern; 30-metal lead; 41-touch chip; 42-display driver chip; 50-package cover; 61-touch electrode; 62-touch electrode line; 631-hole injection layer; 632-hole transport layer; 633-pad layer; 634-buffer layer; 635-light-emitting layer; 636-electron transport layer; 70-pixel defining layer; 80-blocking wall; 81-first strip sub-blocking wall; 82-second strip sub-blocking wall; 83-third strip sub-blocking wall. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] An embodiment of the present invention provides a display substrate, comprising: a substrate, an anode layer and a cathode layer sequentially arranged on the substrate. Figure 1 As shown, the cathode layer disposed on the substrate 10 includes a plurality of first electrodes 21 that are insulated from each other and arranged in an array, and a wiring 22 electrically connected to each first electrode 21; the resistance of the wiring 22 electrically connected to different first electrodes 21 is consistent. Wherein, the substrate 10 includes a first region 3 and a second region 4, the first region 3 is located on the left side of the substrate 10, and the second region 4 is located on the right side of the substrate 10; among the first electrodes 21 located in the first region 3, in order from left to right, the width and length of the wiring 22 electrically connected to the first electrodes 21 of the first column A1, the second column A2, and the third column A3 are equal; among the first electrodes 21 located in the second region 4, in order from right to left, the width and length of the wiring 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′, and the third column A3′ are equal.

[0037] In order to prevent the wiring 22 connected to the first electrodes 21 in the same row from occupying too much wiring space, the substrate 10 is divided into a first area 3 and a second area 4. The wiring 22 connected to the first electrodes 21 in the first area 3 can extend to the non-display area 2 on the left, and the wiring 22 connected to the first electrodes 21 in the second area 4 can extend to the non-display area 2 on the right. The directional terms such as "left" and "right" are defined relative to the position of the OLED display substrate in the accompanying drawings. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can change accordingly according to the change of the position of the OLED display substrate.

[0038] Here, the sizes of the first area 3 and the second area 4 are not limited. In some embodiments, the left area of ​​the center line of the substrate 10 is set as the first area 3, and the right area of ​​the center line of the substrate 10 is set as the second area 4.

[0039] In some embodiments, in order to save wiring space and simplify the wiring process, between adjacent rows of first electrodes 21 , the wirings 22 connected to the first electrodes 21 in the same row are arranged in parallel with each other.

[0040] In the first electrodes 21 located in the first region 3, the widths and lengths of the traces 22 electrically connected to the first electrodes 21 in the first column A1, the second column A2, and the third column A3, respectively, from left to right, are equal. Figure 2 As shown, among the first electrodes 21 located in the first region 3, the widths of the wiring 22 electrically connected to the first electrodes 21 of the first column A1, the second column A2, and the third column A3 are W1, W2, and W3, respectively, and W1 = W2 = W3. The lengths of the wiring 22 electrically connected to the first electrodes 21 of the first column A1, the second column A2, and the third column A3 are L1, L2, and L3, respectively, and L1 = L2 = L3.

[0041] Similarly, in the first electrodes 21 located in the second region 4, the arrangement of the wiring 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′, and the third column A3′, respectively, from right to left, is also the same, and will not be repeated here. Since the resistance of the wiring 22 electrically connected to different first electrodes 21 is consistent, in some embodiments, the width of the wiring 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′, and the third column A3′ located in the second region 4 is equal to W1, and the length is equal to L1.

[0042] It should be noted that the “consistent” in “the resistance of the wiring 22 is consistent” means that the resistance values ​​of the plurality of wirings 22 are the same or approximately the same within the range allowed by the design and manufacturing tolerances.

[0043] In the embodiment of the present invention, each wiring 22 is electrically connected to a first electrode 21 .

[0044] It can be understood that, since the cathode layer includes a plurality of first electrodes 21 that are insulated from each other and arranged in an array, when a common voltage is input to the first electrode 21 through the wiring 22, the light-emitting layer in the organic material functional layer between the first electrode 21 and the anode in the anode layer is driven to emit light, thereby realizing a display function. When a touch drive signal is input to the first electrode 21 through the wiring 22, the first electrode 21 is used as a touch electrode to identify the touch position.

[0045] That is, when the OLED display substrate is applied to a display panel, when the display panel is in the display stage, a common voltage is input to the first electrode 21 through the wiring 22, so that the first electrode 21 and the anode corresponding thereto form an electric field, thereby stimulating the light-emitting layer between the first electrode 21 and the anode to emit light. When the display panel is in the touch stage, a touch driving signal is input to the first electrode 21 through the wiring 22, and a touch sensing signal is received, so as to determine the touch position according to the coordinates of the self-capacitance where the capacitance value changes.

[0046] In order to input or receive signals to each first electrode 21 individually, a plurality of metal leads may be formed on the substrate 10, and each lead 22 is electrically connected to a metal lead 30 below through a via hole (eg, Figure 3 Based on this, by electrically connecting the metal lead 30 to the touch driver IC (Touch Driver IC, TIC) 41 and the display driver IC (Display Driver IC, DDI) 42, the first electrode 21 can receive signals from the TIC41 and the DDI42, and feed back the collected touch sensing signals to the TIC41.

[0047] TIC41 and DDI42 can be set independently. In some embodiments, Figure 3 As shown, the DDI 42 is directly disposed in the non-display area 2 of the OLED display substrate. The TIC 41 is disposed on a flexible printed circuit (FPC), and the flexible printed circuit is bound to the non-display area 2 of the OLED display substrate.

[0048] Of course, TIC41 and DDI42 can also be integrated into one chip. Based on this, it is only necessary to connect the metal lead 30 to the integrated chip.

[0049] In some embodiments, when the OLED display substrate is applied to a display panel, Figure 3As shown, the display panel further includes a packaging cover plate 50. The packaging cover plate 50 may be a cover glass or a packaging film layer.

[0050] The embodiment of the present invention provides an OLED display substrate. By making the cathode layer include a plurality of first electrodes 21 that are insulated from each other and arranged in an array, the first electrodes 21 can be reused as touch electrodes, thereby realizing full in-cell (FIC) touch control with a simple structure. On this basis, by setting the resistance of the wiring 22 electrically connected to different first electrodes 21 to be consistent, the resistance value of the wiring 22 itself can have the same effect on the signal input to the first electrode 21 connected thereto through each wiring 22, and the acquisition signal output to the TIC41. Therefore, by designing the wiring 22 with equal resistance, the influence of the IR drop (IR-Drop) caused by the resistance difference of the wiring 22 on the display and touch performance is reduced.

[0051] In some embodiments, the cathode layer is made of a metal material.

[0052] Since metal has good ductility, when the OLED display substrate is applied to a flexible display device, a good bending effect can be obtained, thereby solving the defect in the prior art that, when an on-cell touch structure is adopted, the electrodes in the touch structure are made of transparent conductive materials and thus cannot meet the bending requirements.

[0053] On this basis, the anode layer can be set to be opaque, while the cathode layer can be made thinner to make it translucent, thereby improving the light output rate during display based on the microcavity effect.

[0054] In some embodiments, any first electrode 21 and the wiring 22 electrically connected thereto are an integrated structure, that is, the first electrode 21 and the wiring 22 are arranged in the same layer, and the electrical connection between the first electrode 21 and the wiring 22 does not need to pass through a via.

[0055] Based on this, by extending the wiring 22 from the display area 1 to the non-display area 2 (such as Figure 1 As shown), the electrical connection between the wiring 22 and the metal lead 30 is realized in the non-display area 2, and the via hole for electrically connecting the wiring 22 and the metal lead 30 is located in the non-display area 2.

[0056] On the one hand, compared with Figure 4 As shown in FIG. 1 , the touch electrode 61 is electrically connected to the touch electrode line 62 in the display area 1 through a via hole, which will affect the aperture ratio. The embodiment of the present invention can avoid this problem. On the other hand, when the touch electrode 61 is electrically connected to the touch electrode line 62 in the display area 1 through a via hole, as shown in FIG. Figure 5As shown, if the organic material functional layers are, from bottom to top, hole injection layer (HI) 631, hole transport layer (HT) 632, liner layer 633 for adjusting microcavity height, buffer layer (HTEB) 634 for improving hole transport efficiency, light emitting layer (EML) 635 and electron transport layer (ET) 636, then each layer of the organic material functional layer needs to be prepared by a fine mask (FMM), which will result in reduced yield and increased cost. In the example of the present invention, since the via hole electrically connecting the wiring 22 to the metal lead 30 is located in the non-display area 2, as shown in FIG. Figure 6 As shown, in the case where the organic material functional layers between the anode 23 and the first electrode 21 are, from bottom to top, a hole injection layer (HI) 631, a hole transport layer (HT) 632, a liner layer 633 for adjusting the height of the microcavity, a buffer layer (HTEB) 634 for improving the hole transport efficiency, a light-emitting layer (EML) 635, and an electron transport layer (ET) 636, only the light-emitting layer 635 and the liner layer 633 need to be formed by FMM, and the remaining layers can use an open mask plate, thereby reducing the use of FMM, thereby improving the yield and reducing the production cost.

[0057] It should be noted that Figure 5 and Figure 6 The description is made by taking the adjustment of the height of the microcavity where the red (R) light emitting layer 635 and the green (G) light emitting layer 635 are located as an example. When the height of the microcavity where the blue (B) light emitting layer 635 is located needs to be adjusted, the above-mentioned liner layer 633 can also be formed at the position corresponding to the microcavity where the blue (B) light emitting layer 635 is located.

[0058] In some embodiments, Figure 7 As shown, the first region 3 includes at least four columns of first electrodes 21 ( Figure 7 The first region 3 includes four columns of first electrodes 21 for illustration); the second region 4 includes at least four columns of first electrodes 21 ( Figure 7 In the figure, the second region 4 includes four columns of first electrodes 21 for illustration.

[0059] Among them, in the first electrodes 21 located in the first area 3, relative to the width and length of the wiring 22 electrically connected to the first electrodes 21 of the third column A3, starting from the fourth column A4 and as the number of columns increases successively (increasing from left to right), the width and length of the wiring 22 electrically connected to each column of the first electrodes 21 increase successively.

[0060] In the first electrode 21 located in the second area 4, relative to the width and length of the wiring 22 electrically connected to the first electrode 21 of the third column A3′, starting from the fourth column A4′ and as the number of columns increases successively (increasing from right to left), the width and length of the wiring 22 electrically connected to each column of the first electrode 21 increase successively.

[0061] Since the resistance value of the wiring 22 is proportional to its width W and inversely proportional to its length L, therefore, when the first region 3 includes at least four columns of first electrodes 21 and the second region 4 includes at least four columns of first electrodes 21, no matter in the first region 3 or the second region 4, starting from the wiring 22 connected to the fourth column of first electrodes 21, as the length of the wiring 22 increases, its width increases accordingly. Thus, starting from the fourth column of first electrodes 21, the resistance value of the wiring 22 connected to each first electrode 21 can be kept the same or approximately the same as the resistance value of the wiring 22 connected to the first three columns of first electrodes 21, thereby achieving equal resistance design.

[0062] In order to avoid the occurrence of a touch blind area due to the wiring 22 occupying more wiring space, in some embodiments, in the first electrodes 21 located in the first area 3, the width of the wiring 22 electrically connected to the first electrodes 21 in the first column A1, the second column A2 and the third column A3 respectively from left to right is equal to the width of a sub-pixel of the OLED display substrate. That is, W1=W2=W3=1P (P is the width of a sub-pixel).

[0063] In some embodiments, among the first electrodes 21 located in the second region 4, the width of the traces 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′ and the third column A3′ respectively from right to left is equal to the width of a sub-pixel of the OLED display substrate.

[0064] In other embodiments, among the first electrodes 21 located in the first region 3, the width of the wiring 22 electrically connected to the first electrodes 21 of the first column A1, the second column A2, and the third column A3, respectively, from left to right, is equal to the width of one sub-pixel of the OLED display substrate. Among the first electrodes 21 located in the second region 4, the width of the wiring 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′, and the third column A3′, respectively, from right to left, is equal to the width of one sub-pixel of the OLED display substrate.

[0065] In some embodiments, the widths (denoted as L) of all first electrodes 21 are equal.

[0066] Based on this, in some embodiments, among the first electrodes 21 located in the first region 3, the length of the traces 22 electrically connected to the first electrodes 21 in the first column A1, the second column A2, and the third column A3, respectively, from left to right, is equal to twice the width of the first electrodes 21. That is, L1=L2=L3=2L.

[0067] In some embodiments, among the first electrodes 21 located in the second region 4 , the length of the traces 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′ and the third column A3′ respectively in order from right to left is equal to twice the width of the first electrode 21 .

[0068] In other embodiments, among the first electrodes 21 located in the first region 3, in the order from left to right, the length of the traces 22 electrically connected to the first electrodes 21 of the first column A1, the second column A2, and the third column A3 respectively is equal to twice the width of the first electrode 21. Among the first electrodes 21 located in the second region 4, in the order from right to left, the length of the traces 22 electrically connected to the first electrodes 21 of the first column A1′, the second column A2′, and the third column A3′ respectively is equal to twice the width of the first electrode 21.

[0069] In some embodiments, Figure 1 and Figure 7 As shown, the trace 22 electrically connected to the first electrode 21 in the first column A1 on the left side of the first area 3 is a mirror image of an L. The trace 22 electrically connected to the first electrode 21 in the first column A1′ on the right side of the second area 4 is an L-shaped.

[0070] In some embodiments, Figure 1 , Figure 7-Figure 8 As shown, the display substrate further includes a retaining wall 80 disposed on the substrate 10, and the retaining wall 80 is disposed between adjacent first electrodes 21 and adjacent wirings 22. The retaining wall 80 is used to divide the cathode layer into a plurality of first electrodes 21 and wirings 22 electrically connected to each first electrode 21. Figure 8 As shown, the cathode layer further includes a retention pattern 24 disposed on a side of the retaining wall 80 away from the substrate 10, and the retention pattern 24 is connected to the first electrode 21 and the wiring 22 ( Figure 8 (not shown) same-layer arrangement.

[0071] By disposing the retaining wall 80 , no special process is required, and the cathode layer including the first electrode 21 and the wiring 22 can be formed by using a conventional process for preparing the cathode layer (eg, an evaporation process).

[0072] In some embodiments, the retaining wall 80 includes a first retaining wall located in the first area 3 and a second retaining wall located in the second area 4. Figure 1As shown, the first retaining wall includes a plurality of first strip-shaped sub-retaining walls 81 extending in the column direction and a plurality of second strip-shaped sub-retaining walls 82 extending in the horizontal direction, and the first strip-shaped sub-retaining walls 81 correspond to and are connected to the second strip-shaped sub-retaining walls 82 one by one.

[0073] The first retaining wall also includes a plurality of third strip-shaped sub-retaining walls 83 extending in the column direction. In the first area 3, from left to right, the second strip-shaped sub-retaining wall 82 connected to the first first strip-shaped sub-retaining wall 81 in each row is also connected to a third strip-shaped sub-retaining wall 83. The first first strip-shaped sub-retaining wall 81, the second strip-shaped sub-retaining wall 82 connected thereto, and the third strip-shaped sub-retaining wall 83 connected to the second strip-shaped sub-retaining wall 82 define the area of ​​the first electrode 21 on the leftmost side. The area of ​​the trace 22 connected to the first electrode 21 on the leftmost side is defined between the third strip-shaped sub-retaining wall 83 and the second first strip-shaped sub-retaining wall 81 adjacent thereto, and between the second strip-shaped sub-retaining wall 82 connected to the third strip-shaped sub-retaining wall 83 and the second strip-shaped sub-retaining wall 82 adjacent thereto.

[0074] In each row, except for the first first strip-shaped sub-blocking wall 81, any adjacent first strip-shaped sub-blocking walls 81 in the remaining first strip-shaped sub-blocking walls 81 define a first electrode 21 region. In the first region 3, the lengths of the first strip-shaped sub-blocking walls 81 arranged from left to right increase sequentially, and the lengths of the second strip-shaped sub-blocking walls 82 connected to the first strip-shaped sub-blocking walls 81 increase sequentially.

[0075] Continue to refer to Figure 1 and Figure 7 As shown, the structures of the second retaining wall and the first retaining wall are symmetrical.

[0076] Through the structure of the retaining wall 80, the size of the first electrodes 21 in each row can be increased from left to right in the first area 3. The size of the first electrodes 21 in each row can be increased from right to left in the second area 4. This is conducive to realizing the equal resistance design of the wiring 22.

[0077] In some embodiments, Figure 1 As shown, in the first area 3 , the second strip sub-retaining wall 82 connected to any first strip sub-retaining wall 81 located on the rightmost side is also connected to all first strip sub-retaining walls 81 in the next row adjacent to the first strip sub-retaining wall 81 .

[0078] That is, in the first area 3, the second strip sub-retaining wall 82 connected to the first strip sub-retaining wall 81 located on the far right in the first row is also connected to all the first strip sub-retaining walls 81 in the second row. The second strip sub-retaining wall 82 connected to the first strip sub-retaining wall 81 located on the far right in the second row is also connected to all the first strip sub-retaining walls 81 in the third row. The second strip sub-retaining wall 82 connected to the first strip sub-retaining wall 81 located on the far right in the third row is also connected to all the first strip sub-retaining walls 81 in the fourth row. And so on.

[0079] It can be understood that due to the structural symmetry of the second retaining wall and the first retaining wall, in the second area 4, the second strip sub-retaining wall 82 connected to any first strip sub-retaining wall 81 located on the leftmost side is also connected to all first strip sub-retaining walls 81 in the next row adjacent to the first strip sub-retaining wall 81.

[0080] In this way, the structure of the retaining wall 80 can be made simpler, ensuring that the first electrodes 21 formed subsequently are insulated from each other, and the wirings 22 connected to different first electrodes 21 are insulated from each other.

[0081] In some embodiments, Figure 8 As shown, the longitudinal section of the retaining wall 80 is in an inverted trapezoidal shape; the longitudinal section is perpendicular to the substrate 10. In this way, when the cathode layer is formed (for example, the cathode layer is formed by an evaporation process), the cathode layer is ensured to be disconnected at the position of the retaining wall 80, thereby forming independent first electrodes 21 and wirings 22 connected to the first electrodes 21.

[0082] In some embodiments, the OLED display substrate further includes spacers, and the spacers and the retaining walls 80 are made of the same layer and material.

[0083] The spacer can play a supporting role for the packaging substrate 50. The spacer and the retaining wall 80 are made of the same layer and the same material, that is, the spacer and the retaining wall 80 are prepared and formed by the same patterning process, thereby reducing the number of patterning processes.

[0084] In some embodiments, the spacers and the retaining wall 80 may be formed by using negative photoresist, so that the retaining wall 80 with an inverted trapezoidal longitudinal section can be easily formed on the basis of simplifying the preparation process.

[0085] It should be noted that the spacers and the retaining wall 80 do not overlap.

[0086] In some embodiments, Figure 8 As shown, the OLED display substrate further includes a pixel defining layer 70 disposed between the substrate 10 and the retaining wall 80; the retaining wall 80 is disposed on a side of the pixel defining layer 70 away from the substrate 10. That is, the pixel defining layer 70 is formed first, and then the retaining wall 80 is formed.

[0087] In some embodiments, the substrate 10 is a thin film transistor (TFT) substrate.

[0088] That is, Figure 8 As shown, the substrate 10 includes a substrate 11 and a TFT 12 disposed on the substrate 11. In this case, the OLED display substrate is an active matrix organic light emitting diode (AMOLED) display substrate.

[0089] The embodiment of the present invention further provides a display panel, comprising the above-mentioned OLED display substrate. The display panel has the same beneficial effects as the OLED display substrate, which will not be described in detail here.

[0090] When the display panel is tested for lighting, its display brightness can be kept uniform. In addition, during the process of performing lighting effect tests on the display panel for multiple times, it is found that the display panel has good brightness uniformity when displaying images (such as striped images).

[0091] The embodiment of the present invention further provides a display device, comprising the display panel, a flexible printed circuit (FPC) (such as a Figure 3 As shown) and a main board connected to the other end of the FPC; an IC is also provided on the OLED display substrate and / or the FPC.

[0092] In some embodiments, Figure 3 As shown, the IC includes TIC41 and DDI42, etc.

[0093] The display device may be any product or component having a display function, such as a television, a digital photo frame, a mobile phone or a tablet computer.

[0094] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An OLED display substrate, characterized in that: include: A substrate, an anode layer and a cathode layer sequentially arranged on the substrate; and spacers; The cathode layer includes a plurality of first electrodes that are insulated from each other and arranged in an array, and a wiring that is electrically connected to each of the first electrodes; the wiring has a consistent resistance; The substrate comprises a first area and a second area, the first area is located on the left side of the substrate, and the second area is located on the right side of the substrate; Among the first electrodes located in the first region, in order from left to right, the widths and lengths of the wirings electrically connected to the first electrodes in the first column, the second column, and the third column, respectively, are equal; Among the first electrodes located in the second region, in order from right to left, the widths and lengths of the wirings electrically connected to the first electrodes in the first column, the second column, and the third column are equal; The wiring electrically connected to the first electrode in the first column on the leftmost side of the first region has a shape that is a mirror image of an L shape; The wiring electrically connected to the first electrode in the first column located at the rightmost side of the second region is L-shaped.

2. The OLED display substrate according to claim 1, characterized in that: Any of the first electrodes and the wiring electrically connected thereto are an integrated structure.

3. The OLED display substrate according to claim 1 or 2, characterized in that: The first region includes at least four columns of the first electrodes; the second region includes at least four columns of the first electrodes; Among the first electrodes located in the first region, relative to the width and length of the wiring electrically connected to the first electrodes in the third column, starting from the fourth column and as the number of columns increases successively, the width and length of the wiring electrically connected to the first electrodes in each column increase successively; In the first electrodes located in the second area, relative to the width and length of the routing electrically connected to the first electrodes in the third column, starting from the fourth column and as the number of columns increases successively, the width and length of the routing electrically connected to the first electrodes in each column increase successively.

4. The OLED display substrate according to claim 1 or 2, characterized in that: Among the first electrodes located in the first region, the width of the wiring electrically connected to the first electrodes in the first column, the second column and the third column respectively from left to right is equal to the width of one sub-pixel of the OLED display substrate; and / or, In the first electrodes located in the second area, the width of the wiring electrically connected to the first electrodes in the first column, the second column and the third column respectively from right to left is equal to the width of one sub-pixel of the OLED display substrate.

5. The OLED display substrate according to claim 1 or 2, characterized in that: All of the first electrodes have equal widths; Among the first electrodes located in the first region, the length of the wiring electrically connected to the first electrodes in the first column, the second column and the third column respectively from left to right is equal to twice the width of the first electrode; and / or, In the first electrodes located in the second region, the length of the routing lines electrically connected to the first electrodes in the first column, the second column and the third column respectively in order from right to left is equal to twice the width of the first electrode.

6. The OLED display substrate according to claim 2, characterized in that: It also includes a retaining wall disposed on the substrate, wherein the retaining wall is disposed between adjacent first electrodes and between adjacent wirings; The cathode layer further includes a reserved pattern disposed on a side of the retaining wall away from the substrate, and the reserved pattern is disposed in the same layer as the first electrode and the wiring.

7. The OLED display substrate according to claim 6, characterized in that: The retaining wall comprises a first retaining wall located in the first area and a second retaining wall located in the second area; The first retaining wall comprises a plurality of first strip-shaped sub-retaining walls extending in a row direction and a plurality of second strip-shaped sub-retaining walls extending in a horizontal direction, and the first strip-shaped sub-retaining walls correspond to and are connected to the second strip-shaped sub-retaining walls one by one; The first retaining wall further comprises a plurality of third strip-shaped sub-retaining walls extending in the column direction; in the first region, in order from left to right, the second strip-shaped sub-retaining wall connected to the first first strip-shaped sub-retaining wall in each row is also connected to one of the third strip-shaped sub-retaining walls; The first first strip-shaped sub-blocking wall, the second strip-shaped sub-blocking wall connected thereto, and the third strip-shaped sub-blocking wall connected thereto define the area of ​​the first electrode on the far left; the area of ​​the wiring connected to the first electrode on the far left is defined between the third strip-shaped sub-blocking wall and the second first strip-shaped sub-blocking wall adjacent thereto, and between the second strip-shaped sub-blocking wall connected thereto and the second strip-shaped sub-blocking wall adjacent thereto; In each row, except for the first first strip-shaped sub-blocking wall, any adjacent first strip-shaped sub-blocking walls among the remaining first strip-shaped sub-blocking walls define a first electrode region; wherein, in the first region, the lengths of the first strip-shaped sub-blocking walls arranged from left to right increase sequentially, and the lengths of the second strip-shaped sub-blocking walls connected to the first strip-shaped sub-blocking walls increase sequentially; The second retaining wall and the first retaining wall have symmetrical structures.

8. The OLED display substrate according to claim 7, characterized in that: In the first area, the second strip sub-retaining wall connected to any of the first strip sub-retaining walls located on the rightmost side is also connected to all the first strip sub-retaining walls in the next row adjacent to the first strip sub-retaining wall.

9. The OLED display substrate according to claim 6, characterized in that: The longitudinal section of the retaining wall is in the shape of an inverted trapezoid; the longitudinal section is perpendicular to the base plate.

10. The OLED display substrate according to claim 1, characterized in that: The cathode layer is made of metal material.

11. A display panel, characterized in that: The OLED display substrate comprises the OLED display substrate according to any one of claims 1 to 10.

12. A display device, characterized in that: The device comprises the display panel according to claim 11, an FPC bound to an OLED display substrate of the display panel at one end, and a mainboard connected to the other end of the FPC; An IC is also arranged on the OLED display substrate and / or the FPC.

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