High electron mobility transistor with double-thickness barrier layer

Abstract

A method for forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first III-V semiconductor layer and a second III-V semiconductor layer formed on the first III-V semiconductor layer. The second III-V semiconductor layer has a band gap different from that of the first III-V semiconductor layer, so that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V semiconductor layers. The second III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second III-V semiconductor layer.

Description

Background Art

[0001] Semiconductor transistors (particularly field effect controlled switching devices), such as MISFETs (metal insulator semiconductor field effect transistors), also referred to hereinafter as MOSFETs (metal oxide semiconductor field effect transistors), and HEMTs (high electron mobility field effect transistors), also referred to as heterostructure FETs (HFETs) and modulation doped FETs (MODFETs), are used in a variety of applications. HEMTs are transistors in which the junction is between two materials with different band gaps, such as GaN and AlGaN. In GaN / AlGaN-based HEMTs, a two-dimensional electron gas (2DEG) appears near the interface between the AlGaN barrier layer and the GaN channel layer. In HEMTs, 2DEG forms the channel of the device. Similar principles can be used to select the channel and barrier layer that form a two-dimensional hole gas (2DHG) as the channel of the device. 2DEG or 2DHG is generally referred to as a two-dimensional carrier gas. In the absence of additional measures, the heterojunction configuration results in a self-conducting (i.e., normally-on) transistor. Measures must be taken to prevent the channel region of the HEMT from being in the on state in the absence of a positive gate voltage.

[0002] Due to the high electron mobility of the two-dimensional carrier gas in the heterojunction configuration, HEMTs offer high conduction and low losses compared to many conventional semiconductor transistor designs. These favorable conduction characteristics make HEMTs desirable in applications including, but not limited to, use as switches in power supplies and power converters, electric vehicles, air conditioners, and in, for example, consumer electronics.

[0003] Designers are constantly looking for ways to improve the performance of HEMTs, such as power consumption and voltage blocking capability. Exemplary device parameters that designers focus on to improve HEMT performance include leakage current, threshold voltage (V TH ), drain-source on-state resistance (R DSON ) and maximum voltage switching capability, to name a few. Summary of the invention

[0004] A method for forming a semiconductor device is disclosed. According to an embodiment, the method includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first III-V semiconductor layer and a second III-V semiconductor layer formed on the first III-V semiconductor layer. The second III-V semiconductor layer has a band gap different from that of the first III-V semiconductor layer, so that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V semiconductor layers. The heterojunction semiconductor body is provided so that the second III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section of the second III-V semiconductor layer, and the first input-output electrode is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section of the second III-V semiconductor layer, and the second input-output electrode is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section of the second III-V semiconductor layer, and the gate structure is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second III-V type semiconductor layer.

[0005] According to another embodiment, the method includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first III-V semiconductor layer and a second III-V semiconductor layer formed on the first III-V semiconductor layer. The second III-V semiconductor layer has a band gap different from that of the first III-V semiconductor layer, so that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V semiconductor layers. The heterojunction semiconductor body is provided so that the second III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section of the second III-V semiconductor layer, the first input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section of the second III-V semiconductor layer, the second input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section of the second III-V semiconductor layer, the gate structure being configured to control a conductive connection between the first and second input-output electrodes. The gate structure is disposed completely above a first planar upper surface of the second III-V type semiconductor layer, the first planar upper surface extending out from under the gate structure at either side of the gate structure.

[0006] A semiconductor device is disclosed. According to an embodiment, the semiconductor device includes a heterojunction semiconductor body. The heterojunction semiconductor body includes a first III-V semiconductor layer and a second III-V semiconductor layer formed on the first III-V semiconductor layer. The second III-V semiconductor layer has a band gap different from that of the first III-V semiconductor layer, so that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V semiconductor layers. The second III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is formed on the thicker section of the second III-V semiconductor layer, and the first input-output electrode is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section of the second III-V semiconductor layer, and the second input-output electrode is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section of the second III-V semiconductor layer, and the gate structure is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second III-V semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals refer to corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and detailed in the subsequent description.

[0008] Figure 1 A semiconductor device having a multi-thickness barrier layer according to an embodiment is illustrated.

[0009] Figure 2 A semiconductor device having a multi-thickness barrier layer according to another embodiment is illustrated.

[0010] Figure 3 FIG. 1 illustrates providing a heterostructure body in a method of forming a semiconductor device according to an embodiment.

[0011] Figure 4 Processing a heterostructure body to form a double-thickness barrier layer in a method of forming a semiconductor device according to an embodiment is illustrated.

[0012] Figure 5 FIG. 1 illustrates forming a trench for a deep contact structure in a heterostructure body in a method of forming a semiconductor device according to an embodiment.

[0013] Figure 6 FIG. 1 illustrates forming a doped semiconductor layer and a metal layer on a heterostructure body in a method of forming a semiconductor device according to an embodiment.

[0014] Figure 7Structuring a doped semiconductor layer and a metal layer to form an electrode structure in a method of forming a semiconductor device according to an embodiment is illustrated.

[0015] Figure 8 FIG. 1 illustrates forming first and second passivation layers on a structured region in a method of forming a semiconductor device according to an embodiment.

[0016] Fig. 9 FIG. 1 illustrates forming a mask over first and second passivation layers in a method of forming a semiconductor device according to an embodiment.

[0017] Fig.10 FIG. 1 illustrates forming a contact trench in a heterostructure body in a method of forming a semiconductor device according to an embodiment.

[0018] Fig.11 Forming input-output electrodes in a method of forming a semiconductor device according to an embodiment is illustrated.

[0019] Fig.12 Forming a mask over a first passivation layer in an alternative method for forming a semiconductor device according to an embodiment is illustrated.

[0020] Fig.13 FIG. 1 illustrates forming a second passivation layer after removing a metal electrode from a drain bias structure in a method for forming a semiconductor device according to another embodiment.

[0021] Fig.14 FIG. 1 illustrates forming input-output electrodes for a semiconductor device in a method for forming a semiconductor device according to another embodiment. DETAILED DESCRIPTION

[0022] A high electron mobility field effect transistor (HEMT) is described herein. According to an embodiment, a barrier layer of the device includes a thicker region and a thinner region. In one embodiment, the barrier layer has a planar upper surface in both the thicker and thinner regions, and a step-shaped transition between the thicker and thinner regions. A gate and a source electrode are provided on the thinner section, while a drain electrode is provided on the thicker section. Because the gate is provided on the thinner region of the barrier layer, the two-dimensional charge carrier gas below the gate has a relatively lower carrier density than the two-dimensional charge carrier gas below the thicker section of the barrier layer. This reduction in carrier density advantageously enables a higher threshold voltage (V TH ) and harden the gate to withstand high switching voltages. At the same time, without affecting the drain-source on-resistance (R DSON ) because the drift region of the device has a higher carrier density due to the provision of a thicker barrier region in the drift region of the device (ie, between the gate and the drain).

[0023] Methods of forming a HEMT are described herein. According to an embodiment, the method includes using a masked etch technique to form a barrier layer of a device having thicker and thinner regions. This technique advantageously provides precise control of the physical dimensions of the barrier layer and, thus, provides precise control of the performance parameters of the HEMT. In one advantageous process step, a common photolithography process is used to simultaneously form a gate structure, a deep contact structure, and a drain bias structure of the HEMT, which utilizes a single layer of p-type material and a single layer of conductive material.

[0024] Reference Figure 1 , depicts a semiconductor device 100 according to an embodiment. The semiconductor device 100 includes a heterojunction semiconductor body 102. The heterojunction semiconductor body 102 includes a back barrier region 104, a channel layer 106 formed on the back barrier region 104, and a barrier layer 108 formed on the channel layer 106. The barrier layer 108 has a different band gap than the channel layer 106. Due to this difference in band gap, a first two-dimensional charge carrier gas 110 inherently appears near the interface between the channel layer 106 and the barrier layer 108. In addition, the material of the back barrier region 104 has a different band gap than the material of the channel layer 106. Due to this difference in band gap, a second two-dimensional charge carrier gas 112 inherently appears near the interface between the channel layer 106 and the back barrier region 104. The second two-dimensional charge carrier gas 112 has a majority carrier type opposite to that of the first two-dimensional charge carrier gas 110. For example, in the case where the first two-dimensional charge carrier gas 110 is a two-dimensional electron gas (2DEG), the second two-dimensional charge carrier gas 112 is a two-dimensional hole gas (2DHG), and vice versa.

[0025] In general, the channel and barrier layers 106, 108 may be formed of any semiconductor material in which the band gap may be manipulated to form the first two-dimensional charge carrier gas 110. Examples of such materials include III-V type semiconductor materials (e.g., gallium nitride, gallium arsenide, etc.) into which metal elements (e.g., aluminum, indium, etc.) are introduced to adjust the band gap. The material properties (e.g., thickness, band gap, etc.) of the back barrier region 104 are selected to increase carrier confinement in the first two-dimensional charge carrier gas 110 and prevent device leakage through the lower region of the heterojunction semiconductor body 102.

[0026] The heterojunction semiconductor body 102 further comprises a transition region 114 and a base substrate 116. The transition region 114 is formed on the base substrate 116, and the back barrier region 104 is formed on the transition region 114. The base substrate 116 comprises a semiconductor material suitable for epitaxial growth techniques, such as silicon, carbon, silicon carbide, sapphire, etc. The transition region 114 is a so-called lattice transition region 114, which is configured to relieve mechanical stress attributable to the crystal lattice mismatch between the IV-type semiconductor material (e.g., silicon) of the base substrate 116 and the III-V-type semiconductor material of the channel and barrier layers 106, 108. The transition region 114 may comprise, for example, a III-V-type semiconductor material, a metal layer, and an electrical insulator. Moreover, the metal concentration of the transition region 114 may vary in a manner to relieve mechanical stress, for example, having a metal concentration that decreases as one moves away from the base substrate 116.

[0027] According to an embodiment, the heterojunction semiconductor body 102 is a semiconductor body based on gallium nitride (GaN). In this embodiment, the base substrate 116 is provided from a commercially available bulk wafer (such as a silicon wafer). In addition, in this embodiment, the transition region 114 includes aluminum gallium nitride (AlGaN) with an aluminum content that gradually decreases as one moves away from the base substrate 116. Alternatively, the transition region 114 may include an aluminum nitride (AlN) layer periodically inserted between multiple GaN layers or GaN-based layers. In addition, in this embodiment, the back barrier region 104 may be a region of aluminum gallium nitride (AlGaN) with a uniform aluminum content (within process capabilities), for example, between two percent and ten percent throughout the entire back barrier region 104. Alternatively, the back barrier region 104 may be a gradient back barrier region, for example as described in U.S. application Ser. No. 15 / 352,115 to Curatola. According to this design, the back barrier region 104 includes a first back barrier region directly below the channel layer 106, and a second back barrier region below the first back barrier region. The first and second back barrier regions are each a III-V type semiconductor material region having a band gap different from each other. For example, the first back barrier region may be a first layer of AlGaN, and the second back barrier region may be a second layer of AlGaN, wherein the aluminum content is higher than in the first back barrier region. An intentionally doped AlGaN region (e.g., a carbon-doped AlGaN region) may be provided below the second back barrier region 104. In addition, in this embodiment, the channel layer 106 may be an intrinsic layer of pure or substantially pure GaN. Alternatively, the channel layer 106 may include AlGaN with a very low Al content (e.g., less than 10%), and in addition or as an alternative, may include dopant atoms such as (e.g., carbon or iron). In addition, in this embodiment, the barrier layer 108 may be an AlGaN layer having a higher Al content (e.g., greater than 10%, 15%, 20%, etc.) than the channel layer 106.

[0028] The semiconductor device 100 further includes a first conductive input-output electrode 118 and a second conductive input-output electrode 120. Both the first and second input-output electrodes 118, 120 are formed on the barrier layer 108. The first and second input-output electrodes 118, 120 may include metals, such as nickel, copper, titanium, alloys thereof, metal nitrides, such as AlN, TiN, and highly doped semiconductors, such as polysilicon.

[0029] Both the first and second input-output electrodes 118, 120 are in ohmic contact with the first two-dimensional charge carrier gas 110. This can be provided by direct physical contact between the first and second input-output electrodes 118, 120 and the first two-dimensional charge carrier gas 110, for example as depicted. However, direct physical contact between the first two-dimensional charge carrier gas 110 and the first and second input-output electrodes 118, 120 is not necessary, and a variety of known techniques can be used to provide electrical connections.

[0030] The semiconductor device 100 further includes a gate structure 122. The gate structure 122 is formed on the barrier layer 108 between the first and second input-output electrodes 118, 120. The gate structure 122 includes a second semiconductor region 124 formed on the upper surface of the barrier layer 108. The material properties (e.g., doping concentration, thickness, etc.) of the second semiconductor region 124 are selected so that the second semiconductor region 124 applies an electric field to the first two-dimensional charge carrier gas 110 that locally depletes the first two-dimensional charge carrier gas 110 below the gate structure 122 (in the absence of any external bias). According to an embodiment, the second semiconductor region 124 includes p-type GaN. The gate structure 122 further includes a conductive gate electrode 126 formed on the doped semiconductor region 124. The gate electrode 126 may include a metal, such as nickel, copper, titanium, alloys thereof, metal nitrides, such as AlN, TiN, and highly doped semiconductors, such as polysilicon.

[0031] The semiconductor device 100 also includes first and second passivation layers 128, 130 formed on the heterojunction semiconductor body 102. The first passivation layer 128 covers and may directly contact the channel layer 106 in the region between the gate structure 122 and the first input-output electrode 118, and in the region between the gate structure 122 and the second input-output electrode 120. The second passivation layer 130 covers and may conform to the upper side of the first passivation layer 128. Exemplary materials suitable for the first and second passivation layers 128, 130 include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO X N Y ), to name a few examples. According to an embodiment, the first and second passivation layers 128, 130 include Si3N4.

[0032] According to an embodiment, the semiconductor device 100 is configured as a high electron mobility transistor, wherein the first input-output electrode 118 provides a drain of the device, the second input-output electrode 120 provides a source of the device, and the gate electrode 126 provides a voltage-controlled gate terminal that controls the electrical connection between the source and drain terminals of the device. The first two-dimensional charge carrier gas 110 acts as a channel of the device and provides a conductive connection between the first and second input-output electrodes 118, 120. A control signal in the form of a voltage is applied to the gate electrode 126 to locally deplete (or refill) the first two-dimensional charge carrier gas 110 and thereby complete or interrupt the conductive connection between the first and second input-output electrodes 118, 120. Due to the provision of the second semiconductor region 124, the device is configured as a so-called "normally off" device. That is, in the absence of a voltage applied to the gate electrode 126, there is no conductive connection between the first and second input-output electrodes 118, 120, and a sufficient voltage (i.e., a threshold voltage V applied to the gate electrode 126) is sufficient to prevent the first two-dimensional charge carrier gas 110 from being depleted (or refilled) and the first two-dimensional charge carrier gas 110 from being depleted. TH ) refills the depleted region of the first two-dimensional charge carrier gas 110 and thereby completes the conductive connection between the first and second input-output electrodes 118 , 120 .

[0033] The barrier layer 108 includes a thinner section 136 and a thicker section 138. The thinner and thicker sections 136, 138 of the barrier layer 108 are adjacent to each other laterally, wherein a transition 142 is provided between the thicker and thinner sections 136, 138. The thinner section 136 has a first thickness, and the thicker section 138 has a second thickness greater than the first thickness. The thickness of the thinner and thicker sections 136, 138 is measured between a lower surface 144 of the barrier layer 108 facing the channel layer 106 and an upper surface 146 of the barrier layer 108 opposite to the lower surface 144. An exemplary thickness value for the second thickness (i.e., the thickness of the thinner section 136) can be in the range of, for example, 10-20 nanometers. An exemplary thickness value for the second thickness (i.e., the thickness of the thicker section 138) can be in the range of, for example, 20-50 nanometers. The difference between the thinner section 136 and the thicker section 138 (ie, the depth of the recess formed by the thinner section 136 ) may be in the range of, for example, 5-10 nanometers.

[0034] According to an embodiment, one or both of the thinner and thicker sections 136, 138 have a substantially uniform thickness along the entire lateral span of these regions. That is, the upper surface 146 of the barrier layer 108 extends parallel to the lower surface 144 of the barrier layer 108 in one or both of the thinner and thicker sections 136, 138.

[0035] At transition 142, an upper surface 146 of barrier layer 108 is disposed in thinner section 136 at an oblique angle relative to an immediately adjacent upper surface 146 of barrier layer 108. This oblique angle may be a vertical angle (i.e., as depicted), or more generally, any oblique angle (e.g., 30 degrees, 45 degrees, 60 degrees, etc.).

[0036] A gate structure 122 is formed on the thinner section 136 of the barrier layer 108 at a location laterally spaced apart from a transition 142 between the thicker and thinner sections 136, 138. In addition, a second input-output electrode 120 is formed on the thinner section 136 of the barrier layer 108. A first input-output electrode 118 is formed on the thicker section 138 of the barrier layer 108 and may also be laterally spaced apart from the transition 142 between the thicker and thinner sections 136, 138. Thus, a portion of the thinner section 136 and a portion of the thicker section 138 are provided between the gate structure 122 and the first input-output electrode 118.

[0037] In the depicted embodiment, the gate structure 122 and the second input-output electrode 120 are formed on a first planar segment 147 of the upper surface 146 of the barrier layer 108. The first planar segment 147 of the upper surface 146 of the barrier layer 108 is parallel to the lower surface 144 of the barrier layer 108 and extends to the transition 142. Thus, the gate structure 122 and the second input-output electrode 120 are formed on a uniform thickness portion of the barrier layer 108. Moreover, the first planar segment 147 of the upper surface 146 extends out from either side of the gate structure 122 such that the thickness of the barrier layer 108 directly below the gate structure 122 is the same as on portions of the barrier layer 108 directly adjacent to the gate structure 122 on either side. That is, the gate structure 122 is completely above the first planar segment 147 of the upper surface 146, and portions of the first planar segment 147 of the upper surface 146 are exposed from the gate structure 122 on either side of the gate structure 122. By separating the gate structure 122 from the transition 142 between the thicker and thinner sections 136, 138, the gate structure 122 is spaced from destructive electric fields. Additionally, the depicted geometry of the barrier layer 108 is easy to form using a photolithography process because it exceeds the minimum width of the photolithography process.

[0038] Configuring the barrier layer 108 to include thinner and thicker sections 136 , 138 , and lateral positioning of the gate structure 122 , first input-output electrode 118 , and second input-output electrode 120 in the manner described above results in a device having advantageous properties.

[0039] One such advantage of the configuration described above is that the threshold voltage (V TH ) and the drain-source on-state resistance (R DSON) are independently controlled. The threshold voltage of the device (V TH ) can be adjusted by appropriately tailoring the thickness of the barrier layer 108 below the gate electrode, i.e., by adjusting the thickness of the thinner section 136. The lower thickness reduces the carrier density of the first two-dimensional charge carrier gas 108 in the vicinity of the gate structure 122 and thus increases the threshold voltage. At the same time, the drain-source on-state resistance (R DSON ) can be independently adjusted by adjusting the thickness of the barrier layer 108 in the drift region, i.e., by adjusting the thickness of the thicker section 138. A larger thickness increases the carrier density of the first two-dimensional charge carrier gas 108 and thus increases the mobility of the channel in the region between the gate and drain of the device.

[0040] Another such advantage of the configuration described above is a robust gate structure 122 that can withstand high electric fields. This can be attributed to the provision of the gate structure 122 on a thinner portion of the barrier layer 108. Under large switching voltages (e.g., 400V or more between the first and second input-output electrodes 118, 120), the gate of the device and particularly the edge side closest to the drain of the device experience large electric fields. These electric fields can be mitigated by reducing the inversion layer density of the channel just below the gate-drain edge of the device. Therefore, the lower thickness of the barrier layer 108, which reduces this inversion layer density, hardens the gate structure 122 to withstand large electric fields.

[0041] Reference Figure 2 , depicts a semiconductor device 100 according to another embodiment. Figure 2 The semiconductor device 100 is equivalent to the reference Figure 1 The semiconductor device 100 described has the following differences. First, Figure 2 The semiconductor device 100 additionally includes a deep contact structure 131. Next, Figure 2 The semiconductor device 100 additionally includes a drain bias structure 140 .

[0042] The deep contact structure 131 extends through the barrier and channel layers 108, 106 and may extend into the back barrier region 104. Thus, the deep contact structure 131 directly interfaces with the second two-dimensional charge carrier gas 112. In the case where the back barrier region 104 has more than one two-dimensional charge carrier gas, such as described in U.S. application Ser. No. 15 / 352,115 to Curatola, the deep contact structure 131 may extend into the back barrier region 104 to directly interface with each of these secondary two-dimensional charge carrier gases.

[0043] The deep contact structure 131 provides an electrically conductive connection between the second two-dimensional charge carrier gas 112 and the second input-output electrode 120. Due to the electrical connection between the first contact material 132 and the second input-output electrode 120, a low-resistance path is provided for majority carriers present in the second two-dimensional charge carrier gas 112 to flow to and from the second input-output electrode 120. Therefore, the potential of the second two-dimensional charge carrier gas 112 is set to the potential of the second input-output electrode 120 by the deep contact structure 131.

[0044] The deep contact structure 131 includes a first contact material 132 extending through the barrier layer 106 and the channel layer 108 and directly interfacing with the second two-dimensional charge carrier gas 112. The first contact material 132 is selected to permit holes from the second two-dimensional charge carrier gas 112 to easily traverse an interface between the first contact material 132 and the second two-dimensional charge carrier gas 112.

[0045] In one embodiment, the first contact material 132 includes a doped semiconductor material, such as p-type GaN. This material can be appropriately doped to provide a low energy barrier (e.g., no greater than 0.2 eV) to the majority carriers of the two-dimensional charge carrier gas 112. This low energy barrier permits the majority carriers of the two-dimensional charge carrier gas 112 to traverse the interface between the channel layer 108 and the first contact material 132 (e.g., via thermionic emission).

[0046] In another embodiment, the first contact material 132 includes a conductive metal such as tungsten, aluminum, copper, titanium, titanium nitride, etc., and alloys thereof. The non-rectifying junction between the second two-dimensional charge carrier gas 112 and the first contact material 132 can be achieved by selecting a material that minimizes the barrier width and / or barrier height so that the majority carriers of the two-dimensional charge carrier gas 112 can traverse the interface (e.g., via thermionic emission or tunneling).

[0047] The first contact material 132 of the deep contact structure 131 is electrically connected to the second input-output electrode 120. In the depicted embodiment, the deep contact structure 131 also includes a first conductive region 134 formed on top of the first contact material 132 and directly contacting the second input-output electrode 120, thereby providing an electrical connection between the deep contact structure 131 and the first contact material 132. The first conductive region 134 can include a metal, such as aluminum, nickel, copper, titanium, alloys thereof, metal nitrides, such as AlN, TiN, and highly doped semiconductors, such as polysilicon. More generally, the first contact material 132 can be electrically connected to the second input-output electrode 120 in any conventionally known manner, and can optionally directly contact the second input-output electrode 120.

[0048] The drain bias structure 140 is formed on the thicker section 138 of the barrier layer 108 between the transition 142 and the first input-output electrode 118. The drain bias structure 140 includes a third semiconductor region 150 formed on the upper surface 146 of the barrier layer 108. The third semiconductor region 150 may include a semiconductor material of the same type and doping concentration as the second semiconductor region 124 and the first contact material 132 (e.g., p-type GaN). The drain bias structure 140 additionally includes a conductive connection between the third semiconductor region 150 and the first input-output electrode 118. Therefore, the third semiconductor region 150 is set to the same potential (e.g., drain potential) as the first input-output electrode 118. In the depicted embodiment, the drain bias structure 140 includes a third conductive region 152 formed on top of the third semiconductor region 150. The third conductive region 152 may include a metal, such as aluminum, nickel, copper, titanium, alloys thereof, metal nitrides, such as AlN, TiN, and highly doped semiconductors, such as polysilicon. In the depicted embodiment, the third conductive region 152 is formed on the portion of the third semiconductor region 150 exposed from the first and second passivation layers 128, 130, and thus directly contacts the third semiconductor region 150. Thus, an electrical connection between the third semiconductor region 150 and the first input-output electrode 118 is provided through the third conductive region 152. More generally, the third semiconductor region 150 may be electrically connected to the first input-output electrode 118 in any conventionally known manner, and may optionally directly contact that first input-output electrode 118.

[0049] During operation of the semiconductor device 100, the drain bias structure 140 injects holes into the barrier and channel layers 108, 106. In doing so, dynamic switching losses caused by charge traps and / or lattice defects are mitigated.

[0050] In another embodiment (not shown), the semiconductor device 100 includes Figure 2 The deep contact structure 131 is depicted, but does not include the drain bias structure 140. In this embodiment, the deep contact structure 131 provides all of the benefits described herein.

[0051] Reference Figure 3-8 , showing selected process steps for forming a semiconductor device 100 according to an embodiment. These steps combined with conventionally known processing methods (not shown) can be used to form a semiconductor device according to reference Figure 1 and 2 The semiconductor device 100 of any one of the described embodiments.

[0052] Reference Figure 3, a heterostructure semiconductor body 102 is provided. According to an embodiment, the heterostructure semiconductor body 102 is formed using an epitaxial growth technique. According to this process, a base substrate 116 is initially provided. The base substrate 116 may be provided by a commercially available bulk semiconductor wafer (e.g., a silicon wafer) or may alternatively be provided by an epitaxially grown material. After providing the base substrate 116, a nucleation layer (not shown) may be formed on the base substrate 116. The nucleation layer may be a thin material layer that facilitates the growth of a III-V type semiconductor thereon. An example of such a material is AlN (aluminum nitride). An exemplary thickness value for the nucleation layer may be in the range of 100-200 nm. After forming the nucleation layer, the transition region 114, the back barrier region 104, the channel layer 106, and the barrier layer 108 may each be formed in succession using an epitaxial deposition technique. The metal content and / or doping concentration of each of these layers may be controlled during the epitaxial deposition of these layers to achieve the values ​​described previously. Additional doping steps may be performed after completing any of the transition region 114 , the back barrier region 104 , the channel layer 106 , and the barrier layer 108 .

[0053] Reference Figure 4 , the heterostructure semiconductor body 102 has been processed to form the thinner and thicker sections 136, 138 of the barrier layer 108. According to an exemplary technique, the heterostructure semiconductor body 102 is initially provided according to the techniques described above so that the barrier layer 108 has a first substantially uniform thickness across the entire lateral span of the heterostructure semiconductor body 102. The first thickness can be anywhere between 20 and 50 nanometers, for example. Subsequently, a first mask 154 is formed on the upper surface 146 of the barrier layer 108. The first mask 154 is patterned (e.g., using known photolithography techniques) with the desired geometry of the thicker section 138. That is, the first mask 154 is formed to cover the desired area of ​​the thicker section 138 and to expose the desired area of ​​the thinner section 136. In one example, the first mask 154 covers one side of the heterostructure semiconductor body 102 up to a first lateral edge 156 and exposes the other side of the heterostructure semiconductor body 102 up to a second, oppositely facing lateral edge 158. The material of the first mask 154 is configured to permit etching of the barrier layer 108 that is selective to the mask. Exemplary materials for the first mask 154 include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO x N y ), or more generally, any of a variety of photoresist materials, to name a few.

[0054] After patterning of the first mask 154, an etching process is performed to remove semiconductor material from the portion of the barrier layer 108 exposed by the first mask 154. According to an embodiment, an anisotropic etching process (such as an anisotropic wet chemical etching process) is used to remove the semiconductor material. The etching process is performed so that the exposed portion of the barrier layer 108 has a second thickness that is less than the first thickness. The second thickness can be, for example, less than about 20 nanometers, less than about 10 nanometers, or less than about 5 nanometers.

[0055] Instead of the technique described above, the barrier layer 108 may be processed using a reverse technique (not shown) to form the thinner and thicker sections 136, 138. According to this technique, the barrier layer 108 is initially formed to have a second thickness (e.g., between 5 and 10 nm). Subsequently, a mask is formed on the upper surface 146 of the barrier layer 108 and patterned to cover the desired area of ​​the thinner section 136. The mask is formed from an epitaxial growth hindering material such as, for example, silicon dioxide (SiO2). Subsequently, an epitaxial deposition process is performed, thereby forming the same material as the barrier layer 108 (e.g., AlGaN) on the unmasked portion of the barrier layer 108. This epitaxial deposition process is performed until the unmasked portion of the barrier layer 108 has the first thickness.

[0056] Reference Figure 5 After the barrier layer 108 has been processed to form the thinner and thicker sections 136, 138, a second mask 160 is formed on the upper surface 146 of the barrier layer 108. Exemplary materials for the second mask 160 include silicon nitride (SiN), silicon dioxide (SiO2), and silicon oxynitride (SiO x N y ), to name a few examples. The second mask 160 is patterned with the desired geometry of the deep contact structure 131. That is, openings corresponding to the locations of the deep contact structures 131 are formed in the second mask 160. After patterning of the second mask 160, an etching process is performed to remove semiconductor material from the portions of the barrier and channel layers 108, 106 exposed by the second mask 160. The etching process is performed until the contact trench 162 reaches the third III-V type semiconductor layer 110.

[0057] Reference Figure 6, after the contact trench 162 has been formed and the second mask 160 has been removed, a multilayer deposition process is performed. According to this process, a first layer of doped semiconductor material 164 is formed on the exposed surface of the heterostructure semiconductor body 102. This can be done using an epitaxial growth process. The first layer of doped semiconductor material 164 has a doping type opposite to the majority carriers of the first two-dimensional charge carrier gas 110 and a doping type the same as the majority carriers of the second two-dimensional charge carrier gas 112. For example, in the case of an AlGaN / GaN / AlGaN heterostructure semiconductor body 102 as described previously, the first layer of doped semiconductor material 164 includes p-type GaN. The first layer of doped semiconductor material 164 may have a doping type of approximately 1e 19 / cm 3 The total (net) doping concentration, where the concentration of the first conductivity type (e.g., p-type) dopant is 1e 19 / cm 3 To about 1e 17 / cm 3 in the range of.

[0058] The first layer of doped semiconductor material 164 is grown so that it completely fills the contact trench 162 and covers the upper surface 146 of the barrier layer 108, including the thinner section 136, the thicker section 138 and the transition 142. After the first layer of doped semiconductor material 164 is formed, a first conductive layer 166 is formed on top of the first layer of doped semiconductor material 164. This can be done using deposition techniques such as electroless deposition or electroplating. The material of the first conductive layer 166 corresponds to the material of the first, second and third conductive regions 134, 126 and 152 as described previously, i.e., aluminum, nickel, copper, titanium, etc., metal nitrides, such as AlN, TiN, etc., and alloys thereof.

[0059] Reference Figure 7 , a common lithography step is performed to structure the first layer of doped semiconductor material 164 and the first conductive layer 166 into discrete regions. According to this technique, a third mask (not shown) is formed over the first conductive layer 166 and patterned with the desired geometry of the gate structure 122, the drain bias structure 140, and the deep contact structure 131. Subsequently, an etching process is performed, thereby etching away the portions of the first layer of doped semiconductor material 164 and the first conductive layer 166 exposed from the third mask. This etching process can be a multi-step process, whereby different etchant chemistries are used to remove the first layer of doped semiconductor material 164 and the first conductive layer 166. Thus, the upper surface 146 of the barrier layer 108 between the gate structure 122, the drain bias structure 140, and the deep contact structure 131 is exposed.

[0060] Reference Figure 8After structuring the first layer of doped semiconductor material 164 and the first conductive layer 166, the first and second passivation layers 128, 130 are formed. This can be done using a deposition technique such as, for example, chemical vapor deposition (CVD). The first and second passivation layers 128, 130 are conformally deposited so as to cover the gate structure 122, the drain bias structure 140 and the deep contact structure 131 and the exposed upper surface 146 of the barrier layer 108 between these structures.

[0061] Reference Fig. 9 After forming the first and second passivation layers 128, 130, a third mask 168 is formed over the second passivation layer. The third mask 168 includes an etch-resistant material. An exemplary material for the third mask 168 includes silicon dioxide.

[0062] Reference Fig.10 , patterning the third mask 168 to include first and second openings 170, 172. The first opening 170 is formed directly above the deep contact structure 131. The second opening 172 is formed to partially overlap with the drain bias structure 140 so as to expose a portion of the heterostructure semiconductor body 102 adjacent to the drain bias structure 140 and a portion of the drain bias structure 140. After patterning the third mask 168, an etching process selective to the material of the first conductive layer 166 is performed to remove the passivation material and the semiconductor material. Thus, a first trench 176 is formed in the heterostructure semiconductor body 102 adjacent to the deep contact structure 131, and a second trench 178 is formed in the heterostructure semiconductor body 102 adjacent to the drain bias structure 140. The etching process may be performed so that the first and second trenches 176, 178 reach the first two-dimensional charge carrier gas 108. According to other embodiments, no etching of the semiconductor material is necessary and only etching of the passivation layer is required to form an ohmic contact to the first two-dimensional charge carrier gas 108 .

[0063] Reference Fig.11 , a conductive material, such as aluminum, copper, polysilicon, etc., is deposited in the first and second trenches 176, 178. This can be accomplished using any of a variety of deposition techniques, including electroplating, electroless deposition, and epitaxy, to name a few. Thus, first and second input-output electrodes 118, 120 are formed, as well as interconnect structures connecting the first and second input-output electrodes 118, 120 to the drain bias structure 140 and the deep contact structure 131, respectively.

[0064] Reference Figure 3-11 The described technique illustrates the use of the reference Figure 2 The example of the semiconductor device 100 described above includes both the deep contact structure 130 and the drain bias structure 140. A corresponding semiconductor device 100 that does not include one or both of these structures can be obtained by omitting the relevant steps (e.g. Figure 5 contact trench 162 etching) and / or by appropriately performing a photolithography step (e.g., see Figure 7 The mask deposition and etching steps described above are omitted to form these structures.

[0065] Reference Figure 12-13 , shows selected method steps for forming a semiconductor device 100 according to another embodiment. In this embodiment, a different sequence is performed so that the drain bias structure 140 does not include a metal electrode.

[0066] Reference Fig.12 , a heterostructure semiconductor body 102 is provided and processed to include a multi-thickness barrier layer 108, a gate structure 122, a deep contact structure 131 and a drain bias structure 140. This can be described in detail with reference to FIG. Figure 3-7 Then, for example, with reference to Figure 8 The first passivation layer 128 is formed in the manner described above. Different from the previously described method, in forming Figure 8 Before forming the second passivation layer 130 on the first passivation layer 128 shown in , a fourth mask 174 is formed directly on the first passivation layer 128. The fourth mask 174 is patterned to include a third opening 176 directly above the drain bias structure 140. The formation and patterning of the fourth mask 174 can be completed using the techniques described previously. Subsequently, an etching technique is used to remove the exposed portion of the first passivation layer 128 and the underlying conductive material of the first conductive layer 166 formed on the third doped semiconductor region 150. This can be done using the etching techniques described previously.

[0067] Reference Fig.13 After removing the exposed portion of the first passivation layer 128 and the underlying conductive material of the first conductive layer 166 formed on the third doped semiconductor region 150, a second passivation layer 130 is deposited on top of the first passivation layer 128. The second passivation layer 130 may be deposited according to the techniques previously described and with particular reference to Figure 8 The second passivation layer is formed by the techniques described above.

[0068] Reference Fig.14 After patterning the first and second passivation layers 128, 130 to include the first and second openings 172, 174, first and second trenches 176, 178 are formed in the heterostructure semiconductor body 102. This can be done using the previous reference Figure 9-10The masked etching technique described above is performed. According to this process, the p-type material on the top of the deep contact structure 131 can be removed. Subsequently, a conductive material, such as aluminum, copper, polysilicon, etc., is deposited in the first and second openings 172 and 174. Thus, the first and second input-output electrodes 118 and 120, and the interconnection structures connecting the first and second input-output electrodes 118 and 120 to the drain bias structure 140 and the deep contact structure 131, respectively, are formed.

[0069] The processing steps described above advantageously provide a reliable and cost-effective method for forming the semiconductor device 100. In particular, one advantage is the reduced process complexity by forming several of the device features together using common lithography steps. In particular, as described with reference to Figure 6-7 As described, the deep contact structure 131, the gate structure 122, and the drain bias structure 140 are formed by a common process, whereby a single layer of doped III-V type semiconductor material and a single layer of conductive material are used to form the semiconductor and metal regions for each of these structures, respectively, and a single mask is used to define each of these features.

[0070] Another advantage of the processing steps described above is the high degree of controllability and precision over the electrical properties of the semiconductor device 100. As previously discussed, the thickness of the barrier layer 108 in the thinner and thicker regions plays a significant role in the parameters of the device. There is a reliability factor R determined by the ratio of the lateral separation distance from the gate structure 122 to the transition 142 to the lateral separation distance from the gate structure 122 to the first input-output contact 118. DSON For example, to improve R DSON, the designer can form the device so that the gate structure 122 is very close to the transition 142, thereby increasing the ratio of the amount of drift path including the thicker barrier layer 108 to the amount of drift path including the thinner barrier layer 108. However, this is achieved at the expense of reliability because the closer transition increases the supply of carriers at the gate-drain edge. Therefore, the designer can select a compromise that best suits the needs of the application by appropriately trimming the distance between the gate structure 122 and the transition 122. In one example of this technology, the semiconductor device 100 is optimized with respect to the ratio of the distance from the gate structure 122 to the transition 142 to the distance from the gate structure 122 to the first input-output electrode 118 (e.g., the drain electrode). In various embodiments, this ratio can range between 0.25 and 0.5 for optimal performance. Among other things, this ratio depends on the maximum rated voltage of the device. The distance from the gate structure 122 to the first input-output electrode 118 may be in the range of 2-3 microns for a 100V rated transistor and in the range of 10-11 microns for a 500V rated transistor. Figure 4-5 The masked etching step described is easily controlled so that different ratios can be selected with a high degree of precision using relatively inexpensive processes.

[0071] In the embodiments described above, the transition region 114, the back barrier region 104, the channel layer 106 and the barrier layer 108 are described as regions of AlGaN, AlGaN, AlGaN and AlGaN, respectively. These materials are for illustrative purposes only. More generally, any of a variety of combinations of III-V semiconductor materials can be used to provide the device concepts described herein. Examples of these III-V semiconductor materials for these regions include any compound semiconductor materials based on III nitrides. For example, GaN can be combined with AlGaN or InGaN to form an electron gas inversion region as a channel. The compound semiconductor device 100 can have an AlInN / AlN / GaN barrier / spacer / first III-V type semiconductor layer 104 structure. In general, any suitable III nitride technology can be used to realize a normally-off compound semiconductor transistor, such as GaN that permits the formation of an opposite polarity inversion region due to the piezoelectric effect. Broadly speaking, the compound semiconductor transistor described herein can be formed by any binary, ternary or quaternary III nitride compound semiconductor material, wherein the piezoelectric effect is responsible for the device concept.

[0072] The term HEMT is also commonly referred to as HFET (heterostructure field effect transistor), MODFET (modulation doped FET), and MESFET (metal semiconductor field effect transistor). The terms HEMT, HFET, MESFET, and MODFET are used interchangeably herein to refer to any III-nitride based compound semiconductor transistor that incorporates a junction between two materials with different band gaps (i.e., a heterojunction) as a channel.

[0073] As used in this specification, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together - intervening elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohmic electrical connection between elements that are electrically connected together, such as a connection via a metal and / or a highly doped semiconductor.

[0074] As used herein, the terms "having", "containing", "including", "comprising", etc. are opening terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0075] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

1. A method for forming a semiconductor device, the method comprising: A heterojunction semiconductor body is provided, the heterojunction semiconductor body comprising a first III-V type semiconductor layer and a second III-V type semiconductor layer formed on the first III-V type semiconductor layer, the second III-V type semiconductor layer having a different band gap than the first III-V type semiconductor layer, such that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V type semiconductor layers, wherein the heterojunction semiconductor body is provided such that the second III-V type semiconductor layer comprises a thicker section and a thinner section, forming a first input-output electrode on the thicker section of the second III-V type semiconductor layer, the first input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas; forming a second input-output electrode on the thinner section of the second III-V type semiconductor layer, the second input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas; as well as forming a gate structure on the thinner section of the second III-V type semiconductor layer, the gate structure being configured to control a conductive connection between the first and second input-output electrodes, wherein the gate structure is laterally spaced apart from a transition between thicker and thinner sections of the second III-V type semiconductor layer, wherein the thinner section of the second III-V type semiconductor layer includes a first planar upper surface extending along a single plane and reaching a transition, the first planar upper surface being opposite to a lower surface of the second III-V type semiconductor layer facing the first III-V type semiconductor layer, and wherein the gate structure and the second input-output electrode are formed on the first planar upper surface, The forming of the gate structure comprises: forming a first doped III-V type semiconductor region on the first planar upper surface; as well as forming a conductive gate electrode on the first doped III-V type semiconductor region, and Wherein the complete lower side of the first doped III-V semiconductor region faces the first planar upper surface and is coplanar therewith, and wherein the material properties of the first doped III-V semiconductor region locally deplete the first two-dimensional charge carrier gas in the absence of an external bias such that the semiconductor device is normally-off.

2. The method of claim 1 further comprises forming a first electrically insulating passivation layer on the heterojunction semiconductor body after forming the gate structure, wherein the first passivation layer directly conforms to an upper surface of the second III-V type semiconductor layer in thinner sections, thicker sections, and transitions between the thicker and thinner sections.

3. The method of claim 2, further comprising: forming a drain bias structure on the thicker section of the second III-V semiconductor layer, the drain bias structure comprising a second doped III-V semiconductor region on an upper surface of the second III-V semiconductor layer and an electrical connection between the second doped III-V semiconductor region and the first input-output electrode, The drain bias structure and the gate structure are both formed by a common photolithography process, and the common photolithography process includes: depositing a doped III-V type semiconductor material layer on an upper surface of the second III-V type semiconductor layer over the thinner section, the thicker section, and the transition; depositing a first conductive layer on the doped III-V type semiconductor material layer over the thinner section, the thicker section, and the transition; and The doped III-V type semiconductor material layer and the conductive layer are structured to form a gate structure and a second doped III-V type semiconductor region, wherein the second conductive region is on top of the second doped III-V type semiconductor region.

4. The method of claim 3, wherein a first electrically insulating passivation layer is formed to cover the second doped III-V type semiconductor region and the second conductive region, the method further comprising: etching an opening in the first electrically insulating passivation layer exposing the second conductive region; etching a trench in the heterostructure semiconductor body adjacent to the second doped III-V semiconductor region; A conductive material is deposited on the exposed second conductive region and in the trench to form an electrical connection between the first input-output electrode and the second doped III-V type semiconductor region and the first input-output electrode.

5. The method of claim 3, wherein a first electrically insulating passivation layer is formed to cover the second doped III-V type semiconductor region and the second conductive region, the method further comprising: etching an opening in the first electrically insulating passivation layer exposing the second conductive region; removing the exposed second conductive region so as to expose the second doped III-V type semiconductor region; depositing a second electrically insulating passivation layer covering the first electrically insulating passivation layer and the second doped III-V type semiconductor region; etching an opening in the second electrically insulating passivation layer exposing a second doped III-V semiconductor region; etching a trench in the heterostructure semiconductor body adjacent to the second doped III-V semiconductor region; A conductive material is deposited on the exposed second doped III-V type semiconductor region and in the trench to form an electrical connection between the first input-output electrode and the second doped III-V type semiconductor region and the first input-output electrode.

6. The method of claim 1, wherein the heterojunction semiconductor body further comprises a second two-dimensional charge carrier gas disposed below the first two-dimensional charge carrier gas, the second two-dimensional charge carrier gas having a majority carrier type opposite to the first two-dimensional charge carrier gas, and wherein the method further comprises: A deep contact structure is formed in the heterojunction semiconductor body interfacing with the second two-dimensional charge carrier gas and electrically connected to the second input-output electrode.

7. The method of claim 6, wherein forming a deep contact structure comprises: forming a trench in the heterojunction semiconductor body extending from an upper surface of the second III-V type semiconductor layer to the second two-dimensional charge carrier gas; filling the trench with a first contact material directly interfacing with the second two-dimensional charge carrier gas; as well as A second input-output electrode is formed on top of the contact material.

8. The method of claim 7, wherein the first contact material comprises a doped semiconductor material that provides a low energy barrier to carriers in the second two-dimensional charge carrier gas.

9. A method for forming a semiconductor device, the method comprising: providing a base substrate; forming a first III-V type semiconductor layer on a base substrate; forming a second III-V type semiconductor layer on top of the first III-V type semiconductor layer, the second III-V type semiconductor layer having a different band gap than the first III-V type semiconductor layer such that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V type semiconductor layers; processing the second III-V type semiconductor layer to form thinner and thicker sections of the second III-V type semiconductor layer, forming a first input-output electrode on the thicker section of the second III-V type semiconductor layer, the first input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas; as well as forming a second input-output electrode on the thinner section of the second III-V type semiconductor layer, the second input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas; as well as forming a gate structure on the thinner section of the second III-V type semiconductor layer, the gate structure being configured to control a conductive connection between the first and second input-output electrodes, wherein the gate structure is disposed entirely above a first planar upper surface of the second III-V type semiconductor layer, the first planar upper surface extending from below the gate structure at either side of the gate structure, The forming of the gate structure comprises: forming a first doped III-V type semiconductor region on the first planar upper surface; as well as forming a conductive gate electrode on the first doped III-V type semiconductor region, and Wherein the complete lower side of the first doped III-V semiconductor region faces the first planar upper surface and is coplanar therewith, and wherein the material properties of the first doped III-V semiconductor region locally deplete the first two-dimensional charge carrier gas in the absence of an external bias such that the semiconductor device is normally-off.

10. The method of claim 9, wherein the thinner segment has a first generally uniform thickness along a first lateral region extending from under the gate structure to a transition between the thinner and thicker segments, and wherein the thicker segment has a second generally uniform thickness along a second lateral region extending from the transition to the first input-output electrode.

11. The method of claim 10, wherein the second substantially uniform thickness is between 20 and 50 nanometers, and wherein the first substantially uniform thickness is less than 20 nanometers.

12. The method of claim 11, wherein forming the second III-V semiconductor layer comprises growing the second III-V semiconductor layer to have a second substantially uniform thickness across an entire lateral extent of the second III-V semiconductor layer, and wherein processing the second III-V semiconductor layer to form the thinner and thicker sections comprises: covering the area of ​​the second III-V semiconductor layer corresponding to the thicker section with a patterned mask; as well as Semiconductor material is etched away from the second III-V type semiconductor layer until areas of the second III-V type semiconductor layer not covered by the etch-resistant mask have a first substantially uniform thickness.

13. A semiconductor device comprising: A heterojunction semiconductor body comprising a first III-V type semiconductor layer and a second III-V type semiconductor layer formed on the first III-V type semiconductor layer, the second III-V type semiconductor layer having a different band gap than the first III-V type semiconductor layer, such that a first two-dimensional charge carrier gas is formed at an interface between the first and second III-V type semiconductor layers, wherein the second III-V type semiconductor layer comprises a thicker section and a thinner section, a first input-output electrode on the thicker section of the second III-V type semiconductor layer, the first input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas, and a second input-output electrode on the thinner section of the second III-V type semiconductor layer, the second input-output electrode being in ohmic contact with the first two-dimensional charge carrier gas; as well as a gate structure formed on the thinner section of the second III-V type semiconductor layer, the gate structure being configured to control a conductive connection between the first and second input-output electrodes, wherein the gate structure is laterally spaced apart from a transition between thicker and thinner sections of the second III-V type semiconductor layer, wherein the thinner section of the second III-V type semiconductor layer includes a first planar upper surface extending along a single plane and reaching a transition, the first planar upper surface being opposite to a lower surface of the second III-V type semiconductor layer facing the first III-V type semiconductor layer, and wherein the gate structure and the second input-output electrode are formed on the first planar upper surface, The gate structure includes: a first doped III-V type semiconductor region on the first planar upper surface; as well as a conductive gate electrode on the first doped III-V type semiconductor region, and Wherein the complete lower side of the first doped III-V semiconductor region faces the first planar upper surface and is coplanar therewith, and wherein the material properties of the first doped III-V semiconductor region locally deplete the first two-dimensional charge carrier gas in the absence of an external bias such that the semiconductor device is normally-off. 14 . The semiconductor device of claim 13 , wherein the gate structure is disposed entirely above a first planar upper surface of the second III-V type semiconductor layer, the first planar upper surface extending out from under the gate structure at either side of the gate structure.

15. The semiconductor device of claim 13, wherein the thinner section has a first generally uniform thickness along a first lateral region extending from the second input-output electrode to the transition, and wherein the thicker section has a second generally uniform thickness along a second lateral region extending from the transition to the second input-output electrode.

16. The semiconductor device of claim 13, further comprising: a drain biasing structure formed on the thicker section of the second III-V semiconductor layer, the drain biasing structure comprising a second doped III-V semiconductor region on an upper surface of the second III-V semiconductor layer; a first passivation layer conforming to the upper surface of the second III-V type semiconductor layer in the thinner sections, the thicker sections, and the transitions between the thinner and thicker sections; a second passivation layer disposed on the first passivation layer and disposed over the thinner sections, the thicker sections, and the transition between the thicker and thinner sections; a second opening in the second passivation layer exposing an upper side of a second doped III-V type semiconductor region; as well as A conductive interconnect structure is formed in the second opening and electrically connects the second doped III-V type semiconductor region with the second input-output electrode. 17 . The semiconductor device of claim 13 , wherein the second input-output electrode is formed on a thinner section of the second III-V type semiconductor layer.

18. The semiconductor device of claim 13, wherein the heterojunction semiconductor body further comprises a second two-dimensional charge carrier gas disposed below the first two-dimensional charge carrier gas, the second two-dimensional charge carrier gas having a majority carrier type opposite to that of the first two-dimensional charge carrier gas, and wherein the semiconductor device further comprises a deep contact structure forming a conductive connection between the second two-dimensional charge carrier gas and the second input-output electrode.

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