Semiconductor device having high voltage field effect transistor and junction field effect transistor

Abstract

The present invention relates to a semiconductor device having a high voltage field effect transistor and a junction field effect transistor. A semiconductor device is described, which includes: a first N-type well region arranged in a substrate and a second N-type well region in contact with the first N-type well region; a source region arranged in the first N-type well region; a drain region arranged in the second N-type well region; and a first gate electrode and a second gate electrode arranged to be spaced apart from the drain region. In a plan view, the maximum vertical length of the source region in a direction perpendicular to the first gate electrode or the second gate electrode is greater than the maximum vertical length of the drain region in the direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation-in-part of U.S. application No. 15 / 915,105, filed on March 8, 2018, which is a continuation-in-part of U.S. application No. 14 / 942,527, filed on November 16, 2015, which claims the benefit of Korean Patent Application No. 10-2015-0047731 filed in the Korean Intellectual Property Office on April 3, 2015 under 35 U.S.C. § 119(a), and also claims the benefit of Korean Patent Application No. 10-2018-0041261 filed on April 9, 2018 under 35 U.S.C. § 119(a), the entire contents of each of which are incorporated herein by reference for all purposes. Technical Field

[0003] The following description relates to a semiconductor device including a high voltage field effect transistor (HVFET) and a junction field effect transistor (JFET) having a common drain structure. In addition, the following description also relates to a semiconductor device including a JFET configured to control a pinch-off voltage and a current in the HVFET. Background Art

[0004] A high voltage field effect transistor (HVFET) is a device that controls the passage of electric power, has tens to hundreds of voltages associated with the power, and performs switching of such high voltage power. The HVFET must have high voltage resistance so that breakdown does not occur even at high voltages, so as to block current in the off state, and also have a small on-resistance value to reduce power loss in the on state.

[0005] A junction field effect transistor (JFET) is a device included in such a high voltage power controller having an HVFET, and the circuit controlling the gate of the HVFET includes a low voltage transistor; therefore, the JFET limits the voltage and current applied to the circuit so that they cannot exceed the threshold by pinching off.

[0006] The HVFET and JFET in the related art use a relatively large area to perform the above-mentioned features. Therefore, the HVFET and JFET have difficulty in miniaturization.

[0007] In order to solve the above problems, the related art discloses a high voltage transistor and a method for manufacturing a high voltage transistor combined with a junction transistor. However, the junction transistor according to the above technology uses the well region used in the drain drift region of the high voltage transistor as the channel region of the junction field effect transistor. The doping concentration of the well region is determined according to the on-resistance characteristics of the high voltage transistor, and the structure of the buried impurity layer is determined. Therefore, there is a problem that it is difficult to control the current-voltage of the junction transistor accordingly. Summary of the invention

[0008] This summary is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0009] The following description relates to a semiconductor device having characteristics of a junction transistor and a high voltage transistor and a method of manufacturing the same, which improves integration by minimizing the area.

[0010] Furthermore, the following description relates to a semiconductor device having a junction transistor and a manufacturing method thereof, which can control the pinch-off characteristics of the junction transistor while maintaining the on-resistance (Rsp) characteristics of the high voltage transistor.

[0011] In one general aspect, a semiconductor device includes: a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region; a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region; and a first gate electrode and a second gate electrode disposed apart from the drain region, wherein, in a plan view, a maximum vertical length of the source region in a direction perpendicular to the first gate electrode or the second gate electrode is greater than a maximum vertical length of the drain region in the direction.

[0012] The source region and the drain region may be disposed between the first gate electrode and the second gate electrode.

[0013] The first N-type well region and the source region may include a junction field effect transistor (JFET), and the JFET has a rectangular shape in a plan view.

[0014] In a plan view, a vertical length of the rectangular shape in a vertical direction may be greater than a horizontal length in a horizontal direction.

[0015] A cross-sectional area of ​​the first N-type well region may be smaller than a cross-sectional area of ​​the second N-type well region.

[0016] Relative to the top surface of the substrate, the maximum depth of the first N-type well region may be correspondingly less than or equal to the maximum depth of the second N-type well region.

[0017] The semiconductor device may further include a P-type gate region disposed in the first N-type well region.

[0018] The drain region, the first gate electrode, and the second gate electrode of the semiconductor device may include a high voltage field effect transistor (HVFET).

[0019] In another general aspect, a semiconductor device includes: a first gate electrode disposed on a substrate; a second gate electrode disposed on the substrate; and a first source region and a first drain region disposed between the first gate electrode and the second gate electrode, wherein the first source region has a maximum vertical length in a first direction perpendicular to the first gate electrode or the second gate electrode and has a maximum width in a second direction perpendicular to the first direction, and wherein the maximum vertical length of the first source region is greater than the maximum width.

[0020] The semiconductor device may further include a well region, and a source region and a drain region are disposed in the well region.

[0021] The semiconductor device may further include a third gate electrode disposed on the substrate, and a second source region and a second drain region disposed between the second gate electrode and the third gate electrode.

[0022] The first and second source regions may include junction field effect transistors (JFETs), and wherein the first, second and third gate electrodes and the first and second drain regions include high voltage field effect transistors (HVFETs).

[0023] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram showing a semiconductor device according to an embodiment.

[0025] Figure 2 is a top view of a semiconductor device according to a comparative example.

[0026] Figure 3 is a top view of an embodiment of a semiconductor device.

[0027] Figure 4 yes Figure 3 An enlarged view of a portion of a semiconductor device.

[0028] Figure 5 It is along Figure 3 1 is a cross-sectional view of the semiconductor device 1 taken along line AA′.

[0029] Figure 6 (a) and Figure 6 (b) Yes Figure 31 is a cross-sectional view of an embodiment of a semiconductor device 1 along line BB′.

[0030] Figure 7 is a top view of another embodiment of a semiconductor device.

[0031] Figure 8 (a) and Figure 8 (b) Yes Figure 7 1 is a cross-sectional view of an embodiment of a semiconductor device 1 along line CC′.

[0032] Fig. 9 (a) and Fig. 9 (b) Yes Figure 7 2 is a cross-sectional view of an embodiment of a semiconductor device 1 along line DD′.

[0033] Fig.10 is a top view of another embodiment of a semiconductor device.

[0034] Fig.11 is a top view of an embodiment of a semiconductor device.

[0035] Fig.12 is a VI graph according to the operation of the semiconductor device according to the embodiment and the comparative example.

[0036] Fig.13 (a) and Fig.13 (b) is a contour diagram of equipotential electric field lines of the semiconductor devices of the comparative example and the embodiment.

[0037] Like reference numerals refer to like elements throughout the drawings and detailed description. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0038] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be obvious. For example, the order of operations described herein is merely an example and is not limited to those set forth herein, but it is obvious after understanding the disclosure of the present application that, except for the operations that must occur in a specific order, the order of these operations can be changed. In addition, for greater clarity and brevity, the description of features known in the art may be omitted.

[0039] The features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, it will be apparent after understanding the disclosure of the present application that the examples described herein have been provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein.

[0040] Throughout the specification, when an element such as a layer, a region or a substrate is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the element, or one or more other elements may be present in between. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there are no other elements in between.

[0041] For ease of description, spatial relational terms such as "above", "on the upper part of", "below", and "below" may be used herein to describe the relationship of one element to another element, as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, such spatial relational terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, an element described as "above" or "on the upper part of" relative to another element will become "below" or "below" relative to another element. Therefore, the term "above" covers both the upper and lower orientations depending on the spatial orientation of the device. The device can also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relational terms used herein should be interpreted accordingly.

[0042] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. The articles "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise. The terms "comprise", "include" and "have" specify the presence of the features, numbers, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements and / or combinations thereof.

[0043] For convenience of explanation, in the top view of the semiconductor device, a portion where the external electrode D is provided is referred to as a head, and a portion in which the common drain region connected to the external electrode D is divided into two portions and arranged long is referred to as a tail. However, it will be clearly understood that the embodiments of the following disclosure are not limited to the above names, and it is obvious to those skilled in the art that various names may be made.

[0044] In addition, in the following description, in an embodiment, if the substrate of the semiconductor device is of P type, the well region may be of N type. In another embodiment, if the substrate of the semiconductor device is of N type, the well region may be of P type.

[0045] The following description is provided to propose a semiconductor device having structures of a junction field effect transistor (JFET) and a high voltage field effect transistor (HVFET) that minimize the area, thereby improving integration.

[0046] The following description is also provided to propose a semiconductor device having a JFET whose pinch-off characteristics can be controlled while maintaining the on-resistance characteristics of the HVFET.

[0047] The following description is also provided to propose a semiconductor device having a JFET, the amount of current can be controlled while maintaining the on-resistance characteristics of the JFET.

[0048] The following description is also provided to propose a semiconductor device that allows the electric field of the HVFET to be uniformly distributed without being affected by the addition of the JFET.

[0049] It is obvious after understanding the disclosure of the present application that the features of the examples described herein can be combined in various ways. In addition, although the examples described herein have various configurations, it will be obvious after understanding the disclosure of the present application that other configurations are also possible.

[0050] Figure 1 is a block diagram showing a semiconductor device according to an embodiment.

[0051] according to Figure 1 , in order to realize a junction field effect transistor (JFET) 10 and a high voltage field effect transistor (HVFET) 20. Here, the JFET 10 is also referred to as a Tap-JFET. The semiconductor device 1 converts an alternating current (AC) input 3 into a high voltage direct current (DC) voltage signal at a rectifier 2, and receives the DC voltage signal. In the HVFET 20, an application device 6 is connected to the source S terminal, and a control IC 5 is connected to the gate G terminal. In one embodiment, the application device 6 connected to the semiconductor device 1 may be a USB type, and in another embodiment may be an LED lighting driver, but the embodiments of the present specification are not limited thereto, and include various devices using HVFET and JFET at the same time. The JFET 10 and the HV NMOS 20 are integrated into one chip 1. One chip (semiconductor device) 1 can integrate the JFET 10 and the HV NMOS 20 using one common drain. The entire chip area is reduced by embedding the JFET 10 in a specific area of ​​the HVFET 20.

[0052] Figure 2is a plan view of a semiconductor device according to a comparative example.

[0053] Reference Figure 2 , the semiconductor device 1 ′ includes a HVFET 20 and a JFET 10 .

[0054] The JFET 10 includes an N-type source region (first N+ doping region) 110 -S, an N-type drain region 140 -D (second N+ doping region), and a P-type gate region 170 , and the JFET 10 includes a first N-type well region 310 .

[0055] The HVFET 20 includes an N-type drain region (second N+ doping region) 140-D, N-type HVFET source regions 210-S, 211-S (third N+ doping region), a second N-type well region 320, and P-type well regions 112-1, 112-2 formed in the substrate 201. The HVFET 20 shares the drain region 140-D with the JFET 10. Therefore, the drain region 140-D becomes a common drain region for the JFET 10 and the HVFET 20.

[0056] In the semiconductor device 1' of the comparative example, the source region 110-S of the JFET 10 and the first N-type well region 310 extend outward to the boundary of the region of the HVFET 20, so that in a plan view, a T-shaped JFET 10 is formed in the semiconductor device 1'. The T-shaped JFET 10 has an additional area of ​​the first N-type well region 310. Due to the additional area of ​​the first N-type well region 310, the amount of N-type impurities (dopants) in the semiconductor device 1' will increase. The N-type impurities (dopants) and P-type impurities (dopants) in the semiconductor device 1' are unbalanced. That is, the electric field in the semiconductor device 1' of the comparative example is not uniformly distributed. Due to the increased amount of N-type impurities, the electric field will be locally concentrated on a certain part of the semiconductor device 1'. Therefore, the breakdown voltage in the semiconductor device 1' may be reduced (see Fig.12 in “old”).

[0057] Figure 3 3 is a plan view of an embodiment of a semiconductor device. The N-type well region 300 includes an N-type well region 310 and an N-type well region 320. For convenience of description, hereinafter, the N-type well region 310 of the JFET 10 is referred to as the first N-type well region 310, and the N-type well region 320 of the HVFET 20 is referred to as the second N-type well region 320. The area of ​​the first N-type well region 310 is significantly smaller than the area of ​​the second N-type well region 320. The smaller area of ​​the first N-type well region 310 is intended to minimize the increase in the total N-type dopant.

[0058] Reference Figure 3 , in a plan view (top view), the first N-type well region 310 of the JFET 10 of the semiconductor device 1 has a rectangular shape. Therefore, Figure 3 The area of ​​the first N-type well region 310 of the JFET 10 is smaller than Figure 2 The JFET 10 is embedded in the HVFET 20. That is, the JFET 10 is not formed to protrude outward from the boundary of the HVFET 20. Therefore, the overall shape of the HVFET 20 incorporating the JFET 10 is a rectangle.

[0059] Since the area of ​​the first N-type well region 310 is relatively small, Figure 2 Compared with the comparative example shown in FIG. 1 , the amount of N-type impurities does not increase much. The N-type impurities and P-type impurities in the semiconductor device 1 are balanced. Therefore, the semiconductor device 1 according to the embodiment can make the breakdown voltage within a predetermined range (see FIG. 1 ). Fig.12 ), and also minimize the chip size.

[0060] The semiconductor device 1 includes a JFET 10 in a first region 400 and a HVFET 20 in a second region 500. Both the N-type well region 310 and the N-type well region 320 are formed in a substrate 201. The source region 110-S of the JFET 10 is an N+ doped region formed in the first N-type well region 310. In the Y direction in a plan view, the vertical length of the source region 110-S of the JFET 10 is greater than the vertical length of the drain region 140-D of the HVFET 20. A P-type gate region 170 of the JFET 10 is formed between the first N-type well region 310 and the second N-type well region 320. The P-type gate region 170 is formed in the substrate 201.

[0061] The HVFET 20 includes a common drain region 140-D (a second N+ doped region), HVFET source regions 210-S, 211-S, and a gate electrode 221-G, as shown in the second region 500. In the Y direction in the plan view, the maximum vertical length of the source region 110-S of the JFET 10 is greater than the maximum vertical length of the drain region 140-D of the HVFET 20.

[0062] In addition, the HVFET 20 includes a P-type well region 112. In the P-type well region 112, a channel region of the HVFET 20 and a HVFET source region 210-S are formed.

[0063] The HVFET 20 may further include a field plate 160. The field plate 160 may include metal or polysilicon to reduce an electric field on the semiconductor device 1, thereby increasing a breakdown voltage of the semiconductor device 1.

[0064] Figure 4 This is an example of an embodiment of the present specification. Figure 3 An enlarged view of the area 400. Figure 4, the N-type well region 300 includes, in a direction parallel to the surface of the substrate 201: a first N-type well region 310 having a first width W1; and a second N-type well region 320 having a second width W2. The first N-type well region 310 includes the source region 110-S (first N+-doped region) of the JFET 10, such that the source region of the JFET 10 and the first N-type well region 310 can be formed into a rectangular shape. In a plan view, the source region 110-S of the JFET 10 has a vertical length SL1 greater than the horizontal length (width) SW1. The current of the JFET depends on the vertical length SL1 of the source region 110-S and the width SW1 of the source region 110-S. If the vertical length SL1 of the source region 110-S increases, the current of the JFET10 increases. In a plan view, the first N-type well region 310 of the JFET 10 also has a vertical length L1 greater than the horizontal length (width, W1).

[0065] Figure 5 is a cross-sectional view of an embodiment of the semiconductor device 1, which is a cross-sectional view taken along Figure 3 line A-A' of the semiconductor device 1.

[0066] Referring to Figure 5 , in the semiconductor device 1, a well region 300 is formed in the substrate 201. In an embodiment, if the substrate has P-type conductivity, the well region may have N-type conductivity. In another embodiment, if the substrate has N-type conductivity, the well region may have P-type conductivity. The first N-type well region 310 of the JFET 10 is disposed in the substrate 201 and has a first depth d1. A first N+-doped region 110-S is disposed in the first N-type well region 310.

[0067] The semiconductor device 1 further includes a second N+-doped region 140-D in the N-type well region 300. The first N+-doped region 110-S and the second N+-doped region 140-D are disposed on the top surface of the substrate with a space therebetween. The first N+-doped region is the source region of the JFET, and the second N+-doped region is the drain region of the JFET.

[0068] The N-type well region 300 includes: a first N-type well region 310 having a first depth d1 from the top surface of the substrate 201; and a second N-type well region 320 having a second depth d2 from the top surface of the substrate 201. According to various embodiments, the first depth d1 and the second depth d2 may be equal (that is, d1 = d2), or the first depth d1 may be less than the second depth d2 (that is, d1 < d2), as Figure 5 shown.

[0069] The semiconductor device 1 includes a P-type gate region 170, which is disposed in the N-type well region 300 and has a third depth that is less than the corresponding first depth and second depth. The P-type gate region 170 is disposed closer to the source region 110-S than the drain region 140-D. In an embodiment, the P-type gate region 170 can be maintained at a ground voltage, and in another embodiment, can be maintained at a different voltage.

[0070] In an embodiment, the semiconductor device 1 may further include a P+ doped region (not shown) in the P-type gate region 170. According to an embodiment, a ground voltage may be applied to the P+ doped region via a terminal (not shown), and according to another embodiment, a different voltage may be applied to the P+ doped region.

[0071] The drain region (ie, second N+ doping region) 140-D of the HVFET 20 and the JFET 10 is formed in the second N-type well region 320, and the drain region 140-D is formed as N-type and connected to a common drain terminal 150-D. The common drain terminal 150-D is made of a metal line.

[0072] The semiconductor device 1 may further include a field plate 160 on the surface of the field oxide film 120, which is disposed closer to the drain region 140-D than the source region 110-S. The field plate 160 is connected to the common drain region.

[0073] The source region 110-S of the JFET 10 is formed in the first N-type well region 310, and the source region 110-S is formed as an N-type and connected to a source terminal 250-S of the JFET 10. The source terminal 250-S is made of a metal wire.

[0074] The JFET source region and the first N-type well region 310 are formed in the boundary of the HVFET 20, but do not extend to the outside of the HVFET 20, as shown in FIG. Figure 3 As shown in . The first N-type well region 310 and the second N-type well region 320 are both initially formed to be spaced apart by a certain distance, and then, after undergoing a high-temperature heat treatment, meet at a certain point H. The second N-type well region 320 and the first N-type well region 310 are formed by ion implantation with equal impurity concentrations, and the diffusion region 330 is formed by diffusion of the ion-implanted N-type dopant.

[0075] The diffusion region 330 includes a recessed groove H. The N-type impurity concentration of the diffusion region 330 may be lower than the N-type impurity concentration of the first N-type well region 310 or the second N-type well region 320. The depth of the bottom surface of the diffusion region 330 may be lower than or equal to the depth of the bottom surface of the first N-type well region 310 or the second N-type well region 320.

[0076] According to an embodiment, the maximum depth d1 of the first N-type well region 310 may be equal to or different from the maximum depth d2 of the second N-type well region 320.

[0077] In an embodiment, depending on the area of the source region 110-S of the JFET, the maximum depth d1 of the first N-type well region 310 may be less than the maximum depth d2 of the second N-type well region 320 (d1 < d2), but in another embodiment, the corresponding depths may be made equal to each other (d1 = d2) by adjusting the implanted N-type impurity ions. However, the cross-sectional area of the first N-type well region 310 is much smaller than the cross-sectional area of the second N-type well region 320, and the same is true when observed in a plan view.

[0078] Since the overall N-type dopant concentration increases as the cross-sectional area of the first N-type well region 310 becomes larger, the overall N-type dopant concentration can be adjusted by the cross-sectional area of the first N-type well region 310. However, if the dopant concentration of the first N-type well region 310 exceeds a certain level, problems occur in terms of breakdown voltage; therefore, the degree of dopant implantation in the first N-type well region 310 is appropriately adjusted to such a concentration that the reduced surface field (RESURF) does not collapse.

[0079] The field oxide film 120 may be formed on the surface of the substrate between the drain region 140-D and the source region 110-S. The field oxide film 120 is formed by a local oxidation of silicon (LOCOS) process or a shallow trench isolation (STI) process.

[0080] The semiconductor device 1 may further include a buried impurity layer 130, and the buried impurity layer 130 may be electrically connected to the substrate 201 (see Figure 6 ). For example, the buried impurity layer 130 may be formed in the N-type well region 300 parallel to the top surface of the substrate 201. The buried impurity layer 130 may be doped with P-type impurity ions and may be formed to cross the second N-type well region 320, the first N-type well region 310, and the diffusion region 330. The buried impurity layer 130 is spaced apart from the field oxide film 120 by a certain distance and is below the field oxide film 120. The buried impurity layer 130 may be formed in the horizontal direction of the bottom surface of the field oxide film 120. In another example, the buried impurity layer 130 may be formed directly under the field oxide without space. In this specification, one buried impurity layer is proposed, but in another embodiment, at least two buried impurity layers may be formed to be spaced apart from each other in the vertical direction with respect to the top surface of the substrate 201. In addition, the breakdown voltage and on-resistance characteristics of the JFET 10 may vary depending on the number of the buried impurity layers 130.

[0081] The substrate 201 is connected to a ground reference voltage. The output voltage of the source terminal 250-S of the JFET 10 is determined according to the voltage difference between the substrate 201 and the drain region 140-D.

[0082] The P-type gate region 170 of the JFET 10 is formed by implanting P-type impurity ions into the N-type well region 300. The P-type gate region 170 is formed by the P-type buried impurity layer 130 in contact with the bottom surface of the field oxide film 120. The P-type gate region 170 of the JFET 10 is electrically connected to the substrate 201 and is grounded.

[0083] Pinch-off may occur due to the potential difference between the substrate 201 and the source region 110-S. Therefore, the pinch-off voltage V can be adjusted by applying a certain voltage to the source region 110-S of the JFET and setting the P-type gate region 170 to the ground voltage. pinch-off Because the common drain region 140-D is far away from the P-type gate region 170, the potential of the drain at the P-type gate region 170 becomes smaller. Depletion is usually caused by the source region 110-S near the P-type gate region 170, rather than by the potential difference between the drain and the P-type gate region, thereby causing pinch-off.

[0084] When pinch-off occurs in the diffusion region 330, the resistance of the N-type well region 300 between the common drain terminal 150-D and the source terminal 250-S of the JFET increases rapidly. Even if the input voltage of the common drain terminal 150-D keeps increasing, the output voltage of the source terminal 250-S is maintained at a certain pinch-off voltage. However, if the input voltage is less than or equal to the pinch-off voltage, the output voltage of the source terminal 250-S of the JFET increases in proportion to the input voltage of the common drain terminal 150-D. That is, even when a high input voltage is input to the drain region, the JFET 10 controls the voltage amount so that it does not exceed a specific voltage, thereby protecting the internal circuits (e.g., Figure 1 control integrated circuit).

[0085] Figure 6 (a) and Figure 6 (b) is a cross-sectional view of an embodiment of a semiconductor device, which is taken along Figure 3 1 is a cross-sectional view of the semiconductor device 1 taken along line BB′.

[0086] Reference Figure 6(a) In the semiconductor device 1 according to the embodiment, a second N-type well region 320 is provided in the substrate 201, and a common drain region 140-D is provided in one upper side of the well region 300. The common drain region 140-D is electrically connected to a common drain terminal 150-D, and a field oxide film 120 is formed on the remaining top surface of the substrate 201 or the second N-type well region 320 except for the common drain region 140-D.

[0087] The buried impurity layer 130 may be formed in the second N-type well region 320 and the P-type substrate 201, spaced apart from the bottom surface of the field oxide film 120 by a certain distance below the field oxide film 120. In another embodiment, the buried impurity layer 130 may be formed in the second N-type well region 320, contacting with the bottom surface of the field oxide film 120 instead of being spaced apart therefrom. In another embodiment, the buried impurity layer 130 may be a plurality of layers.

[0088] Reference Figure 6 (b) The semiconductor device 1 according to another embodiment may further include a body contact region 161 .

[0089] The body contact region 161 may be formed on the top surface of the substrate 201 where the second N-type well region 320 is not formed. The body contact region 161 is electrically connected to the pickup terminal 165. The bias to be applied to the substrate 201 varies depending on the bias applied to the pickup terminal 165, so that the pinch-off voltage of the JFET varies depending on the voltage difference between the common drain terminal 150-D and the pickup terminal 165.

[0090] The field oxide film 120 is formed between the drain region 140 -D and the body contact region 161 , and is formed on an upper surface of the substrate 201 or the second N-type well region 320 .

[0091] In addition, according to various embodiments, the semiconductor device 1 of the present specification may include a P-type gate region 170 , and a certain voltage may be applied to an electrode (not shown) connected to the P-type gate region 170 .

[0092] In addition, according to various embodiments, the semiconductor device 1 may include a body contact region 161 on the upper surface of the substrate 201 , and a bias may be applied to the pickup electrode 165 .

[0093] Figure 7 is a top view of an embodiment of a semiconductor device.

[0094] Reference Figure 7 , which is similar to Figure 3However, it also includes gate electrodes 221-G1 and 221-G2. The gate electrodes 221-G1 and 221-G2 serve as the gate electrodes of the HVFET 20. Each of the gate electrodes 221-G1 and 221-G2 is disposed in a region where the source region 110-S of the JFET is not provided. Each of the gate electrodes 221-G1 and 221-G2 is symmetrically disposed on two side surfaces of the substrate 201. In one example, the end of the gate electrode 221-G1 or 221-G2 can be formed to horizontally extend from the first N-type well region 310. The HVFET source regions 210-S and 211-S of the HVFET 20 are formed at the side surfaces of each gate electrode. A common drain region 140-D is provided between the first gate electrode 221-G1 and the second gate electrode 221-G2. The source region 110-S and the first N-type well region 310 are provided between the first gate electrode 221-G1 and the second gate electrode 221-G2. The source region 110-S of the JFET and the HVFET source regions 210-S and 211-S of the HVFET 20 are formed to be spaced apart from each other. Each of the P-type well regions 112-1 and 112-2 is formed adjacent to each of the gate electrodes 221-G1 and 221-G2 of the HVFET.

[0095] Figure 8 is Figure 7 a cross-sectional view of the semiconductor device shown in, which is a cross-sectional view of the semiconductor device 1 taken along the line C-C’ of Figure 7 .

[0096] In the semiconductor device 1 according to an embodiment, a field oxide film 120 is provided on the substrate 201.

[0097] Each of the gate electrodes 221-G1 and 221-G2 of the HVFET 20 is provided on the top surface of the field oxide film 120. The semiconductor device 1 further includes a P-type buried impurity layer 130 that is spaced apart from the bottom surface of the field oxide film and has a third depth d3.

[0098] The semiconductor device 1 further includes a first P-type well region 112-1 and a second P-type well region 112-2. As an embodiment, referring to Figure 8 (a), each of the first P-type well region 112-1 and the second P-type well region 112-2 is separately provided from the P-type buried impurity layer 130 and has a fourth depth d4 that is greater than the third depth d3 (d3 < d4). The semiconductor device 1 further includes a first P+-doped region 301-1 and a second P+-doped region 301-2 that are respectively provided in the first P-type well region and the second P-type well region.

[0099] The semiconductor device 1 further includes a plurality of field plates 222 formed on the field oxide film 120. The plurality of field plates 222 are formed to be spaced apart from each other such that at least each part thereof overlaps.

[0100] Reference Figure 8 (b) As another embodiment, the first P-type well region 112-1 and the second P-type well region 112-2 can be combined into one well region. Figure 8 That is, the first P-type well region 112 - 1 , the second P-type well region 112 - 2 , and the third P-type well region 112 - 3 may be formed as one P-type well region 112 .

[0101] Fig. 9 yes Figure 7 Another cross-sectional view of the semiconductor device 1 is shown along the line DD′.

[0102] Reference Fig. 9 The semiconductor device 1 includes at least P-type well regions 112 - 1 , 112 - 2 , a first N-type well region 310 , and a field oxide film 120 .

[0103] The first and second field oxide films 120 are disposed on the top surface of the substrate 201 , and the first N-type well region 310 having a fifth depth d5 ​​is disposed on the top surface of the substrate 201 .

[0104] The semiconductor device 1 further includes at least one first N+ doping region 110 -S (source region of the JFET) disposed in the first N-type well region 310 .

[0105] The first P-type well region 112 - 1 and the second P-type well region 112 - 2 are symmetrically disposed on both sides of the first N-type well region 310 and spaced apart from the first N-type well region 310 , and have a sixth depth d6 that is less than the fifth depth d5 ​​.

[0106] The semiconductor device 1 further includes a first P+ doping region 301 - 1 and a second P+ doping region 301 - 2 disposed in the first P-type well region 112 - 1 and the second P-type well region 112 - 2 , respectively.

[0107] The semiconductor device 1 further includes a first gate electrode 221-G1 and a second gate electrode 221-G2. The first gate electrode 221-G1 and the second gate electrode 221-G2 are spaced apart in a vertical direction of the plane of the substrate 201 and overlap with the first P-type well region 112-1 and the second P-type well region 112-2. The first gate electrode 221-G1 and the second gate electrode 221-G2 are disposed on the field oxide film 120.

[0108] In addition, the semiconductor device 1 further includes first and second field plates 222 formed on the first and second field oxide films 120. The first and second field plates 222 are respectively spaced apart from and overlapped with the first and second gate electrodes 221-G1 and 221-G2 and the plane of the substrate in a vertical direction.

[0109] According to various embodiments, the semiconductor device of the present specification may vary the widths of the first P-type well region and the second P-type well region. Fig. 9 As shown in (b), Fig. 9 (a) Compared with the first P-type well region 112-1 and the second P-type well region 112-2, the width of the first P-type well region 112-1 and the second P-type well region 112-2 can be set wider, and therefore, the breakdown voltage can be adjusted to be larger. That is, if the first P-type well region 112-1 and the second P-type well region 112-2 are set near the first N-type well region 310, the area of ​​the depletion region increases a lot, so the breakdown voltage may be increased.

[0110] Fig.10 FIG. 1 is a top view of another embodiment of a semiconductor device. Figure 3 The difference.

[0111] Reference Fig.10 , a source region 110 -S of a JFET can be formed in the N-type well region 310 and Figure 3 Different from the HVFET 20, the source region 110-S of the JFET vertically extends longer on the side surface of the HVFET 20. The first source region 110-S extends from the second gate electrode 221-G2 toward the first gate electrode 221-G2 in the Y direction, so that the first source region 110-S has a length greater than the width. The vertical lengths of the source region 110-S and the N-type well region 310 increase together. If the vertical length SL1 of the source region 110-S increases, the current of the JFET increases. The source region 110-S is formed longer than Figure 3 The source region of the embodiment is long, therefore, Fig.10 The current in the JFET is higher than Figure 3 The JFET current in the JFET 10. The vertical length of the source region 110-S of the JFET 10 is greater than the vertical length of the common drain region 140-D. The vertical length of the N-type well region 310 of the JFET 10 is also greater than the vertical length of the common drain region 140-D. The length of the source region is controllable or adjustable than the drain region. The JFET current can be increased by increasing the length of the source region. If the length of the source region 110-S of the JFET 10 becomes longer without changes in the HVFET 20, the amount of current can be increased only, while the pinch-off voltage remains unchanged.

[0112] like Fig.10 As shown, the area of ​​the first N-type well region 310 increases, so the total N-type dopant increases. A balance needs to be made between the N-type dopant and the P-type dopant to increase the breakdown voltage of the HVFET 20. Therefore, the P-type well extension region 112E extends toward the source region of the JFET 10.

[0113] Fig.11 is a top view of another embodiment of a semiconductor device.

[0114] Reference Fig.11 As an embodiment, a first source region 110-S1, a first drain region 140-D1, a first gate electrode 221-G1, a second gate electrode 221-G2, a first buried impurity layer 130-1, a first N-type well region 310, and a second N-type well region 320 are formed in the semiconductor device 1. The first source region 110-S1 is disposed at a corner of the semiconductor device 1. The first source region 110-S1 is adjacent to the first gate electrode 221-G1, but not adjacent to the second gate electrode 221-G2.

[0115] The semiconductor device 1 further includes a second source region 110-S2, a second drain region 140-D2, a third gate electrode 221-G3, a second buried impurity layer 130-2, a third N-type well region 350, and a fourth N-type well region 360. The second source region 110-S2 is disposed between the second gate electrode 221-G2 and the third gate electrode 221-G3. The second source region 110-S2 of the JFET 10b is formed near the second gate electrode 221-G2. Two JFETs 10a and 10b are formed in the semiconductor device 1. This helps more JFET current to flow in the semiconductor device 1.

[0116] Fig.12 is a VI curve graph according to the operation of a semiconductor device.

[0117] When measuring Figure 2 When the voltage and current in the semiconductor device 1' (ie, "old") of the comparative example are shown, the well region 310 for inserting the JFET is further implanted outside the HVFET. The well region 310 extends outside the HVFET 20, resulting in a decrease in the breakdown voltage to 200V or less.

[0118] However, in the case of the semiconductor device of the present specification (i.e., "new"), the breakdown voltage is close to 1000 V because the charge or doping amount between the N-type impurity and the P-type impurity is balanced. In contrast, in the case of the semiconductor device ("old"), the breakdown voltage is at or below 200 V. This indicates that it is important to design the JFET to be placed inside the HVFET 20.

[0119] Fig.13 (a) is a graph of electric field distribution according to the operation of the semiconductor device of the comparative example, and Fig.13 (b) is a graph of electric field distribution according to the operation of the semiconductor device of the present specification.

[0120] Fig.13(a) depicts a contour diagram of equipotential electric field lines in the case of the comparative example. The electric field lines of the comparative example are locally concentrated at a specific point. This result is caused by the imbalance of the total N-type charge amount and the total P-type charge amount in the HVFET 20. When the N-type well region 310 including the source region of the JFET is formed outside the HVFET 20, the RESURF of the HVFET collapses. Therefore, the breakdown voltage is reduced to 200V or less, as shown in FIG. Fig.12 shown.

[0121] However, in the case of the semiconductor device of the present specification (ie, novel), as Fig.13 As shown in (b), the electric field is uniformly distributed; therefore, the breakdown voltage is close to 1000 V. This indicates that it is important to design the source region 110 -S and the first N-type well region 310 of the JFET 10 to be arranged within the region or boundary of the HVFET 20 .

[0122] The semiconductor device according to the present specification enables a JFET and an HVFET to share a drain, thereby improving integration.

[0123] In addition, the semiconductor device according to the present specification enables the JFET to be completely inserted into the HVFET, thereby having a design advantage.

[0124] In addition, the semiconductor device according to the present specification forms the P-type well region of the JFET in the N-type well region in the channel region of the HVFET in the direction toward the channel width, thereby individually controlling the pinch-off characteristics of the JFET while maintaining the electrical characteristics of the HVFET.

[0125] In addition, the semiconductor device according to the present specification reduces the area of ​​the well region for the source region of the JFET, thereby having an effect that RESURF does not collapse.

[0126] In addition, the semiconductor device according to the present specification reduces the area of ​​the well region of the JFET, and therefore, the electric field is uniformly distributed, thereby having a higher breakdown voltage.

[0127] In addition, the semiconductor device according to the present specification operates at a relatively high voltage, thereby having an effect that the JFET can be used at the same voltage region together with the HVFET.

[0128] In addition, the semiconductor device according to the present specification individually controls the area of ​​the source region of the JFET, thereby individually controlling the amount of current without any variation in pinch-off.

[0129] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered in a descriptive sense only, and not for the purpose of limitation. The description of the features or aspects in each example is considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents, appropriate results can be achieved. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents should be interpreted as included in the present disclosure.

Claims

1. A semiconductor device, comprising: A first junction field effect transistor JFET, comprising: A first N-type well region is disposed in the substrate; a second N-type well region adjacent to the first N-type well region; a first JFET source region disposed in the first N-type well region; a common drain region disposed in the second N-type well region; and A first high voltage field effect transistor HVFET comprising: A first P-type well region is formed in the substrate; a first HVFET source region disposed in the first P-type well region; The common drain region is disposed in the second N-type well region and is shared by the first JFET and the first HVFET; and A first gate electrode is formed on the first P-type well region and is disposed between the first HVFET source region and the common drain region.

2. The semiconductor device according to claim 1, wherein The maximum vertical length of the first JFET source region is greater than the maximum vertical length of the common drain region.

3. The semiconductor device according to claim 1, wherein The first JFET has a rectangular shape in a plan view.

4. The semiconductor device according to claim 3, wherein: The vertical length of the rectangular shape is greater than the horizontal length.

5. The semiconductor device according to claim 1, wherein The cross-sectional area of ​​the first N-type well region is smaller than the cross-sectional area of ​​the second N-type well region.

6. The semiconductor device according to claim 1, wherein Relative to the top surface of the substrate, a maximum depth of the first N-type well region is less than or equal to a maximum depth of the second N-type well region. 7 . The semiconductor device according to claim 1 , further comprising a P-type gate region disposed between the first N-type well region and the second N-type well region.

8. The semiconductor device according to claim 1, further comprising a second HVFET, wherein the second HVFET comprises: a second P-type well region formed in the substrate; a second HVFET source region disposed in the second P-type well region; The common drain region is arranged in the second N-type well region; as well as a second gate electrode disposed between the second HVFET source region and the common drain region, The common drain region is shared by the first HVFET and the second HVFET.

9. A semiconductor device comprising: Junction field effect transistor JFET, comprising: An N-type well region disposed in the substrate; A JFET source region disposed in the N-type well region; and A common drain region disposed in the N-type well region; and A high voltage field effect transistor HVFET, comprising: a P-type well region spaced apart from the N-type well region; A field oxide film formed above the P-type well region; a gate electrode formed over the field oxide film; and a field plate formed over the field oxide film to overlap the gate electrode, The common drain region is shared by the JFET and the HVFET.

10. The semiconductor device according to claim 9, in, The N-type well region comprises: a first well region; and a second well region adjacent to the first well region, and The JFET source region and the common drain region are formed in the first well region and the second well region respectively.

11. The semiconductor device according to claim 9, in, Relative to the top surface of the substrate, a maximum depth of the N-type well region is greater than a maximum depth of the P-type well region.

12. The semiconductor device according to claim 11, further comprising: A P-type buried layer is spaced apart from a bottom surface of the field oxide film.

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