Semiconductor Devices

Abstract

In one embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device having an active region and an edge termination region surrounding the active region on all sides. The active region includes a first meandering trench in the semiconductor body, a first field plate in the first meandering trench, a second meandering trench in the semiconductor body, and a second field plate in the second meandering trench. The first meandering trench is separated and laterally spaced from the second meandering trench.

Description

Background Art

[0001] A metal oxide semiconductor field effect transistor (MOSFET) generally includes an active region that facilitates conduction of the transistor device and an edge termination region surrounding the active region and around the periphery of the transistor. The edge termination region generally includes an edge termination structure that is designed to have the same or higher breakdown capability as the active region transistor.

[0002] US patent application US 2009 / 0090967 A1 discloses a MOSFET device having active region and edge termination region charge balance to provide uniform voltage breakdown across the active region and the termination region while obtaining a suitably low drain source on resistance (RDSon).

[0003] However, in order to produce more reliable transistor devices with good performance, further improvements in transistor device structures and edge termination structures are desired. Summary of the invention

[0004] In one embodiment, the semiconductor device includes a transistor device. The transistor device includes a semiconductor body having a first main surface, a first trench in the first main surface, the first trench having at least two transverse portions spaced apart by a certain distance, whereby the adjacent ones of the transverse portions are connected by a longitudinal portion so that the first trench has a meandering form, a second trench in the first main surface, the second trench laterally surrounding a third trench and the first trench in the first main surface, wherein the third trench extends from the second trench between the two transverse portions of the first trench and has a distal end spaced apart from the longitudinal portion of the first trench connecting the two transverse portions. A continuous mesa is formed between the first trench, the second trench, and the third trench. A field plate and a gate electrode electrically isolated from the field plate are arranged in the first trench and in the third trench. The field plate may also be arranged in the second trench.

[0005] In one embodiment, a semiconductor device includes a semiconductor body including a field effect transistor device including an active region and an edge termination region surrounding the active region. The active region includes a first meandering trench in the semiconductor body and a first field plate disposed in the first meandering trench, a second meandering trench in the semiconductor body and a second field plate disposed in the second meandering trench. The first meandering trench is separated and laterally spaced from the second meandering trench.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and described in detail in the description that follows.

[0008] Figure 1 A top view of a semiconductor device including a transistor device is illustrated.

[0009] Figure 2 The diagram shows Figure 1 A cross-sectional view of a semiconductor device taken along line AA.

[0010] Figure 3 A top view of a semiconductor device including a transistor device is illustrated.

[0011] Figure 4 A top view of a semiconductor device including a transistor device is illustrated.

[0012] Figure 5 A top view of a semiconductor device including a transistor device is illustrated.

[0013] Figure 6 The diagram shows Figure 5 A cross-sectional view of a semiconductor device taken along line AA.

[0014] Figure 7 The diagram shows Figure 5 A cross-sectional view of a semiconductor device taken along line BB.

[0015] Figure 8 The diagram shows Figure 5 A cross-sectional view of a semiconductor device taken along line CC.

[0016] Fig. 9 The diagram shows Figure 5 A cross-sectional view of a semiconductor device taken along line DD.

[0017] Fig.10 The diagram shows Figure 5 A cross-sectional view of a semiconductor device taken along line EE. DETAILED DESCRIPTION

[0018] In the following detailed description, reference is made to the accompanying drawings forming a part thereof, and specific embodiments in which the present invention may be implemented are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "rear", "front", "rear", etc. are used with reference to the orientation of the (one or more) figures described. Because the components of the embodiments may be positioned in a plurality of different orientations, directional terms are used for purposes of illustration and by no means restrictively. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as having a limiting meaning, and the scope of the present invention is limited only by the appended claims.

[0019] A number of exemplary embodiments will be explained below. In this case, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or range extending generally parallel to the lateral extent of the semiconductor material or semiconductor body. Therefore, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Therefore, the vertical direction extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0020] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it may be directly on or directly extend to the other element or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or extending "directly" onto another element, there are no intervening elements present.

[0021] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] To improve performance, trench power MOSFET devices can utilize charge balancing techniques, such as buried source electrodes, to maintain a relatively uniform electric field in the drift region. Such devices can achieve a predetermined breakdown voltage rating with a higher drift region doping than conventional trench devices without charge balancing. However, edge termination creates a challenge in the design of such devices to achieve the same degree of charge balancing at the transition region from the active region or area to the edge termination region or area as in the bulk of the active area. As a result, the edge termination region may become a limiting factor in the breakdown voltage, and device performance is often traded off to improve the termination breakdown voltage capability.

[0023] In a buried source trench MOSFET, the lower part of the trench contains a buried electrode or field plate, which is insulated from the epitaxial layer (i.e., drift region) using a field oxide, and which is electrically connected to the source potential. For such a design, the active region has a slightly different depletion mechanism during the off state compared to the edge terminated region. In the active region, in the presence of multiple parallel trenches separated by silicon mesas, the mesa drift region is depleted from both sides due to the bias on the buried electrodes in the trenches on either side of the mesa.

[0024] In some edge termination designs, parallel active trenches are connected to each other by means of lateral termination trenches. In these designs, the surrounding mesa drift region between the two parallel trenches and the lateral termination trench is depleted faster than the active area due to depletion extending from three sides. This results in the termination region having a lower breakdown voltage compared to the active area.

[0025] In the embodiments described herein, a meander or winding trench layout is used to improve the termination breakdown voltage capability of a buried field plate device. The design includes an array of meandering trenches that are interdigitated, maintaining uniform spacing between trenches throughout the chip. In this configuration, the depletion behavior of the drift region at the edge termination region is substantially the same as the depletion behavior of the drift region in the bulk of the active region. As a result, the termination region breakdown is not degraded compared to the breakdown of the active region, which enables a more uniform avalanche current distribution across the entire chip, as well as improved device reliability and an improved RDSON to breakdown ratio.

[0026] Figure 1 A top view is shown, and Figure 2A cross-sectional view along line AA of a semiconductor device 20 including a transistor device 21 according to an embodiment is shown. The transistor device 21 includes a semiconductor body 22 having a first main surface 23. The transistor device 21 includes a first trench 24 arranged in the first main surface 23. The first trench 24 includes at least two lateral portions 25, 26, which are spaced apart by a distance. The at least two portions 25, 26 of the first trench 24 are lateral in that each of them extends from one side of the first trench 24 (e.g., Figure 1 The left-hand side in the figure) extends to the other side of the first groove 24 (eg Figure 1 Adjacent ones of the transverse portions 25, 26 are connected by a longitudinal portion 27 which extends lengthwise rather than across the first groove 24, so that the first groove 24 has a meandering (snaking) form.

[0027] exist Figure 1 In the arrangement illustrated in the figure, the first groove 24 can be considered to have a U-form, which provides a single loop of a meandering form. The transistor device 21 also includes a second groove 28 in the first main surface 23, which laterally surrounds the first groove 24. The second groove 28 has a continuous ring form and can have a substantially square or rectangular form in a plan view. The second groove 28 is separated from the first groove 24 by a portion of the semiconductor body 22. The transistor device 21 includes at least one third groove 29 in the first main surface 23. The third groove 29 extends from the second groove 28 between the two lateral portions 25, 26 of the first groove 24 to the open end of the loop and has a distal end 30, which is spaced apart from the longitudinal portion 27 of the first groove 24, and the longitudinal portion 27 connects the two lateral portions 25, 26 and provides a closed end to the loop. The lateral arrangement of the first, second and third trenches 24 , 28 , 29 in the first major surface 23 defines a continuous and uninterrupted mesa 31 formed between facing side walls of the first, second and third trenches 24 , 28 , 29 .

[0028] The lateral arrangement of the first, second and third grooves 24, 28, 29 and the location of the distal end 30 of the third groove 29 and its spacing from the longitudinal portion 27 of the first groove 24 may be selected so that the continuous land 31 has substantially the same width w throughout its length. m For example, the width w of the continuous terrace 31 at any point is m can have a nominal width w m(nom) The width variation is less than its nominal width w m(nom) About 10%.

[0029] As in Figure 2As can be seen in the cross-sectional view of FIG. 2 , the first trench 24, the second trench 28 and the third trench 29 extend from the first main surface 23 into the semiconductor body 22 in the direction of the second main surface 32 of the semiconductor body 22 opposite the first main surface 23. The first trench 24, the second trench 28 and the third trench 29 extend into the first main surface 23 of the semiconductor body 22 to a depth d t , which is essentially the same for all grooves in the illustrated embodiment. Each of these grooves 24, 28, 29 has a width w t , which is also substantially the same for all trenches in this embodiment. Each trench 24, 28 and 29 comprises sidewalls that are substantially perpendicular to the first major surface 23. The inner sidewall 34 of the second trench 28 and the sidewall 33 of the first trench 24 facing the inner sidewall 34 of the second trench 28 and the sidewalls 33 of the first trench 24 and the third trench 29 facing each other and defining a mesa 31 having substantially the same width wm throughout their length.

[0030] The width of the continuous mesa 31 formed between the trenches is substantially the same throughout its length. In some embodiments, the trenches 24, 28, 29 may have different widths, but the width of the continuous mesa 31 formed between them is substantially constant. For example, the second trench 28 may be wider than the first and third trenches 24, 29.

[0031] As in Figure 2 As can be seen in the cross-sectional view of FIG. 2 , the first trench 24 includes a field plate 35 arranged toward the bottom of the trench, and a gate electrode 36 electrically isolated from the field plate 35 within the trench. The third trench 29 also includes a field plate 35 arranged toward the bottom of the trench and a gate electrode 36 arranged toward the top of the trench and electrically isolated from the field plate 35 within the trench. The gate electrode 36 may be arranged in an upper portion of the first trench 24 and in an upper portion of the third trench 29, and spaced apart from the underlying field plate 35 by an insulating material 37. Each of the first and third trenches 24, 29 is lined with an insulating material such that the field plate 35 and the gate electrode 36 are electrically isolated from the semiconductor body 22.

[0032] The second trench 28 also includes a field plate 38 arranged toward the bottom of the trench and an insulating material 39 that electrically insulates the field plate 38 from the semiconductor body 22. The second trench 28 does not include a gate electrode so that electrical contact can be made with the field plate. In the second trench, the insulating material can extend from the field plate 38 to the first main surface 23 and fill the rest of the second trench 28.

[0033] All trenches 24, 28, 29 comprise field plates 35, 38, whereas gate electrodes may be located in only some trenches, for example in only the first and third trenches 24, 29. The second trench 28 may comprise only a single electrode forming a field plate 38 and no gate electrode.

[0034] In some embodiments, second trench 28 includes only a single electrode, which forms a field plate 38 extending to first major surface 23. Field plate 38 is electrically insulated from semiconductor body 22 by insulating material 39, which lines the base and sidewalls of second trench 28 from the base of second trench 28 to first major surface 23.

[0035] In some embodiments, the second trench 28 may include a first electrode forming a field plate 38 and a second electrode electrically insulated from the field plate 38. The second electrode may be surrounded at least on its sides by an insulating layer that is thicker than the insulating layer on the sides of the gate electrode in the first and third trenches 24, 29. The second electrode in the second trench is not coupled to the gate potential.

[0036] In a plan view, the field plate 38 in the second trench 28 may have a continuous ring form corresponding to the continuous ring form of the second trench 28. The gate electrode 36 in the first trench and the field plate 35 in the first trench may also have a meandering form corresponding to the meandering form of the first trench 24. However, in some embodiments, the field plate 35 has a meandering form corresponding to the meandering form of the first trench 24, and the gate 36 is located only in some portions of the meandering first trench 24, for example, in the lateral portion 25 of the first trench 24. In the portions of any trench 24, 28, 29 in which there is no gate electrode, the field plate may extend to the top of the trench in these portions. The field plate 35 and the gate electrode 36 and in the third trench 29 may be substantially linear and extend substantially parallel to the lateral portions 25, 26 and perpendicular to the longitudinal portion 27 of the first trench 24.

[0037] The transistor device 21 includes a body region 40 extending from the first main surface 23 into the semiconductor body 22 and a source region 41 arranged in the body region 40. The body region 40 may extend over a lateral region of the semiconductor body 22 and over a length of the continuous mesa 31, which is defined by the sidewalls 33 of the first trench 24, the inner sidewalls 34 of the third trench 29 and the second trench 28, and in a region of the semiconductor body 22 adjacent to the outer sidewall 42 of the second trench 28. The source region 41 may be arranged on the body region 40 in the region of the continuous mesa 31, which is arranged between the lateral portions 25, 26 of the first trench 24 and the third trench 29.

[0038] The transistor device 21 may further include a drain region 43 disposed at the second main surface 32 . In these embodiments, the transistor device 21 may be considered as a vertical device having a vertical drift path extending from the source region 41 to the drain region 43 .

[0039] The transistor device also includes contacts to the body region 40, the gate 36 and the field plates 35, 38, which are located at Figure 1and 2 Not shown in FIG.

[0040] The semiconductor body 22 may include silicon in the form of a single crystal silicon wafer or a single crystal epitaxial deposition layer (epi layer) on a substrate. The semiconductor body 22 has a first conductivity type, such as n-type, and the body region 40 has a second conductivity type opposite to the first conductivity type, such as p-type in an embodiment where the first conductivity type is n-type. The source region 41 and the drain region 43 have the first conductivity type and may be more highly doped than the semiconductor body 22.

[0041] The transistor device 21 includes an active region or cell field 46, which is defined by a portion of the semiconductor body 22 including the source region 41 and the body region 40. The active region or cell field 46 is laterally surrounded on all sides by an edge termination region 47. The edge termination region 47 does not contribute to current conduction in on-state operation of the semiconductor device 21, and this portion of the semiconductor body 22 does not include the source region 41. The second trench 28 is located in the edge termination region 47. The field plate 42 within the second trench 28 is arranged within the edge termination region 47 and provides a mechanism for reducing the field strength in at least a lateral direction from the cell field 46 to the edge 48 of the semiconductor body 22.

[0042] The continuous mesa 31 is laterally continuously surrounded by the field plates arranged at the bottom of the first, second and third trenches 24, 28, 29. Therefore, the continuous mesa 31 can be uniformly depleted from all sides, so that the depletion behavior of the transistor device 21 in the active area 46 and in the innermost part of the edge termination region 47 is more similar and can be substantially the same. Therefore, the difference between the breakdown voltages of the edge termination region 47 and the cell field 46 is reduced, which enables a more uniform avalanche current distribution across the entire semiconductor device 20, improved device reliability and a lower RDSON of the device at a given breakdown voltage.

[0043] In practice, the lateral shape of the distal ends of the grooves 24 and the corners between the grooves are rounded rather than vertical as shown. The radius of curvature may be selected for processing reasons and / or to further improve the uniformity of mesa compensation.

[0044] Figure 3A top view of a semiconductor device 50 including a transistor device 51 is illustrated. The transistor device 51 includes a semiconductor body 52, a first trench 53, a second trench 54, and a third trench 55. The first trench 53, the second trench 54, and the third trench 55 extend from a first main surface 63 of the semiconductor body 52 into the semiconductor body 52. ​​The first trench 53 includes a plurality of lateral portions 56 and a plurality of longitudinal portions 57. In a plan view, the lateral portions 56 and the longitudinal portions 57 are substantially orthogonal. The lateral portions 56 are arranged substantially parallel to each other, and adjacent ones of the lateral portions 56 are spaced apart by a certain distance.

[0045] The transverse portion 56 may also be curved, for example having a C-shape, and connected to the longitudinal portion 57. The distal end of the third groove 55 may also be rounded. As a result of the manufacture of the groove, a rounded end and a rounded distal end may be formed.

[0046] Adjacent ones of the transverse portions 56 are connected by longitudinal portions 57 to produce a first groove 53 having a zigzag form. The zigzag form can also be considered as a meandering form. Except for those at the lateral outermost sides of the transverse portions 56, longitudinal portions 57 are arranged at the opposite ends of each transverse portion 56, and the longitudinal portions 57 extend in opposite longitudinal directions to form a zigzag shape. The two transverse portions 56 and the longitudinal portions 57 connecting them can be considered to form an open side ring having a U-shape in a plan view, whereby the open sides of adjacent U-shapes of the groove 54 face in opposite directions to provide a zigzag form.

[0047] In plan view, the second groove 54 laterally surrounds the first groove 53 and provides a continuous groove, which in this embodiment is substantially rectangular and has four sections 71, 72, 73, 74. The side walls of the two opposing longitudinal sections 71, 72 of the second groove 54 are spaced apart from and substantially parallel to the outwardly facing side walls 60 of the longitudinal section 57 of the first groove 53. The second groove 54 also includes two transverse sections 73, 74, which extend between the two longitudinal sections 71, 72 and are spaced apart from and substantially parallel to the outermost transverse section 56 of the first groove 53.

[0048] The third groove 55 extends from the inner side walls 70 of the two longitudinal portions 71, 72 of the second groove 54 into the open side ring of the first groove 53 formed by the adjacent transverse portions 56 and the connecting longitudinal portion 57. Since the first groove 53 has a meandering form, the adjacent ones of the third grooves 55 extend from opposite sides of the longitudinal portions 71, 72 of the second groove 54. The third groove 55 extends into the ring so that a land 78 is formed between the side walls 76 of the third groove 55 and the side walls 77 of the transverse portion 56 of the first groove 54, and so that a land 78 is also formed between the distal end 79 of the third groove 55 and the inner wall 61 of the longitudinal portion 57 of the first groove 53. A continuous land 78 is also formed between the inner side wall 70 of the second groove 54 and the outer side wall 60 of the longitudinal portion 57 of the first groove 53, and between the side walls 77 of the transverse portion 56 of the first groove 53 and the side walls 76 of the third groove 55. The continuous mesa 78 also has a meandering or serpentine shape in plan view, and can be considered to have an alternating serpentine form in plan view.

[0049] The first trench 53, the second trench 54 and the third trench 55 include field plates and gate electrodes. Figure 3 The gate electrode is electrically isolated from the field plate. Figure 3 In the region within the region indicated by line 80 , the thickness of the insulating material surrounding the gate electrode is greater than the thickness of the insulating material laterally surrounding the gate electrode in the region laterally outside of line 80 .

[0050] The portion of the continuous mesa 78 formed between the lateral portion 56 of the first trench 53 and the third trench 55 provides the active region of the transistor device 51 and includes the body region and the source region (at Figure 3 5). The location of the source region is indicated by line 81, which defines a substantially rectangular region extending over a portion of the mesa 78 defined by the substantially parallel lateral portions 56 of the first trench 53 and the third trench 55. Line 81 indicates the active region of the transistor device 51. The second trench 54 is located laterally outside of this region. The edge termination region is a region laterally outside of line 81 and does not contain a source region.

[0051] exist Figure 3 5. The metal layers of the transistor device 51 are illustrated in a top view of FIG. A first metal layer 82 is located above the central portion of the first trench 53, the second trench 54, and the third trench 55. The first metal layer 82 is coupled to a source potential. Second metal layers 83, 84 are laterally arranged adjacent to each of two opposing sides of the first metal layer 82. The second metal layers 83, 84 are laterally spaced apart from the first metal layer 82 and are coupled to gate electrodes within the first trench 53 and the third trench 55.

[0052] The field plates within the first trench 53 and the third trench 55 are electrically coupled to the overlying first metal layer 82 through first contacts 87, which extend from the field plates to the overlying first metal layer 82. The lateral location of the first contacts 87 may be at a distal end of the third trench 55 and in a laterally adjacent region of the lateral portion 56 of the first trench 53. The first contacts 87 may include one or more metal layers lining openings in one or more insulating layers disposed between the first main surface 63 of the semiconductor body 52 and the first metal layer 82.

[0053] The second metal layer 83 is located over the longitudinal portion 57 of the first trench 53, over the longitudinal portion 71 of the second trench 54, and over the connection between the third trench 55 and the inner sidewall 70 of the second trench 54. The second metal layer 84 is located over the longitudinal portion 57 of the first trench 53, over the longitudinal portion 72 of the second trench 54, and over the connection between the third trench 55 and the inner sidewall 70 of the second trench 54 on the laterally opposite side of the first metal layer 82. Second conductive contacts 85 may be located in the longitudinal portion 57 of the first trench 53 to electrically couple the gate electrode to the second metal layers 83, 84. The gate electrode in the third trench 55 may be electrically coupled to the second metal layer 83 by one or more second contacts 85 positioned toward the connection between the third trench 55 and the second trench 54, such that the second contacts 85 are positioned laterally adjacent to the first metal layer 82.

[0054] The source region and thus the body region arranged in the continuous mesa 78 can be coupled to the overlying first metal layer 82 by a third contact 86, which extends upward from the source region to the first metal layer 82. The third contact 86 can have a substantially strip-like form and can be positioned in the approximate center of the continuous mesa 78 in the region of the continuous mesa 78 defined by the lateral portion 56 of the first trench 53 and interposing the third trench 55. Since the field plates within the first trench 53, the second trench 54 and the third trench 55 are electrically coupled to the overlying first metal layer 82 by the first contact 87, the field plates are coupled to the source potential. The second and third trenches 54, 55 are connected, and the field plates in the second and third trenches 54, 55 are connected. The field plate in the second trench 54 is coupled to the first metal layer 82 by the first contact 87 of the field plate located above the third trench 55 and extending into the third trench 55.

[0055] Figure 4A semiconductor device 90 is illustrated that includes a transistor device 91 arranged in a semiconductor body 92. The transistor device 91 includes an active region or cell field 93 and an edge termination region 94 that laterally surrounds the active region or cell field 93 on all sides. The cell field 93 includes a first meandering trench 95 and a second meandering trench 96 arranged in the semiconductor body 92. The first meandering trench 95 is separated and laterally spaced from the second meandering trench 96. Figure 4 The first field plate which cannot be seen in the top view of FIG. 1 is arranged in the first meandering trench 95, and Figure 4 The transistor device 91 includes an edge termination trench 97 in the edge termination region 94. The edge termination trench 97 laterally surrounds both the first meandering trench 95 and the second meandering trench 96. The edge termination trench 97 is continuous and uninterrupted and is laterally spaced apart from the first meandering trench 95 and the second meandering trench 96. The edge termination trench 97 is substantially rectangular in plan view and includes two lateral portions 100, 100' connected by two longitudinal portions 101, 101'.

[0056] A first gate electrode is arranged in the first meandering trench 95, which is electrically insulated from the first field plate, and a second gate electrode is arranged in the second meandering trench 96, which is electrically insulated from the second field plate. The edge termination trench 97 includes a third field plate and is devoid of a gate electrode.

[0057] The first serpentine groove 95 includes transverse portions connected by longitudinal portions to form a zigzag or meandering shape in plan view, which includes a plurality of open-sided loops, whereby the open sides of adjacent loops face in opposite directions. Similarly, the second serpentine groove 96 includes transverse portions connected by longitudinal portions to form a zigzag or meandering shape in plan view, which includes a plurality of open-sided loops, whereby the open sides of adjacent loops face in opposite directions.

[0058] The semiconductor device 91 includes a further trench structure 98 including a longitudinal portion 99 extending between and connected to two opposite lateral portions 100, 100' of the edge termination trench 97, such that a first meandering trench 95 is arranged between a first longitudinal portion 101 of the edge termination trench and the trench 99, and such that a second meandering trench 96 is arranged on opposite sides of the trench 99 and between the trench 99 and a longitudinal trench 101' arranged on a side opposite to the first longitudinal trench 101.

[0059] The additional groove structure 98 also includes a transverse portion 102 extending from opposite sides of the groove 99 substantially perpendicular to the groove 99 and parallel to the transverse portions of the first and second meandering grooves 95, 96. The transverse portion 102 extends into the open ends of alternating loops of the first and second meandering structures 95, 96. Transverse portions 104 extend from the longitudinal portion 101 of the edge termination groove 97 into the open ends of alternating loops of the first meandering structure 95. Transverse portions 104' also extend from the opposite longitudinal portion 101' of the edge termination groove 97 into the open ends of alternating loops of the second meandering structure 96.

[0060] The lengths of the transverse portions 104, 104' and the transverse portion 102 are such that the distal ends of the transverse portions 104, 104' and the transverse portion 102 are spaced a certain distance from the longitudinal portions of the first winding groove 95 and the second winding groove 96, and a first continuous table 105 is formed between the longitudinal portions 99 of the first winding groove 95, the edge termination groove 97 and the additional groove structure 98, and a second continuous table 106 is formed between the second winding groove 96, the edge termination groove 97 and the longitudinal portions 99 of the additional groove structure 98.

[0061] Figure 4 Also illustrated are overlying metal layers of transistor device 91. In this embodiment, a first metal layer 110 is disposed over longitudinal portion 99, a second metal layer 111 is disposed over first meandering trench 95, and a third metal layer 112 is disposed over second meandering trench 96.

[0062] The first metal layer 110 is electrically coupled to gate electrodes located in the first meandering trench 95, in the second meandering trench 96, in the lateral portion 102, in the longitudinal trench 99, and in the lateral portions 104, 104'. Contacts 113 extending from the first metal layer 110 to the gate electrodes may be laterally positioned in the longitudinal portion 99, at distal ends of the lateral portions 104, 104' of the further trench structures 98, and in longitudinal portions of the first meandering trench 95 and the second meandering trench 96 positioned adjacent to the longitudinal portion 99 of the further trench structures 98. The contacts 113 located at the distal ends of the lateral portions 102 of the further trench structures 98 connect the field plates in the lateral portions 102 to the overlying metal layers 111, 112 and to the source potential.

[0063] The second metal layer 111 is electrically coupled to the source region disposed in the continuous mesa 105 defining the first meandering trench 95. An elongated and continuous conductive contact 114 may be disposed laterally in the center of the length of the mesa 105 formed between adjacent lateral portions 102 and the first meandering trench 95 and between lateral portions 104, 104' and the first meandering trench 95.

[0064] The third metal layer 112 is electrically coupled to a source region disposed in a second continuous mesa 106 formed by the second meandering trench 96. An elongated conductive contact 115 may be disposed laterally in the center of the length of the mesa 106 formed between adjacent lateral portions 102 and the second meandering trench 96 and lateral portions 104, 104' and the second meandering trench 96.

[0065] Edge termination trench 97 may be coupled to a source potential via a conductive contact 116 extending between longitudinal portion 101 and first metal layer 111 and via a conductive contact 117 extending between longitudinal portion 101 ′ of edge termination trench 97 and second metal layer 112 .

[0066] In this embodiment, a metal layer 110 electrically coupled to a gate electrode is arranged laterally between two metal portions 111 , 112 coupled to a source potential.

[0067] Figure 5 A simplified schematic top view of a semiconductor device 120 comprising a field effect transistor device 121 having a vertical drift path is illustrated. Contacts to source and body regions in the mesa are not illustrated in this simplified view.

[0068] The transistor device 121 comprises a first trench 122 having a meandering form, which comprises a plurality of open side rings 123. Figure 5 In the schematic view of FIG. 1 , three rings 123 are shown, which are formed by four transverse portions 124 and three longitudinal portions 125. However, in reality, the first groove 122 includes a much larger number of rings, for example, the first groove 122 may include 50 rings, 100 rings, or 1000 or more rings. Figure 5 In the schematic view of FIG. 1 , the longitudinal portion 125 extends substantially perpendicularly to the transverse portion 124. However, the shape and arrangement of the longitudinal portions may be different from that shown. For example, the closed end of the loop 123 may be formed by a longitudinal portion having a curved shape, such as a semicircular form or a C-shape in a plan view, to achieve the purpose of connecting the transverse portion 124.

[0069] Each loop 123 is formed by two adjacent or immediately laterally adjacent transverse portions 124, which are arranged substantially parallel to each other and spaced apart, and are connected by a longitudinal portion 125, which in plan view extends substantially perpendicular to the two adjacent transverse portions 124. In order to provide a zigzag form, the longitudinal portions 125 are arranged at opposite ends of the transverse portions 124 to provide a series of open-sided loops 123 having closed sides formed by the longitudinal portions 125. The closed sides and therefore the open sides are alternately arranged at opposite ends of the transverse portions 124 to provide a zigzag or meandering form.

[0070] The first trench 122 is laterally surrounded on all sides by a second trench 126, which has a substantially rectangular ring form and is continuous. The transistor device 121 comprises a further trench 127, which extends from the second trench 126 into the open end of the ring 123 of the first trench 122. Thus, adjacent ones of the further trenches 127 extend from opposite sides 128, 129 of the second trench 126. The second trench 126 and the further trench 127 are arranged laterally relative to the first trench 122 and its transverse portion 124 and longitudinal portion 125, so that a continuous mesa 131 is formed between the innermost wall 130 of the second trench 126 and between the sidewall 132 of the first trench 122 and the further trench 127. The mesa 131 has a width that is substantially the same throughout its length.

[0071] The first trench 122, the second trench 126, the further trench 127 and the edge termination trenches 126, 133 are formed in the upper surface 134 of the semiconductor layer 135 of the semiconductor device 120 and extend substantially perpendicularly to the upper surface 134 of the semiconductor layer 135. The semiconductor layer 135 may be a silicon single crystal or an epitaxially deposited silicon layer having a single crystal structure, i.e., an epi layer. The semiconductor layer 135 forms a drift region of the field effect transistor device 121.

[0072] The second trench 126 forms the innermost one of the plurality of edge termination trenches 133, which is located laterally outside the active area or cell field 138 of the transistor device 121. Figure 5 In the simplified view of FIG, three edge termination grooves 126, 133 are shown. However, one, two or more than three edge termination grooves may be used. Each of the edge termination grooves 126, 133 has a continuous ring form. The groove 133 laterally surrounds the second groove 126 and is spaced a certain distance from the second groove 126 to form a ring-shaped mesa 153 between the second groove 126 and the adjacent grooves 133 and between the adjacent ones of the additional edge termination grooves 133. The spacing between the edge termination grooves 126, 133 may be the same or may vary. In some embodiments, the spacing between the adjacent ones of the edge termination grooves 133 may increase sequentially in the direction from the innermost edge termination groove 126 to the outside.

[0073] exist Figure 5Also illustrated in the top view of FIG. 1 are metal source fingers 136 extending vertically across the further trenches 127 and the lateral portion 124 of the first trench 122 and extending substantially parallel to the longitudinal portion 125 of the first trench 122. The source fingers 136 may be positioned laterally around the center of the length of the lateral portion 24 of the first trench 122. The metal source fingers 136 may be coupled to a further metal source layer that is coupled to a source region of the transistor structure 121 and to field plates located within the first trench 122, the second trench 126, and the further trench 127.

[0074] The semiconductor device 121 further includes a gate metal layer 137 positioned towards the edge of the semiconductor layer 135 and laterally spaced apart from and extending substantially parallel to the source fingers 136. The metal gate layer 137 may have a lateral extent such that it is positioned directly over the distal end of the further trench 127, the longitudinal portion 125 of the first trench 122, the second trench 126 and may optionally be over one or more of the further edge termination trenches 133.

[0075] Figure 6 The diagram shows the Figure 5 1 and 13. The cross-sectional view of line AA of FIG. 1 shows an upper surface 134 of semiconductor layer 135 and an opposite rear surface 140 of semiconductor layer 135 formed by substrate 141. Semiconductor layer 135 has a first conductivity type, such as n-type. Substrate 141 may include a layer highly doped with the first conductivity type, which provides a drain of field effect transistor 121. Figure 6 A first trench 122 and a lateral portion 124 of a further trench 127 in a cell field 138 of a transistor device 121 as well as a plurality of trenches 126 , 133 in an edge termination region 139 of the transistor device 121 are illustrated. Figure 6 The insert of illustrates an enlarged view of the lateral portion 124 of the first trench 122 and the further trench 127 in the cell field 138. The edge termination trenches 133, 126 may have substantially the same lateral dimensions as the trenches 124, 127 in the cell field 138 or may be slightly wider than the trenches 124, 127 in the cell field 138.

[0076] In a cross-sectional view along line AA, the lateral portion 124 of the first trench 122 is interleaved by the further trench 127. Each of the lateral portion 124 of the first trench 122 and the further trench 127 includes a field plate 141 positioned toward the base of the trench 122, 127 and a gate electrode 142 disposed toward the top of the trench 124, 127. Each trench 124, 127 includes an insulating material 143 lining the sidewalls 144 and the base 145 of the trench 124, 127 and an insulating material 146 extending between the field plate 141 and the gate electrode 142 and electrically insulating the gate electrode 142 from the field plate 141. The upper portion of the trench 124, 127 also includes an insulating material 147 lining the sidewalls 144, which forms a gate oxide.

[0077] The mesa 131 formed between adjacent trenches 124, 127 includes a body region 148 doped with a second conductivity type, the second conductivity type being opposite to the first conductivity type, and a source region 149 arranged on the body region 148. The source region 149 is doped with the first conductivity type of the semiconductor layer 135, which provides a drift region of the transistor device 121. If the source region 149 is of n-type, the body region 148 is of p-type. A mesa 153 is formed between laterally adjacent edge termination trenches 126, 133 in the form of a continuous ring. The mesa 153 in the edge termination region 139 may include the body region 148' and does not include the source region. The electrical connection between the source metal layer and the source region 149 and the body region 148 in the mesa 131 is also Figure 6 The diagram is shown in the figure.

[0078] At least one electrically insulating layer 150 is arranged on the first main surface 134 such that it covers the upper surface of the gate electrode 147 and the source region 149 in the cell field 138. The one or more insulating layers 150 also cover the upper surface 134 of the semiconductor layer 135 in the edge termination region 139 and thus the body region 147 forming the upper part of the mesa 153. In some embodiments, if the trenches 126, 133 in the edge termination region 139 do not include a gate electrode and the field plates are recessed in the trenches 126, 133, the one or more insulating layers 150 extend into the trenches 126, 133 in the edge termination region 139 to a depth greater than that extending into the trenches 122, 127 in the cell field 138. In some embodiments, the field plates may extend to the upper surface 134 of the semiconductor layer 135 in the edge termination region 139.

[0079] One or more insulating layers 150 may be conformally deposited on the first main surface 134 and may extend from the first main surface 143 into the semiconductor layer 135, in particular into the edge termination trenches 126, 133 to a depth or distance from the first main surface 134 that is greater in the edge termination region 139 than in the cell field 138. One or more metal layers 151 are arranged on the one or more insulating layers 150.

[0080] To provide electrical connections to the source regions 149 and the body regions 148, one or more conductive contacts 152 are formed that extend through the one or more insulating layers 150 and may extend into the upper surface of the mesas 131 formed between adjacent trenches 124, 127. The contacts 152 may include elongated openings in the one or more insulating layers 150 having bases located within the body regions 148. The openings may be lined with one or more metal layers 151' and may be filled with one or more additional metal layers 151. The metal layers 151, 151' extend above the upper surface of the insulating layer 150.

[0081] The contact 152 has an elongated shape and extends into the upper surface of the mesa 131 formed between the adjacent trenches 124, 127. The contact 152 is located in the region of the mesa 131 adjacent to the gate finger 137' and is interrupted in the mesa region below the gate finger 137'. The contact 152 may also be interrupted and not exist in the region of the mesa 131 located below the source metal layer 136.

[0082] exist Figure 6 In the view of the edge termination region 139 shown in FIG. 1 , the metal layers 151, 151' are spaced apart from the field plates 141 in the trenches 126, 133 and are also spaced apart from the body regions 148' formed in the mesas 153 formed between the edge termination trenches 133 by the insulating layer 150. Figure 6 connected to a source potential at locations not visible in the cross-sectional view of the figure, for example at one or more locations in a plane in front of the figure and / or behind the plane of the figure.

[0083] An electrical connection to a body region 148' in one or more mesas 153 in the edge termination region 139 may be formed at a lateral position between the outermost trench of the cell field 138 and the innermost trench of the edge termination region 139. An electrical connection to the body region 148' of the edge termination region 139 may be formed by positioning a contact 152' comprising an opening through an insulating layer 150 extending into the semiconductor layer 135 and having a base located in the body region 148' of the edge termination region 139. The opening may be lined and / or filled with one or more metal layers 151, 151'. The metal layers 151, 151' also extend into the body region 148 and the source region 149 in the mesas 131 in the active region 138. This arrangement allows the body region 148', which forms part of the edge termination structure 139, to be electrically coupled to a source potential.

[0084] A more highly doped region 154 of the second conductivity type may be formed at the base of the openings in the body regions 148, 148' in the cell field 138 and in the edge termination region 139. The more highly doped region may help provide contact to the body regions 148, 148'.

[0085] Metal layers 151, 151' have lateral extents such that they extend from, and in some embodiments penetrate, active area 138 and into edge termination region 139. One or more outermost edge termination trenches 133 may remain uncovered by one or more metal layers 151.

[0086] Figure 7 The diagram shows the Figure 5 1 is a cross-sectional view taken along line BB of , and illustrates a portion of the transistor device 121 including a cell field 138 and an edge termination region 139 . Figure 7 Connections between the gate electrode 142 in the first trench 122 and in the further trenches 127 and the overlying gate metal layer 137 are illustrated.

[0087] In this portion of the semiconductor device 121, in the region within the innermost edge termination trench 126, the mesa 131 cannot include a source region 149 on the body region, so that the body region 148 forms the first main surface 134. At this location of the transistor device 121, one or more insulating layers 150 are arranged on the first main surface 134 and cover the body region 148 in the ring-shaped mesa 153 in the edge termination region 139, the uppermost part of the edge termination trench 133 and the body region 148 arranged on top of the mesa 131 defined by the trenches 124, 127. The continuous mesa 131 is covered by one or more insulating layers 150.

[0088] A plurality of openings 155 are provided that extend through the insulating layer 150 to the gate electrode 142 arranged in the lateral portions 124 in the first trench 124 and in the further trenches 127. The openings 155 may extend into the gate electrode 142 such that the base and adjacent portions of the sidewalls of the openings 155 are formed by the gate electrode. One or more metal layers 157 are arranged on the insulating layer 150 and line at least the sidewalls of the openings 155. One or more further conductive layers 158 are arranged on the conductive layer 157 and may fill the openings 155 to provide a conductive contact with the gate electrode 142. The openings 155 may be elongated and extend into the plane of the drawing. The openings 155 are arranged substantially parallel to each other in each of the substantially parallel arranged lateral portions 124 of the first trench 122 and the further trenches 127. As in Figure 5 As can be seen in the top view of FIG. 1 , metal layer 137 is separated from metal layer 151 of active layer 136 and is laterally spaced apart therefrom.

[0089] In some embodiments, the transistor device 121 may include one or more gate fingers 137' in addition to or in place of the gate metal 137. The gate fingers 137' are laterally positioned in the active area 138 and include a metal layer 137'. Like the gate metal layer 137 at the periphery of the active area 138, a plurality of openings are provided that extend through the insulating layer to the gate electrode disposed in the first trench 124 and in the lateral portion 124 in the additional trenches 127.

[0090] Figure 8 The diagram shows the Figure 5 1 , and illustrates an electrical connection between a source metal layer 151 arranged on a first main surface 134 and a field plate 141 arranged in a lateral portion 124 of a first trench 122 in a cell field 138 of a transistor device 121. At this lateral position, the first trench 122 and the lateral portion 124 of the further trench 127 include the field plate 141 but do not include a gate electrode. In addition, the uppermost portion of the mesa 131 includes a body region 148, which extends to the uppermost surface 134 in the cell field 138. At this lateral position of the first trench 122 and the lateral portion 124 of the further trench 127, the insulating material 150 extends into the edge termination trench 133 and into the upper part of the lateral portion 124 of the first trench 122 of the further trench 127.

[0091] Openings 160 are arranged in the insulating material 150, which extend through the insulating material 150 to the field plate 141 located in the lateral portion 124 of the first trench 122. These openings 160 are lined with one or more metal layers 157 and filled with one or more additional metal layers 158 to provide electrical connection between the field plate 144 and the source metal layer 151 in the lateral portion 124 of the first trench 122. Figure 8 In the view shown in , the openings 160 extend into alternating grooves, as the lateral portions 124 of the first grooves alternate with further grooves 127 .

[0092] In some embodiments, the openings 160 are positioned so that they extend to the field plates 141 in the further trenches 127. The openings 160 are lined and optionally filled with one or more metal layers that are also coupled to the metal layer 151. In some layer embodiments, these openings that provide electrical connection to the field plates 141 in the further trenches 127 are arranged laterally in a single common row, with the openings 160 extending to the field plates 141 in the lateral portions 124 of the first trench 122. In other embodiments, such as in Figure 8 As shown in FIG. 1 , the opening 160 of the field plate 141 extending into the further trench 127 is arranged to be laterally spaced apart from the opening 160 of the field plate 141 extending into the lateral portion 124 of the first trench 122. For example, these openings may be arranged in Figure 8 In a plane behind or in front of the plane shown in .

[0093] Fig. 9 The diagram shows the Figure 5 DD, and illustrates the region of the lateral portion 124 of the first trench 122 and the further trench 127 in the edge termination region 139. At this lateral position, neither of the trenches 124, 127 includes a gate electrode, and the uppermost surface of the mesas 131, 153 does not include a source region. The uppermost surface of the continuous mesas 131 and the ring-shaped mesas 153 are formed by a region 148' comprising a second conductivity type. This region 148' can be considered as a body region and is manufactured using the body region 148 of the cell field 138. The uppermost portion of the edge termination trenches 126, 133, the first trench 122 and the lateral portion 124 of the further trench 127 are filled with an insulating material 150, which extends from the first main surface 134 into the trenches 122, 127, 133. The gate metal layer 137 is arranged on top of the insulating material 150.

[0094] Fig.10 The diagram shows Figure 51, and illustrates a cross-sectional view along the length of the lateral portion 124 of the first trench 122, the width of the longitudinal portion 129 of the second trench 126, and the width of the edge termination trenches 126, 133. As can be seen in this cross-sectional view along the length of the first trench 124, the field plate 141 and the gate electrode 142 have an elongated shape and are spaced apart from each other by the insulating material 146. The outermost portion of the first trench 122 formed by the longitudinal portion 125 fails to include a gate electrode, so that the laterally outermost portion of the first trench 122 includes only the field plate 141 and the insulating material 150. One or more openings 156 can be formed through the insulating material 150 to expose a region of the gate electrode 142 to enable electrical connection to the gate electrode 142 through a conductive contact 159.

[0095] The field plates 141 disposed in the second trenches 126 and the edge termination trenches 133 are covered by the insulating material 150 and are electrically insulated from the metal layer 137 by the insulating material 150. In some embodiments, such as Fig.10 As shown in , one or more outermost edge termination trenches 133' may include a gate electrode 142'. However, the gate electrode 142' is not coupled to an external potential and may be considered a pseudo gate electrode. In addition, the region of the semiconductor layer 135 where the ring-shaped mesa 153 is formed between the edge termination trenches 133 does not include a source region, but may be doped with a second conductivity type and form a pseudo body region 148'.

[0096] Spatially relative terms such as "below", "beneath", "lower", "above", "upper", and the like are used to explain the positioning of one element relative to a second element for ease of description. These terms are intended to include different orientations of the device other than those depicted in the accompanying drawings. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Throughout the specification, the same terms refer to the same elements.

[0097] As used herein, the terms "having," "containing," "comprising," "including," and the like are open-ended terms that indicate the presence of the elements or features described, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0098] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Transistor devices, including: a semiconductor body comprising a first main surface; a first groove in the first major surface, the first groove having at least two transverse portions spaced a distance apart, wherein adjacent ones of the transverse portions are connected by a longitudinal portion such that the first groove has a meandering form; a second trench in the first major surface, the second trench laterally surrounding the first trench; a third groove in the first major surface, wherein the third groove extends from the second groove between two lateral portions of the first groove and has a distal end spaced apart from a longitudinal portion of the first groove connecting the two lateral portions; a continuous mesa formed between the first trench, the second trench, and the third trench; and A field plate and a gate electrode in each of the first trench and the third trench.

2. The semiconductor device according to claim 1, wherein The second trench does not include an electrode coupled to a gate potential.

3. The semiconductor device according to claim 1, further comprising: A source region is arranged in a body region in a continuous mesa in a portion formed by the first trench and the third trench.

4. The semiconductor device according to claim 3, wherein: The body region extends to the first main surface in a region adjacent to the second trench and forms an edge termination structure together with the second trench.

5. The semiconductor device of claim 1, further comprising a dielectric material, wherein the dielectric material extends from the first major surface into the second trench to a depth greater than a depth of the dielectric material extending from the first major surface into the first trench and into the third trench. 6 . The semiconductor device of claim 1 , further comprising a first metal layer and a first contact extending from the first metal layer to the field plate in the first trench and to the field plate in the third trench. 7 . The semiconductor device of claim 6 , further comprising a second metal layer and a second contact extending from the second metal layer to the gate electrode in the first trench and to the gate electrode in the third trench, the second metal layer being spaced apart from the first metal layer.

8. The semiconductor device according to claim 7, further comprising: a source region arranged in a body region in a continuous mesa in a portion formed by the first trench and the third trench; and A third metal layer and at least one third contact extending from the third metal layer to the continuous mesa and electrically coupled to the source region. 9 . The semiconductor device of claim 8 , further comprising at least one fourth contact extending from the third metal layer to the body region adjacent to the second trench.

10. The semiconductor device according to claim 1, further comprising: a first metal layer and a first contact extending from the first metal layer to the third trench and a field plate in the first trench; at least one third contact extending from the first metal layer to the continuous mesa and electrically coupled to the source region; and At least one fourth contact extends from the first metal layer to the body region adjacent to the second trench.

11. The semiconductor device of claim 1 , further comprising a metal source finger extending over the first trench and the third trench and comprising one or more contacts extending from the metal source finger to the field plate in the first trench and to the field plate in the third trench. 12 . The semiconductor device of claim 11 , wherein the one or more contacts are arranged in a first row and a second row, each contact in the first row being electrically coupled to a field plate in the first trench, and each contact in the second row being electrically coupled to a field plate in the third trench. 13 . The semiconductor device of claim 1 , further comprising one or more further trenches in the first main surface laterally surrounding the second trench. 14 . The semiconductor device of claim 13 , wherein the semiconductor body has a first conductivity type, and the one or more further trenches are separated from each other by mesas having a second conductivity type at the first main surface from the second trench.

15. A semiconductor device according to claim 14, wherein one or more additional trenches include a field plate and do not include a gate electrode and an insulating material, and the insulating material extends into the second trench and the one or more additional trenches to a depth greater than the depth of the insulating layer extending into the first trench and into the third trench.

16. A semiconductor device comprising: A semiconductor body comprising a field effect transistor device comprising an active region and an edge termination region surrounding the active region on all sides, The active areas include: a first meandering trench in a semiconductor body; a first field plate in a first meandering trench; a second meandering trench in the semiconductor body; and The second field plate in the second meandering trench, wherein the first meandering groove is separated and laterally spaced from the second meandering groove, The semiconductor device also includes a trench structure including a longitudinal portion extending into the semiconductor body in a region between the first meandering trench and the second meandering trench, and a lateral portion extending from opposite sides of the longitudinal portion into alternating rings of the first meandering trench and into alternating rings of the second meandering trench.

17. The semiconductor device according to claim 16, further comprising: a first gate electrode disposed in the first meandering trench and electrically insulated from the first field plate; and A second gate electrode is disposed in the second meandering trench and is electrically insulated from the second field plate.

18. The semiconductor device of claim 16, wherein the edge termination region comprises an edge termination trench surrounding the first meandering trench and the second meandering trench, wherein the edge termination trench comprises a third field plate and does not comprise a gate electrode, and wherein the second conductivity type doping region abuts the edge termination trench.

19. The semiconductor device of claim 18, further comprising lateral trenches extending from the edge termination trench into alternating rings of the first meandering trench and into alternating rings of the second meandering trench.

Images