delta-sigma modulators, delta-sigma a / d converters and delta-sigma a / d converters

Abstract

The present application relates to a delta sigma modulator, a delta sigma A / D converter, and an incremental delta sigma A / D converter. The delta sigma modulator comprises an integrator (10, 11) having an operational amplifier (OP, OP1) and an integration capacitor (Cf, Cf1); a quantizer (20) outputting a quantization result (Qout) of an output signal of the operational amplifier; a DAC (30, 31) connected via a first control switch (SD3, SD13) for subtracting a charge based on the quantization result and feeding back the quantization result to the integrator; and a control circuit (40) outputting a digital output value based on the quantization result; and further comprises a sampling capacitor (Cs, Cs1) connected via a second control switch (SS3, SS13) and accumulating a charge based on an analog signal (Vin). The second control switch can be switched on and off to electrically connect the sampling capacitor with an intermediate point of the integration capacitor and the first input terminal, and the feedback of the quantization result is performed multiple times in one sampling period.

Description

[0001] Cross-reference to related applications: This application is based on the contents of Japanese Patent Application No. 2017-26275, filed on February 15, 2017, which are incorporated herein by reference. Technical Field

[0002] This invention relates to a ΔΣ modulator and a ΔΣ A / D converter used in A / D conversion. Background Technology

[0003] Typically, the input signal, which is the target of conversion in an A / D converter, is input to the A / D converter via a driver circuit located in the pre-stage of the A / D converter. In ΔΣ A / D converters, which are well-known for their high precision, a high-speed driver circuit is required because oversampling is used to repeatedly sample the input signal at high speed. Patent Document 1 discloses a ΔΣ modulator that feeds back the quantization result of a multi-bit quantizer via a 1-bit D / A converter.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-146893 Summary of the Invention

[0007] However, to avoid the influence of the driver circuit itself on the input signal of the object being converted, a higher input impedance is preferred in the A / D converter's drive circuit. Drive circuits with high input impedance are typically composed of single-ended amplifiers (including analog differential amplifiers using two single-ended amplifiers). Due to their internal circuitry, single-ended amplifiers are more prone to phase rotation compared to fully differential amplifiers. Therefore, compared to A / D converters that are more commonly constructed with fully differential amplifiers, the drive circuit struggles to operate at high speeds. Consequently, the input signal, as the object being converted, is fed into the A / D converter via the drive circuit, often limiting the speed of the A / D converter.

[0008] On the other hand, the ΔΣ modulator described in Patent Document 1 is a ΔΣ modulator that corresponds to one quantization performed by a multi-bit quantizer and is fed back multiple times by a 1-bit D / A converter. Similar to a typical ΔΣ modulator, the feedback period of the D / A converter is the same as the sampling period of the input signal, meaning high-speed oversampling is required. Therefore, the processing speed of ΔΣ modulation is limited by the drive circuitry preceding the ΔΣ modulator.

[0009] Therefore, the object of the present invention is to provide a ΔΣ modulator that can achieve high-speed ΔΣ modulation while suppressing oversampling sampling frequency, and a ΔΣ A / D converter and an incremental ΔΣ A / D converter using the ΔΣ modulator.

[0010] One embodiment of the ΔΣ modulator of the present invention comprises: an integrator having an operational amplifier and an integrating capacitor inserted between a first input terminal and an output terminal of the operational amplifier; a quantizer outputting a quantization result that quantizes the output signal of the operational amplifier; a DAC connected to the first input terminal of the operational amplifier via a first control switch for subtracting a charge based on the quantization result from a charge stored in the integrating capacitor and for feeding back the quantization result in ΔΣ modulation to the integrator; and a control circuit that outputs a digital output value based on the quantization result.

[0011] In addition, the ΔΣ modulator also includes a sampling capacitor connected to the first input terminal of the operational amplifier via a second control switch, which stores charge based on the analog signal used as the input signal. The second control switch is positioned between the sampling capacitor and the midpoint between the integrating capacitor and the first input terminal, enabling the switching of their electrical connection. Multiple quantization results are fed back during one sampling cycle, which includes the sampling period when the second control switch is off and the period when it is on.

[0012] In conventional ΔΣ modulators, the feedback period of the quantization result is the same as the sampling period of the analog signal. In contrast, in this invention, by turning off the second control switch, the electrical connections between the sampling capacitor and the operational amplifier, integrating capacitor, and DAC can be severed. Therefore, the feedback of the quantization result from the DAC and the sampling of the analog signal from the sampling capacitor can be controlled independently.

[0013] Therefore, the feedback period performed by the DAC can be set independently of the sampling period, so it is not limited by the operating speed of the drive circuit and can perform feedback with a period shorter than the sampling period. Thus, the resolution of the A / D conversion corresponding to one sample can be improved, and compared with conventional ΔΣ modulators, high-speed or high-resolution A / D conversion can be performed at the same sampling frequency. Attached Figure Description

[0014] Regarding the above-mentioned objects, other objects, features, and advantages of the present invention, while referring to the accompanying drawings... Figure 1 The details will become clearer as described below. (See the attached diagram:)

[0015] Figure 1 This is a circuit diagram showing a schematic configuration of the ΔΣ modulator according to the first embodiment.

[0016] Figure 2This is a timing diagram showing the operation of the ΔΣ modulator in the first embodiment.

[0017] Figure 3 This is a timing diagram showing the operation of the ΔΣ modulator in Modified Example 1.

[0018] Figure 4 This is a timing diagram showing the operation of the ΔΣ modulator in Modified Example 1.

[0019] Figure 5 This is a timing diagram showing the operation of the ΔΣ modulator in Modified Example 2.

[0020] Figure 6 This is a timing diagram showing the operation of the ΔΣ modulator in variation example 4.

[0021] Figure 7 This is a timing diagram showing the operation of the ΔΣ modulator in variation example 4.

[0022] Figure 8 This is a circuit diagram showing a schematic configuration of the ΔΣ modulator in the second embodiment.

[0023] Figure 9 This is a timing diagram showing the operation of the ΔΣ modulator in the second embodiment.

[0024] Figure 10 This is a circuit diagram showing a schematic configuration of the ΔΣ modulator in the third embodiment.

[0025] Figure 11 This is a timing diagram showing the operation of the ΔΣ modulator in the third embodiment. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in the following figures, identical or equivalent parts are given the same reference numerals.

[0027] (First Embodiment)

[0028] First, refer to Figure 1 The general configuration of the ΔΣ modulator in this embodiment will be described.

[0029] The ΔΣ modulator 100 is a ΔΣ modulator that can be used in a ΔΣ A / D converter. The analog signal Vin is input to the ΔΣ modulator 100 via a drive circuit, and the ΔΣ modulator 100 converts the analog signal Vin into a digital signal Dout.

[0030] like Figure 1 As shown, the ΔΣ modulator 100 includes an integrator 10 and a quantizer 20 (e.g., Figure 1 The Q), D / A converter 30 (hereinafter referred to as DAC30), and control circuit 40 (e.g., Figure 1 C) in it, and the sampling capacitor Cs.

[0031] The integrator 10 has an operational amplifier OP and an integration capacitor Cf. The integration capacitor Cf is inserted between the inverting input terminal and the output terminal of the operational amplifier OP. That is, the output terminal of the operational amplifier OP is connected to the inverting input terminal of the operational amplifier OP via the integration capacitor Cf. The non-inverting input terminal of the operational amplifier OP is connected to the analog ground level (AGND). AGND is the reference potential of the entire ΔΣ modulator 100, and AGND is not necessarily limited to 0V. The inverting input terminal in the operational amplifier OP corresponds to the first input terminal.

[0032] The output of the integrator 10, that is, the output voltage Vout of the operational amplifier OP, is input to the quantizer 20, and the quantizer 20 outputs a quantization result Qout as a result of quantizing the output voltage Vout. That is, the quantizer 20 quantizes the output voltage Vout as an analog value and transforms it into a quantization result Qout as a digital value. The quantization result corresponds to Qout.

[0033] The quantizer 20 includes a comparator not shown. The comparator is connected to the output terminal of the operational amplifier OP, and the output voltage Vout of the operational amplifier OP is input to the input terminal of the comparator. The comparator outputs the result of comparing Vout with a prescribed reference value (for example, Vth+ and Vth-), that is, the quantization result Qout, to a control circuit 40 described later.

[0034] The quantizer 20 outputs 1 as the quantization result Qout, for example, when Vout≧Vth+. On the other hand, it outputs -1 as Qout when Vout<Vth-. And it outputs 0 as Qout when Vth-≦Vout<Vth+. The quantizer 20 in this case is a quantizer having a resolution of 1.5 bits.

[0035] The control circuit 40 outputs a control signal corresponding to the quantization result Qout to a D / A converter 30 (DAC30) described later, and outputs a ΔΣ modulation result Dout based on the result of integrating the quantization result Qout corresponding to one sampling. Specifically, in the case where multiple quantizations are performed by the quantizer 20 corresponding to one sampling, each time quantization is performed, the ΔΣ modulation result Dout is generated as the result of successively integrating the quantization result Qout. In addition, in a configuration where only one quantization is performed corresponding to one sampling, the ΔΣ modulation result Dout may be generated based on the quantization result Qout of one time. The resolution of the quantizer 20 is not limited to 1.5 bits, and may also be 1 bit, 2 bits or more.

[0036] DAC30 is a D / A converter connected to integrator 10. Based on the quantization result Qout output by quantizer 20 and the control signal output by control circuit 40, DAC30 determines the amount of charge subtracted from the integrating capacitor Cf. DAC30 has Vcm, Vrefp, and Vrefm as reference voltages. For example, Vcm is set to AGND, Vrefp is set to a potential higher than AGND, and Vrefm is set to a potential lower than AGND. Furthermore, Vrefp and Vrefm are set such that, when AGND is 0V, they have the same absolute value but opposite signs, satisfying Vrefp = -Vrefm.

[0037] The connection between DAC30 and integrator 10 is described below. DAC30 has a DAC capacitor Cd. At one end of the DAC capacitor Cd, voltage sources that generate reference voltages Vrefp, Vcm, and Vrefm are connected via switches SDT, SDM, and SDB. Specifically, at one end of the DAC capacitor Cd, Vcm is connected via switch SDM, Vrefp is connected via switch SDT, and Vrefm is connected via switch SDB. The potential at one end of the DAC capacitor Cd is equal to one of Vrefp, Vrefm, or Vcm, which is exclusively selected by switches SDT, SDM, and SDB. The voltage thus selected and determined corresponds to the DAC voltage.

[0038] One end of the DAC capacitor Cd, opposite to the end connected to the reference voltage, is connected via switch SD3 to the midpoint between the inverting input terminal of the operational amplifier OP and the integrating capacitor Cf, and can be connected to AGND via switch SD2. That is, DAC30 is connected to the integrator 10 via switch SD3, and one end of the DAC capacitor Cd can be connected to AGND via switch SD2. In this embodiment, switch SD3 corresponds to the first control switch.

[0039] By turning off switch SD3 and turning on switches SD2 and SDM, the voltage across the DAC capacitor Cd is set to AGND, thus reducing the charge accumulated in the capacitor to zero. In other words, a reset is possible.

[0040] Furthermore, the DAC capacitor Cd is connected to the integrator 10 by turning off switch SD2 and turning on switch SD3. This allows one of the switches SDT, SDB, and SDM to be turned on, thereby discharging the charge accumulated in the integrating capacitor Cf according to the selected reference voltage. That is, feedback corresponding to the quantization result Qout in ΔΣ modulation is achieved through charge subtraction. Additionally, when switch SDM is turned on, the potential at one end of the DAC capacitor Cd remains unchanged from when the charge accumulated in the DAC capacitor Cd is reset; therefore, although a charge subtraction operation is performed, no actual subtraction occurs.

[0041] In this embodiment, the DAC30 and control circuit 40 are configured such that, when performing charge subtraction through the DAC capacitor Cd, switch SDT is turned on when the quantization result of the quantizer 20 is Qout = 1, switch SDM is turned on when Qout = 0, and switch SDB is turned on when Qout = -1. That is, the DAC30 in this embodiment functions as a D / A converter with a resolution of 1.5 bits (3 levels). Furthermore, the resolution of the DAC30 is not limited to 1.5 bits; it can also be 1 bit, 2 bits, or more.

[0042] A sampling capacitor Cs is inserted between the input terminal of the analog signal Vin and the integrator 10. Specifically, one end of the sampling capacitor Cs is connected to the input terminal of the analog signal Vin via switch SS1, and the other end is connected via switch SS3 to the midpoint between the inverting input terminal of the operational amplifier OP and the integrating capacitor Cf. That is, if switch SS3 is closed, one end of the sampling capacitor Cs on the operational amplifier OP side is electrically connected to the integrating capacitor Cf. Furthermore, the midpoint between the sampling capacitor Cs and switch SS1 can be connected to AGND via switch SS4, and the midpoint between the sampling capacitor Cs and switch SS3 can be connected to AGND via switch SS2.

[0043] Switches SS1 and SS2 operate synchronously with the same phase. Furthermore, switches SS3 and SS4 also operate synchronously with the same phase, and their on / off states are opposite to those of switches SS1 and SS2. When switches SS1 and SS2 are on and switches SS3 and SS4 are off, the sampling capacitor Cs is electrically disconnected from the integrator 10 and is connected at one end to AGND, accumulating the charge corresponding to the analog signal Vin in the sampling capacitor Cs. When switches SS1 and SS2 are off and switches SS3 and SS4 are on, the charge accumulated in the sampling capacitor Cs is transferred to the integrating capacitor Cf. In this embodiment, switch SS3 corresponds to the second control switch.

[0044] Furthermore, switches SS1 and SS2 operate synchronously with the same phase, but their on and off timings can be appropriately set with a time difference, as they may not be in exactly the same phase. The same applies to the on and off timings of switches SS3 and SS4. Additionally, switches SS1 and SS2 operate in opposite phases to switches SS3 and SS4, but during the switching process, for example, a period can be set where switches SS1 and SS4, or switches SS2 and SS3, connected to the same end of the sampling capacitor Cs, are simultaneously in the off state.

[0045] The ΔΣ modulator 100 of this embodiment performs multiple charge subtractions based on the DAC 30 within one sampling cycle of ΔΣ modulation. Therefore, compared to conventional ΔΣ modulators, it can perform charge subtractions with substantially higher resolution for the same single sampling based on the sampling capacitor Cs. Consequently, when a drive circuit for driving the sampling capacitor Cs is present in the pre-stage of the ΔΣ modulator 100, even if the operating speed of the drive circuit limits the sampling frequency, the sampling frequency can be set to match the operating speed of the drive circuit, and the DAC 30-based feedback in the ΔΣ modulator 100 can be performed with a shorter cycle. That is, even if the drive circuit is configured with a single-ended or analog differential circuit with a relatively low operating speed limit, high-speed or high-resolution ΔΣ modulation can be performed without being limited by the operating speed of the drive circuit.

[0046] Reference Figure 2 The specific operation of the ΔΣ modulator 100 is explained. Figure 2 The time graph shown uses time as the horizontal axis to represent the on / off state of each switch. The High period represents the on state of the switch, and the Low period represents the off state of the switch. Furthermore, the values ​​of Qout and Dout shown in this embodiment and the embodiments described below are examples; the values ​​of Qout and Dout can vary depending on the input analog signal Vin.

[0047] like Figure 2 As shown, at time t10, switches SS3 and SS4 are turned off and switches SS1 and SS2 are turned on, and sampling of the analog signal Vin by the sampling capacitor Cs begins.

[0048] At time t10, simultaneously with the start of sampling, switch SD3 is turned off. This electrically disconnects DAC30 from integrator 10. Furthermore, switch SD2 is turned on, turning off switches SDT and SDB of DAC30, and turning on switch SDM, thus connecting the two ends of DAC capacitor Cd to AGND. In other words, DAC capacitor Cd is reset.

[0049] At time t10, the output voltage Vout of the operational amplifier OP is quantized by quantizer 20, and the quantization result Qout is output to the control circuit 40. Since Vout at time t10 is Vout≧Vth+, Qout is output as 1.

[0050] Then, at time t11, feedback from DAC30 to integrator 10 based on the quantization result Qout is executed. Specifically, based on the quantization result Qout, control circuit 40 turns off switch SD2 and turns on switch SD3, thereby electrically connecting DAC30 to integrator 10. Furthermore, by turning off switch SDM while turning on switch SDT, DAC30 performs a subtraction of the charge corresponding to the quantization result Qout = 1. Figure 2 As shown, the result of the charge subtraction at time t11 is that the output voltage Vout of the operational amplifier OP decreases by Vrefp. Furthermore, the change in Vout is determined by the capacitance ratio of the DAC capacitor Cd to the feedback capacitor Cf, but... Figure 2 For the sake of simplicity, the capacitance ratio is omitted, and the change in Vout is recorded as -Vrefp. This is also omitted in the timing diagrams of other embodiments described later.

[0051] Furthermore, the feedback of the quantization result Qout, i.e., the subtraction, is performed synchronously with the clock, which serves as the reference for controlling the timing of the ΔΣ modulator 100's operation. The feedback period, i.e., half the operating period of switches such as SD2 and SD3 that are related to the operation of DAC30, is called the unit time based on the clock frequency.

[0052] In conventional configurations, since the time involved in one sampling is a unit time based on the clock frequency, sampling ends at time t11, resulting in a hold state. In contrast, the ΔΣ modulator 100 of this embodiment, having switches SS3 and SS4, controls the operation of the integrator 10 and DAC30 independently by electrically disconnecting the sampling capacitor Cs from them. Therefore, sampling does not need to be terminated at time t11 in conjunction with the operation of the DAC30, and sampling of the analog signal Vin can continue even after time t11.

[0053] The driving of the switches at time t12 after the subtraction based on DAC30 is the same as at time t10, except for continuing to sample based on the sampling capacitor Cs. Specifically, by turning off the switch SD3, DAC30 is electrically disconnected from the integrator 10. In this state, the switch SD2 is turned on, the switches SDT and SDB of DAC30 are in the off state, and the switch SDM is turned on, whereby both ends of the DAC capacitor Cd are connected to AGND. That is, the DAC capacitor Cd is in a reset state.

[0054] At time t12, the quantizer 20 quantizes the output voltage Vout of the operational amplifier OP after performing the first subtraction from time t11 to time t12. That is, the second quantization in one sampling period of the ΔΣ modulation from time t10 to time t14 is performed. Since Vout at time t12 is Vth-≦Vout<Vth+, Qout outputs 0.

[0055] Then, at time t13, feedback based on the quantization result Qout of the second quantization is performed. Specifically, similar to the operation of each switch at time t11, the switch SD2 is turned off and the switch SD3 is turned on, thereby electrically connecting DAC30 to the integrator 10, and the subtraction corresponding to the quantization result Qout = 0 is performed by maintaining the state where the switch SDM is turned on. In addition, when the quantization result is Qout = 0, although the subtraction operation is performed, since AGND is selected as the DAC voltage, the subtraction is not substantially performed.

[0056] At time t13, while the subtraction operation is being performed, the switches SS1 and SS2 are turned off, and the switches SS3 and SS4 are turned on. That is, the electrical connection between the input signal Vin and the sampling capacitor Cs is cut off, and the sampling capacitor Cs is connected to the integrator 10. That is, it transfers to the holding period of transferring the charge based on the input signal Vin stored in the sampling capacitor Cs to the integration capacitor Cf.

[0057] As Figure 2 shown, at time t13, the second subtraction and the charge transfer from the sampling capacitor Cs are performed, subtracting AGND from the output voltage Vout of the operational amplifier OP, and adding the input signal Vin sampled during the period from time t10 to time t13 (recorded as Vin(1) in Figure 2 ).

[0058] Figure 2The period from time t10 to time t13 shown is, in this embodiment, the sampling period during which charge based on the input signal Vin is accumulated in the sampling capacitor Cs. The sampling period in this embodiment corresponds to three times the unit time based on the clock frequency. Furthermore, the period from time t10 to time t14 corresponds to one sampling cycle of the ΔΣ modulation in this embodiment, during which the quantization result Qout is fed back twice. That is, in this embodiment, one sampling and two feedback operations are performed within one sampling cycle of the ΔΣ modulation.

[0059] The operation of the second sampling cycle from time t14 to time t18 is the same as that of the first sampling cycle from time t10 to time t14. The feedback performed from time t14 to time t18 is based on the result of transferring charge to integrator 10 during the period from time t13 to time t14. This charge is the charge accumulated in the sampling capacitor Cs based on the input signal Vin sampled from time t10 to time t13. By repeating the same operation after time t18, the ΔΣ modulation operation can be continuously performed.

[0060] The effects produced by employing the ΔΣ modulator 100 of this embodiment will be explained.

[0061] The ΔΣ modulator 100 of this embodiment includes a switch SS3, which functions as a second control switch. Therefore, by turning off switch SS3, sampling of the analog signal Vin and feedback based on DAC 30 can be performed independently. Consequently, in this embodiment, multiple feedbacks can be performed for a single sample, allowing for more feedback within the same sampling period compared to conventional ΔΣ modulators that perform only one feedback per sample. That is, the quantization resolution based on the ΔΣ modulator can be improved.

[0062] The sampling frequency, which is related to the sampling of the analog signal Vin, is limited by the operating speed of the drive circuit configured in the front stage of the ΔΣ modulator and driving the sampling capacitor. However, if the ΔΣ modulator 100 of this embodiment is used, multiple feedbacks can be performed for one sampling. Therefore, even if the operating speed of the drive circuit is relatively low, the feedback of the quantization result can be maintained at a high speed, which can improve the resolution of the ΔΣ modulator.

[0063] Furthermore, by using a single DAC capacitor Cd in this embodiment, the DAC30 can be configured to eliminate ΔΣ modulation errors caused by DAC capacitor deviations, while also improving the resolution of ΔΣ modulation through multiple feedbacks. Therefore, compared to DACs composed of multiple DAC capacitors used in typical multi-bit ΔΣ modulators, high-resolution ΔΣ modulation feedback can be achieved without being affected by capacitor element deviations.

[0064] (Variation Example 1)

[0065] In addition, such as Figure 3 As shown, the phases related to the driving of switches SS1, SS2, SS3, and SS4 can also be delayed compared to the embodiments described above. Figure 3 In the example shown, the phase ratio related to the driving of switches SS1, SS2, SS3, and SS4 Figure 2 The example shown delays the unit of time. In such an example, since the timing of the turn-off of switches SS3 and SD3 does not overlap with the timing of the turn-off of switches SS2 and SD2, the effect of charge injection that accompanies the switching on and off can be reduced.

[0066] In addition, such as Figure 4 As shown, the phases related to the driving of switches SS1, SS2, SS3, and SS4 can also be advanced compared to the embodiments described above. Figure 4 In the example shown, the phase ratio related to the driving of switches SS1, SS2, SS3, and SS4 Figure 2 The example shown advances the unit time. In this way, with... Figure 3 The example shown, which involves a phase delay related to the driving of switches SS1, SS2, SS3, and SS4, similarly reduces the effect of charge injection into the switches, and... Figure 3 Compared to the example shown, the timing of obtaining the output voltage Vout after feedback is completed can be advanced. Therefore, the timing of quantizer 20 quantizing the output voltage Vout can be advanced, and the time from the execution of quantization to the execution of feedback by DAC 30 can be easily ensured, thus alleviating the speed requirements of quantizer 20.

[0067] (Variation Example 2)

[0068] In the first embodiment described above, an example was given where the sampling period was set to three times the unit time based on the clock frequency (from time t10 to time t13), and the hold period was the same as the unit time. However, since the sampling capacitor Cs, integrator 10, and DAC 30 can be independently controlled via switch SS3, the sampling period can be arbitrarily set. For example, it is possible to... Figure 5 As shown, both the sampling period and the hold period are set to twice the unit time.

[0069] When the circuit preceding the ΔΣ modulator 100 is, for example, a switched-capacitor circuit and operates at a low speed, it is necessary to match the low-speed operation of the switched-capacitor circuit. In addition to ensuring the sampling period of the ΔΣ modulator 100, the length of the hold period must also be sufficiently long to prevent the operation of the ΔΣ modulator 100 from affecting the output of the switched-capacitor circuit during the switching between the sampling and hold periods. By setting both the sampling period and the hold period to twice the unit time, as in this modified example, high-speed ΔΣ modulation feedback can be achieved even when the switched-capacitor circuit operates at a low speed.

[0070] (Variation Example 3)

[0071] Furthermore, in the above-described variation 2, when the input signals are differential analog signals Vin+ and Vin-, when transferring the charge based on Vin+ accumulated in the sampling capacitor Cs to the integrating capacitor Cf, the inverted signal of Vin+, namely Vin-, is input instead of AGND for the potential connected to the sampling capacitor Cs via switch SS4.

[0072] In this modification, since the inverted signal Vin- of Vin+ is used when transferring charge from the sampling capacitor Cs to the integrating capacitor Cf, a charge substantially twice that of the analog signal Vin+ can be transferred to the integrating capacitor Cf when the value of the sampling capacitor Cs is the same as in Modification 2. In other words, in this modification, even if the capacitance value of the sampling capacitor Cs is set to half that of Modification 2, the same amount of charge can be transferred. Therefore, the load on the circuitry used to drive the sampling capacitor Cs can be reduced, and the impact of thermal noise generated by the sampling of the sampling capacitor Cs can be reduced.

[0073] (Variation Example 4)

[0074] In the first embodiment and variations 1 and 2 described above, an example is shown where the quantizer 20 operates in 1.5-bit increments. In the above examples, as... Figures 2-5 As shown, for the charge sampled in one sampling period, multiple quantizations and multiple feedbacks corresponding to the number of quantizations are performed.

[0075] In this variation, the operation of using a quantizer 20 with a resolution of more than 2 bits for one sample and performing ΔΣ modulation based on one quantization of quantizer 20 and multiple feedback based on DAC 30 is explained.

[0076] The configuration of the ΔΣ modulator 100 in this modified example is the same as that of the ΔΣ modulator 100 described in the first embodiment, except for the quantizer 20. Furthermore, for the different element, namely the quantizer 20, a known quantizer with a resolution of 2 bits or more can be used.

[0077] For example, referring to Figure 6 , a method in which the sampling period is set to three times the unit time as in the first embodiment will be described. Similar to the first embodiment, at time t10, quantization is performed on the output voltage Vout at the time point of t10, and sampling starts. Sampling continues until time t13, but a total of two feedbacks are performed at time t11 and time t13 during this period. In addition, after time t10 and until time t14 when the next sampling period starts, quantization is not performed, and the second feedback is performed based on the result of one quantization at time t10.

[0078] In Figure 6 's example, the quantizer 20 is a quantizer with a resolution of 2.5 bits (5 levels), and has Vth1+, Vth1-, Vth2+, Vth2- as quantization reference values. When Vout ≧ Vth2+, the quantizer 20 outputs 2 as Qout; when Vth1+ ≦ Vout < Vth2+, it outputs 1 as Qout; when Vth1- ≦ Vout < Vth1+, it outputs 0 as Qout; when Vth2- ≦ Vout < Vth1-, it outputs -1 as Qout; and when Vout < Vth2-, it outputs -2 as Qout.

[0079] The quantization result Qout of the quantization at time t10 is 1. During the two feedbacks in the period from time t10 to time t14, subtraction based on the reference voltage Vrefp and subtraction based on the reference voltage Vcm are each performed once by the DAC 30. Similarly, the quantization result Qout of the quantization at time t14 is 2, and subtraction based on the reference voltage Vrefp is performed twice during the two feedbacks in the period from time t14 to time t18.

[0080] This example is a case where the sampling period is set to three times the unit time when one quantization is performed on one sampling by a quantizer with a resolution of two bits or more. By performing one quantization on one sampling using a quantizer with a resolution of two bits or more and using the quantization result Qout of this one quantization to perform multiple feedbacks, similar to the first embodiment and modification 1, a higher resolution can be achieved compared to the conventional ΔΣ modulator.

[0081] In addition, as another example, referring to Figure 7The method described is similar to Variation 2, where the sampling time is set to twice the unit time. Similar to Variation 2, at time t10, quantization is performed on the output voltage Vout at time t10, and sampling begins. Sampling continues until time t12, and a hold period occurs from time t12 to time t14. During this period, feedback is performed twice, at times t11 and t13. Furthermore, after time t10, until the start of the next sampling period at time t14, no quantization is performed; instead, the two feedbacks are performed based on the result of the first quantization at time t10. The same operation as from time t10 to time t14 is repeated from time t14 to time t18.

[0082] This example demonstrates how a single sample is quantized once using a quantizer with a resolution of 2 bits or more, and the sampling period is set to twice the unit time. Similar to Variation 2, this example achieves higher resolution compared to conventional ΔΣ modulators.

[0083] (Second Implementation)

[0084] In the first embodiment and variations 1 to 4, an example was described where the ΔΣ modulator 100 has a single sampling capacitor Cs. In contrast, for example, if the preceding drive circuit operates at a lower speed, it is also possible to... Figure 8 The ΔΣ modulator 110 is configured as shown, having two sampling capacitors, Csa and Csb. Therefore, by staggering the sampling periods of the two sampling capacitors, the analog signal Vin input from the drive circuit can be sampled alternately using the two sampling capacitors.

[0085] In this embodiment, the ΔΣ modulator 110 has sampling capacitors Csa and Csb connected in parallel between the input terminal of the analog signal Vin and the integrator 10. The sampling capacitors Csa and Csb have the same configuration as the sampling capacitor Cs and the four switches (SS1, SS2, SS3, SS4) connected to the capacitor in the first embodiment, and are connected in parallel.

[0086] Specifically, the sampling capacitor Csa is inserted between the midpoint of the integrating capacitor Cf and the inverting input terminal of the operational amplifier OP, and the input terminal of the analog signal Vin. Furthermore, a switch SS1a is inserted between the input terminal of the analog signal Vin and the sampling capacitor Csa, and a switch SS3a is inserted between the sampling capacitor Csa and the integrator 10. The midpoint between switch SS1a and the sampling capacitor Csa can be connected to AGND, which serves as a reference potential, via switch SS4a. The midpoint between switch SS3a and the sampling capacitor Csa can be connected to AGND via switch SS2a.

[0087] The sampling capacitor Csb is also inserted between the midpoint of the integrating capacitor Cf and the inverting input terminal of the operational amplifier OP, and the input terminal of the analog signal Vin. Furthermore, a switch SS1b is inserted between the input terminal of the analog signal Vin and the sampling capacitor Csb, and a switch SS3b is inserted between the sampling capacitor Csb and the integrator 10. The midpoint between switch SS1b and the sampling capacitor Csb can be connected to AGND via switch SS4b. The midpoint between switch SS3b and the sampling capacitor Csb can be connected to AGND via switch SS2b.

[0088] Furthermore, the capacitance values ​​of the two sampling capacitors Csa and Csb can be arbitrarily set, but in this embodiment they are set to the same capacitance values. In addition, apart from the differences in the configuration of the sampling capacitors Csa, Csb and the switches connected to these capacitors, the configurations of the integrator 10, quantizer 20 and DAC 30 are the same as in the first embodiment and variations 1 to 4.

[0089] Reference Figure 9 The operation of the ΔΣ modulator 110 in this embodiment will be explained. Figure 9 The time graph shown uses time as the horizontal axis to represent the on / off state of each switch. Furthermore, the actions at times t20 to t28 correspond to the actions at times t10 to t18 in the first embodiment.

[0090] In this embodiment, the sampling capacitor Csa first samples a portion of the analog signal Vin. For example... Figure 9 As shown, at time t20, switches SS3a and SS4a are turned off and switches SS1a and SS2a are turned on, thus initiating the sampling of the analog signal Vin. At this time, the control switch on the sampling capacitor Csb side, i.e., switch SS1b, is turned off, and no sampling occurs in the sampling capacitor Csb.

[0091] At time t20, simultaneously with the start of sampling, switch SD3 is turned off. This electrically disconnects DAC30 from integrator 10. Furthermore, switch SD2 is turned on, and switches SDT and SDB of DAC30 are turned off; switch SDM is turned on, and the two ends of DAC capacitor Cd are connected to AGND. That is, DAC capacitor Cd is reset.

[0092] Furthermore, at time t20, as a result of ΔΣ modulation performed on the signal sampled before time t20, the output voltage Vout of the operational amplifier OP immediately preceding time t20 is quantized to generate the quantization result Qout.

[0093] Then, at time t21, feedback from the DAC 30 to the integrator 10 based on the quantization result Qout is performed. Specifically, based on the quantization result Qout, the control circuit 40 turns off the switch SD2 and turns on the switch SD3, thereby electrically connecting the DAC 30 and the integrator 10. Further, by turning on the switch SDT while the switch SDM is turned off, charge subtraction corresponding to Qout = 1 is performed by the DAC 30.

[0094] The driving of the switches at time t22 after the subtraction by the DAC 30 is the same as at time t20, except that sampling by the sampling capacitor Csa continues. Specifically, by turning off the switch SD3, the DAC 30 is electrically disconnected from the integrator 10. In this state, the switch SD2 is turned on, the switches SDT and SDB of the DAC 30 are turned off, and both ends of the DAC capacitor Cd are connected to AGND by turning on the switch SDM. That is, the DAC capacitor Cd is in a reset state.

[0095] At time t22, the quantizer 20 quantizes the output voltage Vout of the operational amplifier OP after the first subtraction from time t21 to time t22. That is, the second quantization in one sampling period of the ΔΣ modulation from time t20 to time t24 is performed. Since Vout at time t22 is Vth-≦Vout<Vth+, 0 is output for Qout.

[0096] In the present embodiment, at time t24, sampling by the sampling capacitor Csa ends, and sampling by the sampling capacitor Csb starts. As Figure 9 shown, the switches SS1a and SS2a are turned off and the switches SS3a and SS4a are turned on, and the charge stored in the sampling capacitor Csa is transferred to the integration capacitor Cf. In addition, the sampling capacitor Csa is electrically disconnected from the input terminal of the analog signal Vin. At the same time, the switches SS1b and SS2b are turned on and the switches SS3b and SS4b are turned off, and the input terminal of the analog signal Vin is electrically connected to the sampling capacitor Csb. That is, sampling by the sampling capacitor Csb starts.

[0097] In addition, the operations from time t24 to time t28 are the same as the operations from time t20 to time t24, except that the sampling capacitor for sampling the analog signal Vin is switched from Csa to Csb, so detailed description is omitted. As described above, which of the switches SDT, SDM, and SDB is turned on or off is determined according to the quantization result Qout, and the operations of the switches SDT, SDM, and SDB are not limited to Figure 9 the example shown.

[0098] If the ΔΣ modulator 110 of this embodiment is used, two sampling capacitors Csa and Csb can be used to alternately sample an analog signal Vin by staggering the sampling periods. Therefore, even if the operating speed of the front-end drive circuit is lower, the sampling period can be lengthened to match the operating speed of the drive circuit, and feedback based on DAC30 can be executed at high speed.

[0099] (Third Implementation)

[0100] In the first and second embodiments, examples of constructing a ΔΣ modulator using a single integrator 10 are shown. That is, the ΔΣ modulators 100 and 110 in the first and second embodiments are first-order ΔΣ modulators. In contrast, this embodiment describes an example of constructing a second-order ΔΣ modulator.

[0101] First, refer to Figure 10 The configuration of the ΔΣ modulator 120 in this embodiment will be described.

[0102] like Figure 10 As shown, the ΔΣ modulator 120 is configured such that a second modulation circuit 122 is inserted between the output terminal of the operational amplifier OP in the ΔΣ modulator 100 described in the first embodiment and the quantizer 20. For convenience, the portion disposed between the input terminal of the analog signal Vin and the second modulation circuit 122, corresponding to the pre-stage of the quantizer 20 in the ΔΣ modulator 100 of the first embodiment, is referred to as the first modulation circuit 121.

[0103] The first modulation circuit 121 includes a first integrator 11, a first D / A converter 31 (hereinafter referred to as the first DAC 31), and a first sampling capacitor Cs1. The first integrator 11, the first DAC 31, and the first sampling capacitor Cs1 are respectively equivalent to the integrator 10, the DAC 30, and the sampling capacitor Cs in the first embodiment, and their interconnections are also the same.

[0104] That is, the first integrator 11 has a first operational amplifier OP1 and a first integrating capacitor Cf1. The output terminal of the first operational amplifier OP1 is connected to the first input terminal (=inverting input terminal) via the first integrating capacitor Cf1, and the second input terminal (=non-inverting input terminal) is connected to AGND, which serves as a reference potential.

[0105] The first DAC 31 has a first DAC capacitor Cd1. At one end of the first DAC capacitor Cd1, voltage sources generating reference voltages Vrefp, Vcm, and Vrefm are connected via switches SD1T, SD1M, and SD1B. Specifically, at one end of the first DAC capacitor Cd1, Vcm (e.g., AGND) is connected via switch SD1M, Vrefp is connected via switch SD1T, and Vrefm is connected via switch SD1B. The potential at one end of the first DAC capacitor Cd1 is equal to one of Vrefp, Vcm, or Vrefm, which is exclusively selected by switches SDT, SDM, and SDB.

[0106] One end of the first DAC capacitor Cd1, opposite to the end connected to the reference voltage, is connected via switch SD13 to the midpoint between the inverting input terminal of the first operational amplifier OP1 and the first integrating capacitor Cf1, and can be connected to AGND via switch SD12. That is, the first DAC 31 is connected to the first integrator 11 via switch SD13, and one end of the first DAC capacitor Cd1 can be connected to AGND via switch SD12. In this embodiment, switch SD13 corresponds to the first control switch.

[0107] The first sampling capacitor Cs1 is inserted between the input terminal of the analog signal Vin and the first integrator 11. Specifically, one end of the first sampling capacitor Cs1 is connected to the input terminal of the analog signal Vin via switch SS11, and the other end is connected via switch SS13 to the midpoint between the inverting input terminal of the first operational amplifier OP1 and the first integrating capacitor Cf1. That is, if switch SS13 is turned on, the end of the first sampling capacitor Cs1 on the first operational amplifier OP1 side is electrically connected to the first integrating capacitor Cf1. Furthermore, the midpoint between the first sampling capacitor Cs1 and switch SS11 can be connected to AGND via switch SS14, and the midpoint between the first sampling capacitor Cs1 and switch SS13 can be connected to AGND via switch SS12.

[0108] The second modulation circuit 122 has the same constituent elements and connections as the first modulation circuit 121. That is, as shown in the figure... Figure 10 As shown, the second modulation circuit 122 includes a second integrator 12, a second D / A converter 32 (hereinafter referred to as the second DAC 32), and a second sampling capacitor Cs2. The second integrator 12, the second DAC 32, and the second sampling capacitor Cs2 are respectively equivalent to the first integrator 11, the first DAC 31, and the first sampling capacitor Cs1 in the first modulation circuit 121, and their interconnections are also the same.

[0109] That is, for the descriptions related to the configuration of the first modulation circuit 121, simply replace the descriptions of the first integrator 11, the first DAC 31, and the first sampling capacitor Cs1 with the descriptions of the second integrator 12, the second DAC 32, and the second sampling capacitor Cs2. The second integrator 12 has a second operational amplifier OP2 and a second integrating capacitor Cf2, and the second DAC 32 has a second DAC capacitor Cd2. The switches are as follows: the switches corresponding to SS11, SS12, SS13, and SS14 are respectively called switches SS21, SS22, SS23, and SS24; the switches corresponding to SD12 and SD13 are respectively called switches SD22 and SD23; and the switches corresponding to SD1T, SD1M, and SD1B are respectively called switches SD2T, SD2M, and SD2B.

[0110] Furthermore, in the second modulator circuit 122, the output terminal of the second operational amplifier OP2 corresponds to the second output terminal, and the inverting input terminal corresponds to the third input terminal. Additionally, switch SD23 corresponds to the third control switch, and switch SS23 corresponds to the fourth control switch.

[0111] The output voltage Vout1 of the first operational amplifier OP1 in the first modulation circuit 121 is input to the second sampling capacitor Cs2 via switch SS21. On the other hand, the output voltage Vout2 of the second operational amplifier OP2 in the second modulation circuit 122 is input to vectorizer 20. Feedback of the quantization result Qout is performed using both the first DAC31 and the second DAC32.

[0112] Next, refer to Figure 11 The operation of the ΔΣ modulator 120 will be explained. The operation at times t30 to t38 corresponds to the operation at times t10 to t18 in the first embodiment.

[0113] The first DAC31 of the first modulation circuit 121 and the second DAC32 of the second modulation circuit 122 operate synchronously. Specifically, switches SD12 and SD22, switches SD13 and SD23, switches SD1T and SD2T, switches SD1M and SD2M, and switches SD1B and SD2B each perform the same operation. On the other hand, the switching operations related to sampling are different between the first modulation circuit 121 and the second modulation circuit 122.

[0114] At time t30, switches SS11 and SS12 are turned on, while switches SS13 and SS14 are turned off. Thus, sampling is performed with the first sampling capacitor Cs1 electrically disconnected from the first integrator 11.

[0115] At this time, in the second modulation circuit 122, the switches SS21 and SS22 are turned on and the switches SS23 and SS24 are turned off. As a result, the second sampling capacitor Cs2 is electrically disconnected from the second integrator 12. Since the switch SS21 is turned on, the second sampling capacitor Cs2 and the output terminal of the first operational amplifier OP1 are connected. That is, in the second sampling capacitor Cs2, corresponding to the analog signal Vin sampled before time t30, charges corresponding to the output voltage Vout1 output from the first operational amplifier OP1 are accumulated.

[0116] In addition, at time t30, the quantizer 20 quantizes the output voltage Vout2 of the second operational amplifier OP2 at time t30. The quantizer 20 of the present embodiment uses the same quantizer with a resolution of two bits or more as in the fourth modification example, and performs quantization once in one sampling period. At time t30, since Vth2 - ≤ Vout2 < Vth1 -, the quantization result Qout is -1.

[0117] At time t31, the first sampling capacitor Cs1 continues to sample the analog signal Vin, and the sampling of the output voltage Vout1 of the first operational amplifier OP1 by the second sampling capacitor Cs2 in the subsequent second modulator 122 ends. As a result, charges are accumulated in the second sampling capacitor Cs2. That is, the switches SS21 and SS22 are turned on, and the switches SS23 and SS24 are turned off. In addition, when the output voltage Vout1 during the period from time t30 to time t31 is set to Figure 11 the shown Vout1(0), the charges based on Vout1(0) are accumulated in the second sampling capacitor Cs2 during the period from time t30 to time t31, and these charges are transferred to the second integration capacitor Cf2 after time t31.

[0118] Similar to the first embodiment and the second embodiment, during the period from time t31 to time t32 and during the period from time t33 to time t34, feedback based on the quantization result Qout of the first DAC 31 and the second DAC 32 is performed, and subtraction is performed from the charges respectively accumulated in the first integration capacitor Cf1 and the second integration capacitor Cf2. In addition, the change amounts of Vout1 and Vout2 at each time are determined by the capacitance ratio of the ΔΣ modulator 120. However, since it is the same as the magnification of a normal switched-capacitor circuit, similar to other timing diagrams, it is also omitted for simplicity in Figure 11 Herein. In addition, regarding Figure 11The change in Vout2 caused by the use of feedback from the second DAC32 is recorded as -2Vrefm, -2AGND, and -2Vrefp when the amplification of each integrator is set to 1 in a typical feedback-type second-order ΔΣ modulator.

[0119] At time t33, the second subtraction begins. Furthermore, the charge accumulated in the first sampling capacitor Cs1 is transferred to the first integrating capacitor Cf1. In this embodiment, the feedback is also performed twice during the sampling period from time t30 to time t34.

[0120] Subsequently, during the sampling period from time t34 to time t38, each switch performs the same operation as during the sampling period from time t30 to time t34. The sampling period from time t34 to time t38 is equivalent to the second sampling period.

[0121] In this embodiment, a ΔΣ modulator 120 comprising a first sampling capacitor Cs1 and a second sampling capacitor Cs2 is described. The sampling period of the first sampling capacitor Cs1 is three times the unit time, enabling high-speed execution of ΔΣ modulation feedback even when the circuit driving the first sampling capacitor Cs1 is operating at low speed. Furthermore, an example is described where the sampling period of the second sampling capacitor Cs2 is one unit time. However, since the second sampling capacitor Cs2 samples the output voltage Vout1 of the first operational amplifier OP1, when the first operational amplifier OP1 is, for example, a fully differential amplifier capable of high-speed operation, the sampling performed by the second sampling capacitor Cs2 does not limit the operating speed of the ΔΣ modulator 120, allowing for high-speed execution of ΔΣ modulation feedback.

[0122] Furthermore, in this embodiment, the case where the ΔΣ modulator 120 is a second-order ΔΣ modulator has been described, but it is also possible to configure it such that in a ΔΣ modulator with three or more orders, the sampling period of the sampling capacitor corresponding to the first sampling capacitor Cs is set to be longer than the unit time.

[0123] (Other implementation methods)

[0124] The above describes various embodiments of the present invention, but it is not limited to the above embodiments at all. Various modifications can be made to implement the invention without departing from the spirit of the invention.

[0125] In the above embodiments and variations, examples of sampling periods being 2 or 3 times the unit time are given to simplify the explanation of the operation. However, the sampling period is not limited to less than 3 times the unit time and can be set to be greater than 3 times the unit time. Similarly, examples of holding periods being equal to or twice the unit time are given, but can also be set to be greater than twice the unit time.

[0126] Furthermore, in Modification 2, configurations that delay the phase during the sampling period by one unit time and configurations that advance the phase by one unit time relative to the first embodiment were described. However, the phase during the sampling period can also be appropriately changed within a range exceeding one unit time. Similarly, the phase during the sampling period can also be appropriately changed in embodiments and modifications other than the first embodiment and Modification 2.

[0127] Furthermore, in the above embodiments and variations, examples were described of multiple feedbacks of the quantization result Qout within one sampling period, and one feedback within two unit time periods. However, it is also possible to perform feedback once within a period of three or more unit time periods, or once within one unit time period. Moreover, the feedback of the quantization result Qout does not need to be performed at equal time intervals; the timing of the feedback can be determined based on the operating state of the sampling capacitor, the operating state of the circuit preceding the driving sampling capacitor, and the desired resolution.

[0128] Furthermore, in the above embodiments and modifications, a method was described in which the feedback of the quantization result Qout determines the DAC voltage and transfers charge to the integrating capacitor after resetting the DAC capacitor Cd. However, other methods can also be used for the transfer of charge from the DAC capacitor Cd to the integrating capacitor. For example, a method could be chosen where the DAC voltage is determined first and then set to AGND to transfer charge to the integrating capacitor. Alternatively, a method could be chosen where the charge is transferred by first determining the first DAC voltage and then determining the second DAC voltage.

[0129] Furthermore, in the above embodiments and variations, an example of inputting a predetermined analog signal Vin as the quantization result Qout was presented to simplify the explanation of the operation. However, since the quantization result Qout depends on the input analog signal Vin and the number of bits of the quantizer 20, Qout is not necessarily limited to the above example. Therefore, the reference voltages (DAC voltages) of DACs 30, 31, and 32, determined in the feedback of the quantization result Qout, are exclusively selected from Vrefp, Vm, and Vrefm, depending on the analog signal Vin. That is, the reference voltages are appropriately selected based on the quantization result Qout.

[0130] Furthermore, in the above embodiments and variations, the quantizer 20 was described with a resolution of 1.5 bits or 2.5 bits, but a quantizer with a resolution of 1 bit or more is used.

[0131] Furthermore, in the above embodiments and variations, examples of performing quantization once or twice in one sampling period have been described. However, the number of quantizations can be appropriately determined based on the resolution of the quantizer 20, the resolution of the DAC, and the number of times the quantization result Qout is fed back in one sampling period. Moreover, the timing of quantization is such that the quantization result Qout can be obtained before the corresponding quantization result Qout is fed back; therefore, it can be appropriately determined based on the operating state of the DAC and the operating state of the sampling capacitor.

[0132] Furthermore, in the above embodiments and variations, the configuration of a first-order or second-order feedback-type ΔΣ modulator has been described, but higher-order modulators, feedforward type, cascade type, etc., ΔΣ modulators can also be used.

[0133] Furthermore, by using the ΔΣ modulator described in the above embodiments and variations, and by using a digital filter arranged in the same manner as a conventional ΔΣ modulator in the subsequent stage of the ΔΣ modulator, the output of the ΔΣ modulator, i.e., the ΔΣ modulation result (also commonly referred to as the bit stream), can be processed, thereby constructing an A / D converter. Alternatively, the ΔΣ modulator can also be used as a so-called incremental ΔΣ A / D converter, in which an integrator composed of digital circuitry of a number of stages corresponding to the order of the ΔΣ modulator is arranged in place of a digital filter in the subsequent stage of the ΔΣ modulator. After temporarily resetting the integrator composed of the ΔΣ modulator and the digital circuitry, the integrator is operated for a predetermined period, thereby enabling it to operate as an A / D converter.

[0134] Furthermore, in the above embodiments and variations, a single-ended circuit configuration was used for the purpose of simplifying the explanation, but a differential circuit configuration may also be used.

Claims

1. A ΔΣ modulator, comprising: The integrators (10, 11) have operational amplifiers (OP, OP1) and integrating capacitors (Cf, Cf1) inserted between the first input terminal and the output terminal of the operational amplifiers. The quantizer (20) outputs the quantization result (Qout) of the output signal of the above operational amplifier; DACs (30, 31) are connected to the first input terminal of the operational amplifier via the first control switch (SD3, SD13) to subtract the charge based on the quantization result from the charge stored in the integrating capacitor and to feed back the quantization result in ΔΣ modulation to the integrator. The control circuit (40) outputs a digital output value based on the above quantization result; as well as The sampling capacitors (Cs, Cs1) are connected at one end to the first input terminal of the operational amplifier via the second control switch (SS3, SS13), and at the other end to the drive circuit via switches (SS1, SS11), accumulating charge based on the analog signal (Vin) that serves as the input signal to the drive circuit. The second control switch is located between the sampling capacitor, the integrating capacitor, and the midpoint of the first input terminal, and can switch the electrical connection between the sampling capacitor and the midpoint on and off. During one sampling period, which includes the sampling period when the second control switch is in the off state and the sampling period when it is in the on state, the quantization results of the above-mentioned analog signal are fed back to the integrator multiple times during the ΔΣ modulation of the above-mentioned analog signal. The first control switch described above switches on and off multiple times within one sampling period, based on feedback from the integrator to the quantization results obtained from multiple quantizations. The aforementioned switches (SS1, SS11) are turned on for more than half of the aforementioned sampling period.

2. The ΔΣ modulator as claimed in claim 1, wherein, The quantizers described above have a resolution of 1 bit or 1.5 bits. The quantization performed by the quantizer described above is carried out the same number of times the quantization result is fed back to the integrator in one sampling period.

3. The ΔΣ modulator as claimed in claim 1, wherein, Based on the multiple quantization results output in one sampling period, the above digital output value corresponding to each sampling period is determined.

4. The ΔΣ modulator as claimed in claim 1, wherein, The quantizers described above have a resolution of 2 bits or more. By feeding back the quantization results to the integrator via the DAC, quantization by the quantizer is performed only once per sampling period.

5. The ΔΣ modulator as claimed in claim 1, wherein, The sampling period is set to three times the time relative to half the period of the period related to the feedback of the quantization result of the quantizer to the integrator.

6. The ΔΣ modulator as claimed in claim 1, wherein, The sampling period is set to twice the time relative to half the period of the period related to the feedback of the quantization result of the quantizer to the integrator.

7. The ΔΣ modulator as claimed in any one of claims 1 to 6, wherein, The output terminal of the aforementioned operational amplifier is connected to the aforementioned quantizer via the second modulation circuit (122). The second modulation circuit described above includes: The second integrator (12) has a second operational amplifier (OP2) and a second integrating capacitor (Cf2) inserted between the third input terminal and the second output terminal of the second operational amplifier; The second DAC (32), connected to the third input terminal of the second operational amplifier via the third control switch (SD23), determines the DAC voltage for subtracting the charge stored in the second integrating capacitor based on the feedback of the quantization result to the second integrator; and The second sampling capacitor (Cs2) is connected to the third input terminal of the second operational amplifier via the fourth control switch (SS23) to accumulate charge based on the output signal of the operational amplifier. The fourth control switch is located between the second sampling capacitor, the second integrating capacitor, and the third input terminal at the midpoint, and can switch the electrical connection between the second sampling capacitor and the midpoint on and off. During one sampling period, which includes the first sampling period when the second control switch is in the off state and the period when it is in the on state, the quantization results are fed back to the integrator multiple times. During one sampling period, which includes the second sampling period when the aforementioned fourth control switch is in the off state and the period when it is in the on state, the aforementioned quantization results are fed back to the aforementioned second integrator multiple times. The input analog signal is modulated by ΔΣ at least twice.

8. The ΔΣ modulator as claimed in claim 7, wherein, The first control switch and the third control switch mentioned above are driven synchronously.

9. The ΔΣ modulator as claimed in claim 7, wherein, The phases or durations of the first and second sampling periods described above are different from each other.

10. A ΔΣ A / D converter, wherein, The ΔΣ modulator is provided according to any one of claims 1 to 9.

11. An incremental ΔΣ A / D converter, wherein, The ΔΣ modulator is provided according to any one of claims 1 to 9.

Images