Image pickup display terminal

Abstract

This application provides an image capture and display terminal, including a control module, a first optimization unit, a second optimization unit, a first image capture module, a second image capture module, and a first node. The control module outputs control signals to control the first image capture module and the second image capture module to be in working state simultaneously. A first signal interface is electrically connected to the first node. The first optimization unit is electrically connected between the first node and the first image capture module, and the second optimization unit is electrically connected between the first node and the second image capture module. The first optimization unit is used to ensure that the first image signal curve corresponding to the first image captured by the first image capture module is smooth when the first image capture module is in working state, and the second optimization unit is used to ensure that the second image signal curve corresponding to the second image captured by the second image capture module is smooth when the second image capture module is in working state.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to an image capture and display terminal. Background Technology

[0002] As users' demands for image quality increase, electronic terminals typically employ two or more camera modules, such as high-definition cameras, to simultaneously capture images, achieving better shooting results and meeting users' image quality requirements. However, the increase in the number of camera modules also leads to an increase in the number of components and connecting cables required between the camera modules and the image processing module, affecting the board space occupied and the wiring complexity. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an image capture and display terminal that reduces the impact on the space occupied by the circuit board.

[0004] An image capture display terminal includes an image capture switching control module that performs switching for different image capture modules. The image capture switching control module includes a control module, a first optimization unit, a second optimization unit, a first image capture module, a second image capture module, and a first node. The control module includes a first control bus and a first signal interface. The control module is electrically connected to the first image capture module and the second image capture module through the first control bus. The control module outputs control signals to control the first image capture module and the second image capture module to be in a working state simultaneously. The first signal interface is electrically connected to the first node. The first optimization unit is electrically connected to the first node and the first image capture module, and the second optimization unit is electrically connected to the first node and the second image capture module. The first image capture module is used to capture a first image and output a first image signal, and the second image capture module is used to capture a second image and output a second image signal. When the first image acquisition module is in working state under the control of the control signal, the first image signal corresponding to the acquired first image is transmitted to the first signal interface via the first optimization unit, and the first optimization unit is used to ensure that the curve of the first image signal is smooth; when the second image acquisition module is in working state under the control of the control signal, the second image signal corresponding to the acquired second image is transmitted to the first signal interface via the second optimization unit, and the second optimization unit is used to ensure that the curve of the second image signal is smooth.

[0005] The control module can directly control the working status of the first image acquisition module or the second image acquisition module through the control bus. By sharing the first signal interface, it effectively saves the signal interfaces used to transmit image signals provided by different image acquisition modules. There is no need to set up separate analog switching switches for the working status of the first image acquisition module and the second image acquisition module. This effectively reduces the number of components and traces on the circuit board, simplifies the circuit board structure, and provides more layout space for setting up other functional components.

[0006] In one embodiment of this application, the control module controls the first image acquisition module and the second image acquisition module to not be in a working state simultaneously, including: when the first image acquisition module is in a working state, the second image acquisition module is in a non-working state. When the first image acquisition module is in a non-working state, the second image acquisition module is in a working state. When the first image acquisition module is in a working state, that is, the first image acquisition module is in a high-speed low-impedance mode to acquire a first image signal and transmit it from the first signal interface to the control module, the second image acquisition module is in a non-working state, that is, the second image acquisition module is in a low-power high-impedance mode, at which time the second image acquisition module stops acquiring a second image. When the second image acquisition module is in a working state, that is, the second image acquisition module is in a high-speed low-impedance mode, and the first image acquisition module is in a non-working state, that is, the first image acquisition module is in a low-power high-impedance mode, the second image acquisition module acquires a second image signal and transmits it from the first signal interface to the control module, and the first image acquisition module stops acquiring a first image.

[0007] When the first image acquisition module is in a low-power, high-impedance mode, its impedance is greater than 100 ohms; when the second image acquisition module is in a low-power, high-impedance mode, its impedance is greater than 100 ohms. Since the impedance of the image acquisition module in the non-operating state is greater than 100 ohms, signal interference to the image acquisition module in the operating state can be effectively reduced, thus ensuring the quality of the image signal.

[0008] In one embodiment of this application, when the first image acquisition module is in high-speed low-impedance mode and the second image acquisition module is in low-power high-impedance mode, the first optimization unit specifically smooths the curve of the first image signal by eliminating back grooves in the first image signal. Similarly, when the second image acquisition module is in high-speed low-impedance mode and the first image acquisition module is in low-power high-impedance mode, the second optimization unit specifically smooths the curve of the second image signal by eliminating back grooves in the second image signal. The first and second optimization units can effectively eliminate back grooves and noise on the curve of the image signal caused by trace remnants between the non-operating image acquisition module and the operating image acquisition module.

[0009] In one embodiment of this application, the first optimization unit includes a first resistor, and the second optimization unit includes a second resistor. The first resistor is electrically connected to the control module through a first node, and the second resistor is electrically connected to the control module through the first node.

[0010] Wherein, the distance between the first node and the control module is greater than the distance between the first node and the first image acquisition module; or the distance between the first node and the control module is greater than the distance between the first node and the second image acquisition module. The first node, the first optimization unit, and the second optimization unit are set as close as possible to the image acquisition module, thereby effectively reducing the impact of residual wiring.

[0011] In one embodiment of this application, a first image acquisition module and a second image acquisition module are arranged side by side on a first straight line, the first straight line being parallel to the control module. The first node is located on the first straight line or between the first straight line and the control module, thereby making the distance from the first node to the first image acquisition module and the second image acquisition module smaller, further reducing the impact of residual wiring.

[0012] In one embodiment of this application, the first optimization unit further includes a first inductor connected in series between the first resistor and the first image capturing module. The second optimization unit further includes a second inductor connected in series between the second resistor and the second image capturing module. The first inductor is used to filter out noise from the first image signal; the second inductor is used to filter out noise from the second image signal. This further ensures that the image signal provided to the control module is complete, accurate, and of good quality.

[0013] In one embodiment of this application, the first signal interface includes a clock signal interface and a data signal interface. The clock signal interface is used to receive a clock control signal from the first image signal or the second image signal, and the data signal interface is used to receive image data from the first image signal or the second image signal. Specifically, the clock signal interface includes a pair of clock differential pairs electrically connected to the first node, and the data signal interface includes a pair of data differential pairs electrically connected to the first node.

[0014] Specifically, the first optimization unit includes four first resistors, which are electrically connected to the first node and the first image acquisition module, respectively, corresponding to the clock differential pair interface and the data differential pair interface; the second optimization unit includes four second resistors, which are electrically connected to the first node and the second image acquisition module, respectively, corresponding to the clock differential pair interface and the data differential pair interface.

[0015] In one embodiment of this application, the first optimization unit further includes four first inductors, which are electrically connected between the four first resistors and the first image capturing module. The second optimization unit further includes four second inductors, which are electrically connected between the four second resistors and the second image capturing module.

[0016] In the first signal interface, each of the shared clock differential pair interface and data differential pair interface is individually equipped with resistors and inductors to optimize the image signal, thereby ensuring that the image signals transmitted and received by each interface are as interference-free as possible, and remain complete, accurate and of good quality.

[0017] In one embodiment of this application, the first optimization unit further includes two first common-mode inductors, each first common-mode inductor including two first sub-inductors, and a first resistor connected in series with one first sub-inductor; the second optimization unit further includes two second common-mode inductors, each second common-mode inductor including two second sub-inductors, and a first resistor connected in series with one second sub-inductor. Specifically, the two first resistors are connected in series with one first common-mode inductor and electrically connected between the first node and the first image acquisition module corresponding to the clock differential interface; the two second resistors are connected in series with one second common-mode inductor and electrically connected between the first node and the second image acquisition module corresponding to the clock differential interface; the other two first resistors are connected in series with another first common-mode inductor and electrically connected between the first node and the first image acquisition module corresponding to the data differential interface; the other two second resistors are connected in series with another second common-mode inductor and electrically connected between the first node and the second image acquisition module corresponding to the data differential interface.

[0018] Because of the high integration of the common-mode inductor, it can not only eliminate noise in the image signal, but also simplify wiring complexity and improve wiring efficiency.

[0019] In one embodiment of this application, the first node is spaced a first distance from the first image capturing module; the first node is spaced a second distance from the second image capturing module; the first distance and the second distance are the same, the first resistor and the second resistor have the same resistance value, and the first inductor and the second inductor have the same inductance value. Since the first node is at the same distance from the first image capturing module and the second image capturing module, and the component sizes and parameters are also the same, the influence effect of trace stubs between the first node and the first and second image capturing modules is the same, thereby ensuring better consistency of the image signal transmitted from the first node to the control module under low interference conditions.

[0020] Specifically, when the first distance and the second distance are 10 mm, the resistance values ​​of the first resistor and the second resistor are the same, which is 10 ohms, and the inductance values ​​of the first inductor and the second inductor are 27 nanohenries.

[0021] In one embodiment of this application, the first node is spaced a first distance from the first image acquisition module; the second node is spaced a second distance from the second image acquisition module, the first distance being different from the second distance. The first resistor and the second resistor have the same resistance value, while the first inductor and the second inductor have different inductance values. When the distances between the first node and the first image acquisition module and the second image acquisition module are different, the resistor and inductor parameters in the first optimization unit and the second optimization unit are also configured differently accordingly to eliminate the different degrees of interference and noise caused by the different wiring stub parameters, ensuring low image signal interference and good consistency.

[0022] Specifically, the first distance is 10 mm, the second distance is 35 mm, the first resistor and the second resistor have the same resistance value of 10 ohms, the first inductor has an inductance value of 27 nanohenries, and the second inductor has an inductance value of 15 nanohenries.

[0023] In one embodiment of this application, the image acquisition switching control module further includes a third image acquisition module, a second node, and a third optimization unit. The third image acquisition module is electrically connected to the control module via the control bus and is used to acquire a third image to obtain a third image signal. The control module controls the first image acquisition module, the second image acquisition module, and the third image acquisition module to not be in a working state simultaneously. The second optimization unit is electrically connected between the first node and the second node; the second image acquisition module is electrically connected to the second node via the third optimization unit; the third image acquisition module is electrically connected to the second node via the third optimization unit. The second and third optimization units are used to eliminate backlashes and noise in the second image signal to ensure a smooth curve for the second image signal. As the number of image acquisition modules increases, the corresponding number of nodes and optimization units also increases accordingly, effectively ensuring that images acquired by different image acquisition modules and their corresponding image signals can share the same signal interface and be accurately and with high quality transmitted to the control module.

[0024] In one embodiment of this application, the third optimization unit includes a first sub-optimization unit and a second sub-optimization unit. The second image acquisition module is electrically connected to the second node through the first sub-optimization unit, and the third image acquisition module is electrically connected to the second node through the second sub-optimization unit. The second optimization unit and the first sub-optimization unit are used to eliminate backtracking and noise in the second image signal. The second optimization unit and the second sub-optimization unit are used to eliminate backtracking and noise in the third image signal.

[0025] For the second image acquisition module and the third image acquisition module, a first sub-optimization unit and a second sub-optimization unit are respectively set to perform optimization operations such as eliminating backholes and filtering noise on the image signals acquired by the two modules, so as to further ensure that the image signals provided to the control module are complete, accurate and of better quality.

[0026] In one embodiment of this application, the second optimization unit includes a second resistor electrically connected between the first node and the second node; the first sub-optimization unit includes a third resistor and a second inductor, the third resistor and the second inductor being connected in series between the second node and the second image acquisition module; the second sub-optimization unit includes a fourth resistor and a third inductor, the fourth resistor and the third inductor being connected in series between the second node and the third image acquisition module. The resistor and inductor parameters in the first and second sub-optimization units respectively perform trench cancellation and noise filtering, and cooperate to ensure the integrity and accuracy of the image signal.

[0027] In one embodiment of this application, the clock signal interface is further used to receive a clock control signal of the third image signal, and the data signal interface is further used to receive image data in the third image signal. The second optimization unit includes four second resistors, which are connected in series between the first node and the second node, corresponding to the pair of clock differential pairs and the pair of data differential pairs. The first sub-optimization unit includes four third resistors and four second inductors, which are connected in series between the second node and the second image acquisition module, corresponding to the pair of clock differential pairs and the pair of data differential pairs. The second sub-optimization unit includes four fourth resistors and four third inductors, which are connected in series between the second node and the third image acquisition module, corresponding to the pair of clock differential pairs and the pair of data differential pairs.

[0028] For the second and third image acquisition modules, each of the shared differential pair interfaces in the first signal interface is individually equipped with resistors and inductors to optimize the image signal, thereby ensuring that the image signals transmitted and received by each interface are as interference-free as possible, and remain complete, accurate and of better quality.

[0029] In one embodiment of this application, the first node is spaced a first distance from the first image capturing module, the second node is spaced a second distance from the second image capturing module, and the second node is spaced a third distance from the third image capturing module. The first distance is different from the second and third distances. The first resistor and the second resistor have the same resistance value, the second resistor and the third resistor have different resistance values, the third resistor and the fourth resistor have the same resistance value, and the first inductor and the second and third inductors have different inductance values. The second distance and the third distance are the same, and the second inductor and the third inductor have the same inductance value.

[0030] The second node is at the same distance from the second and third image acquisition modules, and its component dimensions and parameters are the same. This ensures that the influence of the wiring stubs between the second node and the second and third image acquisition modules is the same, thereby ensuring better consistency of the image signals transmitted from the first and second nodes to the control module under conditions of low interference.

[0031] Specifically, the first distance is 10 mm, and the sum of the second and third distances is 35 mm. The first and second resistors have the same resistance value of 22 ohms, and the third and fourth resistors have a resistance value of 10 ohms; the first inductor has an inductance value of 18 nanohenries, and the second inductor has an inductance value of 9 nanohenries.

[0032] In one embodiment of this application, the image capture and display terminal further includes a display module, and the control module further includes a second signal interface, a second control bus, and a third node; the third node is electrically connected to the second signal interface. The display module includes a first display unit and a second display unit, which are used to perform image display. The first display unit and the second display unit are electrically connected to the second signal interface via the second node. The control module is electrically connected to the first display unit and the second display unit via the second control bus, and the control module transmits image signals to the first display unit and the second display unit in a time-division multiplexing manner via the second signal interface.

[0033] Therefore, the control module in the image capture and display terminal can share the signal interface for outputting image signals when displaying images, effectively improving the utilization rate of the signal interface on the control module.

[0034] In one embodiment of this application, the control module is a system-on-a-chip, the first signal interface is the camera serial port in the mobile industry processor interface, and the second signal interface is the display screen serial port in the mobile industry processor interface.

[0035] In one embodiment of this application, a fourth optimization unit and a fifth optimization unit are further included, wherein: the fourth optimization unit is electrically connected to the second signal interface and the first display unit through the third node, and the fifth optimization unit is electrically connected to the second signal interface and the second display unit through the third node. The fourth optimization unit is electrically connected between the third node and the first display unit, and is used to eliminate backtracking and noise in the received image signal. The fifth optimization unit is electrically connected between the third node and the second display unit, and is used to eliminate backtracking and noise in the received image signal.

[0036] In one embodiment of this application, the image capture and display terminal further includes a touch module. The touch module is electrically connected to the control module and is used to receive touch operations and identify the location information of the touch operations. The location information indicates the image capture or display unit that needs to be in a working state. The control module outputs control signals to the first image capture module and the second image capture module according to the location information, or outputs the control signals to the first display unit and the second display unit to control the working state of the first image capture module and the second image capture module, and the first display unit and the second display unit.

[0037] In one embodiment of this application, the image capture and display terminal further includes an audio pickup module. The audio pickup module is electrically connected to the control module and is used to receive touch operations and identify audio information in the audio signal. The audio information represents the image capture or display unit that needs to be in a working state. The control module outputs control signals to the first image capture module and the second image capture module according to the audio information, or outputs the control signals to the first display unit and the second display unit to control the working state of the first image capture module and the second image capture module, and the first display unit and the second display unit.

[0038] Users can select image capture modules and display units according to their actual needs through the touch module or audio pickup module, which effectively improves the flexibility of users to control multiple image capture modules and multiple display units.

[0039] In one embodiment of this application, an image capture and display terminal is provided, including a control module, a first optimization unit, a second optimization unit, a first image capture module, a second image capture module, and a first node. The control module includes a first control bus and a first signal interface. The control module is electrically connected to the first image capture module and the second image capture module through the first control bus. The control module outputs control signals to control the first image capture module and the second image capture module to be in a working state at the same time.

[0040] The first signal interface includes a clock signal interface and a data signal interface. The clock signal interface is used to receive a clock control signal from a first image signal or a second image signal. The data signal interface is used to receive image data from a first image signal or a second image signal. The clock signal interface includes a pair of clock differential pairs that are electrically connected to the first node. The data signal interface includes a pair of data differential pairs that are electrically connected to the first node.

[0041] The first signal interface has a pair of clock differential pairs and a pair of data differential pairs that are electrically connected to the four sub-nodes of the first node.

[0042] The first optimization unit is electrically connected to the first node and the first image acquisition module, and the first optimization unit includes four first resistors and four first inductors. The second optimization unit is electrically connected to the first node and the second image acquisition module, and the second optimization unit includes four second resistors and four second inductors. The four first resistors correspond to the clock differential pair interface and the data differential pair interface, respectively, and are electrically connected between the four child nodes and the first image acquisition module. The four second resistors correspond to the clock differential pair interface and the data differential pair interface, respectively, and are electrically connected between the four child nodes and the second image acquisition module.

[0043] The first image acquisition module is used to acquire a first image signal, and the second image acquisition module is used to acquire a second image signal. When the first image acquisition module is in working state, the acquired first image signal is transmitted to the first signal interface via the first optimization unit. The first resistor is used to eliminate backlashes in the first image signal to smooth the curve of the first image signal, and the first inductor is used to filter out noise in the first image signal. When the second image acquisition module is in working state, the acquired second image signal is transmitted to the first signal interface via the second optimization unit. The second resistor is used to eliminate backlashes in the second image signal to smooth the curve of the second image signal, and the second inductor is used to filter out noise in the second image signal.

[0044] The control module can directly control the working status of the first image acquisition module or the second image acquisition module through the control bus. By sharing the first node and the first signal interface, it effectively saves the signal interface used to transmit image signals provided by different image acquisition modules. There is no need to set up a separate analog switching switch for the working status of the first image acquisition module and the second image acquisition module. This effectively reduces the number of components and traces on the circuit board, simplifies the circuit board structure, and provides more layout space for setting up other functional components. Attached Figure Description

[0045] Figures 1a-1b This is a schematic diagram of the planar structure of the image capturing and display terminal on both sides in one embodiment of this application;

[0046] Figure 2 For example Figures 1a-1b A schematic diagram showing the working status control method of multiple image acquisition modules;

[0047] Figure 3 This is a schematic diagram of the functional modules of the image capture switching control module in the first embodiment of this application;

[0048] Figure 4 For example Figure 3 The diagram shows the specific circuit structure of the image capture switching control module.

[0049] Figure 5 For example Figure 4 The diagram shows the connection structure between the first optimization unit and the second optimization unit.

[0050] Figure 6 For example Figure 4 The diagram shows the planar layout structure of the first optimization unit and the second optimization unit.

[0051] Figure 7 As in the second embodiment of this application Figure 4 The diagram shows the planar layout structure of the first optimization unit and the second optimization unit.

[0052] Figure 8 This is a schematic diagram of the functional modules of the image capture switching control module in the third embodiment of this application;

[0053] Figure 9 for Figure 8 The diagram shows the planar layout structure of the first optimization unit and the second optimization unit.

[0054] Figure 10 This is a schematic diagram of the functional modules of the image capture switching control module in the fourth embodiment of this application;

[0055] Figure 11 for Figure 10The diagram shows the planar layout structure of the first optimization unit and the second optimization unit.

[0056] Figure 12 As in the fifth embodiment of this application Figure 3 The diagram shows the specific circuit structure of the image capture switching control module.

[0057] Figure 13 This is a functional structure diagram of the image capturing and display terminal in the sixth embodiment of this application;

[0058] Figures 14a-14b for Figure 13 The image shown is a schematic diagram of the planar structure of the display terminal on both sides. Detailed Implementation

[0059] The present invention will now be described with reference to specific embodiments.

[0060] Please see Figures 1a-1b ,in, Figures 1a-1b This is a schematic diagram of the planar structure of the image capturing and display terminal 1 on both sides in one embodiment of this application. Figures 1a-1b As shown, the image capture and display terminal 1 is used to perform image capture and image display. The image capture and display terminal 1 includes a touch screen TP and a first image capture module 13 disposed on one side, and a housing CA, a second image capture module 14 and a third image capture module 15 disposed on the opposite side.

[0061] In this embodiment, when a user uses the image capture and display terminal 1, the side with the touch screen TP and the first image capture module 13 faces the user and can be referred to as the front of the image capture and display terminal 1. The side with the housing CA, the second image capture module 14, and the third image capture module 15 faces away from the user and can be referred to as the back of the image capture and display terminal 1. Additionally, on the side with the touch screen TP, the image capture and display terminal 1 also includes an audio pickup module VP and other functional modules (not shown in the figure). These other functional modules may include an infrared sensor, an audio player, etc.

[0062] The touch display screen 1a is used for touch detection and image display. The touch display screen 1a includes a display module (not shown) and a touch module (not shown). The display module is used for image display, and the touch module is used for receiving touch operations and identifying the location of the touch operation. In this embodiment, the display module can be a Liquid Crystal Display (LCD) or an Organic Light-Emitting Diode (OLED), and the touch module can be a capacitive touch module, an optical touch module, etc.

[0063] The first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 are used to capture images and save the captured image data, and output the image data as an image signal. The first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 respectively capture images from different positions on the image capturing display terminal 1. Furthermore, the second image capturing module 14 and the third image capturing module 15, located on the same side of the image capturing display terminal 1, can also have different camera functions; for example, the second image capturing module 14 is used to capture color images, while the third image capturing module 15 is used to capture black and white images.

[0064] In this embodiment, the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 are all electrically connected to a signal interface of the control module 10 through the first node N1. That is, the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 share a signal interface corresponding to the first node N1. The control module 10 outputs control signals to the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 to control the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 to be in a time-division multiplexing working state. That is, at any given time, only one of them transmits image data to the control module 10 through the first node N1.

[0065] Alternatively, in other embodiments of this application (not shown), the first image capturing module 13 and the second image capturing module 14 are electrically connected to a signal interface of the control module 10 through a first node N1, while the third image capturing module 15 is directly electrically connected to another signal interface of the control module 10, and does not need to share the same signal interface with the first image capturing module 13 and the second image capturing module 14 through the first node N1.

[0066] Specifically, the first image acquisition module 13 and the second image acquisition module 14 share a signal interface corresponding to the first node N1. The control module 10 outputs control signals to the first image acquisition module 13 and the second image acquisition module 14 to control the first image acquisition module 13 and the second image acquisition module 14 to be in a time-sharing working state, that is, at the same time, only one of them transmits image data to the control module 10 through the first node N1.

[0067] The third image acquisition module 15 is electrically connected directly to another signal interface of the control module 10, independent of the first node N1. Therefore, the third image acquisition module 15 does not need to share a single signal interface with the first image acquisition module 13 and the second image acquisition module 14 to send image signals to the control module 10. Consequently, the operating state of the third image acquisition module 15 under the control of the control signals output by the control module 10 is not limited by the number of signal interfaces. It can operate simultaneously with one of the first image acquisition modules 13 and the second image acquisition module 14 under the control of the control module 10, or it can operate without either of the first image acquisition module 13 or the second image acquisition module 14 simultaneously under the control of the control module 10.

[0068] The control signal output by the control module 10 is a digital logic signal output from the signal output interface of the control module 10. Alternatively, the control signal may also be an analog voltage signal output by the control module 10 through the signal interface.

[0069] Please see Figure 2 , Figure 2 Provided Figures 1a-1b The diagram shows the control method for the working status of multiple image capture and display modules, as shown below. Figure 2 As shown, the operating modes of the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 are mainly controlled by the user's selection of the image acquisition mode based on their needs, which is received by the user through the image acquisition display terminal 1.

[0070] Specifically, the touch screen 1a displays an information prompt box, which includes options for multiple image capture modes that the user can select via touch operation: Selfie mode, normal shooting mode, black and white shooting mode, and panorama shooting mode. For example, the user can select one of the aforementioned four shooting modes according to their actual image capture needs.

[0071] Specifically, when the user selects selfie mode, the control module 10 outputs a control signal to activate the first image acquisition module 13, while simultaneously deactivating the second and third image acquisition modules 14 and 15. During this period, only the first image acquisition module 13 is active. When the user selects normal shooting mode, the control module 10 outputs a control signal to activate the second image acquisition module 14, while simultaneously deactivating the first and third image acquisition modules 13 and 15. During this period, only the second image acquisition module 14 is active. When the user selects the black and white shooting mode, the control module 10 outputs a control signal to control the third image acquisition module 15 to be in working state, while the first image acquisition module 13 and the second image acquisition module 14 are in non-working state. During this period, only the third image acquisition module 15 is in working state. When the user selects the panoramic shooting mode, the control module 10 outputs a control signal to control both the second image acquisition module 14 and the third image acquisition module 15 to be in working state, while the first image acquisition module 13 is in non-working state. Thus, the images captured simultaneously by the second image acquisition module 14 and the third image acquisition module 15 constitute a panoramic image.

[0072] It should be noted that, regardless of whether it's selfie mode, normal shooting mode, black and white shooting mode, or panoramic shooting mode, only one image capture module needs to be active at any given time when multiple image capture modules share a single signal interface. However, when an image capture module is connected to a separate signal interface of the control module 10 and does not share a signal interface with other image capture modules for image signal transmission, that image capture module is not subject to the time-sharing restriction of being active; it can be active or inactive depending on the shooting mode selected by the user. Furthermore, the four modes displayed in the aforementioned image capture display terminal 1 are only examples of some image capture modes. The image capture display terminal 1 may also include night scene shooting mode, professional shooting mode, time-lapse photography mode, watermark shooting mode, close-up shooting mode, etc., and is not limited to these.

[0073] The control module 10, based on the position information of the touch operation received on the touch display screen 1a, obtains the image module selected by the user to perform image acquisition, and outputs a corresponding control signal to control the selected image acquisition module to perform image acquisition, while the other image acquisition modules are in a non-working state. The image acquisition module performing image acquisition transmits the acquired image data to the control module 10 through a common signal interface. The position information of the touch operation indicates the image acquisition module selected to perform image acquisition, such as selecting the first image acquisition module 13, the second image acquisition module 14, or the third image acquisition module 15 to perform image acquisition.

[0074] Of course, the control of the working status of multiple image acquisition modules can also be achieved through input commands provided by external users via voice operation or by receiving commands from other functional modules within the terminal. The control signals can be digital or analog signals.

[0075] In this embodiment, the control module 10 is a system on chip (SoC), and the signal interface used by the aforementioned control module 10 for receiving image data is the camera serial interface (CSI) in the Mobile Industry Processor Interface (MIPI).

[0076] In this embodiment, the first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 are cameras with the same or different resolutions. For example, the first image capturing module 13 is a 2-megapixel (2M resolution) camera, the second image capturing module 14 is an 8-megapixel (8M resolution) camera, and the third image capturing module 15 is an 8-megapixel (8M resolution) camera. In other embodiments of this application, the resolution and other camera parameters of the first to third image capturing modules 13-15 can be set according to actual needs. For example, the first to third image capturing modules 13-15 can also be selected with resolutions of 16 megapixels, 40 megapixels, and 32 megapixels, and are not limited to this. At the same time, the number of image capturing modules included in the image capturing display terminal 1 can also be adjusted according to actual needs. For example, only two image capturing modules, the first image capturing module 13 and the second image capturing module 14, can be set, or other image capturing modules with different camera parameters such as resolution and focal length can be added.

[0077] Please see Figure 3 ,in, Figure 3 As described in the first embodiment of this application Figures 1a-1b The diagram shows a functional module of the image capture switching control module 100 within the image capture display terminal 1, which performs image capture switching. The image capture switching control module 100 is located within the image capture display terminal 1.

[0078] In this embodiment, only the first image capturing module 13 and the second image capturing module 14 are electrically connected to a signal interface of the control module 10 through the first node N1. That is, the first image capturing module 13 and the second image capturing module 14 share a signal interface corresponding to the first node N1. The third image capturing module 15 is directly electrically connected to the control module 10, without needing to be electrically connected to the control module 10 through the first node N1, and without needing to share a signal interface with the first image capturing module 13 and the second image capturing module 14 to send image signals to the control module 10.

[0079] like Figure 3 As shown, the image capture switching control module 100 includes a control module 10, a first optimization unit 11, a second optimization unit 12, a first image capture module 13, and a second image capture module 14. The control module 10 performs image capture switching control for the first image capture module 13 and the second image capture module 14. The control module 10 is electrically connected to the first image capture module 13 and the second image capture module 14 via a first control bus CB1 to output control signals to control the first image capture module 13 and the second image capture module 14 to be in a time-sharing working state. Simultaneously, the first image capture module 13 is also electrically connected to the first signal interface 101 of the control module 10 via the first optimization unit 11, and the second image capture module 14 is also electrically connected to the first signal interface 101 of the control module 10 via the second optimization unit 12. Since the first image capture module 13 and the second image capture module 14 are in a time-sharing working state, they can share the first signal interface 101.

[0080] In this embodiment, the first control bus CB1 is an interface electrically connected to the control module 10 for outputting control signals and to the first image acquisition module 13 and the second image acquisition module 14. The first signal interface 101 is the CSI in the MIPI used by the control module 10 to receive image data.

[0081] Specifically, the first image capturing module 13 is used to capture a first image and output a first image signal corresponding to the first image. That is, when the first image capturing module 13 is in working state, it captures the first image and converts it into a first image signal. The first image signal includes image data corresponding to the first image and clock signals, synchronization signals, etc., for auxiliary image data transmission and display. The second image capturing module 14 is used to capture a second image and output a second image signal corresponding to the second image. When the second image capturing module 14 is in working state, it captures the second image and converts it into a second image signal. The second image signal includes image data corresponding to the second image and clock signals, synchronization signals, etc., for auxiliary image data transmission and display.

[0082] In this embodiment, the first image capturing module 13 and the second image capturing module 14 are cameras with different resolutions. Specifically, the first image capturing module 13 is a 2-megapixel (2M resolution) camera, and the second image capturing module 14 is an 8-megapixel (8M resolution) camera. In other embodiments of this application, the first image capturing module 13 and the second image capturing module 14 may also be cameras with the same resolution.

[0083] The control module 10 is electrically connected to the first image acquisition module 13 and the second image acquisition module 14 respectively via the first control bus CB1. The control module 10 controls the first image acquisition module 13 and the second image acquisition module 14 to work in a time-sharing manner through the control signals output by the first control bus CB1.

[0084] In this embodiment, the control module 10 also includes other interfaces directly electrically connected to the first control bus CB1. The first control bus CB1 is a bus cable used to transmit electrical signals. The electrical signals include control signals for controlling the operating states of the first image acquisition module 13 and the second image acquisition module 14, as well as other signals. The electrical connection is a connection via conductive lines capable of transmitting electrical signals. The conductive lines include PCB traces, flexible flat cables, conductive connectors, or other conductive physical cables.

[0085] Controlling the operating states of the first image acquisition module 13 and the second image acquisition module 14 can be achieved as follows: The control module 10 receives input commands from users outside the image acquisition display terminal 1, such as performing touch operations on the touch screen 1a or sound operations picked up by the audio pickup module VP, or receives commands from other functional modules inside the terminal. The control module 10 then outputs corresponding control signals to the first image acquisition module 13 and the second image acquisition module 14 via the first control bus CB1. These control signals control the operating states of the first image acquisition module 13 and the second image acquisition module 14. The control signals can be digital or analog signals, and the other functional modules can be power modules, image processing modules, etc., but are not limited to these.

[0086] The first optimization unit 11 is electrically connected between the first signal interface 101 and the first image acquisition module 13 via the first node N1. The second optimization unit 12 is electrically connected between the first signal interface 101 and the second image acquisition module 14 via the first node N1. That is, the first node N1 serves as a branch point, and the first optimization unit 11 and the second optimization unit 12 are connected to the first signal interface 101 of the control module 10 through the first node N1.

[0087] After being optimized by the first optimization unit 11, the first image signal is transmitted to the first signal interface 101 via the first node N1. At the same time, the second image signal is also transmitted to the first signal interface 101 via the first node N1 after being optimized by the second optimization unit 12. The control module 10 then provides the optimized first image signal or the second image signal to other modules, such as to the display module (not shown) for display.

[0088] The optimization processing of the first image signal by the first optimization unit 11 and the optimization processing of the second image signal by the second optimization unit 12 specifically include:

[0089] When the first image acquisition module 13 is in operation, it operates in a high-speed (HS) low-impedance mode and transmits the first image signal corresponding to the acquired first image to the first signal interface 101 via the first optimization unit 11. The first optimization unit 11 optimizes the first image signal to ensure a smooth curve.

[0090] Meanwhile, when the first image acquisition module 13 is in working state, that is, when the first image acquisition module 13 is in high-speed low-impedance mode, the second image acquisition module 14 is in non-working state and in low-power (LP) high-impedance mode, thereby stopping the acquisition of the second image.

[0091] In this embodiment, it should be noted that: when the first image acquisition module 13 and the second image acquisition module 14 are in high-speed (HS) low-impedance mode, that is, in working state, the internal functional units of the first image acquisition module 13 and the second image acquisition module 14 are in low-impedance state, so that they can perform image acquisition and convert image data into image signal output; when the first image acquisition module 13 and the second image acquisition module 14 are in low-power (LP) high-impedance mode, that is, in non-working state, the internal functional units of the first image acquisition module 13 and the second image acquisition module 14 are in high-impedance state, and image acquisition is stopped.

[0092] More specifically, since the second image acquisition module 14 is in a non-low-power (LP) high-impedance mode, the conductive lines and components between the second image acquisition module 14 and the first node N1 have a certain impedance. For the first image acquisition module 13, these are equivalent to trace stubs. The presence of these trace stubs easily causes grooves to form on the rising and falling edges of the first image signal curve, resulting in an uneven curve. Because the first image signal has grooves and an uneven curve, it is very easy for the control module 10 to mis-trigger, causing data transmission errors and making the first image acquisition module 13 stutter, which in turn leads to errors in the image data corresponding to the first image and poor image quality.

[0093] Similarly, since the first image acquisition module 13 is in a non-low power (LP) high impedance mode, the conductive lines and components between the first image acquisition module 13 and the first node N1 have a certain impedance. Therefore, relative to the second image acquisition module 14, these are equivalent to trace stubs. The presence of these trace stubs causes grooves to appear on the rising and falling edges of the second image signal curve. These grooves make the second image signal curve unsmooth. The unsmooth second image signal curve caused by these grooves easily leads to false triggering of the control module 10, data transmission errors, and subsequent lag in the second image acquisition module 14, resulting in errors in the corresponding image data and poor image quality. The grooves on the rising and falling edges of the image signal occur when the image signal curve rises smoothly and continuously during the rising and falling edges, or when there is a momentary drop at the falling edge, causing the curve to appear groove-like. Therefore, the presence of these grooves makes the image signal curve unsmooth.

[0094] Therefore, the first optimization unit 11 is electrically connected between the first node N1 and the first image acquisition module 13. By eliminating the backlashes on the rising or falling edges of the second image signal, that is, accurately eliminating the backlashes caused by trace remnants between the first node N1 and the second image acquisition module 14, the smoothness of the first image signal curve is ensured. The first optimization unit 11 eliminates the backlashes on the rising or falling edges of the first image signal by pulling back the momentary drop in the curve of the image signal at the rising or falling edge to the normal rising or falling position, that is, filling in the backlashes on the rising and falling edges of the first image signal curve, thereby ensuring the smoothness of the first image signal curve.

[0095] When the second image acquisition module 14 is in operation, i.e., in high-speed (HS) low-impedance mode, the second image signal corresponding to the acquired second image is transmitted to the first signal interface 101 via the second optimization unit 12. The second optimization unit 12 optimizes the second image signal to ensure a smooth curve. The second optimization unit 12 eliminates the backlash at the rising or falling edges of the second image signal by pulling back the momentary drop in the curve at the rising or falling edge to its normal rising or falling position, thus filling in the gaps at the rising and falling edges of the second image signal curve and ensuring a smooth curve. Of course, other methods can also be used to eliminate the backlash in the image signal, and this is not a limitation.

[0096] Meanwhile, when the second image acquisition module 14 is in working state, that is, when the second image acquisition module 14 is in high-speed low-impedance mode, the first image acquisition module 13 is in non-working state and in low-power (LP) high-impedance mode, thereby stopping the acquisition of the second image.

[0097] The second optimization unit 12 ensures the smoothness of the second image signal curve by eliminating back grooves on the rising or falling edges of the second image signal, that is, by accurately eliminating back grooves caused by the trace remnants of the first node N1 and the first image acquisition module 13.

[0098] To further reduce the impact of residual wiring, when the first image acquisition module 13 is in a low-power, high-impedance mode (i.e., when it is not in operation), its impedance is greater than 100 ohms. Similarly, when the second image acquisition module 14 is in a low-power, high-impedance mode (i.e., when it is not in operation), its impedance is also greater than 100 ohms. Therefore, when the first image acquisition module 13 is not in operation, its impedance effectively prevents interference signals from being transmitted to the second image acquisition module 14 when it is in operation. Likewise, when the second image acquisition module 14 is not in operation, its impedance effectively prevents interference signals from being transmitted to the first image acquisition module 13 when it is in operation.

[0099] In this embodiment, the first control bus CB1, the first optimization unit 11, the second optimization unit 12, and the connection traces between each functional unit are all disposed on a printed circuit board (PCB).

[0100] Control module 10 via Figure 3 The first control bus CB1 shown can directly control the working state of the first image acquisition module 13 and the second image acquisition module 14. By sharing the first signal interface 101, it effectively saves the signal interface used to receive image signals provided by different image acquisition modules. There is no need to set up a separate analog switching circuit to control the working state of the first image acquisition module 13 and the second image acquisition module 14. This effectively reduces the number of components and traces on the circuit board, simplifies the circuit board structure, and provides more layout space for setting up other functional components.

[0101] Please see Figure 4 , Figure 4 for Figure 3 The diagram shows the specific circuit structure of the image capture switching control module. Figure 4As shown, the first signal interface 101 in the control module 10 includes a clock signal interface CLK and a data signal interface DATA.

[0102] The clock signal interface CLK is used to receive the clock control signal from the first image signal or the second image signal, and the data signal interface DATA is used to receive the image data from the first image signal or the second image signal. The control module 10 performs data processing based on the coordination of the clock control signal and the image data. This data processing involves the control module 10 performing shifting, compression, and transmission operations on the image data based on the clock signal and other control signals.

[0103] In this embodiment, the clock signal interface CLK includes a pair of clock differential pairs, specifically including two sub-clock signal terminals: a first sub-clock terminal CLK-DP and a second sub-clock terminal CLK-DN.

[0104] The data signal interface DATA includes at least one pair of data differential pairs, specifically including two sub-data terminals: a first sub-data terminal DA0-DP and a second sub-data terminal DA0-DN.

[0105] The number of data differential pairs in the data signal interface DATA corresponds to the resolution of the image acquisition module. Specifically, for example, when the first image acquisition module 13 has 2 million pixels, the number of data differential pairs in the data signal interface DATA is one pair, that is, the first sub-data terminal DA0-DP and the second sub-data terminal DA0-DN need to transmit data. When the second image acquisition module 14 has 8 million pixels, the number of data differential pairs in the data signal interface DATA is four pairs, that is, the first sub-data terminal DA0-DP and the second sub-data terminal DA0-DN, the third sub-data terminal DA1-DP and the fourth sub-data terminal DA1-DN, the fifth sub-data terminal DA2-DP and the sixth sub-data terminal DA2-DN, and the seventh sub-data terminal DA3-DP and the eighth sub-data terminal DA3-DN need to perform image data transmission.

[0106] In this embodiment, the first image acquisition module 13 and the second image acquisition module 14 are in a time-sharing working state and share the first signal interface 101. That is, the first image acquisition module 13 and the second image acquisition module 14 share a pair of clock differential interfaces and a pair of data differential interfaces in the clock signal interface CLK and the data signal interface DATA through the first node N1, specifically including:

[0107] The first node N1 includes four independent and mutually insulated sub-nodes N1-1 to N1-4. The four sub-nodes N1-1 to N1-4 are respectively electrically connected to the first sub-clock terminal CLK-DP, the second sub-clock terminal CKL-DN, the first sub-data terminal DA0-DP, and the second sub-data terminal DA0-DN.

[0108] The first optimization unit 11 includes four first resistors R1 and four first inductors L1, wherein one first resistor R1 and one first inductor L1 are connected in series in a one-to-one correspondence with the four sub-nodes N1-1 to N1-4. The second optimization unit 12 includes four second resistors R2 and four second inductors L2, wherein one second resistor R2 and one second inductor L2 are connected in series in a one-to-one correspondence with the four sub-nodes N1-1 to N1-4.

[0109] Therefore, corresponding to the clock differential pair interface CLK and the data signal interface DATA, the four first resistors R1 and the four first inductors L1 are electrically connected in a one-to-one correspondence between the four sub-nodes N1-1 to N1-4 in the first node N1 and the first image capturing module 13, and the four second resistors R2 and the four second inductors L2 are electrically connected in a one-to-one correspondence between the four sub-nodes N1-1 to N1-4 in the first node N1 and the second image capturing module 14.

[0110] The first resistor R1 and the second resistor R2 are used to eliminate backlashes at the rising or falling edges of the first and second image signals, respectively, ensuring smooth curves for the first and second image signals. The first inductor L1 and the second inductor L2 are used to further filter noise from the first and second image signals. Therefore, through the cooperation of the first resistor R1 and the first inductor L1, and the cooperation of the second resistor R2 and the second inductor L2, the quality of the first and second image signals can be effectively improved, ensuring high-speed, accurate, and complete transmission of image signals during operation of the first image acquisition module 13.

[0111] In this embodiment, the distance between the first node N1 and the control module 10 is greater than the distance between the first node N1 and the first image capturing module 13, or the distance between the first node N1 and the control module 10 is greater than the distance between the first node N1 and the second image capturing module 14. Of course, the distance between the first node N1 and the control module 10 can also be greater than the distance between the first node N1 and both image capturing modules 13 and 14. The distance between the first node N1 and the control module 10, the first image capturing module 13, and the second image capturing module 14 is the length of the conductive line for signal transmission.

[0112] Therefore, compared to the control module 10, the first node N1 is positioned closer to the first image capturing module 13 and the second image capturing module 14. That is, the first node N1 is positioned as close as possible to the first image capturing module 13 and the second image capturing module 14 on the PCB board, thereby reducing the trace distance between the first node N1 and the image capturing modules and minimizing noise interference. The first inductor L1 is positioned near the board-to-board (BTB) connection of the first image capturing module 13, and the second inductor L2 is positioned near the board-to-board (BTB) connection of the second image capturing module 14. In this embodiment, the four first resistors R1 have the same resistance value, the four second resistors R2 have the same resistance value, and the four first resistors R1 and the four second resistors R2 have the same package size. When arranged on the PCB board, the four first resistors R1 and the four second resistors R2 are positioned close to each other and all near the first node N1, the four first inductors L1 are positioned near the first image capturing module 13, and the four second inductors L2 are positioned near the second image capturing module 14.

[0113] In other embodiments of this application, the distance between the first node N1 and the control module may also be less than the distance between the first node N1 and the first image capturing module 13 and the second image capturing module 14. Correspondingly, the signal interference due to the long trace distance can be reduced by adjusting the resistance values ​​of the first resistor R1 and the second resistor R2.

[0114] Specifically, please refer to Figure 5 , its is like Figure 4 The diagram shows the connection structure between the first optimization unit 11 and the second optimization unit 12.

[0115] like Figure 5 As shown, any first resistor R1 includes a first connection terminal R1-a and a second connection terminal R1-b. Correspondingly, any second resistor R2 includes a first connection terminal (not shown) and a second connection terminal (not shown).

[0116] During the specific connection process between the first optimization unit 11 and the second optimization unit 12, the second connection terminal R1-b of the first resistor R1 is connected to the first node N1, and simultaneously, the second connection terminal of the second resistor R2 is connected to the first node N1. The first connection terminal R1-a of the first resistor R1 is electrically connected to one end of the first inductor L1, and the other end of the first inductor L1 is electrically connected to the first image capturing module 13; the second connection terminal of the second resistor R2 is electrically connected to one end of the second inductor L2, and the other end of the second inductor L2 is electrically connected to the second image capturing module 14.

[0117] In this embodiment, when the first resistor R1, the second resistor R2, the first inductor L1 and the second inductor L2 are disposed on the PCB board, they are disposed on the surface of the PCB board by surface mount technology (SMT) or other packaging technology.

[0118] In this embodiment, the four first resistors R1 and the four second resistors R2 are all disposed adjacent to the first image capturing module 13 and the second image capturing module 14, and the first image capturing module 13 and the second image capturing module 14 are arranged side by side on a straight line parallel to the first straight line Line1. Simultaneously, the four child nodes N1-1 to N1-4 of the first node N1 are also located on a straight line parallel to the first straight line Line1. The first straight line Line1 is parallel to the control module 10. Of course, in other modified embodiments, the four child nodes N1-1 to N1-4 of the first node N1 can also be located at any position between the first straight line Line1 and the first control module 10.

[0119] Please see Figure 6 , its is like Figure 4 The diagram shows the planar layout structure of the first optimization unit 11 and the second optimization unit 12. Figure 6 As shown: In the first optimization unit 11, the first node N1 is spaced apart from the first image acquisition module 13 by a first distance S1. Since the four first resistors R1 are set near the first node N1 and the four first inductors L1 are set near the first image acquisition module 13, the four first resistors R1 are approximately spaced apart from the first image acquisition module 13 by a first distance S1.

[0120] The second optimization unit 12 has a second distance S2 between the first node N1 and the second image acquisition module 14. Since the four second resistors R2 are set close to the first node N1 and the four second inductors L2 are set close to the second image acquisition module 14, the four second resistors R2 are approximately spaced apart from the second image acquisition module 14 by the second distance S2.

[0121] In this embodiment, the first distance S1 and the second distance S2 are the same, the first resistor R1 and the second resistor R2 have the same resistance value, and correspondingly, the first inductor L1 and the second inductor L2 have the same inductance value.

[0122] When the first distance S1 and the second distance S2 are the same and both are 10 mm, the resistance values ​​of the first resistor R1 and the second resistor R2 are the same and both are 10 ohms, and the inductance values ​​of the first inductor L1 and the second inductor L2 are 27 nanohenries. In this embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2, and the inductance values ​​of the first inductor L1 and the second inductor L2 can be adjusted according to actual needs. For example, they can be adjusted based on factors such as the parameters of the first distance S1, the second distance S2, the first image acquisition module 13, and the second image acquisition module 14, and are not limited thereto.

[0123] Please see Figure 7 As shown in the second embodiment of this application Figure 4 The diagram shows the planar layout structure of the first optimization unit 11 and the second optimization unit 12. Figure 7 As shown:

[0124] For the first optimization unit 11, the first node N1 is separated from the first image acquisition module 13 by a first distance S1.

[0125] For the second optimization unit 12, the first node N1 and the second image acquisition module 14 are separated by a second distance S2.

[0126] In this embodiment, the first distance S1 and the second distance S2 are different, the first resistor R1 and the second resistor R2 have the same resistance value, but the first inductor L1 and the second inductor L2 have different inductance values.

[0127] When the first distance S1 is 10 mm and the second distance S2 is 35 mm, the resistance values ​​of the first resistor R1 and the second resistor R2 are the same, both being 22 ohms. The inductance value of the first inductor L1 is 27 nanohenries, and the inductance value of the second inductor L2 is 15 nanohenries. In this embodiment, the resistance values ​​of the first resistor R1 and the second resistor R2, as well as the inductance values ​​of the first inductor L1 and the second inductor L2, can be adjusted according to actual needs. For example, they can be adjusted based on factors such as the parameters of the first distance S1, the second distance S2, the first image acquisition module 13, and the second image acquisition module 14, and are not limited thereto.

[0128] Please refer to the following: Figure 8 ,in, Figure 8 This is a schematic diagram of the functional modules of the image capture switching control module in the third embodiment of this application. Figure 8As shown, the image acquisition switching control module 100 includes a first image acquisition module 13, a second image acquisition module 14, and a third image acquisition module 15, and performs switching control on the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15. The image acquisition switching control module 100 also includes a first node N1, a second node N2, a first optimization unit 11, a second optimization unit 12, and a third optimization unit 16. In this embodiment, the first image acquisition module 13 and the second image acquisition module 14 have the same working principle, working mode, and function as described in the first and second embodiments. The third image acquisition module 15 is used to acquire a third image and output a third image signal corresponding to the third image. When the third image acquisition module 15 is in a working state, that is, in a high-speed low-impedance mode, it acquires a third image and outputs a corresponding third image signal. When the third image acquisition module 15 is in a non-working state, that is, in a low-power high-impedance mode, it stops acquiring the third image and has an impedance greater than 100 ohms.

[0129] The resolution of the third image capturing module 15 is the same as that of the second image capturing module 14. It should be noted that the first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 share the first signal interface 101. Therefore, regardless of the camera mode of the image capturing display terminal 1, only one of the three modules (13, 14, and 15) is active at any given time.

[0130] The third image acquisition module 15 is electrically connected to the control module 10 via the first control bus CB1. The control module 10 controls the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 to not be in working state simultaneously. That is, when the first image acquisition module 13 is in working state, the second image acquisition module 14 and the third image acquisition module 15 are in non-working state; when the second image acquisition module 14 is in working state, the first image acquisition module 13 and the third image acquisition module 15 are in non-working state; and when the third image acquisition module 15 is in working state, the first image acquisition module 13 and the second image acquisition module 14 are in non-working state.

[0131] The first optimization unit 11 is electrically connected between the first node N1 and the first image acquisition module 13, and the second optimization unit 12 is electrically connected between the first node N1 and the second node N2.

[0132] The second image acquisition module 14 is electrically connected to the second node N2 through the third optimization unit 16, and the third image acquisition module 15 is electrically connected to the second node N2 through the third optimization unit 16.

[0133] When the second image acquisition module 14 or the third image acquisition module 15 is in operation, the second optimization unit 12 and the third optimization unit 16 are activated simultaneously to cooperate in eliminating the back grooves in the second and third image signals at the rising and falling edges, thereby ensuring a smooth image signal curve.

[0134] Specifically, please refer to the following: Figures 8-9 ,in, Figure 9 for Figure 8 The schematic diagram of the planar layout structure of the first optimization unit 11, the second optimization unit 12, and the third optimization unit 16 shown is as follows: Figure 9 As shown, the third optimization unit 16 includes a first sub-optimization unit 161 and a second sub-optimization unit 162. The second image acquisition module 14 is electrically connected to the second node N2 through the first sub-optimization unit 161, and the third image acquisition module 15 is electrically connected to the second node N2 through the second sub-optimization unit 162.

[0135] The second optimization unit 12 and the first sub-optimization unit 161 are activated simultaneously and cooperate with each other to eliminate the back grooves of the second image signal at the rising or falling edge to ensure the smoothness of the second image signal curve. The second optimization unit 12 and the second sub-optimization unit 162 are activated simultaneously and cooperate with each other to eliminate the back grooves of the third image signal at the rising or falling edge to ensure the smoothness of the third image signal curve.

[0136] In this embodiment, the first optimization unit 11 includes four first resistors R1 and four first inductors L1; the second optimization unit 12 includes four second resistors R2; the first sub-optimization unit 161 includes four third resistors R3 and four second inductors L2; ​​and the second sub-optimization unit 162 includes a fourth resistor R4 and a third inductor L3. The first node N1 is spaced from the first image acquisition module 13 by a first distance S1; the second node N2 is spaced from the second image acquisition module 14 by a second distance S2; and the second node N2 is spaced from the third image acquisition module 15 by a third distance S3. In this embodiment, the second node N2 also includes four independent and mutually insulated sub-nodes (not shown), each of which corresponds to one of the four sub-nodes N1-1 to N1-4 of the first node N1.

[0137] Since the four second resistors R2 and the four third resistors R3 are located adjacent to the second node N2, and the four second inductors L2 are located adjacent to the second image capturing module 14, and the four third inductors L3 are located adjacent to the third image capturing module 15, the four second resistors R2 and the four third resistors R3 are separated from the second image capturing module 14 by a second distance S2, and the four second resistors R2 and the four fourth resistors R4 are separated from the third image capturing module 15 by a third distance S3.

[0138] In this embodiment, the first distance S1 is different from the second distance S2, and the second distance S2 is the same as the third distance S3.

[0139] The first resistor R1 and the second resistor R2 have the same resistance value. The second resistor R2 and the third resistor R3 have different resistance values. The third resistor R3 and the fourth resistor R4 have the same resistance value. The first inductor L1 and the second inductor L2 have different inductance values. The second inductor L2 and the third inductor L3 have the same inductance value.

[0140] When the first distance S1 is 10 mm and the second distance S2 is 35 mm, the resistance values ​​of the first resistor R1 and the second resistor R2 are the same and are both 22 ohms, the resistance values ​​of the third resistor R3 and the fourth resistor R4 are both 10 ohms, the inductance value of the first inductor L1 is 18 nanohenries, and the inductance values ​​of the second inductor L2 and the third inductor L3 are 9 nanohenries.

[0141] The resistance values ​​of the third resistor R3 and the fourth resistor R4 can be adjusted according to the actual situation. For example, the resistance values ​​of the third resistor R3 and the fourth resistor R4 can be adjusted according to factors such as the first distance S1 and the second distance S2. The adjustment range of the resistance values ​​of the third resistor R3 and the fourth resistor R4 is 0 ohms to x ohms, where x is a value greater than 0.

[0142] Please refer to the following: Figure 10 ,in, Figure 10 This is a schematic diagram of the functional modules of the image acquisition switching control module in the fourth embodiment of this application. Figure 10 As shown, the circuit structure of the image capture switching control module 100 is basically the same as that of the image capture switching control module 100 in the third embodiment. The only difference is that the image capture switching control module 100 also includes a third image capture module 15 and a third optimization unit 16.

[0143] Specifically, the image acquisition switching control module 100 includes a first image acquisition module 13, a second image acquisition module 14, and a third image acquisition module 15, and performs switching control on the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15. It also includes a first node N1, a first optimization unit 11, a second optimization unit 12, and a third optimization unit 16.

[0144] In this embodiment, the first image capturing module 13 and the second image capturing module 14 have the same functions as those described in the first and second embodiments. When the third image capturing module 15 is in a working state, that is, in a high-speed low-impedance mode, the third image capturing module 15 is used to capture a third image and output the corresponding third image signal. When the third image capturing module 15 is in a non-working state and in a low-power high-impedance mode, it stops capturing the third image and has an impedance greater than 100 ohms. The resolution of the third image capturing module 15 is the same as the resolution of the second image capturing module 14.

[0145] It should be noted that the first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 share the first signal interface 101. Therefore, regardless of the camera mode of the image capturing display terminal 1, at any given time, only one of the first image capturing module 13, the second image capturing module 14, and the third image capturing module 15 is in working condition.

[0146] The third image acquisition module 15 is electrically connected to the control module 10 via the first control bus CB1. The control module 10 controls the first image acquisition module 13, the second image acquisition module 14, and the third image acquisition module 15 to not be in working state simultaneously. That is, when the first image acquisition module 13 is in working state, the second image acquisition module 14 and the third image acquisition module 15 are in non-working state; when the second image acquisition module 14 is in working state, the first image acquisition module 13 and the third image acquisition module 15 are in non-working state; and when the third image acquisition module 15 is in working state, the first image acquisition module 13 and the second image acquisition module 14 are in non-working state.

[0147] The first optimization unit 11 is electrically connected between the first node N1 and the first image acquisition module 13; the second optimization unit 12 is electrically connected between the first node N1 and the second image acquisition module 14; and the third optimization unit 16 is electrically connected between the first node N1 and the third image acquisition module 15. In this embodiment, the circuit structure, connection method, and operating timing of the first optimization unit 11 and the second optimization unit 12 are exactly the same as those of the first optimization unit 11 and the second optimization unit 12 in the first embodiment. Meanwhile, the circuit structure and operating principle of the third optimization unit 16 are the same as those of the first optimization unit 11 and the second optimization unit 12.

[0148] When the third image acquisition module 15 is in operation, the third optimization unit 16 ensures the smoothness of the image signal curve by eliminating the back grooves of the third image signal at the rising and falling edges.

[0149] Specifically, please refer to the following: Figures 10-11 ,in, Figure 11 for Figure 10 The schematic diagram of the planar layout structure of the first optimization unit 11, the second optimization unit 12, and the third optimization unit 16 shown is as follows: Figure 11 As shown, the first optimization unit 11 includes four first resistors R1 and four first inductors L1, the second optimization unit 12 includes four second resistors R2 and four second inductors L2, and the third optimization unit 16 includes four third resistors R3 and four third inductors L3. Each third resistor R3 and each third inductor L3 is connected in series with the four sub-nodes N1-1 to N1-4 and the third image acquisition module 15 in a one-to-one correspondence.

[0150] Please see Figure 12 , Figure 12 As in the fifth embodiment of this application Figure 3 The diagram shows the specific circuit structure of the image capture switching control module. In this embodiment, as shown... Figure 12 As shown, the image capture switching control module 100 and Figure 4 The image acquisition switching control module 100 is basically the same as the image acquisition switching control module, except that the four first inductors L1 in the first optimization unit 11 are replaced with two common-mode inductors CL1, and the four second inductors L2 are replaced with two common-mode inductors CL2. In addition to having the same effect of eliminating image signal noise as the first inductors L1 and the second inductors L2, the integration of the first and second common-mode inductors CL1-CL2 is higher than that of the dispersed and independent first and second inductors L1-L2, thus making the assembly simpler and the safety protection higher.

[0151] like Figure 12As shown, the first optimization unit 11 includes four first resistors R1 and two first common-mode inductors CL1, wherein each first common-mode inductor includes two first sub-inductors CLm. One first resistor R1 and one first sub-inductor CLm are connected in series, thus one first common-mode inductor CL1 is connected in series with two of the first resistors R1. Correspondingly, the second optimization unit 12 includes four second resistors R2 and two second common-mode inductors CL2, each second common-mode inductor including two second sub-inductors CLn. One first resistor R1 and one second sub-inductor CLn are connected in series, thus one first common-mode inductor CL1 is connected in series with two of the first resistors R1.

[0152] That is, in the first and second embodiments, the two adjacent first inductors L1 corresponding to a differential pair interface are replaced with a first common-mode inductor CL1 in this embodiment, and in the first and second embodiments, the two adjacent second inductors L2 corresponding to a differential pair interface are replaced with a second common-mode inductor CL2 in this embodiment.

[0153] Meanwhile, corresponding to the clock differential pair interface, two first resistors R1 and one first common-mode inductor CL1 are connected in series, and the two are electrically connected between the first node N1 and the first image capturing module 13; two second resistors R2 and one second common-mode inductor CL2 are connected in series, and the two are electrically connected between the first node N1 and the second image capturing module 14.

[0154] For the corresponding data differential pair interface, the other two first resistors R1 are connected in series with another first common-mode inductor CL1, and the two are electrically connected between the first node N1 and the first image capturing module 13; the other two second resistors R2 are connected in series with another second common-mode inductor CL2, and the two are electrically connected between the first node N1 and the second image capturing module 14.

[0155] The first common-mode inductor CL1 is used to further filter noise from the first image signal. Thus, through the cooperation of the first resistor R1 and the first common-mode inductor CL1, the quality of the first image signal can be effectively improved, ensuring that the first image acquisition module 13 provides high-speed, accurate, and complete image signal transmission during operation.

[0156] Accordingly, the second common-mode inductor CL2 is used to further perform noise filtering on the second image signal. Thus, through the cooperation of the second resistor R2 and the second common-mode inductor CL2, the quality of the second image signal can be effectively improved, ensuring that the second image acquisition module 14 can provide high-speed, accurate, and complete transmission of the image signal during operation.

[0157] Please refer to the following: Figure 13 , Figures 14a-14b , Figure 13This is a functional structure diagram of the image capturing and display terminal 1 in the sixth embodiment of this application. Figures 14a-14b For example Figure 13 A schematic diagram of the planar structure of the image capture and display terminal 1 on two opposite sides.

[0158] like Figure 13 , Figures 14a-14b As shown, the image capture and display terminal 1 includes a display module 200 and an image capture switching control module 100. In this embodiment, the camera switching control module 100 and... Figure 3 The camera switching control module 100 shown has the same structure and function. For example... Figure 13 As shown, the camera switching control module 100 includes a control module 10, a first optimization unit 11, a second optimization unit 12, a first image acquisition module 13, and a second image acquisition module 14. The difference lies in that the image acquisition display terminal 1 also includes a display module 200, and a fourth optimization unit 204 and a fifth optimization unit 205 for optimizing the image data received by the display module 200 for display.

[0159] Specifically, the display module 200 is used to receive image signals and display the image signals, such as... Figures 14a-14b As shown, the display module 200 includes a first display unit 201 and a second display unit 202 disposed on the touch display screen 1a. Both the first display unit 201 and the second display unit 202 are used to perform image display according to the image signal. The image display resolution of the first display unit 201 and the second display unit 202 may be the same or different.

[0160] In this embodiment, the number of display units included in the display module 200 can be set according to requirements, for example, it can include three or more display units, and is not limited thereto. The image signal can come from the first image signal, the second image signal and the third image signal provided by the first image acquisition module 13, the second image acquisition module 14 and the third image acquisition module 15, or it can come from the image generated inside the display terminal or the image signal received by other terminals.

[0161] Specifically, the control module 10 further includes a second signal interface 102, a second control bus CB2, and a third node N3. The second signal interface is the Display Serial Interface (DSI) in the Mobile Industry Processor Interface (MIPI).

[0162] The control module 10 is electrically connected to the first display unit 201 and the second display unit 202 via the second control bus CB2, and outputs control signals to the first display unit 201 and the second display unit 202 via the second control bus CB2 to control whether the first display unit 201 and the second display unit 202 receive image signals and whether they perform image display. Simultaneously, the first display unit 201 and the second display unit 202 are also electrically connected to the second signal interface 102 of the control module 10 via a third node N3, and the control module 10 sends time-division image signals to the first display unit 201 and the second display unit 202 via the second signal interface 102.

[0163] The control module provides image signals to the first display unit 201 and the second display unit 202 at 10-minute intervals, which includes:

[0164] When the first display unit 201 receives an image signal through the second signal interface 102, the second display unit 202 is in a state of not receiving an image signal. Conversely, when the first display unit 201 is not in a state of not receiving an image signal, the second display unit 202 receives an image signal through the second signal interface 102. Since the first display unit 201 and the second display unit 202 receive image signals in a time-sharing manner, they can share the second signal interface 102 to receive image signals.

[0165] The control module 10 can control both the first display unit 201 and the second display unit 202 to be in a state of waiting for image signals at the same time through control signals.

[0166] In addition, to ensure the correct timing and reception of image signals, and to control the first display unit 201 and the second display unit 202 to display images as needed after receiving the image signal, the control module 10 also outputs corresponding control signals to the first display unit 201 and the second display unit 202, thereby controlling the first display unit 201 to be in a waiting state for image signal reception or controlling the second display unit 202 to be in a waiting state for image signal reception. Specifically, when the first display unit 201 is in the image signal reception state, it receives the image signal from the second signal interface 102; when the second display unit 202 is in the image signal reception state, it receives the image signal from the second signal interface 102.

[0167] The scenario in which the first display unit 201 and the second display unit 202 need to be in the image signal receiving state in a time-division manner is as follows: when the user needs to display images in split screen due to the folding display module 200, or needs to display images captured from different positions and different image capture modules on different display units, the user can trigger the control module 10 to control the first display unit 201 and the second display unit 202 to be in the image signal receiving state in a time-division manner by folding or opening the touch screen TP or by touch operation.

[0168] Specifically, the user, through touch operation, enables the control module 10 to receive user input commands from outside the image capture and display terminal 1, and to perform actions such as... Figure 2 The information prompt box displayed on the touch screen 1a shown can be used to perform touch operations, or input commands can be provided through audio signals picked up by the audio pickup module VP, or commands can be received from other functional modules inside the terminal. The position information corresponding to the touch operation is used to identify the display unit selected to perform image display. For example, when the user operates the position of the upper screen display option on the touch screen TP, it indicates that the first display unit 201 is selected to receive the image signal; when the user operates the position of the lower screen display option on the touch screen TP, it indicates that the second display unit 202 is selected to receive the image signal.

[0169] Audio signals can also be used to characterize the display unit selected to receive image signals. For example, by recognizing that the content of the voice information in the audio signal is "upper screen display", the first display unit 201 is characterized as being selected to receive image signals; by recognizing that the content of the voice information in the audio signal is "lower screen display", the second display unit 202 is characterized as being selected to receive image signals.

[0170] It should be noted that although the first display unit 201 and the second display unit 202 receive image signals in a time-division manner, the first display unit 201 and the second display unit 202 can perform image display simultaneously, or only the display unit that receives the image signal can perform image display. This is not a limitation. For example, the first display unit 201 and the second display unit 202 can perform image signal display simultaneously by temporarily storing the received image signal, or only one of the first display unit 201 and the second display unit 202 can display the received image signal.

[0171] like Figure 13As shown, the fourth optimization unit 204 is electrically connected to the second signal interface 102 via the third node N3, and is also electrically connected to the first display unit 201. The fifth optimization unit 205 is electrically connected to the second signal interface 102 via the third node N3, and is also electrically connected to the second display unit 202. The fourth optimization unit 204 and the fifth optimization unit 205 are connected to the second signal interface 102 of the control module 10 via the third node N3, which serves as a branch point.

[0172] In this embodiment, the circuit structure and connection layout of the fourth optimization unit 204 and the fifth optimization unit 205 are the same as those of the first optimization unit 11 and the second optimization unit 12, and will not be described again in this embodiment. Correspondingly, the principles and processes of the optimization processing of the first image signal by the fourth optimization unit 204 and the optimization processing of the second image signal by the fifth optimization unit 205 are the same as those of the optimization processing of the first image signal by the first optimization unit 11 and the optimization processing of the second image signal by the second optimization unit 12.

[0173] Specifically, the fourth optimization unit 204, when the first display unit 201 receives image signals through the second signal interface 102 and the third node N3, can accurately eliminate the loops and noise caused by traces between the third node N3 and the second display unit 202 on the rising or falling edges of the image signal, thus ensuring a smooth image signal curve. Similarly, the fifth optimization unit 205, when the second display unit 202 receives image signals through the second signal interface 102 and the third node N3, accurately eliminates the loops and noise caused by traces between the third node N3 and the first display unit 201 on the rising or falling edges of the image signal, thus smoothing the image signal curve. Therefore, the fourth optimization unit 204 and the fifth optimization unit 205 can ensure that the curves of the received image signals are relatively smooth. For example, when the first display unit 201 and the second display unit 202 receive the first image signal and the second image signal, the curves of either the first image signal or the second image signal are smoothed.

[0174] The above description is a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. An image capture and display terminal, characterized in that, It includes an image acquisition switching control module, comprising a control module, a first optimization unit, a second optimization unit, a first image acquisition module, a second image acquisition module, and a first node. The control module includes a first control bus and a first signal interface. The control module is electrically connected to the first image acquisition module and the second image acquisition module through the first control bus. The control module outputs control signals to control the first image acquisition module and the second image acquisition module to be in working state at the same time. The first signal interface is electrically connected to the first node; The first optimization unit is electrically connected between the first node and the first image acquisition module, wherein the first optimization unit includes a first resistor and a first inductor; The second optimization unit is electrically connected between the first node and the second image acquisition module, wherein the second optimization unit includes a second resistor and a second inductor; The first image acquisition module is used to acquire a first image and output a first image signal; The second image acquisition module is used to acquire a second image and output a second image signal; The first optimization unit, the first image acquisition module, the second optimization unit, and the second image acquisition module are connected in parallel to the first node, and the first distance between the first node and the first image acquisition module is different from the second distance between the first node and the second image acquisition module, and the first resistor and the second resistor have the same resistance value, while the first inductor and the second inductor have different inductance values. When the first image acquisition module is in working state, the second image acquisition module is in high impedance mode in non-working state. The second image acquisition module forms a trace stub relative to the first image acquisition module. The acquired first image signal is transmitted to the first signal interface through the first optimization unit and the first node in sequence. The first optimization unit is used to fill the back groove caused by the instantaneous drop at the rising and falling edges of the curve of the first image signal due to the trace stub formed by the second image acquisition module, so as to ensure that the curve of the first image signal is smooth. When the second image acquisition module is in working state, the first image acquisition module is in high-impedance mode in non-working state. The first image acquisition module forms a trace stub relative to the second image acquisition module. The acquired second image signal is transmitted to the first signal interface sequentially through the second optimization unit and the first node. The second optimization unit is used to fill the back grooves caused by the instantaneous drop at the rising and falling edges of the curve of the second image signal due to the trace stub formed by the first image acquisition module, so as to ensure that the curve of the second image signal is smooth.

2. The image capturing and display terminal according to claim 1, characterized in that, The first optimization unit is specifically used to ensure the smooth curve of the first image signal by eliminating the back grooves of the first image signal when the first image acquisition module is in working state and the second image acquisition module is in non-working state. The second optimization unit is specifically used to ensure the smoothness of the curve of the second image signal by eliminating the back grooves of the second image signal when the second image acquisition module is in working state and the first image acquisition module is in non-working state.

3. The image capturing and display terminal according to claim 1, characterized in that, The first optimization unit includes a first resistor, and the second optimization unit includes a second resistor.

4. The image capturing and display terminal according to claim 1, characterized in that, The distance between the first node and the control module is greater than the distance between the first node and the first image acquisition module; or The distance between the first node and the control module is greater than the distance between the first node and the second image acquisition module.

5. The image capturing and display terminal according to claim 4, characterized in that, The first inductor is connected in series between the first resistor and the first image capturing module; The second inductor is connected in series between the second resistor and the second image capturing module; The first inductor is used to filter out noise from the first image signal; The second inductor is used to filter out noise from the second image signal.

6. The image capturing and display terminal according to claim 5, characterized in that, The first signal interface includes a clock signal interface and a data signal interface. The clock signal interface is used to receive a clock control signal from the first image signal or the second image signal, and the data signal interface is used to receive image data from the first image signal or the second image signal. The clock signal interface includes a pair of clock differential pairs, which are electrically connected to the first node. The data signal interface includes a pair of data differential pairs, which are electrically connected to the first node. The first optimization unit includes four first resistors, which are respectively connected to the clock differential pair interface and the data differential pair interface, and are electrically connected between the first node and the first image acquisition module. The second optimization unit includes four second resistors, which are respectively connected to the clock differential pair interface and the data differential pair interface, and are electrically connected between the first node and the second image acquisition module.

7. The image capturing and display terminal according to claim 6, characterized in that, The first optimization unit further includes four first inductors, which are electrically connected between the four first resistors and the first image acquisition module. The second optimization unit further includes four second inductors, which are electrically connected between the four second resistors and the second image acquisition module.

8. The image capturing and display terminal according to claim 6, characterized in that, The first optimization unit also includes two first common-mode inductors, each of which includes two first sub-inductors, and a first resistor connected in series with one of the first sub-inductors; The second optimization unit also includes two second common-mode inductors, each of which includes two second sub-inductors, with one first resistor connected in series with one second sub-inductor; Two first resistors are connected in series with one first common-mode inductor and are electrically connected between the first node and the first image capturing module corresponding to the clock differential interface. Two second resistors are connected in series with one second common-mode inductor and are electrically connected between the first node and the second image capturing module corresponding to the clock differential interface. The other two first resistors are connected in series with another first common-mode inductor, and are electrically connected between the first node and the first image acquisition module corresponding to the data differential interface. The other two second resistors are connected in series with another second common-mode inductor, and are electrically connected between the first node and the second image acquisition module corresponding to the data differential interface.

9. The image capturing and display terminal according to claim 1, characterized in that, The image acquisition switching control module also includes a third image acquisition module, a second node, and a third optimization unit. The third image acquisition module is electrically connected to the control module through the first control bus and is used to acquire a third image to obtain a third image signal. The control module is also used to control the first image acquisition module, the second image acquisition module and the third image acquisition module to be in working state at the same time. The second optimization unit is electrically connected between the first node and the second node; The second image acquisition module is electrically connected to the second node through the third optimization unit; The third image acquisition module is electrically connected to the second node through the third optimization unit; The second optimization unit and the third optimization unit are used to eliminate back grooves and noise in the second image signal to ensure the smoothness of the curve of the second image signal; The second optimization unit and the third optimization unit are used to eliminate back grooves and noise in the third image signal to ensure that the curve of the third image signal is smooth.

10. The image capturing and display terminal according to claim 9, characterized in that, The third optimization unit includes a first sub-optimization unit and a second sub-optimization unit. The second image acquisition module is electrically connected to the second node through the first sub-optimization unit, and the third image acquisition module is electrically connected to the second node through the second sub-optimization unit. The second optimization unit and the first sub-optimization unit are used to eliminate backtracking and noise in the second image signal; The second optimization unit and the second sub-optimization unit are used to eliminate backtracking and noise in the third image signal.

11. The image capturing and display terminal according to claim 10, characterized in that, The first signal interface includes a clock signal interface and a data signal interface. The clock signal interface is used to receive a clock control signal from the first image signal or the second image signal, and the data signal interface is used to receive image data from the first image signal or the second image signal. The clock signal interface includes a pair of clock differential pairs, which are electrically connected to the first node. The data signal interface includes a pair of data differential pairs, which are electrically connected to the first node. The first optimization unit includes four first resistors and four first inductors. The four first resistors are respectively connected to the clock differential pair interface and the data differential pair interface, and are electrically connected between the first node and the first image acquisition module. The four first inductors are respectively connected between the four first resistors and the first image acquisition module. The second optimization unit includes four second resistors, which are electrically connected between the first node and the second node; The first sub-optimization unit includes a third resistor and a second inductor, wherein the third resistor and the second inductor are connected in series between the second node and the second image acquisition module; The second sub-optimization unit includes a fourth resistor and a third inductor, which are connected in series between the second node and the third image acquisition module.

12. The image capturing and display terminal according to claim 11, characterized in that, The clock signal interface is also used to receive the clock control signal of the third image signal, and the data signal interface is also used to receive the image data in the third image signal; The clock signal interface includes a pair of clock differential pairs, which are electrically connected to the first node. The data signal interface includes a pair of data differential pairs, which are electrically connected to the first node. The first optimization unit includes four first resistors and four first inductors. The four first resistors and the four first inductors correspond to the pair of clock differential pairs and the pair of data differential pairs, and are connected in series between the first node and the first image acquisition module in a one-to-one correspondence manner. The second optimization unit includes four second resistors, which are connected in series between the first node and the second node, corresponding to the pair of clock differential pairs and the pair of data differential pairs. The first sub-optimization unit includes four third resistors and four second inductors. The four third resistors and the four second inductors correspond to the pair of clock differential pairs and the pair of data differential pairs, and are connected in series between the second node and the second image acquisition module in a one-to-one correspondence manner. The second sub-optimization unit includes four fourth resistors and four third inductors. The four fourth resistors and the four third inductors correspond to the pair of clock differential pairs and the pair of data differential pairs, and are connected in series between the second node and the third image acquisition module in a one-to-one correspondence manner.

13. The image capturing and display terminal according to any one of claims 1-12, characterized in that, The image capture and display terminal also includes a display module, and the control module further includes a second signal interface, a second control bus, and a third node; The third node is electrically connected to the second signal interface; The display module includes a first display unit and a second display unit, which are used to perform image display. The first display unit and the second display unit are electrically connected to the second signal interface through a second node. The control module is electrically connected to the first display unit and the second display unit through the second control bus, and the control module transmits image signals to the first display unit and the second display unit in a time-division manner through the second signal interface.

14. The image capturing and display terminal according to claim 13, characterized in that, It also includes a fourth optimization unit and a fifth optimization unit, wherein: The fourth optimization unit is electrically connected between the third node and the first display unit, and is used to eliminate backtracking and noise in the received image signal; The fifth optimization unit is electrically connected between the third node and the second display unit, and is used to eliminate backtracking and noise in the received image signal.

15. The image capturing and display terminal according to claim 14, characterized in that, The control module is a system-on-a-chip, the first signal interface is the camera serial port in the mobile industrial processor interface, and the second signal interface is the display screen serial port in the mobile industrial processor interface.

16. An image capture and display terminal, characterized in that, It includes a control module, a first optimization unit, a second optimization unit, a first image acquisition module, a second image acquisition module, and a first node. The control module includes a first control bus and a first signal interface. The control module is electrically connected to the first image acquisition module and the second image acquisition module through the first control bus. The control module outputs control signals to control the first image acquisition module and the second image acquisition module to be in working state at the same time. The first signal interface includes a clock signal interface and a data signal interface. The clock signal interface is used to receive a clock control signal from a first image signal or a second image signal. The data signal interface is used to receive image data from a first image signal or a second image signal. The clock signal interface includes a pair of clock differential pairs and the data signal interface includes a pair of data differential pairs. The first signal interface has a pair of clock differential pairs and a pair of data differential pairs electrically connected to the four sub-nodes of the first node, respectively. The first optimization unit is electrically connected between the first node and the first image acquisition module, and the first optimization unit includes four first resistors and four first inductors; The second optimization unit is electrically connected between the first node and the second image acquisition module, and the second optimization unit includes four second resistors and four second inductors; The four first resistors correspond to the clock differential pair interface and the data differential pair interface, respectively, and are electrically connected between the four sub-nodes and the first image acquisition module; The four second resistors correspond to the clock differential pair interface and the data differential pair interface, respectively, and are electrically connected between the four sub-nodes and the second image acquisition module; The first image acquisition module is used to acquire a first image and output a first image signal; The second image acquisition module is used to acquire a second image and output a second image signal; The first optimization unit, the first image acquisition module, the second optimization unit, and the second image acquisition module are connected in parallel to the first node, and the first distance between the first node and the first image acquisition module is different from the second distance between the first node and the second image acquisition module, and the first resistor and the second resistor have the same resistance value, while the first inductor and the second inductor have different inductance values. When the first image capturing module is in working state, the second image capturing module is in a high-impedance mode in non-working state. The second image capturing module forms a trace stub relative to the first image capturing module. The first image signal is transmitted to the first signal interface sequentially through the first optimization unit and the first node. The first resistor is used to eliminate and fill the back groove caused by the instantaneous drop at the rising and falling edges of the curve of the first image signal due to the trace stub formed by the second image capturing module, so as to ensure that the curve of the first image signal is smooth. The first inductor is used to filter out the noise of the first image signal. When the second image acquisition module is in working state, the first image acquisition module is in a high-impedance mode in non-working state. The first image acquisition module forms a trace stub relative to the second image acquisition module. The second image signal is transmitted to the first signal interface sequentially through the second optimization unit and the first node. The second resistor is used to eliminate and fill the back groove caused by the instantaneous drop at the rising and falling edges of the curve of the second image signal due to the trace stub formed by the first image acquisition module, so as to ensure the smoothness of the curve of the second image signal. The second inductor is used to filter out the noise of the second image signal.

Images