Semiconductor Devices

Abstract

A semiconductor device comprises: a peripheral circuit layer, including a lower substrate; a memory cell layer, on the peripheral circuit layer, including a first upper substrate and a second upper substrate, the first upper substrate and the second upper substrate being adjacently arranged on the upper surface of the peripheral circuit layer along a first direction; at least one cutting area, between the first upper substrate and the second upper substrate; and at least one semiconductor pattern, between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0047766 filed on April 25, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As the demand for high performance, high speed and / or versatility of electronic devices increases, the integration of semiconductor devices in electronic devices is also increasing. According to the trend of increasing integration of semiconductor devices, the patterns used to form semiconductor devices are becoming smaller and smaller. Therefore, it is very important to reduce or prevent defects in the manufacturing process. Summary of the invention

[0005] An aspect of the inventive concept provides a semiconductor device having improved reliability and a method of manufacturing the same.

[0006] According to one aspect of the present invention, a semiconductor device includes: a peripheral circuit layer, including a lower substrate; a memory cell layer, on the peripheral circuit layer, including a first upper substrate and a second upper substrate, the first upper substrate and the second upper substrate are adjacently arranged on the upper surface of the peripheral circuit layer along a first direction; at least one cutting area, between the first upper substrate and the second upper substrate; and at least one semiconductor pattern, between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting area.

[0007] According to one aspect of the present invention, a semiconductor device includes: a lower substrate; a circuit element on the lower substrate; a lower interlayer insulating layer on the lower substrate and at least partially covering the circuit element; a plurality of upper substrates on the upper surface of the lower interlayer insulating layer; a plurality of gate electrodes, respectively on the plurality of upper substrates; an upper interlayer insulating layer at least partially covering the plurality of gate electrodes; and at least one cutting area between the plurality of upper substrates, passing through the upper interlayer insulating layer and contacting the lower interlayer insulating layer.

[0008] According to one aspect of the inventive concept, a method for manufacturing a semiconductor device includes: forming circuit elements including peripheral circuits on a lower substrate; forming an upper substrate and semiconductor patterns connecting the upper substrates to each other; alternately stacking sacrificial layers and molded insulating layers on the upper substrate; forming a channel structure passing through the sacrificial layers and the molded insulating layers; forming at least one cutting area between the semiconductor patterns; and removing the sacrificial layers and forming a gate electrode in the area where the sacrificial layers are removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 yes Figure 1 An enlarged view of area "A";

[0012] Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Figure 2 The line I-I' is intercepted by

[0013] Figure 4 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept, and shows Figure 2 The corresponding area;

[0014] Figure 5 is a schematic cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0015] Figure 6 is a schematic plan view of a semiconductor device according to an example embodiment of the inventive concept;

[0016] Figure 7 yes Figure 6 An enlarged view of area "A";

[0017] Figure 8 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Figure 7 The line I-I' is intercepted by

[0018] Fig. 9 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept, and shows Figure 7 The corresponding area;

[0019] Fig.10 is a schematic cross-sectional view of a semiconductor device according to an example embodiment of the inventive concept;

[0020] Figures 11 to 14 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept;

[0021] Fig.15 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept;

[0022] Fig.16 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Fig.15 The line I-I' is intercepted by

[0023] Figures 17 to 26 2 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] Some embodiments of the present inventive concept are derived from the following discovery: In the peripheral upper unit (COP) of the VNAND device, during the etching process for forming the channel hole, positive ions can accumulate on the upper substrate below the channel hole, and electrons can accumulate in the amorphous carbon layer (ACL) mask. As a result, a potential difference can be generated, which causes an arc. In order to prevent or reduce the possibility of an arc, a bridge pattern can be formed to connect the upper substrates to each other and to ground the upper substrate to the lower substrate. Then, the channel hole is etched. After the etching of the channel hole is completed, the bridge pattern can be cut using the cutting area defined for the bridge pattern. Therefore, the bridge pattern can be used as a current path to release any potential difference that can be generated during the etching process, thereby reducing the risk of undesirable arcs.

[0026] Figure 1 is a schematic cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts. Figure 2 yes Figure 1 Magnified view of area "A". Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Figure 2 The line I-I' is intercepted.

[0027] Reference Figures 1 to 3, the semiconductor device 10 may include a lower substrate 101, and an upper substrate 201 disposed on the lower substrate 101. The peripheral circuit layer PERI is disposed on the lower substrate 101, which may be considered as a first region, and the memory cell layer CELL is disposed on the upper substrate 201, which may be considered as a second region. The semiconductor device 10 may include a cutting region 265, which is spaced apart from each other at the periphery of the upper substrate 201. The cutting region 265 may be disposed between the upper substrates 201. As shown in the figure, two or three cutting regions 265 are arranged between two adjacent upper substrates 201, but example embodiments are not limited thereto. The semiconductor device 10 may include a semiconductor pattern 210, which is disposed between the upper substrate 201 and the cutting region 265 and protrudes from the upper substrate 201 in a horizontal direction (e.g., an X direction and / or a Y direction). The semiconductor pattern 210 may be in contact with the cutting region 265, respectively. The semiconductor pattern 210 may be a bridge pattern.

[0028] The peripheral circuit layer PERI may include a lower substrate 101 , a circuit element 120 disposed on the lower substrate 101 , a lower interlayer insulating layer 150 covering the circuit element 120 , and a lower wiring structure 130 .

[0029] The lower substrate 101 may have an upper surface extending in the X direction and the Y direction. The lower substrate 101 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, and / or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, and / or silicon germanium. The lower substrate 101 may be configured as a bulk wafer or an epitaxial layer. The lower substrate 101 may include a well region having impurities and an element isolation region 105.

[0030] The circuit element 120 may include a circuit gate dielectric layer 121, a circuit gate electrode layer 123, and a source / drain region 125. The circuit gate dielectric layer 121 may include silicon oxide, and the circuit gate electrode layer 123 may include a conductive material such as metal, polysilicon, and / or metal silicide. The source / drain region 125 may be doped with impurities. In some embodiments, a spacer may be disposed on each sidewall of the circuit gate electrode layer 123. For example, the spacer may be formed of silicon nitride.

[0031] The lower interlayer insulating layer 150 may cover or overlap the lower substrate 101 and at least a portion of the circuit element 120 on the lower substrate 101, and may be disposed between the lower substrate 101 and the upper substrate 201. The lower interlayer insulating layer 150 may be formed of an insulating material.

[0032] The lower wiring structure 130 may include a first lower contact plug 131, a first lower wiring 133, a second lower contact plug 135, and a second lower wiring 137 sequentially stacked from the source / drain region 125 of the lower substrate 101. The number of wirings forming the lower wiring structure 130 may be changed in various example embodiments. The lower wiring structure 130 may include a metal, for example, one or more of tungsten (W), copper (Cu), aluminum (Al), etc.

[0033] The memory cell layer CELL may include an upper substrate 201, gate electrodes 230 spaced apart from each other and stacked vertically with the upper surface of the upper substrate 201, mold insulating layers 220 alternately stacked with the gate electrodes 230, channel structures CHS disposed to pass through the gate electrodes 230, first to third upper interlayer insulating layers 250, 252, and 254 at least partially covering the gate electrodes 230, and gate contact plugs 281. The ground selection transistors, the memory cells, and the string selection transistors are vertically arranged along each channel structure CHS, thereby forming a single memory cell string.

[0034] Each upper substrate 201 may have an upper surface extending in the X direction and the Y direction. Each upper substrate 201 may be set to have a size smaller than that of the lower substrate 101. The upper substrate 201 may include a semiconductor material, such as a group IV semiconductor. For example, the upper substrate 201 may be provided as a polysilicon layer, but example embodiments are not limited thereto. For example, the upper substrate 201 may be provided as an epitaxial layer. The upper substrate 201 may include at least one well region having impurities. For example, the entirety of the upper substrate 201 may form a single p-well region.

[0035] The gate electrodes 230 are spaced apart from each other and stacked vertically on the upper substrate 201, and may extend to different lengths in at least one direction (e.g., in the X direction). Each gate electrode 230 may form a ground selection line of a ground selection transistor of the semiconductor device 10, a word line of a memory cell, and a string selection line of a string selection transistor. The number of gate electrodes 230 may be changed differently based on the data storage capacity of the semiconductor device 10. The gate electrode 230 may include a metal material, such as tungsten (W). According to example embodiments, the gate electrode 230 may include polysilicon and / or a metal silicide material. In example embodiments, the gate electrode 230 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0036] The mold insulating layer 220 may be disposed between the gate electrodes 230. The mold insulating layers 220 may be spaced apart from each other in a direction perpendicular to the upper surface of the upper substrate 201, and may be disposed to extend to different lengths in the X direction in a manner similar to the gate electrodes 230. The mold insulating layer 220 may include an insulating material such as silicon oxide or silicon nitride.

[0037] The channel structures CHS may be spaced apart from each other and may be arranged in rows and columns on the upper substrate 201. The channel structures CHS may be arranged to form a lattice pattern on an XY plane, or may be arranged in a zigzag shape in one direction. The channel structures CHS may have a columnar shape and may have an inclined side surface. The channel structures CHS may have a diameter or width that narrows toward the upper substrate 201.

[0038] Each channel structure CHS may include an epitaxial layer 261, a gate dielectric layer 263, a channel region 264, a channel insulating layer 267, and a channel pad 269. In the channel structure CHS, the channel region 264 may have a ring shape surrounding the channel insulating layer 267 formed therein. However, according to example embodiments, the channel region 264 may have a columnar shape such as a cylinder or a prism without the channel insulating layer 267. The channel region 264 may be electrically connected to the epitaxial layer 261 disposed thereunder. The epitaxial layer 261 may be disposed on the lower substrate 201 at the lower end of the channel structure CHS. The epitaxial layer 261 may be disposed in a recessed region of the upper substrate 201. With respect to the lower substrate 101, the level of the upper surface of the epitaxial layer 261 may be higher than the level of the upper surface of the lowermost gate electrode 230, and may be lower than the level of the lower surface of the gate electrode 230 directly above the lowermost gate electrode. In example embodiments, the epitaxial layer 261 may be omitted. In this case, the channel region 264 can be directly connected to the upper substrate 201. The channel pad 269 can be arranged to cover or overlap the upper surface of the channel insulating layer 267, and is arranged to be electrically connected to the channel region 264. The epitaxial layer 261 and the channel region 264 may include a semiconductor material such as polysilicon or single crystal silicon, and the semiconductor material may be a non-doped material, or a material doped with p-type or n-type impurities. The channel pad 269 may include, for example, doped polysilicon. The gate dielectric layer 263 may be arranged between the gate electrode 230 and the channel region 264. The gate dielectric layer 263 may have an annular shape surrounding the channel region 264. The gate dielectric layer 263 may include a tunneling layer, a charge storage layer, and a blocking layer stacked sequentially starting from the channel region 264. The tunneling layer may allow charges to tunnel to the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer 166 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 263 may extend along the gate electrode 230 in a horizontal direction.

[0039] The first upper interlayer insulating layer 250 may be disposed to cover or overlap the upper substrate 201, the semiconductor pattern 210, and at least a portion of the gate electrode 230 disposed on the upper substrate 201. The second upper interlayer insulating layer 252 and the third upper interlayer insulating layer 254 may be stacked on the first upper interlayer insulating layer 250. The first upper interlayer insulating layer 250, the second upper interlayer insulating layer 252, and the third upper interlayer insulating layer 254 may be formed of an insulating material.

[0040] The semiconductor device 10 may further include a through region 260 and a cutting region 265, the through region 260 being arranged to pass through the upper substrate 201, the cutting region 265 being located between the semiconductor patterns 210 so as to cut the semiconductor patterns 210 or separate the semiconductor patterns 210 from each other. The through region 260 may pass through the gate electrode 230, the mold insulating layer 220, and the upper substrate 201 so as to extend to the upper portion of the lower interlayer insulating layer 150. The through region 260 may be an area where a first through plug 285 is arranged, and the first through plug 285 is used to connect the memory cell layer CELL and the peripheral circuit layer PERI. The through region 260 may be arranged between an area where the channel structure CHS is arranged and an area where the gate contact plug 281 is arranged. The through region 260 may include an insulating material, and the first through plug 285 may be arranged in the through region 260. The first through plug 285 may be electrically connected to the circuit element 120 through the lower wiring structure 130. The first through plug 285 may be connected to the gate contact plug 281, the channel structure CHS, etc. through an upper wiring structure (not shown). The shape of the sidewall of the through region 260 may be inclined, and the width may be narrowed downward. For example, the lower surface of the through region 260 may be narrower than the upper surface of the through region 260, and the upper width of the through region 260 may be larger than the lower width of the through region 260. The second through plug 287 may be formed between the cutting regions 265, and may be electrically connected to the circuit element 120 while passing through the first upper interlayer insulating layer 250.

[0041] The cutting region 265 may pass through the first, second, and third upper interlayer insulating layers 250 , 252 , and 254 and the semiconductor pattern 210 so as to extend to an upper portion of the lower interlayer insulating layer 150 .

[0042] The cutting region 265 may be located between the upper substrates 201. The cutting region 265 may include an insulating material.

[0043] With respect to the lower substrate 101, the lower surface of the through region 260 and the lower surface of the cutting region 265 may be lower than the lower surface of the upper substrate 201. The through region 260 and the cutting region 265 may be formed using different etching processes, and the levels of the lower surfaces of the through region 260 and the cutting region 265 may be different from each other.

[0044] The height of the cutting region 265 may be greater than the height of the passing region 260. An upper surface of the cutting region 265 may be higher than an upper surface of the passing region 260 with respect to the lower substrate 101.

[0045] The shape of the sidewall of the cutting area 265 may be inclined, and the width may narrow downward in the direction of the lower substrate 101. For example, the lower surface of the cutting area 265 may be narrower than the upper surface of the cutting area 265, and the upper width of the cutting area 265 may be wider than the lower width of the cutting area 265. In addition, the height of the cutting area 265 may be greater than the height of the channel structure CHS. Relative to the lower substrate 101, the upper surface of the cutting area 265 may be higher than the upper surface of the channel structure CHS. However, the shape of the cutting area 265 and the relative sizes of the cutting area 265 and the through area 260 are not limited to those shown in the figures, and may be changed differently in example embodiments.

[0046] The semiconductor device 10 may further include a separation region SR that is separated in the X direction and intersects the gate electrode 230 of the memory cell layer CELL. The separation region SR includes an insulating layer 273 and a conductive layer 275, and the conductive layer 275 is a common source line for driving the memory cells. Impurity regions 271 may be respectively disposed below the separation regions SR in the upper substrate 201.

[0047] A portion of the separation region SR may include a portion divided to at least partially surround the passing region 260 .

[0048] Figure 4 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept, and shows Figure 2 The corresponding area. Figure 5 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Figure 4 The line I-I' is intercepted.

[0049] refer to Figure 4 and Figure 5 In the semiconductor device 10A in the example embodiment, the semiconductor pattern 210a may have Figures 1 to 3 The semiconductor device 10 may have a groove that contacts the cutting region 265a in a different manner. The cutting region 265a may include a contact portion (protruding portion) that contacts the groove of the semiconductor pattern 210a, and the contact portion (protruding portion) may include a convex curved surface.

[0050] As reference Fig.26 As described, the cutting area 265a can be provided by the following steps: using an anisotropic dry etching process to form an opening through the first upper interlayer insulating layer 250, the second upper interlayer insulating layer 252, and the third upper interlayer insulating layer 254 and the semiconductor pattern 210a; and then using an additional wet etching process to remove a portion of the semiconductor pattern 210a. The wet etching process can be performed by an etching solution configured to etch, for example, polysilicon.

[0051] Figure 6 is a schematic plan view of a semiconductor device according to an example embodiment of the inventive concept. Figure 7 yes Figure 6 Magnified view of area "A". Figure 8 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Figure 7 The line I-I' is intercepted.

[0052] refer to Figure 6 , Figure 7 and Figure 8 , a semiconductor device 10B according to an example embodiment may include a semiconductor pattern 210' disposed between and spaced apart from an upper substrate 201. A cutting region 265' may be disposed between the upper substrate 201 and the semiconductor pattern 210'. Each cutting region 265' may contact the upper substrate 201 and the semiconductor pattern 210'. The upper substrate 201 and the semiconductor pattern 210' may be electrically isolated by the cutting region 265'. As a result, the upper substrate 201 may be electrically isolated by the cutting region 265'.

[0053] Fig. 9 is a schematic plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept, and shows Figure 7 The corresponding area. Fig.10 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Fig. 9 The line I-I' is intercepted.

[0054] refer to Fig. 9 and Fig.10 , through Figures 6 to 8In a manner different from the semiconductor device 10B of the embodiment, in the semiconductor device 10C according to the example embodiment, the semiconductor pattern 210a' may have a first groove in contact with the cutting region 265a'. The upper substrate 201 may also have a second groove in contact with the cutting region 265a'. The cutting region 265a' may include a contact portion (protruding portion) in contact with the first groove of the semiconductor pattern 210a' and the second groove of the upper substrate 201, and the contact portion (protruding portion) may include a convex curved surface.

[0055] Figures 11 to 14 is a schematic plan view illustrating a portion of a semiconductor device according to example embodiments of the inventive concepts.

[0056] refer to Fig.11 , through Figures 1 to 3 In a different manner from the semiconductor device 10 of the example embodiment, the semiconductor device 10D according to the example embodiment may include at least one cutting region 265b between adjacent upper substrates 201. The semiconductor pattern 210 protruding from the upper substrate 201 may be in contact with the at least one cutting region 265b. For example, the upper substrate 201 may include a first upper substrate 201a and a second upper substrate 201b, and the semiconductor pattern 210 may include a first semiconductor pattern 210a and a second semiconductor pattern 210b. The first semiconductor pattern 210a may be between at least one cutting region 265b and the first upper substrate 201a. The second semiconductor pattern 210b may be between at least one cutting region 265b and the second upper substrate 201b. At least one cutting region 265b is in contact with the first semiconductor pattern 210a and the second semiconductor pattern 210b. At least one cutting region 265b located between the adjacent first upper substrate 201a and the second upper substrate 201b may be a single cutting region.

[0057] refer to Fig.12 , through Figures 1 to 3 In a different manner from the semiconductor device 10E according to example embodiments, the semiconductor device 10E may include a cutting region 265c at least partially surrounding the upper substrate 201. The cutting region 265c may contact all of the semiconductor patterns 210 protruding from the upper substrate 201.

[0058] refer to Fig.13 , through Figure 6 to Figure 7 In a manner different from the semiconductor device 10B, in the semiconductor device 10F according to example embodiments, three semiconductor patterns 210 ′ disposed between adjacent upper substrates 201 may contact a single cutting region 265 b ′.

[0059] A single cutting region 265b' between the upper substrate 201 and the three semiconductor patterns 210' may be disposed on a side surface of the upper substrate 201. The cutting region 265b' may be disposed on each of four side surfaces of the upper substrate 201.

[0060] refer to Fig.14 , through Figure 6 to Figure 7 Differently from the semiconductor device 10B, the semiconductor device 10G according to example embodiments may include cutting regions 265c' respectively at least partially surrounding the upper substrate 201. The cutting regions 265c' may contact some or all side surfaces of the upper substrate 201 and may contact the semiconductor pattern 210'.

[0061] Fig.15 is a schematic plan view illustrating a portion of a semiconductor device according to example embodiments of the inventive concepts. Fig.16 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept, the cross-sectional view being taken along Fig.15 The line I-I' is intercepted.

[0062] refer to Fig.15 and Fig.16 , the semiconductor device 10H according to example embodiments may include a cutting region 265d disposed between adjacent upper substrates 201 and in contact with the upper substrate 201. In the semiconductor device 10H of example embodiments, the semiconductor pattern does not exist between the upper substrates 201.

[0063] Figures 17 to 26 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Fig.17 , Figures 19 to 21 and Figure 23 to Figure 26 In the figure, it is shown that Figure 3 The area shown corresponds to the area. Fig.18 and Fig. 22 , an edge region of the lower substrate 101 is shown.

[0064] refer to Fig.17 and Fig.18 , the circuit elements 120 and the lower wiring structure 130 may be disposed on the lower substrate 101. The element isolation region 105 may be disposed between the circuit elements 120.

[0065] First, a circuit gate dielectric layer 121 and a circuit gate electrode layer 123 may be formed on the lower substrate 101. The circuit gate dielectric layer 121 may be formed of silicon oxide, and the circuit gate electrode layer 123 may be formed of polysilicon, metal silicide and / or metal, but example embodiments are not limited thereto. Then, source / drain regions 125 may be formed in the upper portion of the lower substrate 101 at both sides of the circuit gate electrode layer 123.

[0066] A lower wiring structure 130 and a lower interlayer insulating layer 150 may be formed on the lower substrate 101. The lower wiring structure 130 may include a first lower contact plug 131, a first lower wiring 133, a second lower contact plug 135, and a second lower wiring 137. The lower interlayer insulating layer 150 may be formed of a plurality of insulating layers.

[0067] In addition, an upper substrate 201 and a semiconductor pattern 210 extending from the upper substrate 201 may be disposed on the lower interlayer insulating layer 150 . Fig.18 An edge region of the lower substrate 101 is shown. In the edge region of the lower substrate 101 , the semiconductor pattern 210 extends along a side surface of the lower interlayer insulating layer 150 and may be in contact with the lower substrate 101 .

[0068] The upper substrate 201 and the semiconductor pattern 210 may be formed of, for example, polysilicon. The upper substrate 201 may include, for example, p-type impurities. The upper substrate 201 may be provided to have a size smaller than that of the lower substrate 101 .

[0069] refer to Fig.19 , on the upper substrate 201, the sacrificial layer 240 and the mold insulating layer 220 may be alternately stacked, and portions of the sacrificial layer 240 and the mold insulating layer 220 may be removed by repeatedly performing a photolithography process and an etching process to extend different lengths in the X direction. Therefore, the sacrificial layer 240 and the mold insulating layer 220 may have a stepped form.

[0070] The sacrificial layer 240 may be a layer replaced with the gate electrode 230 by a subsequent process. The sacrificial layer 240 may be formed of a material to be etched while having an etching selectivity relative to the mold insulating layer 220. For example, the mold insulating layer 220 may be formed of silicon oxide and / or silicon nitride, and the sacrificial layer 240 may be formed of a material different from the mold insulating layer 220 and may include silicon, silicon oxide, silicon carbide, and / or silicon nitride. The thickness of a portion of the mold insulating layer 220 may be different from the thickness of the remaining portion.

[0071] Next, a stack structure having the sacrificial layer 240 and the mold insulating layer 220 , and a first upper interlayer insulating layer 250 at least partially covering the upper substrate 201 and the semiconductor pattern 210 may be provided.

[0072] refer to Fig. 20 A passing region 260 passing through the stack structure having the sacrificial layer 240 and the mold insulating layer 220 and the upper substrate 201 may be provided.

[0073] An opening is formed through the stacked structure of the sacrificial layer 240 and the mold insulating layer 220 and the upper substrate 201 to expose the lower interlayer insulating layer 150, and the opening is filled with an insulating material to form a through region 260. The upper surface of the through region 260 may be coplanar with the upper surface of the uppermost sacrificial layer 240.

[0074] refer to Fig.21 and Fig. 22 , a channel hole CHH passing through the stack structure of the sacrificial layer 240 and the mold insulating layer 220 may be provided.

[0075] A mask layer 270 including a hard mask layer, an amorphous carbon layer (ACL), etc. are disposed on the mold insulating layer 220, the through region 260, and the first upper interlayer insulating layer 250 to form a channel hole CHH. Fig. 22 In the edge region of the lower substrate 101, the semiconductor pattern 210 may extend along the side surface of the lower interlayer insulating layer 150 to contact the lower substrate 101. In addition, the mask layer 270 may extend along the side surface of the first upper interlayer insulating layer 250 to contact the lower substrate 101.

[0076] The channel hole CHH may be in the form of a hole having a high aspect ratio and may be formed using an anisotropic etching process. Due to the height of the stacked structure (i.e., due to the high aspect ratio), the sidewall of the channel hole CHH may not be perpendicular to the upper surface of the upper substrate 201. In example embodiments, the channel hole CHH may be formed to allow a portion of the upper substrate 201 to be recessed.

[0077] When a plasma dry etching process is used during the formation of the channel hole CHH, a potential difference between the upper and lower portions of the channel hole CHH may be generated by positive ions and electrons. However, in example embodiments, the upper substrate 201 is connected to the lower substrate 101 through the semiconductor pattern 210 to allow positive ions to flow to the lower substrate 101, and electrons may flow to the lower substrate 101 through the mask layer 270, thereby preventing or reducing the possibility of arc defects caused by the potential difference.

[0078] refer to Fig.23 , an epitaxial layer 261 , a gate dielectric layer 263 , a channel region 264 , a channel insulating layer 267 , and a channel pad 269 are formed in the channel hole CHH to form a channel structure CHS.

[0079] The epitaxial layer 261 may be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 261 may be formed of a single layer or multiple layers. The epitaxial layer 261 may include polysilicon, single crystal silicon, polycrystalline germanium, and / or single crystal germanium doped with impurities or undoped. The gate dielectric layer 263 may be formed to have a uniform thickness using ALD or CVD. The channel region 264 may be disposed on the gate dielectric layer 245 in the channel hole CHH, and the lower portion of the channel region 264 may pass through the gate dielectric layer 245 to connect to the epitaxial layer 261. The channel insulating layer 267 may be formed to fill the inner space of the channel region 264, and may be an insulating material. However, according to example embodiments, a conductive material (rather than the channel insulating layer 267) may fill the inner space of the channel region 264. The channel pad 269 may be formed of a conductive material (e.g., polysilicon).

[0080] refer to Fig.24 , an opening OP is provided, and the sacrificial layer 240 can be removed using the opening. In addition, a conductive material is embedded in the region where the sacrificial layer 240 is removed to form the gate electrode 230.

[0081] The gate electrode 230 may include metal, polysilicon and / or metal silicide material. In example embodiments, before providing the gate electrode 230 , a portion of the gate dielectric layer 263 may be provided first.

[0082] Before providing the opening OP, a second upper interlayer insulating layer 252 covering the mold insulating layer 220 , the channel structure CHS, the passing region 260 , and the first upper interlayer insulating layer 250 may be provided.

[0083] The sacrificial layer 240 exposed through the opening OP may be selectively removed using, for example, wet etching.

[0084] refer to Fig.25 , impurities are implanted into the upper substrate 201 exposed by the opening OP to form an impurity region 271. Then, an insulating layer 273 and a conductive layer 275 are formed in the opening OP. The insulating layer 273 and the conductive layer 275 may be a separation region SR. The conductive layer 275 may be a common source line. The conductive layer 275 may include, for example, tungsten, copper, and / or aluminum.

[0085] refer to Fig.26 , a cutting region 265 may be provided, which passes through the first upper interlayer insulating layer 250 , the second upper interlayer insulating layer 252 , and the third upper interlayer insulating layer 254 and the semiconductor pattern 210 .

[0086] A third upper interlayer insulating layer 254 may be provided, the third upper interlayer insulating layer 254 covering the second upper interlayer insulating layer 252. Then, an anisotropic dry etching process is used to provide the following opening: the opening passes through the first upper interlayer insulating layer 250, the second upper interlayer insulating layer 252 and the third upper interlayer insulating layer 254 and the semiconductor pattern 210 to expose the lower interlayer insulating layer 150, and the opening is filled with an insulating material to form a cutting area 265. The upper surface of the cutting area 265 may be coplanar with the upper surface of the second upper interlayer insulating layer 252. With respect to the lower substrate 101, the upper surface of the cutting area 265 may be higher than the upper surface of the through area 260. With respect to the lower substrate 101, the upper surface of the cutting area 265 may be higher than the upper surface of the channel structure CHS. In other words, with respect to the lower substrate 101, the upper surface of the cutting area 265 may be higher than the upper surface of the channel pad 269.

[0087] The insulating material may be provided using a CVD or physical vapor deposition (PVD) process.

[0088] A cutting region 265 is provided between the semiconductor patterns 210 to cut or separate the semiconductor patterns 210 , thereby allowing the upper substrate 201 to be in a floating state, and the semiconductor patterns 210 connect the upper substrates 201 to each other and to the lower substrate 101 .

[0089] refer to Figure 2 and Figure 3 , a gate contact plug 281 that passes through the first upper interlayer insulating layer 250 and is connected to the gate electrode 230 and a first through plug 285 that passes through the through region 260 and is connected to the lower wiring structure 130 may be provided. Together with the first through plug 285, a second through plug 287 may be provided between the cutting regions 265.

[0090] As described above, according to example embodiments of the inventive concept, after a process of etching a channel hole, a cutting region for cutting a bridge pattern connecting an upper substrate is formed, thereby providing a semiconductor device having improved reliability and a method of manufacturing the same.

[0091] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The peripheral circuit layer includes a lower substrate; a memory cell layer, on the peripheral circuit layer, comprising a first upper substrate and a second upper substrate, a plurality of gate electrodes being spaced apart from each other and vertically stacked with the first upper substrate and the second upper substrate, and memory cells being respectively arranged in regions defined by the first upper substrate and the second upper substrate in a plan view, wherein the first upper substrate and the second upper substrate are adjacently arranged on an upper surface of the peripheral circuit layer along a first direction; at least one cutting region between the first upper substrate and the second upper substrate, wherein the at least one cutting region is formed of an insulating material; at least one semiconductor pattern between the first upper substrate and the second upper substrate and adjacent to the at least one cutting region; and an upper interlayer insulating layer at least partially covering the plurality of gate electrodes on the first upper substrate and the second upper substrate and covering the at least one semiconductor pattern, Wherein, the first upper substrate and the second upper substrate are electrically isolated by the at least one cutting area.

2. The semiconductor device according to claim 1, wherein Each of the at least one semiconductor pattern is between a corresponding cutting area in the at least one cutting area and one of the first upper substrate and the second upper substrate, and extends between the corresponding cutting area in the at least one cutting area and one of the first upper substrate and the second upper substrate along a horizontal direction parallel to the upper surface of the lower substrate.

3. The semiconductor device according to claim 2, wherein: Each of the at least one cutting region includes a protruding portion having a convex curved surface contacting a corresponding semiconductor pattern.

4. The semiconductor device according to claim 2, wherein: The at least one semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern is between the at least one cutting region and the first upper substrate, wherein the second semiconductor pattern is between the at least one cutting region and the second upper substrate, Wherein, the at least one cutting region contacts the first semiconductor pattern and the second semiconductor pattern.

5. The semiconductor device according to claim 1, wherein The at least one cutting region at least partially surrounds the first upper substrate and the second upper substrate.

6. The semiconductor device according to claim 1, wherein The at least one cutting region includes a first cutting region and a second cutting region, the first cutting region is between a corresponding semiconductor pattern among the at least one semiconductor pattern and the first upper substrate, and the second cutting region is between the corresponding semiconductor pattern among the at least one semiconductor pattern and the second upper substrate, The first cutting region contacts the first upper substrate and the corresponding semiconductor pattern of the at least one semiconductor pattern, and The second cutting region contacts the second upper substrate and the corresponding semiconductor pattern of the at least one semiconductor pattern.

7. The semiconductor device according to claim 6, wherein: The at least one semiconductor pattern has a groove contacting the first cutting region and the second cutting region.

8. The semiconductor device according to claim 6, wherein: The first upper substrate has a groove contacting the first cutting area, and the second upper substrate has a groove contacting the second cutting area.

9. The semiconductor device according to claim 1, wherein: The at least one semiconductor pattern includes a plurality of semiconductor patterns between the first upper substrate and the second upper substrate.

10. The semiconductor device according to claim 9, wherein The at least one cutting region includes a first cutting region and a second cutting region, the first cutting region is between the plurality of semiconductor patterns and the first upper substrate, and the second cutting region is between the plurality of semiconductor patterns and the second upper substrate, The first cutting region contacts the first upper substrate and the plurality of semiconductor patterns, and The second cutting region contacts the second upper substrate and the plurality of semiconductor patterns.

11. The semiconductor device according to claim 10, wherein: The first cutting area at least partially surrounds the first upper substrate, and the second cutting area at least partially surrounds the second upper substrate.

12. The semiconductor device according to claim 1, wherein A sidewall of the at least one cutting region is inclined, and an upper width of the sidewall away from the lower substrate is wider than a lower width of the sidewall close to the lower substrate.

13. The semiconductor device according to claim 1, wherein A lower surface of each of the at least one cutting area is lower than lower surfaces of the first upper substrate and the second upper substrate.

14. The semiconductor device according to claim 1, wherein The memory cell layer comprises: a plurality of vertical channel structures extending perpendicularly to the upper surface of the first upper substrate and the upper surface of the second upper substrate while passing through the plurality of gate electrodes, and Wherein, a height of the at least one cutting region above the upper surface of the peripheral circuit layer is greater than a height of the plurality of vertical channel structures above the upper surface of the peripheral circuit layer.

15. The semiconductor device according to claim 1, further comprising: a plurality of through regions passing through the memory cell layer, the first upper substrate and the second upper substrate; as well as A plurality of peripheral circuit contact plugs pass through the plurality of through regions and are electrically connected to circuit elements in the peripheral circuit layer.

16. The semiconductor device according to claim 15, wherein: With respect to the lower substrate, an upper surface of the at least one cutting region is higher than upper surfaces of the plurality of passing regions.

17. A semiconductor device comprising: lower base plate; a circuit element, on the lower substrate; a lower interlayer insulating layer on the lower substrate and at least partially covering the circuit element; A plurality of upper substrates are disposed on the upper surface of the lower interlayer insulating layer; at least one semiconductor pattern between the plurality of upper substrates; A plurality of gate electrodes are respectively disposed on the plurality of upper substrates, wherein the plurality of gate electrodes are respectively disposed within regions defined by the plurality of upper substrates in a plan view; an upper interlayer insulating layer at least partially covering the plurality of gate electrodes on the plurality of upper substrates and covering the at least one semiconductor pattern; as well as at least one cutting region, between the at least one semiconductor pattern and a corresponding upper substrate among the plurality of upper substrates, passing through the upper interlayer insulating layer and contacting the lower interlayer insulating layer, wherein a side surface of the at least one cutting region contacts the at least one semiconductor pattern, Wherein, the plurality of upper substrates are electrically isolated by the at least one cutting region.

18. The semiconductor device according to claim 17, wherein: The at least one cutting region includes a plurality of cutting regions, each cutting region being between a corresponding semiconductor pattern among the at least one semiconductor pattern and a corresponding upper substrate among the plurality of upper substrates, and contacting a corresponding upper substrate among the plurality of upper substrates and a corresponding semiconductor pattern among the at least one semiconductor pattern.

19. The semiconductor device according to claim 17, wherein: The at least one semiconductor pattern includes a plurality of semiconductor patterns, wherein the at least one cutting region comprises a plurality of cutting regions, each cutting region being between a corresponding semiconductor pattern among the plurality of semiconductor patterns and a corresponding upper substrate among the plurality of upper substrates, and The plurality of cutting regions are disposed along side surfaces of the corresponding upper substrates and are in contact with the corresponding upper substrates and the corresponding semiconductor patterns.

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