Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. The semiconductor device may include: an n-type layer, a p+-type region, a p-type region, a first electrode, and a second electrode, wherein the n-type layer is arranged on a first surface of a substrate; the p+-type region is arranged on a first surface of a substrate; the p-type region is arranged on a top surface of the n-type layer; the first electrode is arranged on the p+-type region and on the p-type region; the second electrode is arranged on a second surface of the substrate; wherein a side surface of the p+-type region contacts a side surface of the n-type layer, and a thickness of the p+-type region is the same as a thickness of the n-type layer and a thickness of the p-type region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present application claims priority to Korean Patent Application No. 10-2018-0051816 filed on May 4, 2018, the entire contents of which application is incorporated herein for all purposes by this reference. Technical Field

[0003] The present invention relates to a semiconductor device including silicon carbide (SiC) and a method for manufacturing the same. Background Art

[0004] In recent years, the trend of devices developing towards larger size and larger capacity has led to the emergence of power semiconductor devices with high breakdown voltage, high current, and high-speed switching characteristics. Silicon carbide (SiC) power devices are considered to be the only devices that can meet the above characteristics because of their superior characteristics over conventional silicon (Si) devices. They are currently being actively researched and are in the early stages of entering the market.

[0005] In the case of the SiC PiN diode, since the bipolar element has characteristics of high on-voltage and slow switching speed, there is an aspect that it is suitable for the SiC diode element.

[0006] Therefore, most of the SiC diodes currently mass-produced have a silicon carbide Schottky barrier diode (SBD) structure, and in order to improve the leakage current characteristics of the SBD, a junction barrier Schottky (JBS) structure is provided, in which the p+ type region is formed as the bottom end of the ion-implanted Schottky junction part.

[0007] The information disclosed in this background section of the present invention is only used to enhance the understanding of the general background of the present invention and is not to be regarded as an acknowledgement or any form of suggestion that the information constitutes the prior art for those skilled in the art. Summary of the invention

[0008] Various aspects of the present invention are directed to providing a silicon carbide diode having a high breakdown voltage and a high current density.

[0009] The semiconductor device may include: the n-type layer is arranged on the first surface of the substrate; the p+ type region is arranged on the first surface of the substrate; the p- type region is arranged on the top of the n-type layer; the first electrode is arranged on the p+ type region and on the p- type region; the second electrode is arranged on the second surface of the substrate; wherein the side surface of the p+ type region is in contact with the side surface of the n-type layer, and the thickness of the p+ type region is the same as the sum of the thickness of the n-type layer and the thickness of the p- type region.

[0010] The ion doping concentration of the p+ type region may be higher than the ion doping concentration of the p- type region.

[0011] A side surface of the p+ type region may be in contact with a side surface of the p- type region.

[0012] The amount of charge in the p+ type region is the same as the amount of charge in the n type layer.

[0013] The first electrode may include a first metal layer disposed on the p-type region and a second metal layer disposed on the first metal layer, and the first metal layer may be in continuous contact with the p-type region.

[0014] The first metal layer may include a Schottky metal, and the second metal layer and the second electrode may include an ohmic metal.

[0015] The second metal layer may be disposed on the p+ type region.

[0016] The first metal layer may be disposed on the p+ type region.

[0017] The p + type region may include a first P concentration layer disposed on the first surface of the substrate and a second P concentration layer disposed on the first P concentration layer.

[0018] The ion doping concentration of the first P concentration layer may be higher than the ion doping concentration of the second P concentration layer.

[0019] The n-type layer may include a first N concentration layer disposed on the first surface of the substrate and a second N concentration layer disposed on the first N concentration layer.

[0020] The ion doping concentration of the first N concentration layer may be higher than the ion doping concentration of the second N concentration layer.

[0021] The substrate may be an n+ type silicon carbide substrate.

[0022] A method for manufacturing a semiconductor device may include: forming an n-type layer on a first surface of a substrate; etching a portion of the n-type layer to form a substrate exposed region that exposes a portion of the first surface of the substrate; forming a p+ type region on the substrate exposed region; forming a p-type region on the n-type layer; forming a first electrode at the p+ type region and the p-type region; and forming a second electrode on a second surface of the substrate; wherein a side surface of the p+ type region contacts a side surface of the n-type layer, and a thickness of the p+ type region is the same as the sum of a thickness of the n-type layer and a thickness of the p-type region.

[0023] According to the exemplary embodiments of the present invention, a semiconductor device may have a high breakdown voltage and a high current density.

[0024] The methods and apparatus of the present invention have other features and advantages which will be apparent from, or will be described in detail in, the accompanying drawings and the following detailed description incorporated herein, which together serve to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram showing an example of a cross section of a semiconductor device according to an exemplary embodiment of the present invention.

[0026] Figure 2A , Figure 2B and Figure 2C illustrate Figure 1 Electric field distribution in a semiconductor device.

[0027] Figure 3 , Figure 4 , Figure 5 and Figure 6 2 is a schematic diagram showing an example of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0028] Figure 7 , Figure 8 and Fig. 9 2 are schematic diagrams respectively showing examples of cross sections of semiconductor devices according to various exemplary embodiments of the present invention.

[0029] It should be understood that the drawings are not necessarily drawn to scale, but rather present simplified representations of various features that illustrate the basic principles of the invention. The specific design features disclosed in the present invention, such as specific size, orientation, location, and shape, will be determined in part by the specific application and use environment.

[0030] In the several drawings attached, the same or equivalent components are marked with the same reference numerals. DETAILED DESCRIPTION

[0031] Below will be referred to in detail various embodiments of the present invention, the examples of these embodiments are presented in the accompanying drawings and are described as follows. Although the present invention will be described in conjunction with specific embodiments, it will be appreciated that this specification is not intended to limit the present invention to these specific embodiments. On the other hand, the present invention is intended to not only cover specific embodiments, but also include various alternative embodiments, modified embodiments, equivalent or other embodiments, which are included in the spirit and scope of the present invention as defined by the attached claims.

[0032] Various exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, and all modifications do not depart from the spirit or scope of the present invention. On the other hand, the various exemplary embodiments introduced herein are provided to make the disclosed content thoroughly, completely and fully convey the spirit of the present invention to those skilled in the art.

[0033] In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. It will be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or other layers or substrates may be present therebetween.

[0034] Figure 1 is a schematic diagram showing an example of a cross section of a semiconductor device according to an exemplary embodiment of the present invention.

[0035] refer to Figure 1 , a semiconductor device according to an exemplary embodiment of the present invention includes a substrate 100 , an n-type layer 200 , a p + -type layer 300 , a p-type region 400 , a first electrode 500 and a second electrode 600 .

[0036] The semiconductor device according to the exemplary embodiment of the present invention may be a diode. In this case, the first electrode 500 may be an anode, and the second electrode 600 may be a cathode.

[0037] The substrate 100 may be an n+ type silicon carbide substrate.

[0038] The n-type layer 200 and the p+-type layer 300 are disposed on the first surface of the substrate 100, and the p-type region 400 is disposed on top of the n-type layer 200. The ion doping concentration of the p+-type region 300 is higher than that of the p-type region 400.

[0039] The side surface of the n-type layer 200 and the side surface of the p-type region 400 are in contact with the side surface of the p+ type layer 300. The sum of the thickness of the n-type layer 200 and the thickness of the p-type region 400 may be equal to the thickness of the p+ type layer 300. The p+ type layer 300 and the n-type layer 200 are in contact with each other, and a PN junction is formed at their boundary surface. According to the semiconductor device of the exemplary embodiment of the present invention, the electric field has a maximum value in the PN junction (i.e., the boundary surface of the p+ type layer 300 and the n-type layer 200).

[0040] The first electrode 500 is disposed on the p+ type layer 300 and the p- type region 400, and includes a first metal layer 510 and a second metal layer 520. The first metal layer 510 may include a Schottky metal, and the second metal layer 520 may include an ohmic metal.

[0041] The first metal layer 510 is disposed on the p+ type layer 300 and the p-type region 400, and the second metal layer 520 is disposed on the first metal layer 510. Here, the first metal layer 510 is in contact with the p-type region 400, and a Schottky junction is formed at the boundary surface thereof. The first metal layer 510 is in continuous contact with the p-type region 400. That is, the first metal layer 510 is not in contact with the n-type layer 200.

[0042] The second electrode 600 is disposed on a second surface of the substrate 100. Here, the second surface of the substrate 100 refers to a surface opposite to the first surface of the substrate 100. The second electrode 600 may include an ohmic metal.

[0043] In the semiconductor device according to the exemplary embodiment of the present invention, in the off state, the depletion layer extends in the vertical direction and the horizontal direction with respect to the first surface of the substrate 100. Different from this, in the conventional Schottky barrier diode (SBD) element, in the off state, the depletion layer extends in the vertical direction.

[0044] In the semiconductor device according to the exemplary embodiment of the present invention, the electric field has a maximum value at the contact interface (ie, PN junction) of the p + type layer 300 and the n type layer 200 , and the electric field is maintained in a direction perpendicular to the first surface of the substrate 100 .

[0045] In the following, reference will be made to Figure 2A , Figure 2B and Figure 2C Give a more detailed description.

[0046] Figure 2A The dividing line CC' along the PN junction (the contact boundary surface between the p+ type layer 300 and the n type layer 200) and the dividing line BB' along the direction perpendicular to the PN junction are shown. Figure 2B Shows the Figure 2A The electric field distribution of the dividing line BB`, and Figure 2C Shows the Figure 2A Electric field distribution along the dividing line CC`.

[0047] Figure 2B and Figure 2C A graph showing the electric field distribution when breakdown occurs is shown. The value obtained by integrating the graph is proportional to the breakdown voltage according to Poisson's equation.

[0048] refer to Figure 2B , it can be determined that the semiconductor device according to the exemplary embodiment of the present invention has a predetermined electric field value Ec in the PN junction, and the electric field value is the maximum value. In addition, referring to Figure 2C , it can be determined that the semiconductor device according to the exemplary embodiment of the present invention maintains a predetermined electric field value Ec in the PN junction. Figure 2CIn FIG. 1 , the area of ​​the electric field distribution represents the breakdown voltage, and since a predetermined electric field value Ec is maintained in the PN junction, it can be determined that the breakdown voltage increases with an increase in the electric field distribution area.

[0049] Furthermore, in the semiconductor device according to the exemplary embodiment of the present invention, on-resistance is reduced by the p + type region 300 having the ion doping concentration, thereby allowing current density to increase.

[0050] In the semiconductor device according to the exemplary embodiment of the present invention, when the charge amounts of the p+ type region 300 and the n type layer 200 forming the PN junction are equal, the best performance can be obtained. It is defined as maintaining charge balance and satisfying the following equation.

[0051] Np+×Wp+=Nn×Wn

[0052] Here, Np+ represents the ion doping concentration of the p+ region, Wp+ represents the width of the p+ region, Nn represents the ion doping concentration of the n-type layer, and Wn represents the width of the n-type layer.

[0053] Next, characteristics of the semiconductor device according to the exemplary embodiment and a conventional semiconductor device will be described with reference to Table 1.

[0054] Table 1 shows operation simulation results of the semiconductor device according to the present exemplary embodiment and a conventional semiconductor device.

[0055] The comparative example is a conventional Schottky barrier diode (SBD) element.

[0056] Table 1

[0057] Comparative Example Exemplary embodiments Breakdown voltage(V) 1858 3380 <![CDATA[Current density (A / cm 2 )]]> 274 417 <![CDATA[Conductive area at 100 A (cm 2 )]]> 0.365 0.240

[0058] Referring to Table 1, it can be confirmed that the breakdown voltage of the semiconductor device according to the exemplary embodiment of the present invention is improved by 82%, and the current density is improved by 52%, compared with the diode element of the comparative example.

[0059] In addition, the semiconductor device according to the exemplary embodiment of the present invention can be confirmed to have a 34% reduction in the conductive area at 100 A compared to the diode element of the comparative example. Therefore, for the semiconductor device according to the exemplary embodiment of the present invention, the cost of the semiconductor device can be reduced by increasing the number of semiconductor devices per unit wafer, and the yield can be improved.

[0060] Next, refer to Figures 3 to 6 and Figure 1 A method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention is described.

[0061] Figure 3 , Figure 4 , Figure 5 and Figure 6 2 is a schematic diagram showing an example of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0062] refer to Figure 3 , a substrate 100 may be prepared, and an n-type layer 200 may be formed on a first surface of the substrate 100. Here, the substrate 100 may be an n+ type silicon carbide substrate, and the n-type layer 200 may be formed by epitaxial growth.

[0063] refer to Figure 4 , a portion of the n-type layer 200 is etched to form a substrate exposure region 300 a. The substrate exposure region 300 a exposes a portion of the first surface of the substrate 100.

[0064] refer to Figure 5 , a p+ type region 300 is formed at the substrate exposed region 300a. That is, the p+ type region 300 is formed on the first surface of the substrate 100 and the side surface of the n-type layer 200. Here, the p+ type region 300 may be formed by epitaxial growth.

[0065] In an exemplary embodiment of the present invention, Figure 4 and Figure 5 As shown, after the n-type layer 200 is formed on the substrate 100 by epitaxial growth, a portion of the n-type layer 200 is etched to form a substrate exposed region 300a exposing a portion of the first surface of the substrate 100, and then the p+ type region 300 is formed at the substrate exposed region 300a by epitaxial growth. However, it is not limited thereto, and the n-type layer 200 and the p+ type region 300 may be formed by a multi-epitaxial growth and ion implantation process, or may be formed by a dual epitaxial growth.

[0066] For example, an n-type layer 200 of a predetermined thickness is formed on the first surface of the substrate 100 by epitaxial growth, and then a p+-type region 300 of a predetermined thickness is formed by implanting P-type ions (e.g., boron (B), aluminum (Al), gallium (Ga), and indium (In)) into a portion of the n-type layer 200. Next, an n-type layer 200 of a predetermined thickness is formed on the above-mentioned n-type layer 200 of a predetermined thickness and the p+-type region 300 of a predetermined thickness by epitaxial growth, and then a p+-type region 300 of a predetermined thickness is formed by implanting P-type ions into a portion of the n-type layer 200. The n-type layer 200 and the p+-type region 300 may be completed by repeating the current process.

[0067] Furthermore, after forming the n-type layer 200 on a portion of the first surface of the substrate 100 by epitaxial growth, the p + -type region 300 may be formed on the remaining portion of the first surface of the substrate 100 by epitaxial growth.

[0068] refer to Figure 6 , a p-type region 400 is formed at the top of the n-type layer 200. The p-type region 400 is formed by implanting p-type ions (e.g., boron (B), aluminum (Al), gallium (Ga), and indium (In)) into a portion of the n-type layer 200. However, not limited thereto, the p-type region 400 may be formed at the top of the n-type layer 200 by epitaxial growth. The ion doping concentration of the p+ type region 300 is higher than the ion doping concentration of the p-type region 400. In this case, the sum of the thickness of the n-type layer 200 and the thickness of the p-type region 400 may be the same as the thickness of the p+ type layer 300.

[0069] refer to Figure 1 , a first metal layer 510 and a second metal layer 520 are sequentially formed on the p+ type layer 300 and the p-type region 400, and a second electrode 600 is formed on the second surface of the n+ type silicon carbide substrate 100. Here, the first metal layer 510 and the second metal layer 520 may form the first electrode 500. In addition, the first metal layer 510 and the p-type region 400 are in contact with each other, and a Schottky junction is formed at their boundary surface. The first metal layer 510 and the p-type region 400 are in continuous contact. That is, the first metal layer 510 is not in contact with the n-type layer 200.

[0070] The first metal layer 510 may include a Schottky metal, and the second metal layer 520 and the second electrode 600 may include an ohmic metal.

[0071] refer to Figure 7 , Figure 8 and Fig. 9 Semiconductor devices according to various exemplary embodiments of the present invention are described.

[0072] Figure 7 , Figure 8 and Fig. 9 2 are schematic diagrams respectively showing examples of cross sections of semiconductor devices according to various exemplary embodiments of the present invention.

[0073] refer to Figure 7 , except for the structure of the first electrode 500, the semiconductor device according to this exemplary embodiment of the present invention is Figure 1 Therefore, description of the same structure is omitted.

[0074] The first electrode 500 is positioned on the p+ type layer 300 and the p- type region 400, and includes a first metal layer 510 and a second metal layer 520. The first metal layer 510 may include a Schottky metal, and the second metal layer 520 may include an ohmic metal.

[0075] The first metal layer 510 is disposed on the p-type layer 400, and the second metal layer 520 is disposed on the p+ type region 300 and the first metal layer 510. Here, the first metal layer 510 and the p-type region 400 are in contact with each other, and a Schottky junction is formed at their boundary surface. The first metal layer 510 and the p-type region 400 are in continuous contact. That is, the first metal layer 510 is not in contact with the n-type layer 200. The second metal layer 520 and the p+ type region 300 are in contact with each other, and an ohmic junction is formed at their boundary surface.

[0076] refer to Figure 8 , except for the structure of the p+ type region 300, the semiconductor device according to this exemplary embodiment of the present invention is Figure 1 Therefore, description of the same structure is omitted. In the semiconductor device according to the exemplary embodiment of the present invention, the p+ type region 300 includes two concentration layers having ion doping concentrations different from each other.

[0077] The p+ type region 300 includes a first P concentration layer 310 disposed on the first surface of the substrate 100 and a second P concentration layer 320 disposed on the first P concentration layer 310. Here, the ion doping concentration of the first P concentration layer 310 is higher than the ion doping concentration of the second P concentration layer 320. In addition, the ion doping concentration of the second P concentration layer 320 is higher than the ion doping concentration of the p-type region 400.

[0078] refer to Fig. 9 , except for the structures of the n-type layer 200 and the p+-type region 300, the semiconductor device according to this exemplary embodiment of the present invention is Figure 1 Therefore, description of the same structure is omitted. In the semiconductor device according to the exemplary embodiment of the present invention, the n-type layer 200 and the p+-type region 300 respectively include two concentration layers having different ion doping concentrations from each other.

[0079] The n-type layer 200 includes a first N concentration layer 210 disposed on the first surface of the substrate 100 and a second N concentration layer 220 disposed on the first N concentration layer 210. Here, the ion doping concentration of the first N concentration layer 210 is higher than that of the second N concentration layer 220.

[0080] The p+ type region 300 includes a first P concentration layer 310 disposed on the first surface of the substrate 100 and a second P concentration layer 320 disposed on the first P concentration layer 310. Here, the ion doping concentration of the first P concentration layer 310 is higher than the ion doping concentration of the second P concentration layer 320. In addition, the ion doping concentration of the second P concentration layer 320 is higher than the ion doping concentration of the p-type region 400.

[0081] The p-type region 400 is disposed on the n-type layer 200. That is, the p-type region 400 is disposed on the second N concentration layer 220.

[0082] For convenience of interpretation and accurate definition in the appended claims, the terms "upper", "lower", "inner", "outer", "up", "lower", "above", "below", "upward", "downward", "front", "back", "back", "inside", "outside", "inward", "outward", "inner", "external", "inner", "outer", "forward", and "backward" are used to describe the features of the exemplary embodiments with reference to the positions of the features shown in the figures.

[0083] For the purpose of illustration and description, the specific exemplary embodiments of the present invention have been described above. They are not intended to be exhaustive or limit the present invention to the disclosed precise scheme, and it is obvious that various modifications and changes can be made according to the above teachings. The exemplary embodiments selected and described are to explain certain principles of the present invention and its practical application, so that other persons skilled in the art can make and use various exemplary embodiments of the present invention, and alternatives and modifications thereof. The purpose is that the scope of the present invention is limited by the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: An n-type layer disposed on the first surface of the substrate; A p+ type region disposed on a first surface of the substrate; a p-type region disposed on a top surface of the n-type layer; a first electrode disposed on a top surface of the p+ type region and on a top surface of the p- type region; a second electrode disposed on a second surface of the substrate; Wherein, the side surface of the p+ type region contacts the side surface of the n type layer, so that the p+ type region and the n type layer form a PN junction; The thickness of the p+ type region is the same as the sum of the thickness of the n type layer and the thickness of the p- type region; The first electrode includes a first metal layer disposed on a top surface of the p-type region and a second metal layer disposed on the first metal layer; The first metal layer is in continuous contact with the p-type region, so that the first metal layer forms a Schottky junction with the p-type region; The depletion layer of the PN junction and the depletion layer of the Schottky junction extend in different directions; The ion doping concentration of the p+ type region is higher than the ion doping concentration of the p- type region.

2. The semiconductor device according to claim 1, wherein A side surface of the p+ type region is in contact with a side surface of the p- type region.

3. The semiconductor device according to claim 2, wherein: The amount of charge of the p+ type region is the same as the amount of charge of the n type layer.

4. The semiconductor device according to claim 1, wherein The first metal layer includes a Schottky metal; The second metal layer and the second electrode include an ohmic metal.

5. The semiconductor device according to claim 1, wherein The second metal layer is disposed on a top surface of the p+ type region, and the first metal layer is disposed on a top surface of the p- type region.

6. The semiconductor device according to claim 1, wherein The first metal layer is disposed on a top surface of the p+ type region and a top surface of the p- type region.

7. The semiconductor device according to claim 1, wherein The p+ type region includes a first P concentration layer disposed on the first surface of the substrate and a second P concentration layer disposed on the first P concentration layer; The first metal layer of the first electrode is disposed on a top surface of the p-type region and a top surface of the second P concentration layer.

8. The semiconductor device according to claim 7, wherein: The ion doping concentration of the first P concentration layer is higher than the ion doping concentration of the second P concentration layer.

9. The semiconductor device according to claim 8, wherein: The n-type layer includes a first N concentration layer disposed on the first surface of the substrate and a second N concentration layer disposed on the first N concentration layer; The p-type region is disposed on a top surface of the second N concentration layer.

10. The semiconductor device according to claim 9, wherein The ion doping concentration of the first N concentration layer is higher than the ion doping concentration of the second N concentration layer.

11. The semiconductor device according to claim 1, wherein The substrate is an n+ type silicon carbide substrate.

12. A method for manufacturing a semiconductor device, comprising: forming an n-type layer on the first surface of the substrate; etching a portion of the n-type layer to form a substrate exposure region exposing a portion of the first surface of the substrate, wherein the substrate exposure region is formed by the first surface of the substrate and a side surface of the n-type layer; forming a p+ type region at the exposed region of the substrate; forming a p-type region on the n-type layer; forming a first electrode on a top surface of the p+ type region and on a top surface of the p- type region; forming a second electrode on the second surface of the substrate; Wherein, the side surface of the p+ type region contacts the side surface of the n type layer, so that the p+ type region and the n type layer form a PN junction; The thickness of the p+ type region is the same as the sum of the thickness of the n type layer and the thickness of the p- type region; The first electrode includes a first metal layer and a second metal layer; The second metal layer is disposed on the p+ type region, and the first metal layer is disposed on the p- type region and is in continuous contact with the p- type region, so that the first metal layer forms a Schottky junction with the p- type region; The depletion layer of the PN junction and the depletion layer of the Schottky junction extend in different directions; The ion doping concentration of the p+ type region is higher than the ion doping concentration of the p- type region.

13. The method according to claim 12, wherein: A side surface of the p+ type region is in contact with a side surface of the p- type region.

14. The method according to claim 13, wherein: The amount of charge of the p+ type region is the same as the amount of charge of the n type layer.

15. The method according to claim 14, wherein: The first metal layer includes a Schottky metal; The second metal layer and the second electrode include an ohmic metal.

16. The method according to claim 15, wherein: The first metal layer is disposed on the p+ type region and the p- type region.

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