Electronic device and method of manufacturing the same

Abstract

An electronic device includes a first dielectric layer, a second dielectric layer, and at least one first post bump. The second dielectric layer is disposed on the first dielectric layer. The first post bump is disposed in the first dielectric layer and the second dielectric layer. The first post bump includes a bump portion and a post portion, and the post portion is disposed on the bump portion.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing it, and to an electronic device comprising at least one post protrusion and a method for manufacturing the electronic device. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips are integrated with an increased number of electronic components to achieve better electrical performance and more functions. Therefore, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the size of both the semiconductor chip and the semiconductor package may correspondingly increase. Consequently, manufacturing costs may increase accordingly. Alternatively, to minimize the size of semiconductor packages containing semiconductor chips with an increased number of I / O connections, the semiconductor substrate used to support the semiconductor chip should be redesigned accordingly. For electronic devices, such as semiconductor substrates, functional improvements and size reductions can be achieved by changing their materials or by altering their structural design. When changing the materials of electronic devices, the settings or parameters of production equipment and manufacturing methods can be modified accordingly, which may be more complex and expensive compared to adjusting their structural design. Therefore, an effective way to improve the functionality and reduce the size of electronic devices is through structural design. Summary of the Invention

[0003] In some embodiments, an electronic device includes a first dielectric layer, a second dielectric layer, and at least one first pillar bump. The second dielectric layer is disposed on the first dielectric layer. The first pillar bump is disposed in the first and second dielectric layers. The first pillar bump includes a bump portion and a pillar portion, with the pillar portion disposed on the bump portion.

[0004] In some embodiments, a method for manufacturing an electronic device includes: (a) providing a carrier; (b) forming at least one first pillar bump on the carrier, wherein the first pillar bump includes a bump portion and a pillar portion, and the pillar portion is disposed on the bump portion; (c) forming a first dielectric layer to cover at least a portion of the bump portion of the first pillar bump; and (d) forming a second dielectric layer on the first dielectric layer to cover at least a portion of the pillar portion of the first pillar bump. Attached Figure Description

[0005] Some aspects of embodiments of this disclosure are related to the appendix. Figure 1 The best way to understand this text is by reading the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the structures may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 A cross-sectional view of an electronic device 1 according to some embodiments of the present disclosure is shown.

[0007] Figure 2 illustrate Figure 1 The enlarged view of area "A" shown in the image.

[0008] Figure 3 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0009] Figure 4 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0010] Figure 5 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0011] Figure 6 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0012] Figure 7 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0013] Figure 8 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0014] Figure 9 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0015] Figure 10 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0016] Figure 11 illustrate Figure 10 The enlarged view of area "B" shown in the image.

[0017] Figure 12 An enlarged view illustrating a cross-sectional view of an electronic device according to some embodiments of the present disclosure.

[0018] Figure 13 illustrate Figure 12 Top view.

[0019] Figure 14 An enlarged top view illustrating an electronic device according to some embodiments of the present disclosure.

[0020] Figure 15 Explanation along Figure 14 The cross-sectional view taken from line II.

[0021] Figure 16 An enlarged view illustrating a cross-sectional view of an electronic device according to some embodiments of the present disclosure.

[0022] Figure 17 illustrate Figure 16 Top view.

[0023] Figure 18 An enlarged top view illustrating an electronic device according to some embodiments of the present disclosure.

[0024] Figure 19 Explanation along Figure 18 The cross-sectional view taken from line II-II.

[0025] Figure 20 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0026] Figure 21 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0027] Figure 22 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0028] Figure 23 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0029] Figure 24 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0030] Figure 25 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0031] Figure 26 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0032] Figure 27 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0033] Figure 28 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0034] Figure 29 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0035] Figure 30 A cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0036] Figure 31 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0037] Figure 32This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0038] Figure 33 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0039] Figure 34 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0040] Figure 35 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0041] Figure 36 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0042] Figure 37 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0043] Figure 38 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0044] Figure 39 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0045] Figure 40 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0046] Figure 41 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0047] Figure 42 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0048] Figure 43 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0049] Figure 44 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0050] Figure 45This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0051] Figure 46 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0052] Figure 47 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0053] Figure 48 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0054] Figure 49 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0055] Figure 50 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0056] Figure 51 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0057] Figure 52 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0058] Figure 53 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0059] Figure 54 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0060] Figure 55 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure.

[0061] Figure 56 This describes one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0062] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0063] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, define a relationship between the various embodiments and / or configurations discussed.

[0064] At least some embodiments of the present invention provide an electronic device comprising at least one stud bump disposed in two dielectric layers. At least some embodiments of the present invention provide techniques for manufacturing said electronic device.

[0065] In a comparative semiconductor substrate, multiple conductive vias are included for vertical electrical connections between different layers. Each of the conductive vias is in the shape of a solid cylinder or a solid cone. A method for manufacturing conductive vias may include the following steps: First, a first through-hole is formed on a first dielectric layer by, for example, photolithography or laser drilling. Subsequently, a conductive material (e.g., copper) is formed in the first through-hole by, for example, plating, to form the first conductive via. Subsequently, a second dielectric layer is formed to cover the first dielectric layer and the first conductive via. Subsequently, a second through-hole is formed on the second dielectric layer by, for example, photolithography or laser drilling. The location of the second through-hole may correspond to the first conductive via. Thus, the first conductive via may be exposed from the second through-hole. Subsequently, a conductive material is formed in the second through-hole by, for example, plating, to form the second conductive via disposed on and / or in direct contact with the first conductive via. As stated in the foregoing method, at least two hole-formation processes and at least two plating processes are required. However, the more processes used, the greater the risk of failure for any particular process. In other words, more processes increase the risk of semiconductor substrate failure. Furthermore, more processes increase the manufacturing cost of semiconductor substrates.

[0066] Furthermore, if the material of the first dielectric layer contains glass fibers, the sidewalls of the first through-hole can be irregular and uneven after the laser drilling process. That is, the tips of broken fibers may protrude from the sidewalls of the first through-hole. Therefore, during the plating process, the metal particles of the conductive material cannot be tightly stacked and arranged across the entire sidewall of the first through-hole. Consequently, the bonding strength between the first conductive via and the first dielectric layer is weak after the plating process. When warping of the semiconductor substrate occurs due to a mismatch in the coefficient of thermal expansion (CTE) between the first conductive via and the first dielectric layer, the first conductive via may easily peel off from the first dielectric layer. Similarly, the bonding strength between the second conductive via and the second dielectric layer is also weak, and the second conductive via may easily peel off from the second dielectric layer.

[0067] Furthermore, due to the composition of the electrolyte used in the plating, the conductive material of the first conductive via tends to form a dimple shape or a protrusion shape. In other words, the upper surface of the first conductive via is not planar. Because of the dimple or protrusion shape of the first conductive via, circuit structures such as conductive traces or second conductive vias cannot be properly positioned on or above the first conductive via. Moreover, if the second conductive via is positioned on the first conductive via, the bonding strength between the second and first conductive vias is weak due to the boundary between them. When a normal force is applied to the assembly structure of the second and first conductive vias, the assembly structure may easily crack at the boundary between the second and first conductive vias, resulting in an open circuit between them. That is, the assembly structure of the second and first conductive vias has a low resistance to normal and shear forces. Furthermore, due to the aforementioned pitting problem during the plating process, the aspect ratio (A / R) of the first and second conductive vias is low, for example, less than 10:1.

[0068] This invention provides an electronic device comprising at least one pillar bump to address at least the aforementioned problems. In some embodiments, the pillar bump is disposed in two dielectric layers for vertical electrical connection. The pillar bump can be formed by a wirebonding process rather than photolithography or laser drilling and plating processes. The pillar bump provides improved tolerance to normal forces and shear forces.

[0069] Figure 1 A cross-sectional view of an electronic device 1 according to some embodiments of the present disclosure is shown. Figure 2 illustrate Figure 1 The image shows an enlarged view of area "A". The electronic device 1 can be a wiring structure or a semiconductor substrate for carrying a semiconductor chip or semiconductor die. The electronic device 1 includes a carrier 10, at least one first pillar bump 2, a first dielectric layer 12, a second dielectric layer 14, an upper circuit layer 16 (also referred to as the "first circuit layer"), a lower circuit layer 18 (also referred to as the "second circuit layer"), and at least one second pillar bump 3.

[0070] The carrier 10 can be, for example, a metallic material, a ceramic material, a glass material, a substrate, or a semiconductor wafer. The shape of the carrier 10 can be, for example, rectangular or square. Alternatively, the shape of the carrier 10 can be, for example, circular or elliptical. Figure 1 In the embodiments described herein, the carrier 10 is a metallic material. The thickness of the carrier 10 may be in the range of about 100 μm to about 500 μm, about 200 μm to about 800 μm, or about 500 μm to about 1500 μm.

[0071] The first column protrusion 2 can be formed or placed on the carrier 10. Figure 1 In the embodiment described herein, the first post protrusion 2 directly contacts the carrier 10. The material of the first post protrusion 2 (that is, the material contained in the first post protrusion 2) may be a conductive metal, such as copper and / or gold, or another metal or a combination of metals, and may be formed or disposed by a wire bonding process. The first post protrusion 2 has a top surface 21 and a bottom surface 23.

[0072] like Figure 1As shown, the first stud protrusion 2 may include a bump portion 22, a shoulder portion 24, and a stud portion 26. The bump portion 22 is formed or disposed on the carrier 10, and the stud portion 26 is disposed on or above the bump portion 22. The shoulder portion 24 is located between the stud portion 26 and the bump portion 22. In some embodiments, the bump portion 22, the shoulder portion 24, and the stud portion 26 are integrally and simultaneously formed; therefore, the first stud protrusion 2 is a single-piece structure, with no boundary between the bump portion 22 and the shoulder portion 24, and no boundary between the shoulder portion 24 and the stud portion 26. The volume of the protrusion portion 22 of the first pillar protrusion 2 may be greater than the volume of the pillar portion 26 of the first pillar protrusion 2 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The volume of the pillar portion 26 of the first pillar protrusion 2 may be greater than the volume of the shoulder portion 24 of the first pillar protrusion 2 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more).

[0073] like Figure 2 As shown, the maximum width W1 of the protrusion portion 22 of the first pillar protrusion 2 may be greater than the maximum width W2 of the shoulder portion 24 of the first pillar protrusion 2 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The maximum width W2 of the shoulder portion 24 of the first pillar protrusion 2 may be greater than the maximum width W3 of the pillar portion 26 of the first pillar protrusion 2 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The height h1 of the protrusion portion 22 of the first pillar protrusion 2 can be greater than or equal to the height h3 of the pillar portion 26 of the first pillar protrusion 2, and the height h1 of the protrusion portion 22 of the first pillar protrusion 2 can be greater than the height h2 of the shoulder portion 24 of the first pillar protrusion 2 (for example, it can be about 1.3 times or more, about 1.5 times or more, or about 2.0 times or more).

[0074] In some embodiments, the maximum width W3 of the post portion 26 of the first post protrusion 2 may be approximately equal to the bonding line 54 used during the bonding process. Figure 31 The diameter D of the first column protrusion 2. The height h1 of the protrusion portion 22 of the first column protrusion 2 can be equal to the joint line 54. Figure 31 The diameter D of the first column protrusion 2 is approximately 1.2 to 3 times that of the first column protrusion 2, and the total height h is approximately 1.2 to 3 times that of the first column protrusion 2. tIt can be approximately 2 to 3 times the diameter D of the bonding line 54. For example, the diameter D of the bonding line 54 can range from approximately 0.8 mils (thousandths of an inch) to approximately 2 mils, that is, from approximately 20 μm to approximately 50.8 μm, and the total height h of the first post protrusion 2 is... t It can be found in the range of approximately 25 μm to approximately 120 μm.

[0075] In some embodiments, the protrusion portion 22 of the first pillar protrusion 2 is generally disk-shaped or puck-shaped (e.g., a puck-shaped puck with outwardly convex sidewalls), the shoulder portion 24 of the first pillar protrusion 2 is generally disk-shaped or puck-shaped, and the pillar portion 26 of the first pillar protrusion 2 is generally conical (e.g., a cone with outwardly convex sidewalls). The protrusion portion 22 of the first pillar protrusion 2 has a top surface 221, and the shoulder portion 24 of the first pillar protrusion 2 is disposed on the top surface 221 of the protrusion portion 22. Therefore, the sidewalls of the protrusion portion 22 are not connected to the sidewalls of the shoulder portion 24. Furthermore, the shoulder portion 24 of the first pillar protrusion 2 has a top surface 241, and the pillar portion 26 of the first pillar protrusion 2 is disposed on the top surface 241 of the shoulder portion 24. Therefore, the sidewall of the shoulder portion 24 is not connected to the sidewall of the column portion 26.

[0076] like Figure 1As shown, the first dielectric layer 12 may be a passivation layer and may comprise or be formed of the following: a photoresist layer; a cured photosensitive material; a cured photoimageable dielectric (PID) material, such as polyamide (PA), polyimide (PI), epoxy resin, or polybenzoxazole (PBO); or a combination of two or more thereof. In one or more embodiments, the first dielectric layer 12 may comprise or be formed of a dry film material comprising a resin and a plurality of fillers. In one or more embodiments in which the dry film material is a photosensitive material, such dry film material may further comprise any one of a sensitizer, a photoinitiator, and a cross-linker. In one or more embodiments in which the dry film material is a non-photosensitive material, such dry film material does not contain a sensitizer, a photoinitiator, or a cross-linker. In another embodiment, the first dielectric layer 12 may comprise or be formed of a liquid material comprising a homogeneous resin without fillers. In one or more embodiments where the liquid material is a photosensitive material, such liquid material may further comprise diazonaphthoquinone (DNQ). In one or more embodiments where the liquid material is a non-photosensitive material, such liquid material may not contain diazonaphthoquinone (DNQ). In some embodiments, the first dielectric layer 12 may be a dry film material. In some embodiments, the material of the first dielectric layer 12 may comprise an inorganic material (e.g., SiO2). x SiN x TaO x The dielectric layer 12 can be made of glass, silicon, or ceramic. The thickness of the first dielectric layer 12 can range from about 5 μm to about 10 μm.

[0077] A first dielectric layer 12 covers at least a portion of the carrier 10 and the first post protrusion 2. The first dielectric layer 12 has a first surface 121 and a second surface 122 opposite to the first surface 121. The first surface 121 of the first dielectric layer 12 contacts the carrier 10, and the second surface 122 of the first dielectric layer 12 is lower than the top surface 221 of the protrusion portion 22. Therefore, the first dielectric layer 12 covers the lower portion of the protrusion portion 22 of the first post protrusion 2, and the lower portion of the protrusion portion 22 of the first post protrusion 2 is embedded in the first dielectric layer 12. The upper portion of the protrusion portion 22 of the first post protrusion 2 is positioned at a higher elevation than the second surface 122 of the first dielectric layer 12. Figure 1 In the embodiments described herein, the first dielectric layer 12 may be formed or disposed after the first pillar bump 2 is formed. Therefore, the surface conditions (e.g., surface roughness) of the boundary between the first dielectric layer 12 and the bump portion 22 of the first pillar bump 2 are determined by the surface conditions (e.g., surface roughness) of the sidewalls of the bump portion 22 of the first pillar bump 2. Thus, the surface conditions (e.g., surface roughness) of the boundary between the first dielectric layer 12 and the bump portion 22 of the first pillar bump 2 may be smoother than the surface conditions (e.g., surface roughness) of the sidewalls of the through-hole of the dielectric layer of the comparative semiconductor substrate.

[0078] The lower circuit layer 18 (i.e., the second circuit layer) may be a redistribution layer (RDL) and disposed on the second surface 122 of the first dielectric layer 12. For example, the lower circuit layer 18 may include a first metal layer 181, a second metal layer 182, and a third metal layer 183 sequentially disposed on the first dielectric layer 12. The first metal layer 181 and the second metal layer 182 may be seed layers, comprising, for example, titanium and / or copper, another metal or alloy, and may be formed or disposed by sputtering. For example, the first metal layer 181 may comprise titanium, and the second metal layer 182 may comprise copper. The third metal layer 183 may comprise, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, such as Figure 1As shown, the lower circuit layer 18 may include multiple conductive traces and / or multiple bonding pads. The lower circuit layer 18 shall not contact the bump portion 22 of the first pillar bump 2. However, in some embodiments, the lower circuit layer 18 may contact the bump portion 22 of the first pillar bump 2. In one or more embodiments, the linewidth / spacing (L / S) of the lower circuit layer 18 may be equal to or less than about 3 micrometers (μm) / about 3 μm, equal to or less than about 2 μm / about 2 μm (e.g., about 1.8 μm / about 1.8 μm or less, about 1.6 μm / about 1.6 μm or less, or about 1.4 μm / about 1.4 μm or less), equal to or less than about 1 μm / about 1 μm, or equal to or less than about 0.5 μm / about 0.5 μm.

[0079] The second pillar protrusion 3 can be formed or placed on the bonding pad of the lower circuit layer 18. Figure 1 In the embodiments described herein, the shape of the second post protrusion 3 is similar to that of the first post protrusion 2, and the height of the second post protrusion 3 is less than the height of the first post protrusion 2. That is, the second post protrusion 3 can be considered as a compressed first post protrusion 2. The material of the second post protrusion 3 (that is, the material contained in the second post protrusion 3) can be a conductive metal, such as copper and / or gold, or another metal or a combination of metals, and can be formed or disposed by a wire bonding process.

[0080] like Figure 1 As shown, the second pillar protrusion 3 may include a protrusion portion 32, a shoulder portion 34, and a pillar portion 36. The protrusion portion 32 is formed or disposed on a bonding pad of the lower circuit layer 18, and the pillar portion 36 is disposed on or above the protrusion portion 32. The shoulder portion 34 is located between the pillar portion 36 and the protrusion portion 32. In some embodiments, the protrusion portion 32, the shoulder portion 34, and the pillar portion 36 are integrally and simultaneously formed; therefore, the second pillar protrusion 3 is a monolithic structure, with no boundary between the protrusion portion 32 and the shoulder portion 34, and no boundary between the shoulder portion 34 and the pillar portion 36. The volume of the protrusion portion 32 of the second pillar protrusion 3 may be greater than the volume of the pillar portion 36 of the second pillar protrusion 3 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The volume of the pillar portion 36 of the second pillar protrusion 3 may be greater than the volume of the shoulder portion 34 of the second pillar protrusion 3 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more).

[0081] The maximum width of the protrusion portion 32 of the second pillar protrusion 3 may be greater than the maximum width of the shoulder portion 34 of the second pillar protrusion 3 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The maximum width of the shoulder portion 34 of the second pillar protrusion 3 may be greater than the maximum width of the pillar portion 36 of the second pillar protrusion 3 (for example, it may be about 1.1 times or more, about 1.2 times or more, about 1.3 times or more, or about 1.4 times or more). The height of the protrusion portion 32 of the second pillar protrusion 3 may be greater than or equal to the height of the pillar portion 36 of the second pillar protrusion 3, and the height of the protrusion portion 32 of the second pillar protrusion 3 may be greater than the height of the shoulder portion 34 of the second pillar protrusion 3 (for example, it may be about 1.3 times or more, about 1.5 times or more, or about 2.0 times or more).

[0082] In some embodiments, the maximum width of the post portion 36 of the second post protrusion 3 may be approximately equal to the bonding line 54 used during the wire bonding process. Figure 41 The diameter D of the second column protrusion 3. The height of the protrusion portion 32 of the second column protrusion 3 can be equal to the joint line 54. Figure 41 The diameter D is approximately 1.2 to 3 times that of the second column protrusion 3, and the total height of the second column protrusion 3 can be equal to the joint line 54. Figure 41 The diameter D is approximately 2 to 3 times that of the junction line 54. Figure 41 The diameter D of the second column protrusion 3 can range from about 0.8 mils (thousandths of an inch) to about 2 mils, that is, from about 20 μm to about 50.8 μm, and the total height of the second column protrusion 3 can range from about 25 μm to about 120 μm.

[0083] In some embodiments, the protrusion portion 32 of the second pillar protrusion 3 is generally in the shape of a disc or ice puck (e.g., an ice puck-shaped block with outwardly convex sidewalls), the shoulder portion 34 of the second pillar protrusion 3 is generally in the shape of a disc or ice puck, and the pillar portion 36 of the second pillar protrusion 3 is generally in the shape of a cone (e.g., a cone with outwardly convex sidewalls).

[0084] The second dielectric layer 14 may be a passivation layer and may comprise or be formed of the following: a photoresist layer; a cured photosensitive material; a cured photoimageable dielectric (PID) material, such as polyamide (PA), polyimide (PI), epoxy resin, or polybenzoxazole (PBO); or a combination of two or more thereof. In one or more embodiments, the second dielectric layer 14 may comprise or be formed of a dry film material comprising a resin and a plurality of fillers. In one or more embodiments where the dry film material is a photosensitive material, such dry film material may further comprise any one of a sensitizer, a photoinitiator, and a crosslinking agent. In one or more embodiments where the dry film material is a non-photosensitive material, such dry film material does not contain a sensitizer, a photoinitiator, or a crosslinking agent. In another embodiment, the second dielectric layer 14 may comprise or be formed of a liquid material comprising a homogeneous resin without fillers. In one or more embodiments where the liquid-type material is a photosensitive material, such liquid-type material may further comprise diazonaphthoquinone (DNQ). In one or more embodiments where the liquid-type material is a non-photosensitive material, such liquid-type material may not contain diazonaphthoquinone (DNQ). In some embodiments, the second dielectric layer 14 may be a dry film material. In some embodiments, the material of the second dielectric layer 14 may comprise an inorganic material (e.g., SiO2). x SiN x TaO x The material of the second dielectric layer 14 may be the same as or different from that of the first dielectric layer 12. The thickness of the second dielectric layer 14 may range from about 10 μm to about 20 μm. The thickness of the second dielectric layer 14 may be greater than that of the first dielectric layer 12.

[0085] The second dielectric layer 14 covers at least a portion of the first dielectric layer 12, the lower circuit layer 18, the first pillar bump 2, and the second pillar bump 3. The second dielectric layer 14 has a first surface 141 and a second surface 142 opposite to the first surface 141. The first surface 141 of the second dielectric layer 14 contacts the second surface 122 of the first dielectric layer 12; therefore, the first surface 141 of the second dielectric layer 14 or the second surface 122 of the first dielectric layer 12 forms the boundary between the second dielectric layer 14 and the first dielectric layer 12. Figure 1As shown, the boundary between the second dielectric layer 14 and the first dielectric layer 12 (e.g., the first surface 141 of the second dielectric layer 14 or the second surface 122 of the first dielectric layer 12) is lower than the top surface 221 of the protrusion portion 22 of the first pillar protrusion 2. Therefore, the second dielectric layer 14 covers the pillar portion 26 and the shoulder portion 24 of the first pillar protrusion 2, as well as the upper portion of the protrusion portion 22 of the first pillar protrusion 2.

[0086] The second surface 142 of the second dielectric layer 14 is substantially coplanar with the top surface 21 of the first pillar protrusion 2 and the top surface 31 of the second pillar protrusion 3. In some embodiments, the top surface 21 of the first pillar protrusion 2 and the top surface 31 of the second pillar protrusion 3 may be exposed from the second surface 142 of the second dielectric layer 14. The total height h of the first pillar protrusion 2 t It is approximately equal to the sum of the thickness of the first dielectric layer 12 and the thickness of the second dielectric layer 14. Furthermore, the thickness of the second dielectric layer 14 is approximately equal to the sum of the height of the second pillar protrusion 3 and the thickness of the lower circuit layer 18.

[0087] The upper circuit layer 16 (i.e., the first circuit layer) may be a redistribution layer (RDL) and disposed on the second surface 142 of the second dielectric layer 14. For example, the upper circuit layer 16 may include a first metal layer 161, a second metal layer 162, and a third metal layer 163 sequentially disposed on the second dielectric layer 14. The first metal layer 161 and the second metal layer 162 may be seed layers, comprising, for example, titanium and / or copper, another metal or alloy, and may be formed or disposed by sputtering. For example, the first metal layer 161 may comprise titanium, and the second metal layer 162 may comprise copper. The third metal layer 163 may comprise, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, such as Figure 1 As shown, the upper circuit layer 16 may include multiple conductive traces and / or multiple bonding pads. A portion of the upper circuit layer 16 may cover and contact the top surface 21 of the first pillar protrusion 2 and the top surface 31 of the second pillar protrusion 3. Therefore, a portion of the upper circuit layer 16 may cover and contact the pillar portion 36 of the second pillar protrusion 3, and the two ends of the second pillar protrusion 3 may respectively contact the lower circuit layer 18 and the upper circuit layer 16. The upper circuit layer 16 may be electrically connected to the lower circuit layer 18 via the second pillar protrusion 3. Furthermore, another portion of the upper circuit layer 16 may cover and contact the pillar portion 26 of the first pillar protrusion 2.

[0088] In one or more embodiments, the linewidth / spacing (L / S) of the upper circuit layer 16 may be equal to or less than about 3 μm / about 3 μm, equal to or less than about 2 μm / about 2 μm (e.g., about 1.8 μm / about 1.8 μm or less, about 1.6 μm / about 1.6 μm or less, or about 1.4 μm / about 1.4 μm or less), equal to or less than about 1 μm / about 1 μm, or equal to or less than about 0.5 μm / about 0.5 μm. In one or more embodiments, the linewidth / spacing (L / S) of the lower circuit layer 18 is greater than the linewidth / spacing (L / S) of the upper circuit layer 16.

[0089] exist Figure 1 In the electronic device 1, the first pillar bump 2 and the second pillar bump 3 are used for vertical electrical connection. The first pillar bump 2 and the second pillar bump 3 can be formed by a wire bonding process instead of photolithography or laser drilling and plating processes. Therefore, fewer processes in the electronic device 1 will reduce the risk of failure. In addition, fewer processes will reduce the manufacturing cost of the electronic device 1. Furthermore, because the first dielectric layer 12 can be formed or placed after the formation of the first pillar bump 2, the bonding strength between the first pillar bump 2 and the first dielectric layer 12 is relatively high. When warping of the electronic device 1 occurs, the first pillar bump 2 will not easily peel off from the first dielectric layer 12. Similarly, the bonding strength between the second pillar bump 3 and the second dielectric layer 14 is also relatively high, and the second pillar bump 3 will not easily peel off from the second dielectric layer 14.

[0090] Furthermore, because the first pillar bump 2 and the second pillar bump 3 are formed by wire bonding rather than plating, no recessed or protruding shapes will be formed at the top of the first pillar bump 2 and the second pillar bump 3. In other words, the second surface 142 of the second dielectric layer 14 can be substantially coplanar with the top surface 21 of the first pillar bump 2 and the top surface 31 of the second pillar bump 3. Therefore, the upper circuit layer 16 can be properly positioned on or above the first pillar bump 2 and the second pillar bump 3. In addition, because the first pillar bump 2 is integrally formed (i.e., a monolithic structure), the first pillar bump 2 may not easily crack when a normal force is applied to it. That is, the first pillar bump 2 has a relatively high ability to resist normal forces and shear forces. Furthermore, the aspect ratio (A / R) of the first pillar bump 2 and the second pillar bump 3 can be relatively high, for example, greater than 10:1 or greater, greater than 20:1 or greater, or greater than 50:1 or greater.

[0091] Figure 3 A cross-sectional view of an electronic device 1a according to some embodiments of the present disclosure is shown. The electronic device 1a is similar to... Figure 1 and Figure 2The electronic device 1 shown in the image, except for the structure of the first pillar protrusion 2a and the second pillar protrusion 3a, does not include the first pillar protrusion 2a of the electronic device 1a. Figure 1 and Figure 2 The first pillar protrusion 2a has a shoulder portion 24. Therefore, the first pillar protrusion 2a only includes a protrusion portion 22 and a pillar portion 26. The pillar portion 26 of the first pillar protrusion 2a is disposed on the top surface 221 of the protrusion portion 22. The maximum width W1 of the protrusion portion 22 of the first pillar protrusion 2a is greater than the maximum width W3 of the pillar portion 26 of the first pillar protrusion 2a. Furthermore, the second pillar protrusion 3a of the electronic device 1a does not contain... Figure 1 The shoulder portion 34 of the second pillar protrusion 3. Therefore, the second pillar protrusion 3a only includes the protrusion portion 32 and the pillar portion 36. The pillar portion 36 of the second pillar protrusion 3a is mounted on the protrusion portion 32.

[0092] Figure 4 This illustration shows a cross-sectional view of an electronic device 1b according to some embodiments of the present disclosure. The electronic device 1b is similar to... Figure 1 and Figure 2 The electronic device 1 shown in the figure further includes a metal layer 11 between a first dielectric layer 12 and a carrier 10a. The metal layer 11 may contain, for example, copper or another metal or a combination of metals. The carrier 10a may be a non-metallic material, such as a ceramic material, a glass material, a substrate, or a semiconductor wafer. A first pillar bump 2 and a second pillar bump 3 are formed or disposed on the metal layer 11.

[0093] Figure 5 This illustration shows a cross-sectional view of an electronic device 1c according to some embodiments of the present disclosure. The electronic device 1c is similar to... Figure 1 and Figure 2 The electronic device 1 shown in the image, except for the lower circuit layer 18 which contacts the protrusion portion 22 of the first pillar protrusion 2, is as follows: Figure 4 As shown, a portion of the lower circuit layer 18 extends along the sidewall of the upper portion of the protrusion portion 22 of the first pillar protrusion 2. Furthermore, [the following can be omitted] Figure 1 The second column protrusion 3.

[0094] Figure 6 A cross-sectional view of an electronic device 1d according to some embodiments of the present disclosure is illustrated. The electronic device 1d is similar to... Figure 5The electronic device 1c shown in the figure has a boundary between the second dielectric layer 14 and the first dielectric layer 12 (e.g., the first surface 141 of the second dielectric layer 14 or the second surface 122 of the first dielectric layer 12) that is higher than the top surface 221 of the protrusion portion 22 of the first pillar protrusion 2. Therefore, the first dielectric layer 12 covers the protrusion portion 22 of the first pillar protrusion 2, and the second dielectric layer 14 does not contact the protrusion portion 22 of the first pillar protrusion 2. The thickness of the second dielectric layer 14 may be less than the thickness of the first dielectric layer 12.

[0095] Figure 7 A cross-sectional view of an electronic device 1e according to some embodiments of the present disclosure is illustrated. The electronic device 1e is similar to... Figure 4 The electronic device 1b shown in the image has had its carrier 10a removed, and the metal layer 11 is patterned to form the bottom circuit layer 20. For example... Figure 7 As shown, the bottom surface of the first dielectric layer 12 (i.e., the first surface 121) is away from the second dielectric layer 14 and is substantially coplanar with the bottom surface 23 of the first pillar protrusion 2. Therefore, the bottom circuit layer 20 is disposed on the bottom surface (i.e., the first surface 121) of the first dielectric layer 12 and covers and contacts the bottom surface 23 of the protrusion portion 22 of the first pillar protrusion 2. The bottom circuit layer 20 is flat.

[0096] Figure 8 A cross-sectional view of an electronic device 1f according to some embodiments of the present disclosure is illustrated. The electronic device 1f is similar to... Figure 1 and Figure 2 The electronic device 1 shown further includes a third dielectric layer 35 and a third circuit layer 37. The third dielectric layer 35 is inserted between the first dielectric layer 12 and the second dielectric layer 14. The material of the third dielectric layer 35 may be the same as that of the first dielectric layer 12 or the second dielectric layer 14. The third dielectric layer 35 covers at least a portion of the first dielectric layer 12, the lower circuit layer 18, and the first pillar bumps 2a, 2b. The third circuit layer 37 may be a redistribution layer (RDL) and disposed on the third dielectric layer 35. For example, the third circuit layer 37 may include a first metal layer 371, a second metal layer 372, and a third metal layer 373 disposed sequentially on the first dielectric layer 12. The first metal layer 371 and the second metal layer 372 may be seed layers, comprising, for example, titanium and / or copper, another metal or alloy, and may be formed or disposed by sputtering. For example, the first metal layer 371 may comprise titanium, and the second metal layer 372 may comprise copper. The third metal layer 373 may comprise, for example, copper, or another metal or combination of metals, and may be formed or disposed by electroplating. In some embodiments, such as Figure 8As shown, the third circuit layer 37 may include multiple conductive traces and / or multiple bonding pads. The third circuit layer 37 shall not contact the first post bumps 2a, 2b. However, in some embodiments, the third circuit layer 37 may contact the first post bumps 2a, 2b. In one or more embodiments, the linewidth / spacing (L / S) of the third circuit layer 37 may be equal to or less than about 3 μm / about 3 μm, or equal to or less than about 2 μm / about 2 μm.

[0097] The second dielectric layer 14 covers at least a portion of the third dielectric layer 35, the third circuit layer 37, and the first pillar bumps 2a and 2b. The upper circuit layer 16 may be a redistribution layer (RDL) and is disposed on the second surface 142 of the second dielectric layer 14. A portion of the upper circuit layer 16 may cover and contact the top surfaces of the first pillar bumps 2a and 2b. Figure 8 As shown, the following can be omitted. Figure 1 The second pillar protrusion 3, and the shapes of the first pillar protrusions 2a and 2b are different. Figure 1 and Figure 2 The shape of the first pillar protrusion 2a. The first pillar protrusion 2a may include a protrusion portion 22a, a shoulder portion 24a, and a pillar portion 26a. The height of the pillar portion 26a of the first pillar protrusion 2a may be greater than the height of the pillar portion 26a of the first pillar protrusion 2a. The pillar portion 26a of the first pillar protrusion 2a extends through the third circuit layer 37. The first pillar protrusion 2b may include a protrusion portion 22b, a shoulder portion 24b, and a pillar portion 26b. The height of the protrusion portion 22b of the first pillar protrusion 2b may be greater than the height of the protrusion portion 22b of the first pillar protrusion 2a. Therefore, the density of the third circuit layer 37 near the first pillar protrusion 2a is greater than the density of the third circuit layer 37 near the first pillar protrusion 2b. Furthermore, the height of the pillar portion 26a of the first pillar protrusion 2a may be different from the height of the pillar portion 26b of the first pillar protrusion 2b. In some embodiments, the height of the pillar portion 26a of the first pillar protrusion 2a may be greater than the height of the pillar portion 26b of the first pillar protrusion 2b.

[0098] Figure 9 This illustration shows a cross-sectional view of an electronic device 1g according to some embodiments of the present disclosure. The electronic device 1g is similar to... Figure 8The electronic device 1f shown further includes a fourth dielectric layer 38 and a fourth circuit layer 39. The fourth dielectric layer 38 is located between the third dielectric layer 35 and the second dielectric layer 14. The fourth circuit layer 39 is disposed on the fourth dielectric layer 38. In one or more embodiments, the linewidth / spacing (L / S) of the fourth circuit layer 39 may be equal to or less than about 3 μm / about 3 μm, or equal to or less than about 2 μm / about 2 μm. The second dielectric layer 14 covers at least a portion of the fourth dielectric layer 38, the fourth circuit layer 39, and the first pillar bumps 2a, 2b. An upper circuit layer 16 is disposed on the second surface 142 of the second dielectric layer 14. A portion of the upper circuit layer 16 may cover and contact the top surfaces of the first pillar bumps 2a, 2b. Figure 9 As shown, the electronic device 1g may include a plurality of second pillar protrusions 3a and 3b. The second pillar protrusion 3a may be disposed in the first dielectric layer 12 and the third dielectric layer 32, and may contact the third circuit layer 37. The second pillar protrusion 3b may be disposed in the second dielectric layer 14 and the fourth dielectric layer 38, and may be electrically connected to the third circuit layer 37 and the upper circuit layer 16.

[0099] Figure 10 A cross-sectional view of an electronic device 1h according to some embodiments of the present disclosure is shown. Figure 11 illustrate Figure 10 The enlarged view of area "B" shown in the image. The electronic device 1h is similar to... Figure 1 and Figure 2 The electronic device 1 shown includes a plurality of first pillar bumps 2, and a first dielectric layer 12 defines a first recess 124 between two adjacent first pillar bumps 2. A portion of the conductive trace 184 of the lower circuit layer 18 can be disposed in the first recess 124 and contact the two adjacent first pillar bumps 2. See also Figure 11 Thickness "T1" is defined as the distance between the lowest point of the first notch portion 124 and the first surface 121 of the first dielectric layer 12. That is, thickness T1 is the thinnest portion of the first dielectric layer 12. Furthermore, thickness "T2" is defined as the distance between the highest point of the first notch portion 124 and the first surface 121 of the first dielectric layer 12. In some embodiments, the highest point of the first notch portion 124 may contact the sidewall of the protrusion portion 22 of the first pillar protrusion 2. Therefore, thickness T2 may be equal to or less than the average thickness of the first dielectric layer 12. Furthermore, gap "g" is defined as the gap between two adjacent first pillar protrusions 2. Figure 11As shown, the electronic device 1h satisfies the predetermined design rule g > 0.2 * h1, meaning that the gap g between two adjacent first pillar protrusions 2 is greater than 0.2 times the height h1 of the protrusion portion 22 of the first pillar protrusion 2. Therefore, due to process capability and material properties, 0.04 * h1 <T1

[0100] Figure 12 An enlarged view illustrating a cross-sectional view of an electronic device according to some embodiments of the present disclosure. Figure 13 illustrate Figure 12 A top view. Figure 12 and Figure 13 In the embodiment described herein, the upper circuit layer 16 and the second dielectric layer 14 are omitted for clarity. The first dielectric layer 12 defines a first recessed portion 124a between two adjacent first pillar bumps 2, and the gap g1 between the two adjacent first pillar bumps 2 is less than 0.2 times the height h1 of the bump portion 22 of the first pillar bump 2. That is, g1 < 0.2 * h1. Therefore, due to process capability and material properties, T1 < 0.004 * h1. Because the thickness T1 is so small (i.e., very close to zero), a portion of the conductive trace 184 of the lower circuit layer 18 in the first recessed portion 124a may not contact the two adjacent first pillar bumps 2.

[0101] Figure 14 An enlarged top view illustrating an electronic device according to some embodiments of the present disclosure. Figure 15 Explanation along Figure 14 The cross-sectional view taken from line II. Figure 14 and Figure 15 The embodiments described herein are similar to Figure 12 and Figure 13 The embodiment described herein, apart from the orientation of the conductive traces in the lower circuit layer 18, is shown below. See also... Figure 14 ​The conductive traces 185 of the lower circuit layer 18 extend vertically and are positioned between two adjacent first pillar bumps 2. A portion of the conductive traces 185 of the lower circuit layer 18 may be positioned within the first recessed portion 124a of the first dielectric layer 12. The gap g1 between the two adjacent first pillar bumps 2 is less than 0.2 times the height h1 of the bump portion 22 of the first pillar bump 2. That is, g1 < 0.2 * h1. Therefore, due to process capability and material properties, T1 < 0.004 * h1. Because the thickness T1 is too small (i.e., very close to zero), a portion of the conductive traces 185 of the lower circuit layer 18 in the first recessed portion 124a may not contact other portions of the conductive traces 185 of the lower circuit layer 18 on the first dielectric layer 12. Therefore, the conductive traces 185 of the lower circuit layer 18 are discontinuous at the first recessed portion 124a, resulting in an open circuit.

[0102] Figure 16 An enlarged view illustrating a cross-sectional view of an electronic device according to some embodiments of the present disclosure. Figure 17 illustrate Figure 16 A top view. Figure 16 and Figure 17 In the embodiments described herein, the lower circuit layer 18 is omitted for clarity. The second dielectric layer 14 defines a second recess 144a corresponding to the first recess 124a of the first dielectric layer 12. A portion of the conductive trace 164 of the upper circuit layer 16 may be disposed in the second recess 144a of the second dielectric layer 14. Figure 16 As shown, the second notch portion 144a of the second dielectric layer 14 is conformally fitted to the first notch portion 124a of the first dielectric layer 12. Therefore, a portion of the conductive trace 164 of the upper circuit layer 16 in the second notch portion 144a of the second dielectric layer 14 may not contact other portions of the conductive trace 164 of the upper circuit layer 16 on the second dielectric layer 14. Consequently, the conductive trace 164 of the upper circuit layer 16 is discontinuous at the second notch portion 144a, resulting in an open circuit.

[0103] Figure 18 An enlarged top view illustrating an electronic device according to some embodiments of the present disclosure. Figure 19 Explanation along Figure 18 The cross-sectional view taken from line II-II. Figure 18 and Figure 19 The embodiments described herein are similar to Figure 16 and Figure 17 The embodiments described herein, apart from the orientation of the conductive traces in the upper circuit layer 16, are as follows. See also... Figure 18The conductive trace 165 of the upper circuit layer 16 extends vertically and is positioned between two adjacent first post protrusions 2. A portion of the conductive trace 165 of the upper circuit layer 16 may be positioned within a second recessed portion 144a of the second dielectric layer 14. This portion of the conductive trace 165 of the upper circuit layer 16 in the second recessed portion 144a may not contact other portions of the conductive trace 165 of the upper circuit layer 16 on the second dielectric layer 14. Therefore, the conductive trace 165 of the upper circuit layer 16 is discontinuous at the second recessed portion 144a, resulting in an open circuit.

[0104] Figure 20 A cross-sectional view illustrating an electronic device 4 according to some embodiments of the present disclosure. The electronic device 4 is similar to... Figures 1 to 2 The electronic device 1 shown in the image, in addition to Figure 20 The electronic device 4 further includes at least one electronic component 40 and an encapsulant 44. Therefore, Figure 20 The electronic device 4 can also be called a "semiconductor package".

[0105] Electronic component 40 is mounted on electronic device 1. For example... Figure 20 As shown, electronic component 40 is disposed adjacent to the second surface 142 of the second dielectric layer 14 and electrically connected to the upper circuit layer 16. For example, electronic component 40 may be a semiconductor die. Electronic component 40 has a first surface 401 (e.g., an active surface) and a second surface 402 (e.g., a back surface) opposite the first surface 401. Furthermore, electronic component 40 includes or is electrically connected to at least one conductive pillar 403 and at least one solder bump 42 sequentially disposed on the first surface 401 of electronic component 40. Solder bump 42 is electrically connected to bonding pads of the upper circuit layer 16. Thus, electronic component 40 is attached to electronic device 1 via flip-chip bonding.

[0106] Package 44, such as a molding compound, is disposed on the second surface 142 of the second dielectric layer 14 and covers the electronic component 40, conductive pillars 403, solder bumps 42, and upper circuit layer 16. Package 44 has a first surface 441 and a second surface 442 opposite to the first surface 441. The second surface 442 of package 44 may be substantially coplanar with the second surface 402 of electronic component 40. Therefore, the second surface 402 of electronic component 40 may be exposed from the second surface 442 of package 44.

[0107] Figure 21 A cross-sectional view of an electronic device 4a according to some embodiments of the present disclosure is shown. The electronic device 4a is similar to... Figure 20The electronic device 4 shown in the image has the same structure as electronic device 1i. For example... Figure 21 As shown, remove carrier 10 ( Figure 20 The bottom surface 23 of the bump portion 22 of the first pillar bump 2 is recessed from the first surface 121 (i.e., the bottom surface) of the first dielectric layer 12. Furthermore, a seed layer 46 is formed or disposed on the bottom surface 23 of the bump portion 22 of the first pillar bump 2, and an external connector 48 is formed or disposed on the seed layer 46. For example, the seed layer 46 may include a first metal layer 461 and a second metal layer 462 sequentially disposed on the bump portion 22 of the first pillar bump 2. For example, the first metal layer 461 may contain titanium, and the second metal layer 462 may contain copper, and may be formed or disposed by sputtering. The material of the external connector 48 may be a conductive metal, such as tin and / or silver, or another metal or a combination of metals.

[0108] Figure 22 This illustration shows a cross-sectional view of an electronic device 4b according to some embodiments of the present disclosure. The electronic device 4b is similar to... Figure 21 The electronic device 4a shown in the image has the same structure as electronic device 1j. (As shown in the image) Figure 22 As shown, it further includes a third dielectric layer 35, a third circuit layer 37, a fourth dielectric layer 38, and a fourth circuit layer 39. It should be noted that... Figure 22 The third dielectric layer 35, the third circuit layer 37, the fourth dielectric layer 38, and the fourth circuit layer 39 can be connected with Figure 8 and Figure 9 The third dielectric layer 35, the third circuit layer 37, the fourth dielectric layer 38, and the fourth circuit layer 39 are identical. Furthermore, the seed layer 46 and the external connector 48 are further formed or disposed on the recessed bottom surface of the second pillar protrusion 3a.

[0109] Figure 23 A cross-sectional view of an electronic device 4c according to some embodiments of the present disclosure is illustrated. The electronic device 4c is similar to... Figure 21 The electronic device 4a shown in the figure omits the seed layer 46, and the external connector 48 is directly formed or placed on the bottom surface 23 of the protrusion portion 22 of the first pillar protrusion 2.

[0110] Figure 24 This illustration shows a cross-sectional view of an electronic device 4d according to some embodiments of the present disclosure. The electronic device 4d is similar to... Figure 21 The electronic device 4a shown in the image has an external connector 48 that is shaped like a cubic column rather than a sphere.

[0111] Figure 25 A cross-sectional view of an electronic device 4e according to some embodiments of the present disclosure is illustrated. The electronic device 4e is similar to... Figure 21The electronic device 4a shown in the image has the same structure as the electronic device 1k. (For example...) Figure 25 As shown, electronic device 1k is formed by two stacked electronic devices 1i.

[0112] Figure 26 A cross-sectional view of an electronic device 4f according to some embodiments of the present disclosure is illustrated. The electronic device 4f is similar to... Figure 21 The electronic device 4a shown in the figure is further included between the electronic component 40 and the second dielectric layer 14, except that the underfill 50 is also included and covers the first surface 401, conductive pillars 403 and solder bumps 42 of the electronic component 40.

[0113] Figure 27 This illustration shows a cross-sectional view of an electronic device 4g according to some embodiments of the present disclosure. The electronic device 4g is similar to... Figure 21 The electronic device 4a shown in the figure is attached to the electronic device 1i by means of electronic component 40 via wire bonding. That is, the second surface 402 of electronic component 40 is bonded to the second surface 402 of the second dielectric layer 14, and the first surface 401 of electronic component 40 is electrically connected to the upper circuit layer 16 via bonding wire 52.

[0114] Figure 28 This illustration shows a cross-sectional view of an electronic device 4h according to some embodiments of the present disclosure. The electronic device 4h is similar to... Figure 21 The electronic device 4a shown in the image has the same structure as the electronic device 1m. Figure 28 In the electronic device 1m, Figure 21 The first dielectric layer 12 is removed, exposing the lower circuit layer 18.

[0115] Figure 29 A cross-sectional view of an electronic device 4i according to some embodiments of the present disclosure is illustrated. The electronic device 4i is similar to... Figure 28 The electronic device 4h shown in the figure has at least one external connector 48b formed or disposed on the bonding pad of the lower circuit layer 18.

[0116] Figure 30 This illustration shows a cross-sectional view of an electronic device 4j according to some embodiments of the present disclosure. The electronic device 4j is similar to... Figure 21 The electronic device 4a shown in the image has the same structure as the electronic device 1n. Figure 30 In the electronic device 1n, at least one second post bump 3c is disposed in the first dielectric layer 12 to contact the lower circuit layer 18, and at least one external connector 48c is attached to and electrically connected to the second post bump 3c. Therefore, the lower circuit layer 18 is electrically connected to the second post bump 3c via the external connector 48c.

[0117] Figures 31 to 56This invention describes methods for manufacturing electronic devices according to some embodiments of the present disclosure. In some embodiments, the methods are used to manufacture, for example... Figure 21 Electronic devices such as electronic device 4a are displayed in the exhibition.

[0118] See Figure 31 A carrier 10 is provided. The carrier 10 may be, for example, a metallic material, a ceramic material, a glass material, a substrate, or a semiconductor wafer. The shape of the carrier 10 may be, for example, rectangular or square. Alternatively, the shape of the carrier 10 may be, for example, circular or elliptical. Figure 1 In the embodiments described herein, the carrier 10 is a metallic material. The thickness of the carrier 10 may be in the range of about 100 μm to about 500 μm, about 200 μm to about 800 μm, or about 500 μm to about 1500 μm.

[0119] Subsequently, at least one first column protrusion 2 may be formed or disposed on the carrier 10. Figure 31 In the embodiments described herein, the first post protrusion 2 may be formed or disposed via a wire bonding process. The bonding wire 54 used in the wire bonding process has a diameter D. The first post protrusion 2 may include a protrusion portion 22, a shoulder portion 24, a post portion 26, and a tip portion 27. The protrusion portion 22, the shoulder portion 24, and the post portion 26 are connected with… Figure 1 and Figure 2 The protrusion portion 22, shoulder portion 24, and pillar portion 26 described herein are identical. In some embodiments, the maximum width W3 of the pillar portion 26 of the first pillar protrusion 2 is... Figure 2 It can be roughly equal to the diameter D of the joint line 54. The height h1 of the protrusion portion 22 of the first column protrusion 2 ( Figure 2 The total height h of the first post protrusion 2 can be approximately 1.2 to 3 times the diameter D of the bonding line 54. t ( Figure 2 The diameter of the bonding line 54 can be approximately 2 to 3 times that of the diameter D. For example, the diameter D of the bonding line 54 can range from approximately 0.8 mils (thousandths of an inch) to approximately 2 mils, i.e., from approximately 20 μm to approximately 50.8 μm, and the total height h of the first post protrusion 2 is... t It can be found in the range of approximately 25 μm to approximately 120 μm.

[0120] A protrusion portion 22 is formed or disposed on the carrier 10, and a pillar portion 26 is disposed on or above the protrusion portion 22. A shoulder portion 24 is located between the pillar portion 26 and the protrusion portion 22. A tip portion 27 is disposed on or protrudes from the pillar portion 26. In some embodiments, the protrusion portion 22, the shoulder portion 24, the pillar portion 26, and the tip portion 27 are integrally and simultaneously formed; therefore, the first pillar protrusion 2 is a monolithic structure, there is no boundary between the protrusion portion 22 and the shoulder portion 24, no boundary between the shoulder portion 24 and the pillar portion 26, and no boundary between the pillar portion 26 and the tip portion 27.

[0121] See Figure 32 A first dielectric layer 12 is formed, for example, by coating or lamination, to cover at least a portion of the bump portion 22 of the carrier 10 and the first pillar bump 2. The first dielectric layer 12 has a first surface 121 and a second surface 122 opposite to the first surface 121. The first surface 121 of the first dielectric layer 12 contacts the carrier 10, and the second surface 122 of the first dielectric layer 12 is lower than the top surface 221 of the bump portion 22. Because the first dielectric layer 12 can be formed after the formation of the first pillar bump 2, the surface conditions (e.g., surface roughness) of the boundary between the first dielectric layer 12 and the bump portion 22 of the first pillar bump 2 are determined by the surface conditions (e.g., surface roughness) of the sidewalls of the bump portion 22 of the first pillar bump 2. Therefore, the surface conditions (e.g., surface roughness) of the boundary between the first dielectric layer 12 and the bump portion 22 of the first pillar bump 2 can be smoother than the surface conditions (e.g., surface roughness) of the sidewalls of the through-hole of the dielectric layer of a corresponding semiconductor substrate. Next, the first dielectric layer 12 is cured.

[0122] See Figures 33 to 38 ,form Figure 1 The lower circuit layer 18. See also Figure 33 A first metal layer 181 is formed or disposed on the second surface 122 of the first dielectric layer 12 to cover the exposed portions of the first dielectric layer 12 and the first post bump 2, and a second metal layer 182 is formed or disposed on the first metal layer 181. The first metal layer 181 and the second metal layer 182 may be seed layers, comprising, for example, titanium and / or copper, another metal or alloy, and may be formed or disposed by sputtering. For example, the first metal layer 181 may comprise titanium, and the second metal layer 182 may comprise copper.

[0123] See Figure 34 The photoresist layer 56 is formed on the second metal layer 182 by, for example, coating or lamination.

[0124] See Figure 35Multiple openings 561 are formed in the photoresist layer 56 by, for example, a photolithography process (e.g., including exposure and development) to expose portions of the second metal layer 182. It should be noted that the positions of the openings 561 do not correspond to the positions of the first pillar bumps 2.

[0125] See Figure 36 The third metal layer 183 may be formed, for example, by electroplating or disposed on the second metal layer 182 in the opening 561 of the photoresist layer 56.

[0126] See Figure 37 For example, the photoresist layer 56 can be removed by stripping.

[0127] See Figure 38 The portions of the first metal layer 181 and the second metal layer 182 not covered by the third metal layer 183 are removed, for example, by etching. Simultaneously, a lower circuit layer 18 is formed. Therefore, the lower circuit layer 18 may include the first metal layer 181, the second metal layer 182, and the third metal layer 183. The lower circuit layer 18 may not contact the bump portion 22 of the first pillar bump 2.

[0128] See Figures 39 to 40 ,form Figure 5 The lower circuit layer 18. See also Figure 39 (that is) Figure 34 (Subsequently), multiple openings 561a are formed in the photoresist layer 56 by, for example, a photolithography process (e.g., including exposure and development) to expose portions of the second metal layer 182. It should be noted that the positions of the openings 561a correspond to the positions of the first pillar bumps 2. Figure 39 As shown, the opening 561a of the photoresist layer 56 can extend to a position above the protrusion portion 22 of the first pillar protrusion 2. Subsequently, a third metal layer 183 can be formed, for example, by electroplating, or disposed on the second metal layer 182 in the opening 561a of the photoresist layer 56.

[0129] See Figure 40 For example, the photoresist layer 56 is removed by stripping. Subsequently, portions of the first metal layer 181 and the second metal layer 182 not covered by the third metal layer 183 are removed by etching, for example. Simultaneously, a lower circuit layer 18 is formed. The lower circuit layer 18 can contact the bump portion 22 of the first pillar bump 2.

[0130] See Figure 41 At least one second pillar protrusion 3 may be formed or disposed on the bonding pad of the lower circuit layer 18. Figure 41In the embodiments described herein, the shape of the second pillar protrusion 3 is similar to that of the first pillar protrusion 2, and the height of the second pillar protrusion 3 is less than the height of the first pillar protrusion 2. That is, the second pillar protrusion 3 can be considered as a compressed first pillar protrusion 2. The second pillar protrusion 3 can be formed or disposed through a wire bonding process. The second pillar protrusion 3 may include a protrusion portion 32, a shoulder portion 34, a pillar portion 36, and a tip portion 37. The protrusion portion 32 is formed or disposed on a bonding pad of the lower circuit layer 18, and the pillar portion 36 is disposed on or above the protrusion portion 32. The shoulder portion 34 is located between the pillar portion 36 and the protrusion portion 32. The tip portion 37 is disposed on or protrudes from the pillar portion 36. In some embodiments, the protrusion portion 32, the shoulder portion 34, the pillar portion 36, and the tip portion 37 are integrally and simultaneously formed. Therefore, the second pillar protrusion 3 is a single-piece structure, with no boundary between the protrusion portion 32 and the shoulder portion 34, no boundary between the shoulder portion 34 and the pillar portion 36, and no boundary between the pillar portion 36 and the tip portion 37.

[0131] In some embodiments, the maximum width of the post portion 36 of the second post protrusion 3 may be substantially equal to the diameter D of the bonding wire 54 used in the wire bonding process. The height of the protrusion portion 32 of the second post protrusion 3 may be approximately 1.2 to 3 times the diameter D of the bonding wire 54, and the total height of the second post protrusion 3 may be approximately 2 to 3 times the diameter D of the bonding wire 54. For example, the diameter D of the bonding wire 54 may range from approximately 0.8 mils (thousandths of an inch) to approximately 2 mils, i.e., approximately 20 μm to approximately 50.8 μm, and the total height of the second post protrusion 3 may range from approximately 25 μm to approximately 120 μm.

[0132] See Figure 42 The second dielectric layer 14 can be formed or disposed on the first dielectric layer 12 by, for example, coating or laminating, to cover the first dielectric layer 12, the lower circuit layer 18, at least a portion of the pillar portion 26 of the first pillar bump 2, and the second pillar bump 3. The second dielectric layer 14 has a first surface 141 and a second surface 142 opposite to the first surface 141. The first surface 141 of the second dielectric layer 14 contacts the second surface 122 of the first dielectric layer 12; therefore, the first surface 141 of the second dielectric layer 14 or the second surface 122 of the first dielectric layer 12 is the boundary between the second dielectric layer 14 and the first dielectric layer 12. Figure 42As shown, the boundary between the second dielectric layer 14 and the first dielectric layer 12 (e.g., the first surface 141 of the second dielectric layer 14 or the second surface 122 of the first dielectric layer 12) is lower than the top surface 221 of the protrusion portion 22 of the first pillar protrusion 2. Therefore, the second dielectric layer 14 covers the pillar portion 26 and shoulder portion 24 of the first pillar protrusion 2, as well as the upper portion of the protrusion portion 22 of the first pillar protrusion 2. Furthermore, the tip portion 27 of the first pillar protrusion 2 and the tip portion 37 of the second pillar protrusion 3 can protrude from the second surface 142 of the second dielectric layer 14. Subsequently, the second dielectric layer 14 is cured.

[0133] See Figure 43 The compression head 58 is applied to the second surface 142 of the second dielectric layer 14 to compress and expel the tip portion 27 of the first pillar protrusion 2 and the tip portion 37 of the second pillar protrusion 3. That is, the tip portion 27 of the first pillar protrusion 2 is compressed into the pillar portion 26 to form a flat top surface 21. Figure 44 ), and the tip portion 37 of the second column protrusion 3 is compressed into the column portion 36 to form a flat top surface 31. Figure 44 Therefore, the second surface 142 of the second dielectric layer 14 is substantially coplanar with the top surface 21 of the first pillar protrusion 2 and the top surface 31 of the second pillar protrusion 3. In some embodiments, the tip portion 27 of the first pillar protrusion 2 and the tip portion 37 of the second pillar protrusion 3 can be removed by grinding.

[0134] See Figure 44 A first metal layer 161 and a second metal layer 162 are sequentially formed or disposed on the second dielectric layer 14. The first metal layer 161 and the second metal layer 162 may be seed layers, comprising, for example, titanium and / or copper, another metal or alloy, and may be formed or disposed by sputtering. For example, the first metal layer 161 may comprise titanium, and the second metal layer 162 may comprise copper. In some embodiments, such as... Figure 44 As shown, a portion of the first metal layer 161 may cover and contact the top surface 21 of the first pillar protrusion 2 and the top surface 31 of the second pillar protrusion 3. In one or more embodiments, the linewidth / spacing (L / S) of the lower circuit layer 18 is greater than that of the upper circuit layer 16.

[0135] See Figure 45 The photoresist layer 60 is formed on the second metal layer 162 by, for example, coating or lamination.

[0136] See Figure 46Multiple openings 601 are formed in the photoresist layer 60 by, for example, a photolithography process (e.g., including exposure and development) to expose portions of the second metal layer 162. Subsequently, a third metal layer 163 may be formed or disposed on the second metal layer 162 in the openings 601 of the photoresist layer 60 by, for example, electroplating.

[0137] See Figure 47 The photoresist layer 60 is removed, for example, by stripping. Subsequently, portions of the first metal layer 161 and the second metal layer 162 not covered by the third metal layer 163 are removed, for example, by etching. Simultaneously, an upper circuit layer 16 is formed. Therefore, the upper circuit layer 16 may include the first metal layer 161, the second metal layer 162, and the third metal layer 163. Thus, a portion of the upper circuit layer 16 may cover and contact the pillar portion 36 of the second pillar bump 3, and the two ends of the second pillar bump 3 may respectively contact the lower circuit layer 18 and the upper circuit layer 16. The upper circuit layer 16 may be electrically connected to the lower circuit layer 18 via the second pillar bump 3. Furthermore, another portion of the upper circuit layer 16 may cover and contact the pillar portion 26 of the first pillar bump 2. It should also be noted that at this stage, the obtained... Figure 1 and Figure 2 Electronic device 1.

[0138] See Figure 48 At least one electronic component 40 is disposed on the electronic device 1. In some embodiments, the electronic component 40 is disposed adjacent to a second surface 142 of the second dielectric layer 14 and electrically connected to an upper circuit layer 16. For example, the electronic component 40 may be a semiconductor die. The electronic component 40 has a first surface 401 (e.g., an active surface) and a second surface 402 (e.g., a back surface) opposite the first surface 401. Furthermore, the electronic component 40 includes or is electrically connected to at least one conductive post 403 and at least one solder bump 42 sequentially disposed on the first surface 401 of the electronic component 40. The solder bump 42 is electrically connected to a bonding pad of the upper circuit layer 16. Thus, the electronic component 40 is attached to the electronic device 1 by flip-chip bonding.

[0139] Subsequently, a package 44, such as a molding compound, is formed or disposed on the second surface 142 of the second dielectric layer 14 and covers the electronic component 40, conductive pillars 403, solder bumps 42, and upper circuit layer 16. The package 44 has a first surface 441 and a second surface 442 opposite to the first surface 441. The second surface 442 of the package 44 may be substantially coplanar with the second surface 402 of the electronic component 40. Therefore, the second surface 402 of the electronic component 40 may be exposed from the second surface 442 of the package 44. It should be noted that at this stage, [the package 44] is obtained... Figure 20 4. Electronic devices.

[0140] See Figure 49 The shape of the electronic device 1 (including the carrier 10) can be generally rectangular or square.

[0141] See Figure 50 The shape of the electronic device 1 (including the carrier 10) can be generally circular or elliptical.

[0142] See Figure 51 The carrier 10 is removed by, for example, peeling or coarse etching. Subsequently, the bottom surface 23 of the bump portion 22 of the first pillar bump 2 is chemically fine-etched. Therefore, the bottom surface 23 of the bump portion 22 of the first pillar bump 2 is recessed from the first surface 121 of the first dielectric layer 12. In some embodiments, the carrier 10 is thinned and patterned to form the bottom circuit layer 20. Figure 7 In order to obtain Figure 7 Electronic device 1e.

[0143] See Figure 52 A seed layer 46 is formed or disposed on the bottom surface 23 of the bump portion 22 of the first pillar bump 2 and the first surface 121 of the first dielectric layer 12. For example, the seed layer 46 may include a first metal layer 461 and a second metal layer 462 sequentially disposed on the bump portion 22 of the first pillar bump 2. For example, the first metal layer 461 may contain titanium, and the second metal layer 462 may contain copper, and may be formed or disposed by sputtering.

[0144] See Figure 53 The photoresist layer 62 is formed on the second metal layer 462 of the seed layer 46 by, for example, coating or lamination.

[0145] See Figure 54 Multiple openings 621 are formed in the photoresist layer 62 by, for example, a photolithography process (e.g., including exposure and development) to expose portions of the second metal layer 462. Subsequently, solder material 64 may be formed or disposed on the second metal layer 462 in the openings 621 of the photoresist layer 62 by, for example, electroplating. The solder material 64 may be a conductive metal, such as tin and / or silver, or another metal or a combination of metals.

[0146] See Figure 55 The photoresist layer 62 is removed, for example, by stripping. Subsequently, portions of the first metal layer 461 and the second metal layer 462 not covered by the solder material 64 are removed, for example, by etching. Simultaneously, a patterned seed layer 46 is formed.

[0147] See Figure 56The reflow process transforms the solder material 64 into a generally spherical external connector 48. Simultaneously, it yields... Figure 21 Electronic device 4a. In addition, a singulation process can be performed to form multiple electronic devices or semiconductor packages.

[0148] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangements.

[0149] As used herein, the terms “approximately,” “generally,” “quite considerably,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation definitively occurs or is very close to occurring. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same or equal.

[0150] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered to be coplanar or substantially coplanar.

[0151] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0152] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to carry electric current. Conductive materials are generally those that exhibit little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10⁴ S / m (e.g., at least 10⁵ S / m or at least 10⁶ S / m). The conductivity of a material may sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0153] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0154] While the invention has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Artistic representations in this disclosure may differ from actual devices due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. An electronic device comprising: First dielectric layer; A second dielectric layer is disposed on the first dielectric layer; as well as At least one first pillar bump is disposed in the first dielectric layer and the second dielectric layer, and includes a bump portion and a pillar portion disposed on the bump portion, wherein the pillar portion of the first pillar bump is conical and the bump portion of the first pillar bump is disc-shaped, wherein the top surface of the bump portion is parallel to the top surface of the first dielectric layer. The upper circuit layer is disposed on the second dielectric layer and contacts the pillar portion; as well as A lower circuit layer is disposed on the first dielectric layer, wherein the line width and line spacing of the lower circuit layer are greater than the line width and line spacing of the upper circuit layer.

2. The electronic device according to claim 1, wherein the volume of the protrusion portion of the first pillar protrusion is greater than the volume of the pillar portion of the first pillar protrusion.

3. The electronic device of claim 1, wherein the first pillar protrusion further includes a shoulder portion located between the pillar portion and the protrusion portion of the first pillar protrusion, the maximum width of the protrusion portion of the first pillar protrusion being greater than the maximum width of the shoulder portion of the first pillar protrusion, and the maximum width of the shoulder portion of the first pillar protrusion being greater than the maximum width of the pillar portion of the first pillar protrusion, wherein the top surface of the protrusion portion is parallel to the top surface of the shoulder portion.

4. The electronic device according to claim 1, wherein the maximum width of the protrusion portion of the first pillar protrusion is greater than the maximum width of the pillar portion of the first pillar protrusion.

5. The electronic device according to claim 1, wherein the pillar portion of the first pillar protrusion and the protrusion portion of the first pillar protrusion are integrally formed.

6. The electronic device according to claim 1, wherein the sidewall of the protrusion portion of the first pillar protrusion is convex.

7. The electronic device of claim 1, wherein the boundary between the first dielectric layer and the second dielectric layer is lower than the top surface of the protrusion portion of the first pillar protrusion.

8. The electronic device of claim 1, wherein the boundary between the first dielectric layer and the second dielectric layer is higher than the top surface of the protrusion portion of the first pillar protrusion.

9. The electronic device of claim 1, further comprising a semiconductor die electrically connected to the upper circuit layer.

10. The electronic device of claim 1, wherein the lower circuit layer contacts the bump portion of the first pillar bump.

11. The electronic device of claim 1, wherein the at least one first pillar bump comprises at least two first pillar bumps, each of the bump portions of the two first pillar bumps having a height, and the heights of the bump portions of the two first pillar bumps being different.

12. The electronic device of claim 1, wherein the material of the first dielectric layer is the same as the material of the second dielectric layer.

13. The electronic device of claim 1, further comprising a bottom circuit layer disposed on a bottom surface of the first dielectric layer away from the second dielectric layer, wherein the bottom circuit layer contacts the bump portion of the first pillar bump.

14. The electronic device of claim 1, wherein the bottom surface of the bump portion of the first pillar bump is recessed from the bottom surface of the first dielectric layer.

15. The electronic device of claim 1, further comprising at least one second pillar protrusion, wherein two ends of the second pillar protrusion respectively contact the lower circuit layer and the upper circuit layer.

Images