Semiconductor Devices

Abstract

A semiconductor device comprises: a first unit to a fourth unit sequentially arranged on a substrate; a first diffusion interrupt structure to a third diffusion interrupt structure; a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first diffusion interrupt structure to the third diffusion interrupt structure; a second fin structure configured to protrude from the substrate and spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first diffusion interrupt structure to the third diffusion interrupt structure; a first gate electrode to a fourth gate electrode, respectively arranged in the first unit to the fourth unit, and the number of fins in each of the first unit, the second unit and the fourth unit is two.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2018-0056538 filed in the Korean Intellectual Property Office on May 17, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to semiconductor devices. Background Art

[0003] Semiconductor devices include integrated circuits (ICs) including metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices are gradually reduced, MOSFETs are shrinking in size more and more rapidly. The reduction in the size of MOSFETs may lead to short channel effects, thereby reducing the operating characteristics of semiconductor devices. Therefore, various methods have been studied to form semiconductor devices with better performance by overcoming the limitations caused by the increase in the integration density of semiconductor devices.

[0004] In addition, ICs are designed to achieve high operational reliability and low power consumption. Therefore, methods of forming devices with higher reliability and lower power consumption in smaller spaces are also being studied. Summary of the invention

[0005] Aspects of the present disclosure provide a semiconductor device having improved operating performance.

[0006] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: first to fourth units, which are sequentially arranged on a substrate in a first direction; first to third diffusion interrupt structures, which are configured to separate the first to fourth units from each other, the first diffusion interrupt structure is inserted between the first unit and the second unit, the second diffusion interrupt structure is inserted between the second unit and the third unit, and the third diffusion interrupt structure is inserted between the third unit and the fourth unit; a first fin structure, which is configured to protrude from the substrate and extend in the first direction, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion interrupt structures; a second fin structure, which is configured to extend from the substrate in the first direction; The substrate protrudes, is spaced apart from the first fin structure in a second direction intersecting the first direction and extends in the first direction, the second fin structure includes fifth to eighth fins separated from each other by the first diffusion interrupt structure to the third diffusion interrupt structure; and first to fourth gate electrodes are configured to extend in the second direction on the first fin structure and the second fin structure, the first to fourth gate electrodes are respectively arranged in the first unit to the fourth unit, wherein each of the first to fourth gate electrodes intersects with the first fin structure at the n-region of the substrate and intersects with the second fin structure at the p-region of the substrate, and the number of fins in each of the first unit, the second unit and the fourth unit is two.

[0007] According to another aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a substrate including an n-region and a p-region; a first fin disposed on the substrate in the n-region and extending in a first direction; a second fin disposed on the substrate in the p-region and extending in the first direction, the second fin being spaced apart from the first fin in a second direction intersecting the first direction; a gate electrode configured to extend in the second direction on the first fin and the second fin; a field insulating film configured to contact a side surface of the first fin in the first direction; a first dummy gate electrode formed on the n-region and formed on a top surface of the field insulating film and a top surface of the first fin, the first dummy gate electrode being configured to extend in the second direction; and a single diffusion interrupter film formed on the p-region and aligned with the first dummy gate electrode in the second direction, the single diffusion interrupter film being in contact with a side surface of the second fin in the first direction.

[0008] According to another aspect of the present invention, there is provided a semiconductor device, comprising: a substrate; a first power rail and a second power rail configured to extend in a first direction on the substrate, the first power rail and the second power rail being spaced apart from each other in a second direction intersecting the first direction; a first fin configured to protrude from the substrate and extend in the first direction; a second fin configured to protrude from the substrate and extend in the first direction, the second fin being spaced apart from the first fin in the second direction; a first diffusion interrupt structure and a second diffusion interrupt structure configured to define both ends of the first fin and the second fin; and a gate electrode configured to extend on the first fin and the second fin in the second direction, wherein the first fin is a fin closest to the first power rail in the second direction, the second fin is a fin closest to the second power rail in the second direction, and the first fin and the second fin have no fin between them in the second direction.

[0009] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0012] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0013] Figure 3 is along Figure 1 A cross-sectional view taken along line BB';

[0014] Figure 4a is along Figure 1 A cross-sectional view taken along line CC';

[0015] Figure 4b is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0016] Figure 5a is along Figure 1 A cross-sectional view taken along line D-D';

[0017] Figure 5b is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0018] Figure 6 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0019] Figure 7 is along Figure 6 A cross-sectional view taken along line BB';

[0020] Figure 8 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0021] Fig. 9 is along Figure 8 A cross-sectional view taken along line BB';

[0022] Fig.10 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0023] Fig.11 is along Fig.10 A cross-sectional view taken along line BB';

[0024] Fig.12 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0025] Fig.13 is along Fig.12 A cross-sectional view taken along line BB';

[0026] Fig.14 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0027] Fig.15 is along Fig.14 A cross-sectional view taken along line EE';

[0028] Fig.16 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0029] Fig.17 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0030] Fig.18 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0031] Fig.19 is along Fig.18 A cross-sectional view taken along line AA';

[0032] Fig. 20 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0033] Fig.21 is along Fig. 20 A cross-sectional view taken along line AA';

[0034] Fig. 22 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0035] Fig.23 is along Fig. 22 A cross-sectional view taken along the lines F-F' and G-G';

[0036] Fig.24 is along Fig. 22 A cross-sectional view taken along line BB';

[0037] Fig.25 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0038] Fig.26 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0039] Fig. 27 is along Fig.26 A cross-sectional view taken along the lines F-F' and G-G';

[0040] Fig.28 is along Fig.26 A cross-sectional view taken along line BB';

[0041] Fig.29 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0042] Fig.30 is along Fig.29 A cross-sectional view taken along line BB';

[0043] Fig.31 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure;

[0044] Fig.32 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure; and

[0045] Fig.33 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0046] In the following, reference will be made to Figures 1 to 3 , Figure 4a , Figure 4b , Figure 5a and Figure 5bSemiconductor devices according to some exemplary embodiments of the present disclosure are described.

[0047] Figure 1 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Figure 2 is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 is along Figure 1 A cross-sectional view taken along line BB'. Figure 4a is along Figure 1 A cross-sectional view taken along line CC'. Figure 5a is along Figure 1 A cross-sectional view taken along line D-D'.

[0048] Reference Figures 1 to 3 , Figure 4a and Figure 5a The semiconductor device according to some exemplary embodiments of the present disclosure may include a substrate 100, first to fourth cells C1 to C4, first to fifth diffusion interruption structures B1 to B5, a first fin structure Fs1, a second fin structure Fs2, first to fourth gate electrodes G1 to G4, a first gate insulating film 310, a first capping film 340, a first spacer 350, a first source and drain region 400, a second source and drain region 401, a first interlayer insulating film 510, a second interlayer insulating film 520, a first contact portion 410, a second contact portion 411, etc. The semiconductor device may be a semiconductor chip.

[0049] The first direction X may be any one of the lateral directions. The second direction Y may be a direction intersecting the first direction X, for example, a direction perpendicular to the first direction X. The third direction Z may be a direction intersecting both the first direction X and the second direction Y. For example, the third direction Z may be a direction perpendicular to both the first direction X and the second direction Y. In this case, the first direction X and the second direction Y may be lateral directions perpendicular to each other, and the third direction Z may be a vertical direction. For example, the first direction X, the second direction Y, and the third direction Z may be directions orthogonal to each other.

[0050] The substrate 100 may be formed of at least one semiconductor material selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium phosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), and indium phosphide (InP). In addition, a silicon on insulator (SOI) substrate may be used as the substrate 100.

[0051] A plurality of cells may be formed on the substrate 100. Specifically, the substrate 100 may include first to fourth cells C1 to C4. The first to fourth cells C1 to C4 may be sequentially arranged in the first direction X. Each of the first to fourth cells C1 to C4 may be defined by an adjacent diffusion interruption structure among the first to fifth diffusion interruption structures B1 to B5.

[0052] Specifically, the first cell C1 may be defined by the first diffusion interruption structure B1 and the second diffusion interruption structure B2, and the fourth cell C4 may be defined by the fourth diffusion interruption structure B4 and the fifth diffusion interruption structure B5. The second diffusion interruption structure B2 may be located between the first cell C1 and the second cell C2, and the third diffusion interruption structure B3 may be located between the second cell C2 and the third cell C3. The fourth diffusion interruption structure B4 may be located between the third cell C3 and the fourth cell C4.

[0053] The first unit C1 to the fourth unit C4 may each be a different circuit module. For example, the first unit C1 may be a master latch circuit module of a master-slave latch, and the second unit C2 may be a slave latch circuit module of a master-slave latch. The third unit C3 may be a clock circuit module, and the fourth unit C4 may be an output circuit module. Therefore, the first unit C1 to the fourth unit C4 may be used together as a trigger circuit module. However, the present disclosure is not limited thereto. Each of the first unit C1 to the fourth unit C4 may include one standard unit or a plurality of standard units. A standard unit refers to a unit cell having a specific function, for example, an AND gate, an OR gate, an inverter, etc.

[0054] The first to fifth diffusion interruption structures B1 to B5 may insulate the first to fourth cells C1 to C4 from each other. For example, the first to fifth diffusion interruption structures B1 to B5 may separate the first to fourth cells C1 to C4 from each other so that the first to fourth cells C1 to C4 may be used as modules having different functions.

[0055] The substrate 100 may include an n region Rn and a p region Rp. As described below, an N-type metal oxide semiconductor (NMOS) transistor may be formed in the n region Rn, and a P-type metal oxide semiconductor (PMOS) transistor may be formed in the p region Rp. As shown in the figure, the n region Rn and the p region Rp may be regions adjacent to each other in the second direction Y. Therefore, each of the first to fourth cells C1 to C4 is included in the n region Rn and the p region Rp, and the n region Rn and the p region Rp may be aligned with each other in the first direction X. For example, Figure 1As shown, all n regions Rn may be disposed upward along the second direction Y, and all p regions Rp may be disposed downward along the second direction Y. In the semiconductor device according to some exemplary embodiments of the present disclosure, positions of the n regions Rn and the p regions Rp may be exchanged.

[0056] The first fin structure Fs1 may extend in the first direction X. The first fin structure Fs1 may be located in the n region Rn. The first fin structure Fs1 may be divided into first to fourth fins F1 to F4 by first to fifth diffusion interruption structures B1 to B5. The first to fourth fins F1 to F4 may be disposed in first to fourth cells C1 to C4, respectively. In this case, although the first to fourth fins F1 to F4 are aligned with each other in the first direction X, the first to fourth fins F1 to F4 may not be aligned with each other in some embodiments.

[0057] The second fin structure Fs2 may extend in the first direction X. The second fin structure Fs2 may be spaced apart from the first fin structure Fs1 in the second direction Y. The second fin structure Fs2 may be located in the p region Rp. The second fin structure Fs2 may be divided into fifth fins F5 to eighth fins F8 by the first diffusion interruption structure B1 to the fifth diffusion interruption structure B5. The fifth fins F5 to the eighth fins F8 may be respectively disposed in the first cell C1 to the fourth cell C4. In this case, although the fifth fins F5 to the eighth fins F8 are aligned in the first direction X, in some embodiments the fifth fins F5 to the eighth fins F8 may not be aligned with each other.

[0058] The first fin structure Fs1 and the second fin structure Fs2 may protrude from the substrate 100 in a third direction Z (eg, a vertical direction). The first fin structure Fs1 and the second fin structure Fs2 may be a portion of the substrate 100 or include an epitaxial layer grown from the substrate 100. The first fin structure Fs1 and the second fin structure Fs2 may include, for example, silicon (Si) or silicon germanium (SiGe).

[0059] The first fin structure Fs1 and the second fin structure Fs2 may be at different distances from the centers of the first to fourth cells C1 to C4 in the second direction Y. For example, the position of the first fin structure Fs1 may not be symmetrical with the position of the second fin structure Fs2 in the second direction Y. In addition, the first fin structure Fs1 and the second fin structure Fs2 may include compound semiconductors, such as group IV-IV compound semiconductors or group III-V compound semiconductors.

[0060] For example, when the first fin structure Fs1 and the second fin structure Fs2 include a Group IV-IV compound semiconductor, the first to eighth fins F1 to F8 may include a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping such a binary compound or a ternary compound with a Group IV element.

[0061] For example, when the first fin structure Fs1 and the second fin structure Fs2 include a group III-V compound semiconductor, the first fin structure Fs1 and the second fin structure Fs2 may include one of a binary compound, a ternary compound, or a quaternary compound obtained by combining at least one group III element of aluminum (Al), gallium (Ga), and indium (In) with at least one group V element of phosphorus (P), arsenic (As), and antimony (Sb).

[0062] In the semiconductor device according to the exemplary embodiment of the present disclosure, it is assumed that the first fin structure Fs1 and the second fin structure Fs2 include silicon.

[0063] The first to fourth gate electrodes G1 to G4 may extend in the second direction Y. Each of the first to fourth gate electrodes G1 to G4 may be disposed on the first and second fin structures Fs1 and Fs2 across both the first and second fin structures Fs1 and Fs2 .

[0064] The first gate electrode G1 may be disposed in the first cell C1, and the second gate electrode G2 may be disposed in the second cell C2. The third gate electrode G3 may be disposed in the third cell C3, and the fourth gate electrode G4 may be disposed in the fourth cell C4. In this case, the number of each of the first to fourth gate electrodes G1 to G4 may vary according to needs and purposes. Although for the sake of simplicity, Figure 1 Two first gate electrodes G1 , two second gate electrodes G2 , one third gate electrode G3 , and one fourth gate electrode G4 are shown in FIG. 1 , but the present disclosure is not limited thereto.

[0065] The first to fourth gate electrodes G1 to G4 may all have the same first width W1. The expression "same" used herein may be a concept including slight differences caused by a manufacturing process.

[0066] The first power rail P1 may extend in the first direction X. The second power rail P2 may extend in the first direction X and be spaced apart from the first power rail P1 in the second direction Y. The first and second power rails P1 and P2 may be interconnection lines formed over the first to fourth gate electrodes G1 to G4.

[0067] In example embodiments, the first power rail P1 may be electrically connected to a ground voltage (e.g., GND or VSS) or a negative voltage less than the ground voltage, and the second power rail P2 may be electrically connected to a power supply voltage (e.g., VDD or VCC) or an internal power supply voltage (e.g., Vint) generated from an internal voltage generator circuit of the semiconductor device. For example, each of the first to fourth cells C1 to C4 may be provided with a ground voltage or a negative voltage through the first power rail P1, and provided with a power supply voltage or an internal power supply voltage through the second power rail P2.

[0068] In example embodiments, the first to fifth diffusion interrupt structures B1 to B5 may have different structures in the n-region Rn and the p-region Rp. Specifically, each of the first to fifth diffusion interrupt structures B1 to B5 may have a double diffusion interrupt film in the n-region Rn and two single diffusion interrupt films in the p-region Rp. Therefore, the first to fifth diffusion interrupt structures B1 to B5 may have a structure including a mixed diffusion interrupt (MDB) film in which a double diffusion interrupt film and a single diffusion interrupt film are mixed.

[0069] In this case, the double diffusion interrupter film and the single diffusion interrupter film can be formed simultaneously or at different times. That is, although the MDB film can be formed once by a series of continuous operations, the MDB film can also be ultimately formed by several discrete operations separated in time by other processes. The double diffusion interrupter film and the single diffusion interrupter film can include the same material or different materials.

[0070] Each of the first diffusion interruption structure B1 to the fifth diffusion interruption structure B5 may include two dummy gate electrodes. Specifically, the second diffusion interruption structure B2 may include a first dummy gate electrode DG1 and a second dummy gate electrode DG2, and the third diffusion interruption structure B3 may include a third dummy gate electrode DG3 and a fourth dummy gate electrode DG4. The fourth diffusion interruption structure B4 may include a fifth dummy gate electrode DG5 and a sixth dummy gate electrode DG6.

[0071] In an example embodiment, the dummy gate electrode includes one or more layers formed at the same height as the normal gate electrode and adjacent to the normal gate electrode. The dummy gate electrode is patterned from the same layer from which such a normal gate electrode is formed. For example, the dummy gate electrode can be formed simultaneously with the normal gate electrode by the same process of depositing and patterning the layer. Typically, the dummy gate electrode in a semiconductor device cannot achieve data transmission to an external device. For example, the dummy gate electrode may not be electrically connected to the gate of a cell of the semiconductor device, or if the dummy gate electrode is electrically connected to the gate of a dummy cell (e.g., including a dummy source and drain) of the semiconductor device, such a dummy gate electrode may not be activated, or if activated, it will not cause any data in such a dummy cell to be transmitted to a source outside the semiconductor device.

[0072] The first to sixth dummy gate electrodes DG1 to DG6 may extend in the second direction Y and be arranged in parallel with the first to fourth gate electrodes G1 to G4. The first to sixth dummy gate electrodes DG1 to DG6 and the first to fourth gate electrodes G1 to G4 may be spaced apart from each other by the same distance in the first direction X. That is, the first to sixth dummy gate electrodes DG1 to DG6 and the first to fourth gate electrodes G1 to G4 may be electrode structures formed at a constant interval and used as gate electrodes or dummy gate electrodes as needed. Therefore, similar to the gate electrode, the dummy gate electrode may have a first width W1 in the first direction X.

[0073] The double diffusion interruption film may include two dummy gate electrodes, and the single diffusion interruption film may occupy a space corresponding to one dummy gate electrode. Therefore, the MDB film in which one double diffusion interruption film and two single diffusion interruption films are connected in the second direction Y may occupy a space corresponding to two dummy gate electrodes. For example, each of the first diffusion interruption structure B1 to the fifth diffusion interruption structure B5 may occupy a space corresponding to two dummy gate electrodes.

[0074] The second fin F2 may be separated from the third fin F3 by the third diffusion interruption structure B3 on the substrate 100. In addition, the sixth fin F6 may be separated from the seventh fin F7 by the third diffusion interruption structure B3 on the substrate 100. Specifically, referring to Figure 2 , the second fin F2 may be separated from the third fin F3 by the first trench T1. The first trench T1 may be partially filled with the first field insulating film 200.

[0075] The first field insulating film 200 may be formed on the substrate 100 , covering portions of sidewalls of the first and second fin structures Fs1 and Fs2 , and exposing upper portions of the first and second fin structures Fs1 and Fs2 .

[0076] The first field insulating film 200 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material having a dielectric constant lower than that of silicon oxide. The low-k dielectric material may include, for example, flowable oxide (FOX), eastern silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), dry gel, aerogel, amorphous fluorinated carbon, organic silicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer material, or a combination thereof, but the present disclosure is not limited thereto.

[0077] The first field insulating film 200 may include a material capable of applying stress to the first fin structure Fs1. When the first field insulating film 200 applies stress to a channel of a transistor formed in the first fin structure Fs1, mobility of electrons serving as carriers may be improved.

[0078] The second gate electrode G2 and the third gate electrode G3 may be formed on the second fin F2 and the third fin F3 , respectively. The second gate electrode G2 and the third gate electrode G3 may include a first gate insulating film 310 , a first work function metal 320 , and a first filling metal 330 in the n region Rn.

[0079] The first gate insulating film 310 may include an interface film and a high-k dielectric film, the interface film including a silicon oxide film, and the high-k dielectric film including a high-k dielectric material. The high-k dielectric film may include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide film. The high-k dielectric material may include, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, but the present disclosure is not limited thereto.

[0080] In this case, the high-k dielectric film may include a dipole-forming material to control a threshold voltage of a gate electrode (hereinafter, the threshold voltage may be referred to for a transistor in a cell). Here, the dipole-forming material may include at least one of lanthanum (La), neodymium (Nd), europium (Eu), dysprosium (Dy), holmium (Ho), and ytterbium (Yb). However, the present disclosure is not limited thereto.

[0081] The first work function metal 320 may be formed on the first gate insulating film 310. The first work function metal 320 may include an n-type work function control material. The n-type work function control material may include at least one of titanium nitride (TiN), tantalum nitride (TaN), and titanium aluminum carbide (TiAlC). However, the present embodiment is not limited thereto.

[0082] The first filling metal 330 may be formed on the first work function metal 320. The first filling metal 330 may include at least one of tungsten (W) and titanium nitride (TiN), but the present disclosure is not limited thereto.

[0083] Due to the first work function metal 320 and the first filling metal 330 , the second gate electrode G2 and the third gate electrode G3 may serve as gate electrodes of the NMOS transistor in the n region Rn.

[0084] The first capping film 340 may be disposed on each of the second gate electrode G2 and the third gate electrode G3. The first capping film 340 may include silicon nitride, but the present disclosure is not limited thereto.

[0085] The first spacer 350 may be disposed on the side surfaces of the second gate electrode G2, the third gate electrode G3, and the first capping film 340. Although the first spacer 350 is exemplarily shown as a single-layer film in the drawings, the first spacer 350 may be a plurality of spacers formed by stacking a plurality of films. Depending on the manufacturing process or purpose, each of the plurality of spacers forming the first spacer 350 may have an I-shape, an L-shape, or a combination thereof. The first spacer 350 may include, for example, silicon nitride (SIN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN) and at least one of a combination thereof.

[0086] The third and fourth dummy gate electrodes DG3 and DG4 may have similar structures to the second and third gate electrodes G2 and G3 , respectively. The third and fourth dummy gate electrodes DG3 and DG4 may include a first dummy gate insulating film 210 , a first dummy work function metal 220 , and a first dummy filling metal 230 .

[0087] In this case, the first dummy gate insulating film 210 may include the same material as the first gate insulating film 310 and have the same thickness as the first gate insulating film 310. Similarly, the first dummy work function metal 220 may include the same material as the first work function metal 320 and have the same thickness as the first work function metal 320. The first dummy fill metal 230 may include the same material as the first fill metal 330.

[0088] However, each of the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 may be formed on the top surface of the corresponding fin in the second fin F2 and the third fin F3 and the top surface of the first field insulating film 200. Therefore, each of the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 may have a stepped bottom surface along the step between the first field insulating film 200 and the second fin F2 and the third fin F3. Since the first dummy gate insulating film 210 and the first dummy work function metal 220 are formed along the stepped bottom surface, the first dummy gate insulating film 210 and the first dummy work function metal 220 may also have a stepped bottom surface. In addition, the first dummy filling metal 230 filling the remaining space may also have a stepped bottom surface.

[0089] The first dummy cover film 240 may be disposed on each of the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 . The first dummy cover film 240 may include the same material as the first cover film 340 and have the same thickness as the first cover film 340 .

[0090] The first source and drain region 400 may be disposed on the side of the second gate electrode G2, the third gate electrode G3, the third dummy gate electrode DG3, and the fourth dummy gate electrode DG4. The first source and drain region 400 may include an epitaxial layer formed using an epitaxial process. In addition, the first source and drain region 400 may be a raised source and drain region. The first source and drain region 400 located in the n region Rn may include, for example, a silicon (Si) epitaxial layer or a silicon carbide (SiC) epitaxial layer. In this case, the first source and drain region 400 may include SiP or SiPC heavily doped with phosphorus (P).

[0091] The first interlayer insulating film 510 may cover the top surfaces of the substrate 100, the first source and drain regions 400, and the first field insulating film 200. The first interlayer insulating film 510 may fill the space between the side surfaces of the gate electrode and the dummy gate electrode. The top surface of the first interlayer insulating film 510 may be coplanar with the top surfaces of the first spacer 350, the first dummy spacer 250, the first capping film 340, and the first dummy capping film 240.

[0092] The second interlayer insulating film 520 may be formed on the first interlayer insulating film 510. Each of the first and second interlayer insulating films 510 and 520 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material having a lower dielectric constant than silicon oxide.

[0093] The first contact portion 410 may be formed through the first interlayer insulating film 510 and the second interlayer insulating film 520 and contact the first source and drain region 400. The first contact portion 410 may be formed to a depth deeper than the top surface of the first source and drain region 400. Silicide may be formed at an interface between the first contact portion 410 and the first source and drain region 400. A barrier metal may be formed on a surface of the first contact portion 410 contacting the first interlayer insulating film 510, the second interlayer insulating film 520, and the first source and drain region 400.

[0094] Each of the second gate electrode G2 and the third gate electrode G3 in the p region Rp may include a first gate insulating film 310 , a first work function metal 320 , a second work function metal 325 , and a first filling metal 330 .

[0095] The second work function metal 325 may be formed on the first work function metal 320. The second work function metal 325 may include a p-type work function control material. The p-type work function control material may include at least one of TiN, TaN, and TiAlC. However, the present embodiment is not limited thereto. The first filler metal 330 may be formed on the second work function metal 325.

[0096] Due to the first work function metal 320 , the second work function metal 325 , and the first filling metal 330 , the second gate electrode G2 and the third gate electrode G3 may function as gate electrodes of a PMOS transistor in the p region Rp.

[0097] The third diffusion interruption structure B3 may include two single diffusion interruption films 600 instead of the third and fourth dummy gate electrodes DG3 and DG4 . Each single diffusion interruption film 600 may be formed in each of the second and third trenches T2 and T3 .

[0098] The second trench T2 may be formed to a relatively large depth at the location where the third dummy gate electrode DG3 is located, and the third trench T3 may be formed to a relatively large depth at the location where the fourth dummy gate electrode DG4 is located. Therefore, the second trench T2 and the third trench T3 may separate the sixth fin F6 and the seventh fin F7 and simultaneously define an isolation fin FI. The isolation fin FI may be a portion of the second fin structure Fs2 isolated by two single diffusion interrupter films 600.

[0099] The second trench T2 and the third trench T3 formed in the p region Rp may have a smaller width than the first trench T1 formed in the n region Rn. However, the present embodiment is not limited thereto.

[0100] The lower side surface of the single diffusion interrupter film 600 may be defined by the sixth fin F6, the seventh fin F7, and the isolation fin FI, and the upper side surface of the single diffusion interrupter film 600 may be defined by the first dummy spacer 250. For example, the first dummy spacer 250 may be located on the side surface of the single diffusion interrupter film 600.

[0101] Since each single diffusion interrupter film 600 is located at the position where the existing third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 are located, each single diffusion interrupter film 600 may have the same first width W1 as the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4. In addition, the top surface of the single diffusion interrupter film 600 may be at the same height as the top surfaces of the first capping film 340 and the first interlayer insulating film 510.

[0102] The single diffusion interrupter film 600 may include a material capable of applying stress to the second fin structure Fs2. When the single diffusion interrupter film 600 applies stress to the channel of the transistor formed in the second fin structure Fs2, the mobility of holes serving as carriers may be improved. Therefore, the single diffusion interrupter film 600 may include a material different from that of the first field insulating film 200.

[0103] The second source and drain regions 401 may be disposed on the sides of the second gate electrode G2 and the third gate electrode G3 . In addition, the dummy source and drain regions 402 may be disposed on the isolation fins FI between the single diffusion interrupter films 600 .

[0104] The second source and drain regions 401 and the dummy source and drain regions 402 may include an epitaxial layer formed using an epitaxial process. In addition, the second source and drain regions 401 and the dummy source and drain regions 402 may be elevated source and drain regions. The second source and drain regions 401 and the dummy source and drain regions 402 located in the p region Rp may include, for example, a SiGe epitaxial layer.

[0105] The outer peripheral surfaces of the first source and drain regions 400, the second source and drain regions 401, and the dummy source and drain regions 402 may have at least one of a rhombus, a circle, and a rectangle. Figure 4a , a rhombus (or a pentagon or a hexagon) is shown as an example.

[0106] The process of forming the single diffusion stopper film 600 may be performed after the process of forming the second source / drain region 401 and the dummy source / drain region 402. Therefore, the dummy source / drain region 402 may be formed at one side of each single diffusion stopper film 600.

[0107] In the semiconductor device according to some exemplary embodiments of the present disclosure, a process of forming the single diffusion interrupter film 600 may be performed before forming the second source and drain regions 401 and the dummy source and drain regions 402. In this case, the dummy source and drain regions 402 may not be separately formed on the isolation fin FI.

[0108] The second contact portion 411 may be formed through the first interlayer insulating film 510 and the second interlayer insulating film 520, and may be formed to contact the second source and drain region 401. The second contact portion 411 may be formed to have a depth deeper than the top surface of the second source and drain region 401. Silicide may be formed at an interface between the second contact portion 411 and the second source and drain region 401. A barrier metal may be formed on a surface of the second contact portion 411 contacting the first interlayer insulating film 510, the second interlayer insulating film 520, and the second source and drain region 401.

[0109] Reference Figure 4a and Figure 5a , the first groove Gr1 and the second groove Gr2 may be disposed on the side of the third fin F3 in the second direction Y. The first groove Gr1 and the second groove Gr2 may be traces obtained by forming a specific fin together with the third fin F3 and then cutting a portion of the specific fin. Similarly, the third groove Gr3 and the fourth groove Gr4 may be disposed on the side of the seventh fin F7 in the second direction Y. Although Figure 4a An example is shown in which one groove is provided on each of both sides of the third fin F3 and the seventh fin F7 , but the embodiment is not limited thereto.

[0110] In the semiconductor device according to the present embodiment, a transistor may be implemented using only one fin in each of the n region Rn and the p region Rp. Compared with a structure using multiple fins, the single fin structure of the semiconductor device may have lower power consumption and higher integration density.

[0111] Furthermore, the semiconductor device according to the present embodiment can obtain a relatively wide space margin in the upper contact and the interconnection structure, thereby greatly improving the operational reliability of the semiconductor device.

[0112] Conventional structures using multiple fins can have a more stable distribution in threshold voltage than single fin structures. The distribution of threshold voltage can more significantly affect PMOS transistors with high threshold voltages. When a double diffusion interrupt film structure is used, the distribution of threshold voltage may be more problematic. This is because of the fact that the double diffusion interrupt film structure has a layout effect compared to a single diffusion interrupt film structure, which causes the threshold voltage of the gate electrode to increase.

[0113] However, in the semiconductor device according to the present embodiment, two single diffusion interrupter films can be formed in the p region Rp where the PMOS transistor is formed instead of the double diffusion interrupter films. Therefore, the threshold voltage of the PMOS transistor can be stably controlled, so that the semiconductor device can have high reliability and improved operating performance.

[0114] In the following, reference will be made to Figure 1 , Figure 4b and Figure 5bSemiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0115] Figure 4b is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 5b is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure. Figure 4b is along Figure 1 The cross-sectional view taken along the C-C' line, Figure 5b is along Figure 1 Cross-sectional view taken along line D-D'.

[0116] Reference Figure 1 , Figure 4b and Figure 5b The fin cut trench Fct may be disposed on both sides of the third fin F3 and the seventh fin F7. The bottom surface of the fin cut trench Fct may be located at a height lower than the top surface of the substrate 100. Figure 4a and Figure 5a Unlike the groove of the fin cut groove Fct, the fin cut groove Fct may be a trace obtained by deeply removing the fin. Although the position of the fin cut groove Fct is shown on both sides of the third fin F3 and the seventh fin F7 for simplicity, the present embodiment is not limited thereto.

[0117] In the following, reference will be made to Figure 6 and Figure 7 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0118] Figure 6 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Figure 7 is along Figure 6 A cross-sectional view taken along line BB'.

[0119] Reference Figure 6 and Figure 7In the semiconductor device according to some exemplary embodiments of the present disclosure, the dummy gate electrode may be formed on the single diffusion interruption film 600. For example, the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 may be formed not only in the n region Rn but also in the p region Rp. The third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 in the p region Rp may have structures similar to the second gate electrode G2 and the third gate electrode G3 in the p region Rp, respectively. The third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 in the p region Rp may include a first dummy gate insulating film 210, a first dummy work function metal 220, a second dummy work function metal 225, and a first dummy filling metal 230. The second dummy work function metal 225 may be formed on the first dummy work function metal 220. The second dummy work function metal 225 may include the same material as the second work function metal 325 and may have the same thickness as the second work function metal 325. This is because of the fact that after the single diffusion interruption film 600 is formed, the gate electrodes G2 and G3 and the third and fourth dummy gate electrodes DG3 and DG4 are formed.

[0120] along Figure 6 The cross-sectional view taken along the line A-A' can be compared with Figure 2 same.

[0121] In the following, reference will be made to Figure 8 and Fig. 9 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0122] Figure 8 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig. 9 is along Figure 8 A cross-sectional view taken along line BB'.

[0123] Reference Figure 8 and Fig. 9 , the semiconductor device according to some exemplary embodiments of the present disclosure may include a double diffusion break film in the n region Rn, and include a single diffusion break film in the p region Rp.

[0124] In example embodiments, the p-region Rp of each of the first to fourth cells C1 to C4 may be wider than the n-region Rn. For example, the third diffusion interruption structure B3 may include a third dummy gate electrode DG3 and a fourth dummy gate electrode DG4 in the n-region Rn. In contrast, the third diffusion interruption structure B3 may include only a single diffusion interruption film 600 in the p-region Rp, which extends in the second direction Y starting from the third dummy gate electrode DG3, and may form a third gate electrode G3 extending in the second direction Y starting from the fourth dummy gate electrode DG4, which operates as the third cell C3. In this case, the third cell C3 may have two third gate electrodes G3. Of course, the third dummy gate electrode DG3 may extend continuously in the second direction Y, so that a dummy gate electrode may be formed even in the p-region Rp.

[0125] along Figure 8 The cross-sectional view taken along the line A-A' can be compared with Figure 2 same.

[0126] The present embodiment can stably control the threshold voltage by using the single diffusion interrupter film 600 instead of the double diffusion interrupter film in the p region Rp. In addition, a wide space margin can be obtained in the p region Rp, thereby improving the operating characteristics of the semiconductor device.

[0127] In the following, reference will be made to Fig.10 and Fig.11 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0128] Fig.10 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig.11 is along Fig.10 A cross-sectional view taken along line BB'.

[0129] Reference Fig.10 and Fig.11 In the semiconductor device according to some exemplary embodiments of the present disclosure, the diffusion interruption film 610 may be provided between the dummy gate electrodes in the p region Rp.

[0130] Specifically, the fourth trench T4 may be formed between the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4. The fourth trench T4 may separate the sixth fin F6 and the seventh fin F7 from each other in the first direction X. The lower portion of the fourth trench T4 may be defined by the side surfaces of the sixth fin F6 and the seventh fin F7 in the first direction X. The middle portion of the fourth trench T4 may be defined by the side surfaces of the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4. The upper portion of the fourth trench T4 may be defined by the first interlayer insulating film 510 and the second interlayer insulating film 520.

[0131] An insulating liner 620 may be formed along the sidewall of the fourth trench T4 defined by the first interlayer insulating film 510 and the second interlayer insulating film 520. The insulating liner 620 may be formed along the entire sidewall of the fourth trench T4, and a portion of the insulating liner 620 may be removed so that only a portion of the insulating liner 620 may remain. Therefore, the insulating liner 620 may also remain on the other sidewalls of the fourth trench T4. Alternatively, the insulating liner 620 may be completely removed using an etching process and the insulating liner 620 may not exist.

[0132] The diffusion interruption film 610 may completely fill the fourth trench T4. Although the diffusion interruption film 610 is illustrated as a single-layer film, the diffusion interruption film 610 may have a structure in which a plurality of films are stacked.

[0133] In the present embodiment, a dummy gate electrode may be formed in both the p region Rp and the n region Rn, and then the diffusion interruption film 610 may be formed only in the p region Rp. Fig.10 The cross-sectional view taken along the line A-A' can be compared with Figure 2 Therefore, the process can be relatively simple. Therefore, a semiconductor device with relatively high reliability can be provided.

[0134] In the following, reference will be made to Fig.12 and Fig.13 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0135] Fig.12 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig.13 is along Fig.12 A cross-sectional view taken along line BB'.

[0136] Reference Fig.12 and Fig.13In the semiconductor device according to some exemplary embodiments of the present disclosure, the first to fifth diffusion interruption structures B1 to B5 may include a single diffusion interruption film 600 not only in the p-region Rp but also in the n-region Rn. In addition, only one single diffusion interruption film 600 (instead of two single diffusion interruption films) may extend in the second direction Y in each of the first to fifth diffusion interruption structures B1 to B5.

[0137] In this embodiment, since only one single diffusion interruption film 600 is formed in each of the first to fifth diffusion interruption structures B1 to B5, the integration density of the semiconductor device can be improved. In addition, the threshold voltage of the transistor can be stably controlled by reducing the layout effect.

[0138] In the following, reference will be made to Figure 1 , Fig.14 and Fig.15 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0139] Fig.14 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig.15 is along Fig.14 A cross-sectional view taken along line EE'.

[0140] Reference Figure 1 , Fig.14 and Fig.15 In the semiconductor device according to some exemplary embodiments of the present disclosure, the third cell C3 may include four third gate electrodes G3. A portion of the first contact portion 410 may be electrically connected to the first power rail P1 through the third via V3. A portion of the first contact portion 410 may be connected to the second interconnection line M2 through the first via V1.

[0141] Similarly, a portion of the second contact portion 411 may be electrically connected to the second power rail P2 through the third via V3. A portion of the second contact portion 411 may be connected to the second interconnection line M2 through the first via V1.

[0142] The gate contact 420 may be formed on the third gate electrode G3 and connected to the first interconnection line M1 through the second via V2 .

[0143] A third interlayer insulating film 540 may be formed on the second interlayer insulating film 520, and a fourth interlayer insulating film 550 may be formed on the third interlayer insulating film 540. First to third vias V1 to V3 may be formed through the third interlayer insulating film 540, and first and second interconnection lines M1, M2, first power rails P1, and second power rails P2 may be formed in the fourth interlayer insulating film 550.

[0144] The first interconnection line M1, the second interconnection line M2, the first power rail P1 and the second power rail P2 can all be formed at the same height. The first through vias V1 to the third through vias V3 can also be formed at the same height below the first interconnection line M1, the second interconnection line M2, the first power rail P1 and the second power rail P2.

[0145] The first contact portion 410 , the second contact portion 411 , and the gate contact portion 420 may be formed at the same height below the first to third via holes V1 to V3 . However, the present embodiment is not limited thereto.

[0146] The shapes of the first contact 410 , the second contact 411 , the gate contact 420 , the first interconnection line M1 , and the second interconnection line M2 may not necessarily be the same as those shown in the drawings, but may be changed as needed.

[0147] In the following, reference will be made to Figure 1 and Fig.16 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0148] Fig.16 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.16 is along Figure 1 A cross-sectional view taken along line AA'.

[0149] Reference Figure 1 and Fig.16 , the top surface of the second field insulating film 201 can be at the same height as the top surfaces of the second fin F2 and the third fin F3. Therefore, the bottom surfaces of the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 can also be formed flatly without a step. The bottom surfaces of the first dummy gate insulating film 210, the first dummy work function metal 220, and the first dummy filling metal 230 in the third dummy gate electrode DG3 and the fourth dummy gate electrode DG4 can also be formed flatly.

[0150] In the following, reference will be made to Fig.17 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0151] Fig.17 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure.

[0152] Reference Fig.17 Among the first diffusion interrupt structure B1 to the fifth diffusion interrupt structure B5, the third diffusion interrupt structure B3 and the fourth diffusion interrupt structure B4 configured to define the third unit C3 may have an MDB film structure, while the remaining first diffusion interrupt structure B1, the second diffusion interrupt structure B2 and the fifth diffusion interrupt structure B5 may simply have a double diffusion interrupt film structure.

[0153] For example, as the distance between the gate electrode and the diffusion interruption structure becomes closer, the above layout effect can be more obvious. Therefore, only the third cell C3 to which the layout effect can be obviously applied can adopt the MDB film structure, so that the p region Rp can have no double diffusion interruption film structure but a single diffusion interruption film structure.

[0154] Therefore, in the semiconductor device according to this embodiment, the difficulty of the process of forming other cells can be reduced and the reliability of other regions can be increased, thereby improving the operating characteristics of the entire device, and at the same time, the distribution of the threshold voltage of the third cell C3 can be stably controlled.

[0155] In the following, reference will be made to Fig.18 and Fig.19 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0156] Fig.18 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig.19 is along Fig.18 A cross-sectional view taken along line AA'.

[0157] refer to Fig.18 and Fig.19 , the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5.

[0158] The fifth cell C5 may be a cell adjacent to or spaced apart from the first to fourth cells C1 to C4. The fifth cell C5 may be included in the n-region Rn and the p-region Rp, similar to the first to fourth cells C1 to C4. The ninth fin F9 and the tenth fin F10 may be disposed in the fifth cell C5. The ninth fin F9 may extend in the first direction X in the n-region Rn, and the tenth fin F10 may extend in the first direction X in the p-region Rp. The ninth fin F9 and the tenth fin F10 may be spaced apart from each other in the second direction Y.

[0159] The fifth gate electrode G5 may extend in the second direction Y on the ninth and tenth fins F9 and F10 to cross the ninth and tenth fins F9 and F10 .

[0160] In this case, the fifth gate electrode G5 may have a first width W1 in the first direction X, and the first to fourth gate electrodes G1 to G4 of the first to fourth cells C1 to C4 may have a second width W2 in the first direction X. The second width W2 may be different from the first width W1. For example, the second width W2 may be greater than the first width W1.

[0161] In this case, all dummy gate electrodes including the third and fourth dummy gate electrodes DG3 and DG4 and the single diffusion interrupter film 600 may have the second width W2. This is because the dummy gate electrodes and the single diffusion interrupter film 600 are determined using the same process as patterning the gate electrodes.

[0162] However, in the semiconductor device according to some exemplary embodiments of the present disclosure, only the width of the gate electrode may be controlled, while the widths of the dummy gate electrode and the single diffusion interrupter film are not controlled.

[0163] In the semiconductor device according to the present embodiment, the widths of all gate electrodes of the first to fourth cells C1 to C4 can be controlled, thereby controlling the threshold voltage and its distribution. For example, by controlling the width of the gate electrode in the first direction X, the channel length of the gate electrode can be controlled, thereby controlling the threshold voltage of the gate electrode.

[0164] Since the distribution of the threshold voltage decreases as the width of the gate electrode increases, the distribution of the threshold voltage may be reduced by controlling the width of the gate electrode.

[0165] Therefore, even if the semiconductor device according to the present embodiment adopts a single fin structure, a transistor having a stable threshold voltage distribution can be implemented.

[0166] In the following, reference will be made to Fig. 20 and Fig.21 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0167] Fig. 20 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure, Fig.21 is along Fig. 20 A cross-sectional view taken along line AA'.

[0168] Reference Fig. 20 and Fig.21In the semiconductor device according to some exemplary embodiments of the present disclosure, only the gate electrode of the third cell C3 may be formed to have the second width W2, and the gate electrodes of the remaining cells may be formed to have the first width W1. In addition, only the diffusion interruption structure configured to define the third cell C3 may adopt the MDB film, and the remaining diffusion interruption structures may adopt the double diffusion interruption film.

[0169] Therefore, in the present embodiment, the difficulty of the process of forming other cells can be reduced, and the reliability of other regions can be increased, thereby improving the operating characteristics of the entire device, and at the same time, the threshold voltage of the third cell C3 can be stably controlled.

[0170] In the following, reference will be made to Figure 22 to Figure 24 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0171] Fig. 22 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.23 is along Fig. 22 Cross-sectional view along line F-F' and line G-G'. Fig.24 is along Fig. 22 A cross-sectional view taken along line BB'.

[0172] refer to Figure 22 to Figure 24 , the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5. A ninth fin F9 and a tenth fin F10 may be disposed in the fifth cell C5. The ninth fin F9 may extend along the first direction X in the n region Rn, and the tenth fin F10 may extend along the first direction X in the p region Rp. The ninth fin F9 and the tenth fin F10 may be spaced apart from each other in the second direction Y. The fifth gate electrode G5 may extend along the second direction Y on the ninth fin F9 and the tenth fin F10 to intersect the ninth fin F9 and the tenth fin F10.

[0173] The first to fifth diffusion interruption structures B1 to B5 of the semiconductor device according to some exemplary embodiments of the present disclosure may all have a double diffusion interruption film structure. Unlike the fifth cell C5, the threshold voltage of the gate electrode of each of the first to fourth cells C1 to C4 may be reduced by using a gate electrode structure in the p region Rp.

[0174] Specifically, in the fifth cell C5, the fifth gate electrode G5 may be formed on the ninth fin F9 and the tenth fin F10. The fifth gate electrode G5 may include a second gate insulating film 1310, a third work function metal 1320, and a second filling metal 1330 in the n region Rn. A second capping film 1340 may be formed on the fifth gate electrode G5, and a second spacer 1350 may be formed on the side surfaces of the fifth gate electrode G5 and the second capping film 1340.

[0175] The third source and drain regions 1400 may be formed at both sides of the fifth gate electrode G5 in the n region Rn, and the third contact portion 1410 may be formed through the first and second interlayer insulating films 510 and 520 and contact the third source and drain regions 1400 .

[0176] The fifth gate electrode G5 in the p region Rp may include a second gate insulating film 1310, a third work function metal 1320, a fourth work function metal 1325, and a second filling metal 1330. A second capping film 1340 may be formed on the fifth gate electrode G5, and a second spacer 1350 may be formed on side surfaces of the fifth gate electrode G5 and the second capping film 1340.

[0177] Fourth source and drain regions 1401 may be formed at both sides of the fifth gate electrode G5 in the p region Rp, and fourth contacts 1411 may be formed through the first and second interlayer insulating films 510 and 520 and contact the fourth source and drain regions 1401 .

[0178] In this case, the third work function metal 1320 may have a first thickness a1 in both the n region Rn and the p region Rp.

[0179] In contrast, the threshold voltages of the first to fourth cells C1 to C4 in the p region Rp may be lower than the threshold voltage of the fifth cell C5. To this end, the first work function metal 320 of each of the first to fourth cells C1 to C4 may have a second thickness a2 different from the first thickness a1. For example, the second thickness a2 may be greater than the first thickness a1.

[0180] In this embodiment, the structure of the gate electrode in the p region Rp can be changed to adjust the threshold voltage of the gate electrode, thereby facilitating stabilization of the distribution of the threshold voltage. As a result, even if the semiconductor device has a single fin structure, the threshold voltage can be stabilized, so that the semiconductor device can have improved operating characteristics.

[0181] In another case, the semiconductor device according to some exemplary embodiments of the present disclosure can adjust the concentration of the dipole material in the gate insulating film and reduce the threshold voltage of the p region Rp. In this case, the above-mentioned separate process for adjusting the thickness may not be required. Of course, in the semiconductor device according to some exemplary embodiments of the present disclosure, the threshold voltage can be adjusted by adjusting both the concentration and the thickness.

[0182] In the following, reference will be made to Fig. 22 and Fig.25 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0183] Fig.25 is a cross-sectional view showing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.25 is along Fig. 22 A cross-sectional view taken along line BB'.

[0184] Reference Fig. 22 and Fig.25 , the semiconductor device according to some exemplary embodiments of the present disclosure may adjust the threshold voltage of the p-region Rp of the third cell C3, and may not adjust the threshold voltage in other cells. For example, the first work function metal 320 of each of the first gate electrode G1, the second gate electrode G2, and the fourth gate electrode G4 may have a first thickness a1, and the first work function metal 320 of the third gate electrode G3 may have a second thickness a2 greater than the first thickness a1. Therefore, the first cell C1 to the fourth cell C4 at the n-region Rn may all have substantially the same threshold voltage, and the third cell C3 at the p-region Rp may have a threshold voltage lower than the threshold voltages of the first cell C1, the second cell C2, and the fourth cell C4 in the p-region Rp.

[0185] Therefore, in the present embodiment, the difficulty of the process of forming other cells can be reduced, and the reliability of other regions can be increased, thereby improving the operating characteristics of the entire device, and at the same time, the threshold voltage of the third cell C3 can be stably controlled.

[0186] In the following, reference will be made to Figure 26 to Figure 28 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0187] Fig.26 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig. 27 is along Fig.26 Cross-sectional view along line F-F' and line G-G'. Fig.28 is along Fig.26 A cross-sectional view taken along line BB'.

[0188] refer to Figure 26 to Figure 28 , the semiconductor device according to some exemplary embodiments of the present disclosure may further include a fifth cell C5. A ninth fin F9 and a tenth fin F10 may be disposed in the fifth cell C5. The ninth fin F9 may extend along the first direction X in the n region Rn, and the tenth fin F10 may extend along the first direction X in the p region Rp. The ninth fin F9 and the tenth fin F10 may be spaced apart from each other in the second direction Y. The fifth gate electrode G5 may extend along the second direction Y on the ninth fin F9 and the tenth fin F10 to intersect the ninth fin F9 and the tenth fin F10.

[0189] The fifth gate electrode G5 of the fifth cell C5 may have a first width W1 in the first direction X, and the third work function metal 1320 may have a first thickness a1.

[0190] In contrast, the gate electrodes of the first to fourth cells C1 to C4 may have a second width W2 greater than the first width W1 in the first direction X, and the first work function metal 320 may have a second thickness a2 greater than the first thickness a1. That is, the semiconductor device of the present embodiment may control the threshold voltage by adjusting the channel length using the width and adjusting the thickness of the work function metal of the gate electrode. Therefore, the distribution of the threshold voltage of the semiconductor device may be stabilized.

[0191] In the following, reference will be made to Fig.29 and Fig.30 Semiconductor devices according to some exemplary embodiments of the present inventive concept are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0192] Fig.29 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure. Fig.30 is along Fig.29 A cross-sectional view taken along line BB'.

[0193] Reference Fig.29 and Fig.30In the semiconductor device according to some exemplary embodiments of the present disclosure, only in the third cell C3, the width of the third gate electrode G3 may be controlled to be the second width W2, and the thickness of the first work function metal 320 may be controlled to be the second thickness a2, so that the threshold voltage may be stably controlled. For example, each of the first gate electrode G1, the second gate electrode G2, and the fourth gate electrode G4 may have a first width W1, and the third gate electrode G3 may have a second width W2 greater than the first width W1. In addition, the first work function metal 320 of each of the first gate electrode G1, the second gate electrode G2, and the fourth gate electrode G4 may have a first thickness a1, and the first work function metal 320 of the third gate electrode G3 may have a second thickness a2 greater than the first thickness a1.

[0194] Therefore, in the present embodiment, the difficulty of the process of forming other cells can be reduced, and the reliability of other regions can be increased, thereby improving the operating characteristics of the entire device, and at the same time, the threshold voltage of the third cell C3 can be stably controlled.

[0195] In the following, reference will be made to Fig.31 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0196] Fig.31 1 is a layout diagram for illustrating a semiconductor device according to some exemplary embodiments of the present disclosure.

[0197] refer to Fig.31 According to some exemplary embodiments of the present disclosure, the semiconductor device may further include a 3-1st fin F3-1. For example, due to the layout effect, the third cell C3 may have a relatively high threshold voltage distribution, and a transistor may be formed using multiple fins rather than a single fin to stabilize the threshold voltage distribution of the n region Rn.

[0198] Therefore, the present embodiment can utilize multiple fins to strengthen a specific region (ie, the n region Rn) of the weaker third cell C3 while utilizing a single fin in other cells, thereby improving the operating characteristics of the entire device.

[0199] Although for the sake of brevity Fig.31 An example is shown in which the 3-1th fin F3 - 1 is adjacent to the p region Rp, but the present embodiment is not limited thereto.

[0200] In the following, reference will be made to Fig.32 Semiconductor devices according to some exemplary embodiments of the present disclosure are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0201] Fig.32 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure.

[0202] refer to Fig.32 , a semiconductor device according to some exemplary embodiments of the present disclosure may include a 7-1th fin F7-1. That is, due to the layout effect, the third cell C3 may have a relatively high threshold voltage distribution, and a transistor may be formed using multiple fins rather than a single fin to stabilize the threshold voltage distribution of the p region Rp.

[0203] Therefore, the present embodiment can utilize multiple fins to strengthen a specific region (ie, the p region Rp) of the weaker third cell C3 while utilizing a single fin in other cells, thereby improving the operating characteristics of the entire device.

[0204] In the following, reference will be made to Fig.33 Semiconductor devices according to some exemplary embodiments of the present inventive concept are described. Descriptions of components in the present exemplary embodiment that are the same as those of the above-described exemplary embodiments will be omitted or briefly described.

[0205] Fig.33 is a layout diagram showing a semiconductor device according to some exemplary embodiments of the present disclosure.

[0206] Reference Fig.33 , a semiconductor device according to some exemplary embodiments of the present disclosure may include a 3-1st fin F3-1 and a 7-1st fin F7-1. For example, due to a layout effect, the third cell C3 may have a relatively high threshold voltage distribution, and a transistor may be formed using multiple fins rather than a single fin.

[0207] Therefore, the present embodiment can utilize multiple fins to strengthen the weaker third cell C3 while utilizing a single fin in other cells, thereby improving the operating characteristics of the entire device.

[0208] Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Therefore, it is expected that the present embodiment is considered to be illustrative rather than restrictive in all aspects, and reference is made to the appended claims rather than the foregoing description to indicate the scope of the present invention.

Claims

1. A semiconductor device, comprising: The first unit, the second unit, the third unit and the fourth unit are sequentially arranged on the substrate in a first direction; a first diffusion interruption structure, a second diffusion interruption structure, and a third diffusion interruption structure configured to separate the first to fourth cells from each other, the first diffusion interruption structure being inserted between the first cell and the second cell, the second diffusion interruption structure being inserted between the second cell and the third cell, and the third diffusion interruption structure being inserted between the third cell and the fourth cell; a first fin structure configured to protrude from the substrate and extend in the first direction, the first fin structure including first to fourth fins separated from each other by the first diffusion interruption structure, the second diffusion interruption structure, and the third diffusion interruption structure; a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure in a second direction intersecting the first direction and to extend in the first direction, the second fin structure comprising fifth to eighth fins separated from each other by the first diffusion interruption structure, the second diffusion interruption structure, and the third diffusion interruption structure; as well as A first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode are configured to extend in the second direction on the first fin structure and the second fin structure, and the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are respectively disposed in the first unit, the second unit, the third unit, and the fourth unit, wherein each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode intersects with the first fin structure at an n-region of the substrate and intersects with the second fin structure at a p-region of the substrate, and The number of fins in each of the first unit, the second unit, and the fourth unit is two.

2. The semiconductor device according to claim 1, wherein The number of fins in the third unit is at least three.

3. The semiconductor device according to claim 1, wherein Each of the second diffusion interruption structure and the third diffusion interruption structure includes a first portion in contact with the first fin structure and a second portion in contact with the second fin structure, Wherein, the first part includes: a double diffusion interrupter film including two dummy gate electrodes, and Wherein, the second part includes: a single diffusion interrupter film including a dummy source and drain region.

4. The semiconductor device according to claim 3, wherein: The first diffusion interruption structure includes a double diffusion interruption film.

5. The semiconductor device according to claim 3, wherein: A width of the third gate electrode in the first direction is different from a width of each of the first gate electrode, the second gate electrode, and the fourth gate electrode in the first direction.

6. The semiconductor device according to claim 1, further comprising: a fifth unit, different from each of the first to fourth units; a ninth fin configured to extend in the first direction in the fifth unit; as well as a fifth gate electrode configured to extend in the second direction on the ninth fin, The width of each of the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode in the first direction is greater than the width of the fifth gate electrode in the first direction.

7. The semiconductor device according to claim 1, wherein Each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode at the n region includes an n-type work function control material, and Each of the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode at the p region includes an n-type work function control material and a p-type work function control material disposed on the n-type work function control material.

8. The semiconductor device according to claim 7, wherein: The first cell, the second cell, the third cell, and the fourth cell at the n region all have the same threshold voltage, and wherein a threshold voltage of the third cell at the p-region is lower than a threshold voltage of each of the first cell, the second cell, and the fourth cell at the p-region.

9. The semiconductor device according to claim 1, further comprising: a fifth unit that is different from each of the first unit, the second unit, the third unit, and the fourth unit; a ninth fin configured to extend in the first direction in the fifth unit; as well as a fifth gate electrode configured to extend in the second direction on the ninth fin, the fifth gate electrode extending at the n region and the p region, A threshold voltage of each of the first cell, the second cell, the third cell, and the fourth cell at the p-region is lower than a threshold voltage of the fifth cell at the p-region. 10 . The semiconductor device according to claim 1 , further comprising a groove configured to protrude from the substrate to a height lower than the first fin structure and the second fin structure and extend in the first direction, the groove being spaced apart from the first fin structure and the second fin structure in the second direction. 11 . The semiconductor device according to claim 1 , further comprising a fin-cut trench interposed between the first fin structure and the second fin structure, a bottom surface of the fin-cut trench being located at a lower height than a top surface of the substrate.

12. A semiconductor device comprising: A substrate, including an n-region and a p-region; A first fin is disposed on the substrate in the n-region and extends in a first direction; a second fin disposed on the substrate in the p region and extending in the first direction, the second fin being spaced apart from the first fin in a second direction intersecting the first direction; a gate electrode configured to extend in the second direction on the first fin and the second fin; a field insulating film configured to be in contact with a side surface of the first fin in the first direction; a first dummy gate electrode formed on the n-region and formed on a top surface of the field insulating film and a top surface of the first fin, the first dummy gate electrode being configured to extend in the second direction; as well as A single diffusion interrupter film is formed on the p region and aligned with the first dummy gate electrode in the second direction, the single diffusion interrupter film being in contact with a side surface of the second fin in the first direction. 13 . The semiconductor device according to claim 12 , further comprising an isolation fin spaced apart from the second fin by the single diffusion interrupter film. 14 . The semiconductor device according to claim 13 , further comprising dummy source and drain regions formed on the isolation fin.

15. The semiconductor device according to claim 14, wherein: The dummy source and drain regions include silicon germanium.

16. A semiconductor device comprising: substrate; A first power rail and a second power rail are configured to extend in a first direction on the substrate, the first power rail and the second power rail being spaced apart from each other in a second direction intersecting the first direction; a first fin configured to protrude from the substrate and extend in the first direction; a second fin configured to protrude from the substrate and extend in the first direction, the second fin being spaced apart from the first fin in the second direction; A first diffusion interruption structure and a second diffusion interruption structure are configured to define two ends of the first fin and the second fin, respectively; as well as a gate electrode configured to extend on the first fin and the second fin in the second direction, The first fin is a fin closest to the first power rail in the second direction, the second fin is a fin closest to the second power rail in the second direction, and there is no fin between the first fin and the second fin in the second direction.

17. The semiconductor device according to claim 16, wherein: Each of the first diffusion interruption structure and the second diffusion interruption structure: contacting the first fin at an n-region of the substrate and contacting the second fin at a p-region of the substrate, including a double diffusion interrupter film formed in the n region, and A single diffusion interrupter film is included which is formed in the p region.

18. The semiconductor device according to claim 17, wherein: The double diffusion interrupter film comprises: a groove defined by a side surface of the first fin; a field insulating film configured to fill a portion of the trench; forming a first dummy gate electrode on the field insulating film and the first fin, the first dummy gate electrode being configured to extend in the second direction; and A second dummy gate electrode is formed on a portion of the field insulating film and is configured to extend in the second direction, the second dummy gate electrode being spaced apart from the first dummy gate electrode in the first direction.

19. The semiconductor device according to claim 18, wherein: The single diffusion interrupter film comprises: a first single diffusion interrupter film aligned with the first dummy gate electrode in the second direction; and A second single diffusion interrupter film is aligned with the second dummy gate electrode in the second direction.

20. The semiconductor device according to claim 19, wherein Each of the first single diffusion interrupter film and the second single diffusion interrupter film includes a material different from that of the field insulating film.

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