Semiconductor device package and method of manufacturing the same

Abstract

At least some embodiments of the present disclosure are directed to a semiconductor device package and a method of manufacturing the semiconductor device package. The semiconductor device package includes a substrate, a first solder paste, an electrical contact, and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes a surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than a melting point of the first solder paste. The first encapsulant includes a first surface facing the substrate and a second surface opposite the first surface. The second surface of the first encapsulant is exposed to air.

Description

[0001] Cross-citation of related applications

[0002] This application claims the benefit and priority of U.S. Provisional Application No. 62 / 688,937, filed June 22, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device package. More specifically, this disclosure relates to a semiconductor device package comprising an electrical contact having a high melting point portion and an encapsulation in contact with the high melting point portion of the electrical contact. Background Technology

[0004] Semiconductor packages can contain multiple electronic components to enhance their performance and functionality. To reduce the area or coverage of a semiconductor package, electronic components can be mounted on both the upper and lower surfaces of a substrate. To protect the electronic components mounted on the substrate, a double-sided molding technique can be used to form the package body on each of the upper and lower surfaces of the substrate. However, forming the package body on both sides of the substrate increases the thickness of the semiconductor package. Producing double-sided molded modules with relatively thin thickness is challenging. Summary of the Invention

[0005] In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a first solder paste, an electrical contact, and a first encapsulation. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulation encapsulates a portion of the electrical contact and exposes a surface of the electrical contact. The electrical contact has a surface facing away from the substrate. The melting point of the electrical contact is greater than the melting point of the first solder paste. The first encapsulation includes a first surface facing the substrate and a second surface opposite to the first surface. The second surface of the first encapsulation is exposed to air.

[0006] In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a first solder paste, an electrical contact, and an encapsulation body. The substrate includes a conductive pad. The first solder paste is disposed on the conductive pad. The electrical contact is disposed on the first solder paste. The encapsulation body encapsulates the electrical contact. The electrical contact includes a high-melting-point portion. The melting point of the high-melting-point portion of the electrical contact is greater than the melting point of the first solder paste. The encapsulation body is in contact with the high-melting-point portion of the electrical contact.

[0007] In some embodiments, according to another aspect, a method for manufacturing a semiconductor device package is disclosed. The method includes: disposing a first solder paste on a substrate; disposing an electrical contact on the first solder paste, wherein the electrical contact includes a high-melting-point portion having a melting point greater than that of the first solder paste; forming an encapsulation to encapsulate the electrical contact, the encapsulation contacting the high-melting-point portion of the electrical contact; and disposing a second solder paste on the electrical contact. Attached Figure Description

[0008] Figure 1A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0009] Figure 1B A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0010] Figure 2A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0011] Figure 2B A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0012] Figure 2C A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0013] Figure 2D A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0014] Figure 2E A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0015] Figure 2F A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0016] Figure 3A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0017] Figure 3B A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0018] Figure 3C A cross-sectional view showing an enlarged view of a portion of a semiconductor packaging apparatus according to some embodiments of the present disclosure.

[0019] Figure 4A A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0020] Figure 4B A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0021] Figure 4C A cross-sectional view illustrating a semiconductor device package according to some embodiments of the present disclosure is provided.

[0022] Figures 5A to 5C This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0023] Figures 6A to 6C This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0024] Figures 7A to 7D This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0025] Figures 8A to 8B This invention describes a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure. Detailed Implementation

[0026] Common reference numerals are used throughout the drawings and detailed embodiments to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Spatial descriptions, such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are specified relative to a particular component or group of components or a plane of a component or group of components to orient one or more components as shown in the associated figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged spatially in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangement.

[0028] Figure 1AThis is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, electronic components 11a, 11b and 13, encapsulation bodies 12 and 14, solder paste 15s, electrical contacts 15 and solder paste 16. In some embodiments, the semiconductor device package 1 is a two-sided module. The semiconductor device package 1 may include conformal shields (not shown) disposed on the outer surfaces of the encapsulation bodies 12, 14 and the substrate 10 to provide electromagnetic interference (EMI) shielding.

[0029] The substrate 10 may be, for example, a printed circuit board (PCB), a paper-based copper foil laminate, a composite copper foil laminate, a polymer-impregnated glass fiber copper foil laminate, or a combination of both or more thereof. The substrate 10 may include interconnect structures, such as a redistribution layer (RDL). The substrate 10 has an upper surface 101 and a lower surface 102 opposite to the upper surface 101. The substrate 10 has conductive pads 10p on or adjacent to the lower surface 102. Solder paste 15s is disposed on the conductive pads 10p.

[0030] Electronic components 11a and 11b are disposed on the upper surface 101 of substrate 10. Electronic component 11a may be an active component, such as an integrated circuit (IC) chip or die. Electronic component 11b may be a passive component, such as a capacitor, resistor, or inductor. Electronic components 11a and 11b may be electrically connected to another electronic component and / or one or more of the substrate 10 (e.g., electrically connected to an interconnect layer), and the electrical connection may be obtained by means of flip-chip or wire bonding technology.

[0031] Encapsulation 12 is disposed on the upper surface 101 of substrate 10. Encapsulation 12 covers or encapsulates substrate 10 and electronic components 11a and 11b. In some embodiments, encapsulation 12 comprises epoxy resin with filler, molding material (e.g., epoxy molding material or other molding material), polyimide, phenolic compound or material, material wherein silicone is dispersed, or a combination thereof.

[0032] Electronic component 13 is disposed on the lower surface 102 of substrate 10. Electronic component 13 has a surface 131. In some embodiments, surface 131 is the back surface of electronic component 13. Electronic component 13 is adjacent to electrical contact 15. Electronic component 13 can be an active component (e.g., an IC chip or die) or a passive component (e.g., a capacitor, resistor, or inductor). Electronic component 13 can be electrically connected to substrate 10 (e.g., electrically connected to an interconnect layer), and the electrical connection can be obtained by means of flip-chip or wire bonding techniques. Electronic component 13 can be electrically connected to electronic components 11a and 11b through the interconnect layer within substrate 10.

[0033] Electrical contact 15 is disposed on solder paste 15s. Solder paste 15s bonds electrical contact 15 to conductive pad 10p. Electrical contact 15 is disposed on the lower surface 102 of substrate 10. Electrical contact 15 can be electrically connected to the upper surface 101 of substrate 10 via an interconnect structure. In some embodiments, electrical contact 15 is a controlled collapse chip connection (C4) bump, a solder bump, one or more pad grid arrays (LGAs), or a combination of both or more thereof.

[0034] A portion of the electrical contact 15 is exposed from the encapsulation 14. For example, surface 151 (e.g., a cut surface) of the electrical contact 15 is exposed from the encapsulation 14. In some embodiments, surface 151 of the electrical contact 15 is substantially coplanar with lower surface 142 of the encapsulation 14. In some embodiments, the electrical contact 15 is formed of or contains copper (Cu), an alloy (e.g., CuAg or CuAu), or a high-melting-point soldering material (e.g., high-melting-point Sn). The melting point of the electrical contact 15 is greater than the melting points of solder pastes 15s and 16. In some embodiments, the electrical contact 15 is shaped as a portion of a sphere. When the electrical contact 15 is a portion of a metal sphere, the distance between the lower surface 102 of the substrate 10 and surface 151 of the electrical contact 15 is less than the diameter of the entire metal sphere. In some embodiments, the electrical contact 15 may be a portion of a metal sphere, an alloy sphere, a plastic sphere, or a metal pillar.

[0035] Encapsulation 14 includes an upper surface 141 facing the substrate 10 and a lower surface 142 opposite to the upper surface 141. Encapsulation 14 covers or encapsulates the lower surface 102 of the substrate 10 and the electronic component 13. The lower surface 142 of encapsulation 14 at least partially exposes the surface 151 of the electrical contact 15. The lower surface 142 of encapsulation 14 is exposed to air. The lower surface 142 of encapsulation 14 is substantially coplanar with the surface 151 of the electrical contact 15. The lower surface 142 of encapsulation 14 is substantially coplanar with the surface 131 of the electronic component 13. In some embodiments, the surface 131 of the electronic component 13 and the surface 151 of the electrical contact 15 are exposed from encapsulation 14. In some embodiments, encapsulation 14 may contain the same material as encapsulation 12. Encapsulation 14 may contain a different material than encapsulation 12.

[0036] Solder paste 16 is disposed on the surface 151 of electrical contact 15 to prevent oxidation of electrical contact 15 and to provide electrical connection between semiconductor device package 1 and any other device or component. Solder paste 16 may act as a conductive pad. In some embodiments, solder paste 16 may contain the same material as solder paste 15s. Solder paste 16 may contain a different material than solder paste 15s. In some embodiments, solder paste 16 may be omitted.

[0037] Figure 1BThis is an enlarged cross-sectional view of a portion of a semiconductor packaging apparatus 1 according to some embodiments of the present disclosure. A substrate 10 includes a dielectric / insulating layer 10i. The dielectric layer 10i may be a solder resist layer. The dielectric layer 10i partially covers a conductive pad 10p. The dielectric layer 10i and solder paste 15s are spaced apart by an encapsulation 14. The encapsulation 14 contacts the dielectric layer 10i, the conductive pad 10p, the solder paste 15s, and the electrical contacts 15. The encapsulation 14 may contact solder paste 16. In some embodiments, the encapsulation 14 may be spaced apart from the solder paste 16.

[0038] Electrical contact 15 is part of an entire copper ball or high-melting-point solder ball. Encapsulation 14 covers more than half of the entire ball to form a locking structure (circled by the dashed line) to prevent delamination (e.g., ball drop) between electrical contact 15 and encapsulation 14. In other words, the distance H between the lower surface 102 of substrate 10 and the surface 151 (e.g., cut surface) of electrical contact 15 is less than the diameter of the entire metal ball. The width of surface 151 of electrical contact 15 is greater than the radius of the entire metal ball. The width of surface 151 of electrical contact 15 is less than the diameter (D1) of the entire ball. The diameter of electrical contact 15 can be adjusted to be as small as possible to meet fine-pitch requirements, thereby increasing the number of input / output terminals.

[0039] In some embodiments, the electrical contact 15 has a high melting point greater than the reflow temperature (e.g., 260°C). The electrical contact 15 includes a high-melting-point portion. The entire electrical contact 15 has a high melting point. The melting point of the high-melting-point portion of the electrical contact 15 is greater than the melting points of the solder pastes 15s and 16. Therefore, the appearance of the electrical contact 15 will not be affected by the high temperature during the reflow operation, thus preventing deformation of the electrical contact 15. Because the electrical contact 15 can withstand the temperature of the reflow operation, the distance H between the lower surface 102 of the substrate 10 and the surface 151 of the electrical contact 15 is not limited (e.g., it can be greater than, equal to, or less than the radius of the entire high-melting-point solder ball). The distance H between the lower surface 102 of the substrate 10 and the surface 151 of the electrical contact 15 can be easily controlled, allowing for a flexible design window. The thickness of the encapsulation 14 can be reduced. The dimensions of the semiconductor device package 1 can be scaled.

[0040] Figure 2A This is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 is similar to... Figure 1A The semiconductor device package 1 is an exception in that the electrical contacts 25 of the semiconductor device package 2 are an entire high-melting-point metal ball (e.g., a copper ball or a high-melting-point solder ball).

[0041] Encapsulation 14 includes a recess 14c to receive an electrical contact 25. The electrical contact 25 is disposed on a conductive pad 10p on the surface 102 of the substrate 10. In some embodiments, the electrical contact 25 extends beyond the surface 142 of the encapsulation 14 by a distance greater than or equal to 30 μm. In some embodiments, the electrical contact 25 contacts the sidewall of the recess 14c of the encapsulation 14. Alternatively, the electrical contact 25 is spaced apart from the sidewall of the recess 14c of the encapsulation 14. Depending on the embodiment, the surface 131 of the electronic component 13 may be covered by or exposed from the encapsulation 14.

[0042] When the thickness of the capsule seal 14 is thick, the size of the electrical contact 25 can be larger. When the thickness of the capsule seal 14 is thin, the size of the electrical contact 25 can be smaller. The size of the groove 14c can be adjusted.

[0043] Figure 2B This is an enlarged cross-sectional view of a portion of a semiconductor packaging device 2 according to some embodiments of the present disclosure. The electrical contact 25 may be a copper ball. In some embodiments, the electrical contact 25 may be covered by a nickel (Ni) layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contact 25 is connected to the conductive pad 10p of the substrate 10 via solder paste 25s.

[0044] Substrate 10 includes a dielectric layer 10i. The dielectric layer 10i partially covers the conductive pad 10p. The dielectric layer 10i is spaced apart from the solder paste 25s and the electrical contact 25. Encapsulation 14 contacts the dielectric layer 10i and the conductive pad 10p. Encapsulation 14 may contact the electrical contact 25. Encapsulation 14 is spaced apart from the solder paste 25s.

[0045] Recess 14c exposes at least a portion of the conductive pad 10p of substrate 10. Recess 14c exposes solder paste 25s and electrical contacts 25.

[0046] Figure 2C This is an enlarged cross-sectional view of a portion of a semiconductor package device 2' according to some embodiments of the present disclosure. The semiconductor package device 2' is similar to the semiconductor package 2, except that it includes electrical contacts 25' with relatively small sizes. For example, the electrical contacts 25' do not protrude from the lower surface 142 of the package 14. For example, the diameter of the electrical contacts 25' is equal to or less than the depth of the recess 14c. This arrangement reduces the size of the electrical contacts 25' and the recess 14c, which is suitable for fine-pitch connections. The electrical contacts 25' may be copper balls. In some embodiments, the electrical contacts 25' may be covered by a Ni layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contacts 25' are connected to the conductive pads 10p of the substrate 10 via solder paste 25s.

[0047] Solder paste 26 is disposed on electrical contacts 25' to prevent oxidation of electrical contacts 25' and to provide electrical connection between the semiconductor device package 2' and any other device or component. Solder paste 26 may act as a conductive pad. Solder paste 26 is spaced apart from the encapsulation 14. In some embodiments, solder paste 26 may contain the same material as solder paste 25s. Solder paste 26 may contain a different material than solder paste 25s.

[0048] Recess 14c exposes at least a portion of the conductive pad 10p of substrate 10. Recess 14c exposes solder paste 25s, electrical contacts 25, and solder paste 26.

[0049] Figure 2D This is a cross-sectional view of a semiconductor device package 2” according to some embodiments of the present disclosure. The semiconductor device package 2” is similar to Figure 2B The semiconductor device package 2 is an exception in that solder paste 25's is disposed on conductive pad 10p and in contact with dielectric layer 10i. Electrical contacts 25 are disposed on solder paste 25's. Solder paste 25's are exposed by recesses 14c of the package 14.

[0050] Encapsulation 14 contacts the dielectric layer 10i and solder paste 25's. Encapsulation 14 contacts the electrical contact 25. In some embodiments, encapsulation 14 is spaced apart from the electrical contact 25.

[0051] Figure 2E This is a cross-sectional view of a semiconductor device package 2”' according to some embodiments of the present disclosure. The semiconductor device package 2”' is similar to Figure 2A The semiconductor device package 2 is an exception in that the conductive layer 21 is disposed on the encapsulation bodies 12 and 14, and a portion of the substrate 10 and the electrical contact 25” is disposed on the conductive pad 10p. The electrical contact 25” may contain solder material (e.g., Sn).

[0052] The conductive layer 21 contacts the encapsulations 12 and 14 and the sidewalls of the substrate 10. The conductive layer 21 can be used as a shielding layer to improve electromagnetic interference (EMI) shielding. In the spirit of this disclosure, the conductive layer 21 can be added as referenced. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 4B or Figure 4C The structure that is described and explained.

[0053] Figure 2FThis is an enlarged cross-sectional view of a portion of a semiconductor packaging device 2”' according to some embodiments of the present disclosure. Substrate 10 includes a dielectric layer 10i. The dielectric layer 10i partially covers a conductive pad 10p. The dielectric layer 10i is spaced apart from an electrical contact 25”. Encapsulation 14 contacts the dielectric layer 10i and the conductive pad 10p. Encapsulation 14 may contact the electrical contact 25”.

[0054] The conductive pad 10p is partially exposed from the dielectric layer 10i. The conductive pad 10p is partially exposed from the groove 14c of the encapsulation body 14. The electrical contact 25” is at least partially disposed within the groove 14c and on a portion of the conductive pad 10p.

[0055] Figure 3A This is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to... Figure 1A The semiconductor device package 1 is an exception in that the electrical contacts 35 of the semiconductor device package 3 are an entire high-melting-point metal ball (e.g., a copper ball or a high-melting-point solder ball).

[0056] Encapsulation 14 covers or encapsulates a portion of electrical contact 35. Encapsulation 14 partially exposes another portion of electrical contact 35. The portion of electrical contact 35 is a high-melting-point portion. Solder paste 36 is disposed on the exposed portion of electrical contact 35 to provide electrical connection. Solder paste 36 may act as a conductive pad. Solder paste 36 prevents oxidation of electrical contact 35 and facilitates connection between semiconductor device package 3 and any other device or component. Encapsulation 14 includes recesses 14c to receive electrical contact 35 and solder paste 36. Encapsulation 14 is spaced apart from solder paste 36.

[0057] Figure 3B This is an enlarged cross-sectional view of a portion of a semiconductor packaging device 3 according to some embodiments of the present disclosure. The electrical contact 35 may be a copper ball. In some embodiments, the electrical contact 35 may be covered by a Ni layer. In some embodiments, the thickness of the Ni layer is about 1 μm. The electrical contact 35 is connected to the conductive pad 10p of the substrate 10 via solder paste 35s. The thickness of the electrical contact 35 exposed from the encapsulation 14 is less than the radius of the electrical contact 35.

[0058] Substrate 10 includes a dielectric layer 10i. The dielectric layer 10i partially covers the conductive pad 10p. The dielectric layer 10i is spaced apart from the solder paste 35s and the electrical contact 35. Encapsulation 14 is in contact with the dielectric layer 10i, the conductive pad 10p, the solder paste 35s, and the electrical contact 35. Encapsulation 14 is in contact with the high-melting-point portion of the electrical contact 35.

[0059] The diameter of the electrical contact 35 is equal to or less than the thickness of the package 14. The electrical contact 35 may not protrude beyond the surface 142 of the package 14 to provide electrical connection. Therefore, solder paste 36 (e.g., solder pads) can be formed on the electrical contact 35 to prevent oxidation of the electrical contact 35 and to provide better electrical connection between the semiconductor device package 3 and any other device or component. This arrangement reduces the size of the electrical contact 35, making it suitable for fine-pitch connections.

[0060] Figure 3C This is an enlarged cross-sectional view of a portion of a semiconductor package 3' according to some embodiments of the present disclosure. The semiconductor package 3' is similar to... Figure 3B The semiconductor device package 3 is an exception in that solder paste 35's completely covers the conductive pad 10'p of the substrate 10'. The substrate 10' contains a dielectric layer 10'i. The dielectric layer 10'i is spaced apart from the solder paste 35's. The solder paste 35's is partially exposed by the recess 14c of the encapsulation 14.

[0061] Encapsulation 14 contacts the dielectric layer 10'i and solder paste 35's. Encapsulation 14 contacts the electrical contact 35. In some embodiments, encapsulation 14 is spaced apart from the electrical contact 35.

[0062] In some embodiments, solder paste may be formed on electrical contacts 35 as needed to prevent oxidation.

[0063] Figure 4A This is a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. The semiconductor device package 4 is similar to... Figure 1A The semiconductor device package 1 is an exception in that the electrical contact 45 is an entire metal sphere and the encapsulation 44 has a stepped profile.

[0064] Encapsulation 44 is disposed on the lower surface 102 of substrate 10 to cover or encapsulate electronic component 13. Encapsulation 44 includes an upper surface 441, a lower surface 442 opposite to the upper surface 441, and a lower surface 443 between the upper surface 441 and the lower surface 442. The distance between the lower surface 442 of encapsulation 44 and the lower surface 102 of substrate 10 is greater than the distance between the lower surface 443 of encapsulation 44 and the lower surface 102 of substrate 10.

[0065] Electrical contacts 45 are placed on solder paste 45s. Electrical contacts 45 are exposed by a capsule 44. The thickness of the capsule 44 (e.g., the distance between the upper surface 441 and the lower surface 443) can be flexibly adjusted according to different design requirements.

[0066] Electrical contact 45 contains copper (Cu), an alloy (e.g., CuAg or CuAu), or a high-melting-point welding material (e.g., high-melting-point Sn).

[0067] Figure 4B This is a cross-sectional view of a semiconductor device package 4' according to some embodiments of the present disclosure. The semiconductor device package 4' is similar to... Figure 4A The semiconductor device package 4 is an exception in that the surface 131 of the electronic component 13 is exposed by the encapsulation 44. The surface 131 of the electronic component 13 is substantially coplanar with the lower surface 442 of the encapsulation 44.

[0068] Figure 4C This is a cross-sectional view of a semiconductor device package 4” according to some embodiments of the present disclosure. The semiconductor device package 4” is similar to Figure 4A The semiconductor device package 4 is an exception in that the electrical contact 45' contains solder material. The electrical contact 45' is disposed on the conductive pad 10p. The electrical contact 45' contacts the substrate 10 and the encapsulation 44. The electrical contact 45' is integrally formed.

[0069] Figures 5A to 5C Some embodiments of a method for manufacturing a semiconductor device package 1 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0070] refer to Figure 5A A method for manufacturing a semiconductor device package 1 includes providing a substrate 10. Solder paste 15s is disposed on the substrate 10. Electronic components 11a and 11b are disposed on an upper surface 101 of the substrate 10. Electronic component 13 and a metal ball 15' are disposed on a lower surface 102 of the substrate 10. The metal ball 15' is disposed on the solder paste 15s. In some embodiments, the metal ball 15' may be formed by drop balling, screen printing, electroplating, or any other suitable operation. Encapsulations 12 and 14 are formed on the upper surface 101 and lower surface 102 of the substrate 10, respectively, to adequately cover the electronic components 11a, 11b, and 13 and the metal ball 15'. In some embodiments, encapsulations 12 and 14 are formed in a single molding operation. Alternatively, encapsulations 12 and 14 may be formed in separate molding operations.

[0071] In some embodiments, the metal ball 15' is formed of or contains copper (Cu), an alloy (e.g., CuAg or CuAu), or a high-melting-point soldering material (e.g., high-melting-point Sn). The melting point of the metal ball 15' is greater than that of the solder paste 15s. The metal ball 15' will not be affected by reflow operations or any subsequent high-temperature operations.

[0072] refer to Figure 5BA portion of the encapsulant 14 and the metal ball 15' is removed to form the electrical contact 15 and expose the back side 131 of the electronic component 13. In some embodiments, the encapsulant 14 and the metal ball 15' are removed by, for example, a grinding operation or any other suitable operation. In some embodiments, half of the metal ball 15' is removed. Removing a portion of the encapsulant 14 and the solder ball 15' can promote uniformity of the thickness of the encapsulant 14. For example, the uniformity of the thickness of the encapsulant 14 can be improved from + / -30 μm to + / -10 μm. Furthermore, no residual resin will remain on the electronic component 13. The ground surface 151 of the electrical contact 15 has an interface with the exposed grain. In some embodiments, the electrical contact 15 and the solder paste 16, which contain different materials, can exhibit different colors at the interface. The electrical contact 15 includes a high-melting-point portion. The melting point of the high-melting-point portion of the electrical contact 15 is greater than the melting point of the solder paste 15s.

[0073] refer to Figure 5C The distance between the lower surface 102 of the substrate 10 and the polished surface 151 of the electrical contact 15 can be equal to, less than, or greater than the radius of the entire metal sphere. Solder paste 16 is formed on the polished surface 151 of the electrical contact 15 to form a shape such that... Figure 1A The semiconductor device package 1 shown is illustrated. In some embodiments, solder paste 16 can be formed by printing. In some embodiments, the thickness of the semiconductor device package 1 can be reduced to 0.7 mm or less compared to existing double-sided molding modules. Additionally, the bottom molding cover can be reduced (e.g., from 180 μm to 80 μm). Solder paste 15s expands onto the electrical contacts 15 during hot operation. Solder paste 16 expands onto the electrical contacts 15 during hot operation.

[0074] Figures 6A to 6C Some embodiments of a method for manufacturing a semiconductor device package 2 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0075] refer to Figure 6A A substrate 10 is provided. Solder paste 25s is disposed on the substrate 10. Electronic components 11a and 11b are disposed on the upper surface 101 of the substrate 10. Electronic component 13 and solder paste 25s are disposed on the lower surface 102 of the substrate 10. Solder paste 25s is disposed on a conductive pad 10p. Encapsulants 12 and 14 are formed on the upper surface 101 and lower surface 102 of the substrate 10 to adequately cover electronic components 11a, 11b, and 13 and solder paste 25s. In some embodiments, encapsulants 12 and 14 are formed in a single molding operation. Alternatively, encapsulants 12 and 14 may be formed in separate molding operations. In some embodiments, a polishing operation may be further performed to expose the back side 131 of electronic component 13.

[0076] refer to Figure 6BOne or more grooves 14c are formed to penetrate the encapsulation 14 to expose the solder paste 25s. In some embodiments, the grooves 14c can be formed by laser cutting or any other suitable operation. Since the electrical contacts 25 to be formed in the grooves 14c will not be affected by the reflow operation, the size of the grooves 14c can be as small as possible. Therefore, the offset window for operation can be increased.

[0077] refer to Figure 6C Electrical contact 25 is formed within groove 14c to form as shown. Figure 2A The semiconductor device package 2 shown is illustrated. A conductive layer 21 is disposed on the encapsulation bodies 12 and 14 and a portion of the substrate 10. In some embodiments, electrical contacts 25 are formed by drop balls. Solder paste 25s bonds the electrical contacts 25 to the conductive pads 10p. The electrical contacts 25 extend beyond the lower surface 142 of the encapsulation body 14. In some embodiments, solder paste may be formed on the electrical contacts 25 as needed to prevent oxidation. The solder paste 25s expands onto the electrical contacts 25 during thermal operation.

[0078] Electrical contact 25 includes a high-melting-point portion. The melting point of the high-melting-point portion of electrical contact 25 is greater than the melting point of solder paste 25s.

[0079] In the spirit of this disclosure, Figures 6A to 6C The operation can be applied to, for example, reference Figures 2C to 2E The encapsulation structure described and illustrated.

[0080] Figures 7A to 7D Some embodiments of a method for manufacturing a semiconductor device package 3 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0081] refer to Figure 7A A method for manufacturing a semiconductor device package 3 includes providing a substrate 10. Solder paste 35s is disposed on the substrate 10. Electronic components 11a and 11b are disposed on an upper surface 101 of the substrate 10. Electronic component 13 and electrical contact 35 are disposed on a lower surface 102 of the substrate 10. Electrical contact 35 is disposed on solder paste 35s. Encapsulation 14 is formed on the lower surface 102 of the substrate 10 to adequately cover electronic component 13 and electrical contact 35. In some embodiments, encapsulations 12 and 14 are formed in a single molding operation. Alternatively, encapsulations 12 and 14 may be formed in separate molding operations.

[0082] Electrical contact 35 includes a high-melting-point portion. The melting point of the high-melting-point portion of electrical contact 35 is greater than the melting point of solder paste 35s.

[0083] refer to Figure 7BA portion of the encapsulation 14 is removed to expose the back side 131 of the electronic component 13. In some embodiments, the encapsulation 14 is removed by, for example, a grinding operation or any other suitable operation. The electrical contacts 35 remain covered and encapsulated by the encapsulation 14.

[0084] refer to Figure 7C One or more grooves 14c are formed to expose electrical contacts 35. In some embodiments, the grooves 14c may be formed by laser cutting or any other suitable operation.

[0085] refer to Figure 7D Solder paste 36 is formed by printing to cover the exposed portion of electrical contacts 35. Solder paste 36 prevents oxidation of electrical contacts 35 and provides better electrical connection between the semiconductor device package 3 and any other device or component. Solder paste 35 expands onto electrical contacts 35 during hot operation.

[0086] Figures 8A to 8B Some embodiments of a method for manufacturing a semiconductor device package 4 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0087] refer to Figure 8A A method for manufacturing a semiconductor device package 4 includes providing a substrate 10. Solder paste 45s is disposed on the substrate 10. Electronic components 11a and 11b are disposed on the upper surface 101 of the substrate 10. Electronic component 13 and electrical contacts 45 are disposed on the lower surface 102 of the substrate 10. Electrical contacts 45 are disposed on solder paste 45s. Solder balls 45 may be formed by drop balling, screen printing, electroplating, or any other suitable operation. Encapsulation 44 is formed on the lower surface 102 of the substrate 10 to adequately cover the electronic components 13 and electrical contacts 45. In some embodiments, encapsulations 12 and 44 are formed in a single molding operation. Alternatively, encapsulations 12 and 44 may be formed in separate molding operations.

[0088] Electrical contact 45 includes a high-melting-point portion. The melting point of the high-melting-point portion of electrical contact 45 is greater than the melting point of solder paste 45s.

[0089] refer to Figure 8B Remove a portion of the capsule seal 44 to partially expose the electrical contacts 45 to form Figure 4AThe semiconductor device package 4 is described. The encapsulation 44 includes a stepped profile. In some embodiments, the encapsulation 44 can be removed by laser polishing or plasma etching. The thickness of the encapsulation 44 can be flexibly defined. For example, the distance between surfaces 441 and 442 of the encapsulation 44 can be adjusted. The distance between surfaces 441 and 443 of the encapsulation 44 can also be adjusted. In some embodiments, solder paste can be formed on the electrical contacts 45 as needed to prevent oxidation. The solder paste 45s expands onto the electrical contacts 45 during thermal operation.

[0090] As used herein and unless otherwise defined, the terms “substantially,” “substantially,” “approximately,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation occurs precisely or is very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces lying within a micrometer along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane.

[0091] Unless the context clearly specifies otherwise, the singular terms “a” and “described” as used herein may include multiple indicators. In the description of some embodiments, a component positioned “on” or “above” another component may encompass a situation where the preceding component is directly on the following component (e.g., in physical contact with the following component) and a situation where one or more intervening components are located between the preceding and following components.

[0092] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternatives may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and limitations, artistic representations in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt specific circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless specifically indicated herein.

Claims

1. A semiconductor device package comprising: A substrate comprising a conductive pad; A first solder paste is applied to the conductive pad and partially exposes the conductive pad; An electrical contact is disposed on the first solder paste, the electrical contact having a surface facing away from the substrate, wherein the electrical contact comprises a copper alloy or a high-melting-point soldering material, the melting point of the electrical contact being greater than the melting point of the first solder paste, so that the electrical contact can withstand the temperature of a reflow operation. A second solder paste is applied to the surface of the electrical contact to prevent oxidation of the electrical contact. and A first encapsulation body encapsulates a portion of the electrical contact, contacts the conductive pad, and exposes the surface of the electrical contact. The first encapsulation body includes a first surface facing the substrate and a second surface opposite to the first surface, wherein the second surface of the first encapsulation body is exposed to air. The electrical contact is formed by removing a portion of a metal sphere. The width of the surface of the electrical contact is greater than the radius of the metal sphere but smaller than its diameter. The first encapsulation body covers more than half the height of the entire metal sphere to form a locking structure. The structure of the first solder paste, the electrical contact, and the second solder paste is used to provide electrical connection between the semiconductor device package and other external devices.

2. The semiconductor device package of claim 1, wherein the surface of the electrical contact is substantially coplanar with the second surface of the first encapsulation, the substrate further includes an insulating layer partially covering the conductive pad, and the first solder paste is spaced apart from the insulating layer of the substrate by the first encapsulation, wherein the electrical contact is a copper ball and the second solder paste is a nickel layer, the copper ball being covered by the nickel layer having a thickness of 1 μm, the diameter of the electrical contact being equal to or less than the thickness of the first encapsulation, and the electrical contact not protruding beyond the second surface of the first encapsulation.

3. The semiconductor device package of claim 1, wherein the high melting point solder material is a high melting point Sn, and the width of the electrical contact is greater than the width of the first solder paste, wherein the width of the second solder paste is greater than the width of the first solder paste, and wherein the first encapsulation includes a groove that accommodates the exposed surface of the electrical contact and the second solder paste covering the exposed surface, and the first encapsulation is spaced apart from the second solder paste.

4. The semiconductor device package of claim 1, wherein the second solder paste extends over the electrical contacts and the first encapsulation, and the second solder paste partially covers the second surface of the first encapsulation.

5. The semiconductor device package of claim 1, wherein the melting point of the second solder paste is lower than the melting point of the electrical contact, and the second solder paste completely covers the exposed portion of the electrical contact.

6. The semiconductor device package of claim 1, wherein the first encapsulation includes a recess to receive the electrical contact.

7. The semiconductor device package of claim 6, wherein the first encapsulation is spaced apart from the second solder paste, and the second solder paste protrudes from the first encapsulation.

8. The semiconductor device package of claim 6, wherein the substrate further comprises an insulating layer partially covering the conductive pad and the conductive pad has a portion of the insulating layer, wherein the thickness of the electrical contact exposed from the first encapsulation is less than the radius of the electrical contact and greater than the width of the portion of the conductive pad.

9. The semiconductor device package of claim 6, wherein the recess exposes at least a portion of the conductive pad of the substrate.

10. The semiconductor device package of claim 6, wherein the first solder paste partially covers the conductive pad of the substrate, the first solder paste being spaced apart from the first encapsulation.

11. The semiconductor device package of claim 10, further comprising an insulating layer covering a portion of the conductive pad, wherein the conductive pad is exposed to air.

12. The semiconductor device package of claim 1, further comprising a first electronic component disposed on a first surface of the substrate and arranged side-by-side with the electrical contact, wherein the back surface of the first electronic component is substantially coplanar with the second surface of the first encapsulation, thereby exposing the back surface of the first electronic component to air.

13. The semiconductor device package of claim 1, further comprising: A second electronic component is disposed on a second surface of the substrate opposite to the first surface; and The second encapsulation body encapsulates the second electronic component.

14. A semiconductor device package comprising: A substrate comprising a conductive pad; A first solder paste is applied to the conductive pad and partially exposes the conductive pad; An electrical contact is disposed on the first solder paste, wherein the electrical contact comprises a copper alloy or a high-melting-point soldering material, the electrical contact includes a high-melting-point portion, and the melting point of the high-melting-point portion of the electrical contact is greater than the melting point of the first solder paste, so that the electrical contact can withstand the temperature of the reflow operation. A second solder paste is applied to the exposed portion of the electrical contact to prevent oxidation of the electrical contact. and An encapsulation body that encapsulates the electrical contact, wherein the encapsulation body is in contact with the high-melting-point portion of the electrical contact. The electrical contact is formed by removing a portion of a metal sphere. The width of the exposed portion of the electrical contact is greater than the radius of the metal sphere but smaller than its diameter. The encapsulation body covers more than half the height of the entire metal sphere to form a locking structure. The structure of the first solder paste, the electrical contact, and the second solder paste is used to provide electrical connection between the semiconductor device package and other external devices.

15. The semiconductor device package of claim 14, wherein the high-melting-point solder material is a high-melting-point Sn, the substrate further includes an insulating layer partially covering the conductive pad, and the first solder paste is spaced apart from the insulating layer of the substrate by the encapsulation, wherein the width of the second solder paste is greater than the width of the first solder paste, and wherein the encapsulation includes a groove that receives the exposed portion of the electrical contact and the second solder paste covering the exposed portion, and the encapsulation is spaced apart from the second solder paste.

16. The semiconductor device package of claim 14, further comprising an electronic component disposed on a first surface of the substrate and arranged side-by-side with the electrical contact, wherein the melting point of the second solder paste is lower than that of the electrical contact, the second solder paste extends over the electrical contact and the encapsulation, and the second solder paste partially covers a second surface of the encapsulation, wherein the electrical contact is a copper ball and the second solder paste is a nickel layer, the copper ball being covered by the nickel layer having a thickness of 1 μm, the diameter of the electrical contact being equal to or less than the thickness of the encapsulation, and the electrical contact not protruding beyond the second surface of the encapsulation.

17. The semiconductor device package of claim 16, wherein the encapsulation includes a first surface facing the substrate and a second surface opposite to the first surface, the second surface of the encapsulation at least partially exposing the surface of the electrical contact, the surface of the electrical contact being substantially coplanar with the second surface of the encapsulation, and the back surface of the electronic component being substantially coplanar with the second surface of the encapsulation, thereby exposing the back surface of the electronic component to air.

18. The semiconductor device package of claim 17, wherein the encapsulation includes a recess to receive an exposed portion of the surface of the electrical contact, and the width of the electrical contact is greater than the width of the first solder paste.

19. The semiconductor device package of claim 18, wherein the thickness of the electrical contact exposed from the encapsulation is less than the radius of the electrical contact, and wherein the exposed portion of the electrical contact is completely covered by the second solder paste.

20. A method for manufacturing a semiconductor packaging device, comprising: The first solder paste and electronic components are placed on the substrate; An electrical contact is placed on the first solder paste, wherein the electrical contact comprises a copper alloy or a high-melting-point soldering material, the electrical contact includes a high-melting-point portion, the melting point of the high-melting-point portion of the electrical contact being greater than the melting point of the first solder paste, so that the electrical contact can withstand the temperature of the reflow operation, and the electronic component and the electrical contact are arranged side by side. A capsule is formed to encapsulate the electrical contact, and the capsule is in contact with the high-melting-point portion of the electrical contact. A portion of the encapsulation is removed by laser excision to form a groove, thereby exposing a portion of the electrical contacts. and Apply the second solder paste to the electrical contact. The electrical contact is formed by removing a portion of a metal sphere. The width of the exposed portion of the electrical contact is greater than the radius of the metal sphere but smaller than its diameter. Furthermore, the encapsulation covers more than half the height of the entire metal sphere to form a locking structure. The structure of the first solder paste, the electrical contact, and the second solder paste is used to provide electrical connections between the semiconductor packaging device and other external devices.

21. The method of claim 20, further comprising heating the first solder paste to spread the first solder paste onto the electrical contact, the width of the electrical contact being greater than the width of the heated first solder paste, and the width of the second solder paste being greater than the width of the first solder paste, wherein the high-melting-point soldering material is a high-melting-point Sn, and wherein the groove of the encapsulation contains the exposed portion of the electrical contact and covers the exposed portion with the second solder paste, and the encapsulation is spaced apart from the second solder paste.

22. The method of claim 21, further comprising heating the second solder paste to spread the second solder paste onto the electrical contact, the width of the electrical contact being greater than the width of the heated second solder paste.

23. The method of claim 20, wherein after the removal operation, the back surface of the electronic component is substantially coplanar with the surface of the encapsulation, thereby exposing the back surface of the electronic component to air, and wherein the electrical contacts are copper balls and the second solder paste is a nickel layer, the copper balls being covered by the nickel layer having a thickness of 1 μm, the diameter of the electrical contacts being equal to or less than the thickness of the encapsulation, and the electrical contacts not protruding beyond the surface of the encapsulation.

24. The method of claim 23, wherein after the second solder paste is applied to the electrical contact, the second solder paste extends over the electrical contact and the encapsulation and partially covers the surface of the encapsulation.

25. A semiconductor packaging apparatus, comprising: A substrate comprising a first surface, a second surface opposite to the first surface, a conductive pad disposed adjacent to the first surface, and an insulating layer disposed on the conductive pad, wherein the insulating layer exposes a portion of the conductive pad; A first encapsulation body encapsulates the insulating layer, wherein the first encapsulation body includes a groove that exposes the portion of the conductive pad; An electrical contact, at least partially disposed within the groove and on said portion of the gasket, wherein the electrical contact comprises a copper alloy or a high-melting-point welding material; A first solder paste is disposed between the conductive pad and the electrical contact and partially exposes the conductive pad, wherein the melting point of the electrical contact is greater than the melting point of the first solder paste, so that the electrical contact can withstand the temperature of the reflow operation. and A second solder paste is applied to the exposed portion of the electrical contacts to prevent oxidation of the contacts. The electrical contact is formed by removing a portion of a metal sphere. The width of the surface of the electrical contact exposed from the groove is greater than the radius of the metal sphere but smaller than its diameter. Furthermore, the first encapsulation body covers more than half the height of the entire metal sphere to form a locking structure. The structure of the first solder paste, the electrical contact, and the second solder paste is used to provide electrical connections between the semiconductor packaging device and other external devices.

26. The semiconductor packaging apparatus of claim 25, wherein the first encapsulation body contacts the portion of the conductive pad, wherein the width of the electrical contact is greater than the width of the first solder paste, the width of the second solder paste is greater than the width of the first solder paste, and the conductive pad is exposed to air, wherein the high-melting-point soldering material is a high-melting-point Sn, and wherein the groove of the first encapsulation body accommodates the exposed surface of the electrical contact and the second solder paste covering the exposed surface, and the first encapsulation body is spaced apart from the second solder paste.

27. The semiconductor packaging apparatus of claim 26, further comprising an electronic component disposed on the first surface of the substrate and disposed alongside the electrical contact, wherein the electrical contact is a copper ball and the second solder paste is a nickel layer, the copper ball is covered by the nickel layer having a thickness of 1 μm, the diameter of the electrical contact is equal to or less than the thickness of the first encapsulation, and the electrical contact does not protrude beyond the second surface of the first encapsulation.

28. The semiconductor packaging apparatus of claim 25, further comprising a second encapsulation body encapsulating the second surface of the substrate.

29. The semiconductor packaging apparatus of claim 28, further comprising a conductive layer disposed on the first encapsulation, the second encapsulation, and a portion of the substrate.

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