Semiconductor packaging device and manufacturing method thereof

Abstract

A semiconductor packaging device includes a substrate, an electronic component, and a thermally conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermally conductive layer is disposed above the first surface of the electronic component. The thermally conductive layer includes a plurality of portions spaced apart from each other.

Description

Technical Field

[0001] This invention generally relates to semiconductor packaging devices, and more specifically, to semiconductor packaging devices including thermally conductive layers and methods of manufacturing the same. Background Technology

[0002] Thermal interface materials (TIMs) are typically used between semiconductor packages and motherboards to dissipate heat generated by the semiconductor package, where the package and motherboard are connected via input / output (I / O) connectors such as solder balls, and the TIM is attached to the motherboard's heat dissipation structure. However, achieving proper alignment between the TIM and the motherboard's heat dissipation structure, as well as high consistency between the TIM and the I / O connectors, can be challenging. Furthermore, delamination between the TIM and the motherboard can occur due to a mismatch in the coefficients of thermal expansion (CTE) during temperature cycling across various manufacturing processes. Summary of the Invention

[0003] In one aspect, according to some embodiments, a semiconductor packaging device includes a substrate, an electronic component, and a thermally conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermally conductive layer is disposed above the first surface of the electronic component. The thermally conductive layer includes a plurality of portions spaced apart from each other.

[0004] In another embodiment, according to some embodiments, the electrical device includes a motherboard, a packaging device, and a thermally conductive material. The packaging device is disposed on the motherboard and includes a substrate, a first electronic component, and a thermally conductive layer. The substrate includes a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the substrate and includes a first surface facing the motherboard and a second surface facing the substrate. The thermally conductive layer is disposed above the first surface of the first electronic component. The thermally conductive layer includes a plurality of portions spaced apart from each other. The thermally conductive material connects the motherboard to the packaging device.

[0005] In another aspect, according to some embodiments, a method of manufacturing an electrical device includes: forming a thermally conductive layer on an electronic component; providing a motherboard; providing a plurality of flowable thermally conductive materials between the thermally conductive layer and the motherboard; and connecting the thermally conductive layer to the motherboard via the flowable thermally conductive materials. The flowable thermally conductive materials form non-signal emission areas. Attached Figure Description

[0006] The various aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of features depicted in the drawings may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A Cross-sectional views of an electrical device according to some embodiments of the present invention are shown.

[0008] Figure 1B A cross-sectional view illustrating a portion of an electrical device according to some embodiments of the present invention.

[0009] Figure 1C A cross-sectional view illustrating a portion of an electrical device according to some embodiments of the present invention.

[0010] Figure 1D A cross-sectional view illustrating a portion of an electrical device according to some embodiments of the present invention.

[0011] Figure 1D A cross-sectional view illustrating a portion of an electrical device according to some embodiments of the present invention.

[0012] Figure 1E Cross-sectional views of an electrical device according to some embodiments of the present invention are shown.

[0013] Figure 1F A cross-sectional view illustrating an exemplary configuration of a portion of a semiconductor packaging apparatus according to some embodiments of the present invention.

[0014] Figure 1G A cross-sectional view illustrating an exemplary configuration of a portion of a semiconductor packaging apparatus according to some embodiments of the present invention.

[0015] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Figure 2I This is a cross-sectional view of an electrical device manufactured at various stages according to some embodiments of the present invention.

[0016] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a cross-sectional view of a semiconductor packaging device manufactured at various stages according to some embodiments of the present invention.

[0017] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. The invention will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0018] According to some embodiments of the present invention, by means of a thermally conductive layer comprising multiple segmented (or spaced) portions and provided between the semiconductor package device and the motherboard, the alignment between the thermally conductive layer and the heat dissipation structure of the motherboard can be improved, and the high consistency between the thermally conductive layer and other I / O connections connecting the motherboard and the semiconductor package device can also be improved. Furthermore, the enhanced structural strength can reduce or prevent delamination between the semiconductor package device and the motherboard.

[0019] Figure 1A A cross-sectional view of an electrical device 1a according to some embodiments of the present invention is shown.

[0020] The electrical device 1a includes a semiconductor packaging device 1a1, a motherboard 50, and a thermally conductive material 60. The semiconductor packaging device 1a1 is mounted on the motherboard 50 and connected to the motherboard 50 via the thermally conductive material 60 and a connecting element 95.

[0021] The semiconductor packaging device 1a1 includes a substrate 10, electronic components 20, 70 and 75, a thermally conductive layer 30, encapsulants 40 and 80, an antenna device 90, and a connecting element 95.

[0022] Substrate 10 includes surface 101 and surface 102 opposite to surface 101. Substrate 10 may contain, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. Substrate 10 may contain interconnect structures, such as a redistribution layer (RDL) or a grounding element.

[0023] Electronic component 20 is disposed on surface 101 of substrate 10 and includes surface 201 and surface 202 opposite to surface 201. Surface 201 faces the motherboard 50 or faces away from substrate 10. Surface 202 faces substrate 10. In some embodiments, surface 202 may be an active surface on which circuitry is disposed for signal transmission (e.g., between electronic component 20 and substrate 10), and surface 201 may be a back-side surface. Figure 1A In the embodiment shown, the surface 201 of the electronic component 20 is exposed from the encapsulation 40.

[0024] Electronic component 20 may be a chip or die containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0025] The thermally conductive layer 30 is disposed near the surface 201 of the electronic component 20, for example, on or above the surface 201 of the electronic component 20. Figure 1AIn the embodiment shown, the thermally conductive layer 30 contacts the surface 201 of the electronic component 20. The thermally conductive layer 30 includes a plurality of portions 35 spaced apart from each other. The portions 35 of the thermally conductive layer 30 may be electrically insulated from each other. In some embodiments, the thermally conductive layer 30 includes an epoxy resin and / or a thermally conductive filler. In some embodiments, the thermally conductive layer 30 includes a metal; for example, the portions 35 may include a metal platform. The portions 35 may include laminates of different materials, such as titanium (Ti), tantalum (Ta), chromium (Cr), copper (Cu), nickel (Ni), gold (Au), and silver (Ag). For example, the portions 35 may include layers of Ti, Ta, or Cr and layers of Cu, Ni, and / or Au laminated together. In some embodiments, the portions 35 may be or may include a Cu paste and / or an Au paste. In some embodiments, the thermally conductive layer 30 includes a material suitable for solder wetting.

[0026] Encapsulation 40 is disposed on or covers surface 101 of substrate 10. Encapsulation 40 covers, encapsulates, or surrounds electronic component 20 and connection element 95. Encapsulation 40 exposes a portion of each of the connection elements 95 for electrical connection. Encapsulation 40 may comprise epoxy resin with filler, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material having silicone dispersed therein, or combinations thereof.

[0027] Electronic components 70 and 75 are disposed on surface 102 of substrate 10. Electronic components 70 and / or 75 may be chips or dies containing a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. Integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0028] Encapsulant 80 is disposed on or covers surface 102 of substrate 10. Encapsulant 80 covers, encapsulates, or surrounds electronic components 70 and 75. Encapsulant 80 may comprise epoxy resin with filler, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material having silicone dispersed therein, or combinations thereof.

[0029] The antenna device 90 is disposed near the surface 102 of the substrate 10, for example, the antenna device 90 is disposed on the surface 102 of the substrate 10. Figure 1A In the embodiment shown, the antenna device 90 includes an antenna pattern comprising a plurality of portions 93.

[0030] Connecting element 95 is disposed on surface 101 of substrate 10 and is surrounded or encapsulated by encapsulant 40. Figure 1AIn the embodiments shown, each connection element 95 has a portion exposed from the encapsulation 40 and connected to a pad 55 of the motherboard 50. Connection element 95 may include solder balls. In some embodiments, connection element 95 may serve as an I / O connection element between the semiconductor package 1a1 and the motherboard 50 for signal transmission. For example, connection element 95 may be a portion of a substrate insert containing circuitry and pads on its surface. In some embodiments, connection element 95 may be or may include a through-molded via (TMV) filled with a conductive material. In some embodiments, connection element 95 may be or may include a conductive pillar, which may be formed by, for example, plating to form the pillar and molding or encapsulating the pillar and exposing it.

[0031] The motherboard 50 may include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The motherboard 50 may include interconnect structures, such as a redistribution layer (RDL) or grounding elements.

[0032] Thermally conductive material 60 is disposed between the semiconductor packaging device 1a1 and the motherboard 50. For example... Figure 1A As shown, thermally conductive material 60 is disposed between the thermally conductive layer 30 of the semiconductor package device 1a1 and the pad 55 of the motherboard 50. The thermally conductive material 60 contacts the surface 301 of the thermally conductive layer 30. In some embodiments, the lateral surface 303 of the thermally conductive layer 30 may be exposed from the electronic component 20 or the encapsulation 40 and may contact or be covered by the thermally conductive material 60. The thermally conductive material 60 may contain solder. In some embodiments, the surface 601 of the thermally conductive material 60 is coplanar with the surface 951 of the connecting element 95.

[0033] In some embodiments, when a semiconductor package 1a1 is mounted on a motherboard 50, a thermally conductive layer 30 comprising multiple segmented or spaced portions 35 can improve or facilitate alignment between the thermally conductive layer 30 (or the semiconductor package 1a1) and the thermally conductive material 60 (which is a heat dissipation structure) of the motherboard 50. Additionally, it can improve the high consistency or high control between the thermally conductive layer 30 (or the thermally conductive material 60) and the connecting element 95, which can prevent or reduce delamination between the semiconductor package 1a1 and the motherboard 50. In some embodiments, the separated portions 35 of the thermally conductive layer 30 can prevent heat accumulation or heat concentration and improve reliability. When the thermally conductive layer 30 is a single piece, a mismatch in the coefficient of thermal expansion (CTE) between the thermally conductive layer 30 and the thermally conductive material 60 and / or the motherboard 50 can cause misalignment or high inconsistency. In some embodiments, a single-piece thermally conductive layer 30 can cause relatively large areas of wetting between the connecting element 60 (which may be a single piece) and the thermally conductive layer 30 during, for example, a reflow process. Extensive wetting may cause the package to become misaligned / bent / tilted, making the gap between one or more connecting elements 95 and the motherboard 50 too far for the connecting element 95 and the motherboard 50 to be connected, which may cause functional failure.

[0034] Figure 1B A cross-sectional view illustrating a portion of an electrical device 1b according to some embodiments of the present invention is provided. The electrical device 1b may be used with... Figure 1A The electrical devices 1a in the description are the same or similar, but have some differences as described below.

[0035] The surface 201 of the electronic component 20 and the lateral surface 303 of a portion 35 of the thermally conductive layer 30 are covered or encapsulated by an encapsulant 40. The portion 35 of the thermally conductive layer 30 may contain epoxy resin, which may improve the adhesion between the portion 35 and the encapsulant 40 (which may also contain epoxy resin) or between the portion 35 and the electronic component 20. The lateral surface 603 of the thermally conductive material 60 may be partially covered by the encapsulant 40. A connecting element 65 is disposed between the connecting element 95 and the motherboard 50 and between the thermally conductive material 60 and the motherboard 50. The connecting element 65 may have similar properties to the connecting element 95 or the thermally conductive material 60 and may contain solder. Figure 1B As shown, an antenna device 90 comprising multiple portions (or traces) 93 is disposed near the surface 102 of the substrate 10.

[0036] In some embodiments, the encapsulant 40 may expose a portion of the lateral surface 303 of the thermally conductive layer 30 or a portion of the lateral surface 603 of the thermally conductive material 60. The exposed portions of the lateral surfaces 303 and / or 603 may be wetted or in contact with the connecting element 65. Controlling the amount of exposed portions of the lateral surfaces 303 and / or 603 prevents bridging between adjacent connecting elements 65.

[0037] Figure 1C This illustration shows a cross-sectional view of a portion of an electrical device 1c according to some embodiments of the present invention. The electrical device 1c may be used with... Figure 1B The electrical devices 1b are the same or similar, but have some differences as described below.

[0038] A portion of the lateral surface 303 and the surface 301 of the portion 35 of the conductive layer 30 are exposed from the encapsulation 40. Figure 1C omitted in Figure 1B The conductive material 60 of the electrical device 1b is present. The connecting element 65 contacts the surface 301 of the conductive layer 30. In some embodiments, the connecting element 65 may contact or cover the exposed portion of the lateral surface 303 of the conductive layer 30.

[0039] In some embodiments, the encapsulant 40 may expose a portion of the lateral surface 303 of the portion 35 of the thermally conductive layer 30. The exposed portion of the lateral surface 303 may wet or contact the connecting element 65. Control of the amount of exposed portion of the lateral surface 303 may prevent bridging between adjacent connecting elements 65.

[0040] Figure 1D This illustration shows a cross-sectional view of a portion of an electrical device 1d according to some embodiments of the present invention. The electrical device 1d may be connected to... Figure 1B The electrical devices 1b are the same or similar, but have some differences as described below.

[0041] A portion 35 of the thermally conductive layer 30 is disposed on the surface 401 of the encapsulation 40 and spaced apart from the electronic component 20 by a portion of the encapsulation 40. The lateral surface 303 and the surface 301 of the portion 35 of the conductive layer 30 are exposed from the encapsulation 40. Figure 1D omitted in Figure 1B The conductive material 60 of the electrical device 1b is present. A connecting element 65 contacts the surface 301 of the conductive layer 30. In some embodiments, the connecting element 65 may contact or cover the lateral surface 303 of the conductive layer 30. In some embodiments, a portion 35 of the thermally conductive layer 30 may comprise epoxy resin, which may improve the adhesion between the portion 35 and the encapsulant 40 (which may also comprise epoxy resin).

[0042] Figure 1D A cross-sectional view illustrating a portion of an electrical device 1d according to some embodiments of the present invention. The electrical device 1d' may be used with... Figure 1D The electrical devices 1d in the present invention are the same or similar, but have some differences as described below.

[0043] Wires 25 are positioned to electrically connect electronic component 20 to substrate 10. Figure 1DIn the embodiment shown, surface 201 of electronic component 20 may be an active surface and surface 202 of electronic component 20 may be a back-side surface. Electronic component 20 may be mounted on substrate 10 via die attachment film (DAF).

[0044] Figure 1E A cross-sectional view of an electrical device 1e according to some embodiments of the present invention is shown. The electrical device 1e is similar to... Figure 1A The electrical device 1a in the present invention has some differences as described below.

[0045] Electronic components 70 and 75, encapsulation 80, and antenna assembly 90 are omitted. Antenna assembly 97 is mounted on pad 13 of substrate 10 via connecting element 77. Antenna assembly 97 includes antenna pattern 971. Connecting element 77 may have similar or the same characteristics as connecting element 95.

[0046] Figure 1F A cross-sectional view illustrating an exemplary configuration of a portion of a semiconductor packaging device 1f according to some embodiments of the present invention. The semiconductor packaging device 1f may have... Figure 1B The structure is similar to that in the previous one, except that the motherboard 50 is omitted, and there are some differences described below.

[0047] Figure 1F The electronic component 20 can be embedded in the substrate 10, and the surface 201 of the electronic component 20 is coplanar with the surface 101 of the substrate 10. The connecting element 95 and the thermally conductive material 60 are aligned in the same plane. In some embodiments, the connecting element 95 and the thermally conductive material 60 may have the same or similar size and / or material.

[0048] Figure 1G A cross-sectional view illustrating an exemplary configuration of a portion of a semiconductor packaging device 1g according to some embodiments of the present invention. The semiconductor packaging device 1g may have... Figure 1B The structure is similar to that in the previous one, except that the motherboard 50 is omitted, and there are some differences described below.

[0049] The connecting element 95 includes a connecting element 953 disposed on the surface 101 of the substrate 10 and a connecting element 954 disposed on the surface 201 of the electronic assembly 20. For example... Figure 1G As explained, connecting elements 953 and 954 may have different sizes. However, the end of connecting element 953 facing away from substrate 10 may be coplanar with the end of connecting element 954 facing away from substrate 10.

[0050] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Figure 2I This is a cross-sectional view of an electrical device 2i manufactured at various stages according to some embodiments of the present invention. The figures have been simplified for a better understanding of the various aspects of the invention.

[0051] refer to Figure 2A Electronic component 20 is mounted on carrier CR. Carrier CR may contain glass or other materials. (See reference) Figure 2B Remove a portion of the electronic component 20 to define surface 201, which may be an active or passive surface.

[0052] refer to Figure 2C A thermally conductive layer 30 is disposed on the surface 201 of the electronic component 20, wherein operations such as physical vapor deposition (PVD), lamination, plating, screen printing, and / or curing can be performed. (Reference) Figure 2D A patterned photoresist layer P1 is formed on the thermally conductive layer 30, wherein coating, photolithography, and / or development operations can be performed. A portion of the thermally conductive layer 30 is exposed from the patterned photoresist layer P1.

[0053] refer to Figure 2E The exposed portion of the thermally conductive layer 30 is removed, where an etching operation can be performed. Multiple segments or individual portions 35 are formed to create the thermally conductive layer. A portion of the surface 201 of the exposed electronic component 20 is also exposed. (Reference) Figure 2F Remove the patterned photoresist layer P1, where an etching operation can be performed.

[0054] refer to Figure 2G The carrier CR is removed to expose the surface 202 of the electronic component 20. The surface 202 of the electronic component 20 may be an active surface with circuitry thereon. The electronic component 20 is mounted on the surface 101 of the substrate 10. A connecting element 95 is mounted on the surface 101 of the substrate 10, wherein ball mounting operations can be performed.

[0055] refer to Figure 2H Encapsulation 40 is formed on surface 101 of substrate 10, where molding operations can be performed. Encapsulation 40 surrounds electronic component 20 and connection element 95, and exposes surface 201 of electronic component 20, portion 35 of thermally conductive layer 30 and a portion of each connection element 95.

[0056] refer to Figure 2I , provides motherboard 50. Figure 2HThe structure is mounted on the motherboard 50. A portion 35 of the thermally conductive layer 30 is connected to the motherboard 50 via multiple segmented or individual thermally conductive materials 60, which may be flowable during reflow operation. Because the surface 201 of the electronic component 20 may be an active or passive surface, the thermally conductive material 60 can form a non-signal emission area where no signal emission occurs (e.g., between the electronic component 20 and the motherboard 50). A connecting element 95 is mounted on the motherboard 50 and can be mounted simultaneously with the portion 35 of the thermally conductive layer 30 mounted on the motherboard 50. The electrical device 2i can be connected to... Figure 1A The electrical device 1a is similar or identical to that in the example, except that electronic components 70 and 75, antenna device 90 and encapsulation 80 are omitted.

[0057] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a cross-sectional view of a semiconductor packaging device 3e manufactured at various stages according to some embodiments of the present invention. The figures have been simplified for a better understanding of the various aspects of the invention.

[0058] refer to Figure 3A Electronic component 20 is mounted on carrier CR. Carrier CR may contain glass or other materials. (See reference) Figure 3B Remove a portion of the electronic component 20 to define surface 201, which may be an active or passive surface.

[0059] refer to Figure 3C A mask (or mold) M1 with multiple openings O1 is provided on the surface 201 of the electronic component 20. A thermally conductive layer 30 is printed or screened onto the surface 201 of the electronic component 20 through the mask M1. (Reference) Figure 3D The carrier CR is removed to expose the surface 202 of the electronic component 20. The surface 202 of the electronic component 20 may be an active surface with circuitry thereon. A curing operation can be performed to cure the thermally conductive layer 30.

[0060] refer to Figure 3E Electronic components 20 are mounted on the surface 101 of the substrate 10. Connecting elements 95 are mounted on the surface 101 of the substrate 10, wherein ball-mounting operations are performed. A semiconductor package 3e is formed. The semiconductor package 3e can be similar to... Figure 2G The structure.

[0061] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or where it occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same. For example, "substantially" parallel can refer to an angular variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “basically” vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0062] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces are considered to be coplanar or substantially coplanar. If the difference between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface is considered to be planar or substantially planar.

[0063] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, the phrase “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0064] Although the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the invention. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be drawn to scale. Artistic representations of the invention may differ from actual devices due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A semiconductor packaging device, comprising: Substrate; An electronic component disposed on the substrate, the electronic component including a passive surface facing away from the substrate; A plurality of metal layers spaced apart from each other are disposed on the passive surface of the electronic component, wherein the plurality of metal layers are spaced portions electrically insulated from each other; Multiple solder layers spaced apart from each other, each of the multiple solder layers being disposed on a corresponding one of the multiple metal layers, wherein the solder layer is a flowable thermally conductive material configured to flow during reflow operation; A motherboard connected to the passive surface of the electronic component via the plurality of solder layers and the plurality of metal layers, wherein the motherboard is a printed circuit board including an interconnect structure, the motherboard including a first pad and a second pad, the first pad being in contact with the plurality of solder layers; as well as A connecting element disposed on the substrate, the connecting element connecting the substrate and the second pad of the motherboard; The plurality of metal layers are aligned with the solder layer for conducting heat to the motherboard, and the spaced portions of the metal layers cooperate with the alignment so that the metal layers and the solder layer maintain a high degree of consistency with the connecting elements to avoid delamination between the motherboard and the electronic components.

2. The semiconductor packaging apparatus of claim 1, wherein the plurality of metal layers contact the passive surface of the electronic component, and the plurality of solder layers contact the lateral surface of the first pad.

3. The semiconductor packaging apparatus of claim 1, further comprising an encapsulant covering the substrate and the electronic component, wherein the plurality of metal layers and the plurality of solder layers are not encapsulated by the encapsulant.

4. The semiconductor packaging apparatus of claim 3, wherein the spacer portions of the plurality of metal layers are disposed on the surface of the encapsulation and spaced apart from the passive surface of the electronic component by a portion of the encapsulation, and a first surface and a second surface perpendicular to the first surface of the spacer portions of the plurality of metal layers are exposed from the encapsulation.

5. The semiconductor packaging apparatus of claim 3, wherein the spacer portion of the plurality of metal layers includes a surface facing away from the electronic component and a lateral surface, the encapsulant exposing a portion of the lateral surface of the spacer portion, the portion of the lateral surface and the surface contacting the solder layer.

6. An electrical device comprising: A motherboard, which is a printed circuit board containing interconnect structures, the motherboard including a first pad and a second pad; A packaging device disposed on the motherboard, wherein the packaging device includes: A substrate, comprising a first surface and a second surface opposite to the first surface; A first electronic component is disposed on the first surface of the substrate, the first electronic component including a passive surface facing the motherboard and an active surface facing the substrate. A plurality of metal layers spaced apart from each other are disposed above the passive surface of the first electronic component, wherein the plurality of metal layers are spaced portions electrically insulated from each other. A plurality of first solder layers spaced apart from each other, each of the plurality of first solder layers being disposed on a corresponding one of the plurality of metal layers, a first pad contacting the plurality of first solder layers, wherein the first solder layers are flowable thermally conductive materials configured to flow during reflow operation; and A plurality of second solder layers are disposed on the first surface of the substrate and surround the plurality of first solder layers, the plurality of first solder layers being used for thermal conduction, the plurality of second solder layers being used for electrical connection of the first electronic component and the second pad of the motherboard, and the thickness of one of the plurality of first solder layers being different from the thickness of one of the plurality of second solder layers. The motherboard is connected to the passive surface of the first electronic component via the plurality of first solder layers and the plurality of metal layers, wherein the plurality of metal layers are aligned with the first solder layers for conducting heat to the motherboard, and the spacing portions of the metal layers cooperate with the alignment so that the metal layers and the first solder layers maintain a high degree of consistency with the second solder layer to avoid delamination between the motherboard and the electronic component.

7. The electrical device of claim 6, wherein the first solder layer contact surface faces the surface of the metal layer of the motherboard, and the first solder layer contacts the lateral surface of the metal layer, and the plurality of first solder layers contact the lateral surface of the first pad.

8. The electrical device of claim 6, further comprising a first encapsulator encapsulating the first electronic component, wherein the plurality of metal layers and the plurality of first solder layers are not encapsulated by the first encapsulator.

9. The electrical device of claim 8, further comprising a second electronic component disposed on the second surface of the substrate.

10. The electrical device of claim 9, further comprising a second encapsulation encapsulating the second electronic component.

11. The electrical device according to claim 8, further comprising an antenna arrangement disposed on the second surface of the substrate.

12. The electrical device of claim 11, wherein the antenna device includes an antenna pattern formed on the second surface of the substrate.

13. A method of manufacturing an electrical device, comprising: Provide substrate; An electronic component including a passive surface facing away from the substrate is provided on the substrate, and a plurality of metal layers spaced apart from each other are formed on the passive surface of the electronic component, wherein the plurality of metal layers are spacers that are electrically insulated from each other. A motherboard is provided, wherein the motherboard is a printed circuit board including an interconnect structure, and the motherboard includes a first pad and a second pad; A plurality of solder layers spaced apart from each other are provided between the plurality of metal layers and the motherboard, wherein the solder layers are flowable thermally conductive materials configured to flow during reflow operation; A connecting element is provided, which is disposed on the substrate, the connecting element connecting the substrate and the second pad of the motherboard; The plurality of metal layers are connected to the first pad of the motherboard through the plurality of solder layers, wherein the plurality of solder layers form a non-signal emission area; as well as The plurality of metal layers are aligned with the solder layer used for thermal conduction of the motherboard, and the spaced portions of the metal layers mate with the alignment, so that the metal layers and the solder layer maintain a high degree of consistency with the connecting elements to avoid delamination between the motherboard and the electronic components.

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