Semiconductor devices

Abstract

The semiconductor device of the present invention includes: a semiconductor layer of the first conductivity type, which has a first main surface on one side and a second main surface on the other side; a trench gate structure, which includes a gate trench formed on the first main surface of the semiconductor layer, and a gate electrode buried in the gate trench via a gate insulating layer; a trench source structure, which includes a source trench formed on the first main surface of the semiconductor layer with a gap from the gate trench to form a source trench deeper than the gate trench, a source electrode buried in the source trench, and a well region of the second conductivity type formed in the region along the source trench in the semiconductor layer, and the ratio of the depth of the trench source structure to the depth of the trench gate structure is greater than 1.5 and less than 4.0; a body region of the second conductivity type, which is formed in the surface portion of the first main surface of the semiconductor layer in the region between the gate trench and the source trench; a source region of the first conductivity type, which is formed in the surface portion of the body region; and a drain electrode connected to the second main surface of the semiconductor layer.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device having gate trenches and source trenches. The gate trenches and source trenches are formed at substantially equal depths on the surface of an n-type semiconductor layer. A p-type body region is formed in the surface portion of the semiconductor layer, in the region between the gate trenches and the source trenches.

[0003] An n+ type source region is formed on the surface of the p-type body region, and a p-type withstand voltage maintaining region (deep well region) is formed in the semiconductor layer along the source trench.

[0004] A gate electrode is embedded in the gate trench via a gate insulating layer. A source electrode is embedded in the source trench. A drain electrode is connected to the back surface of the semiconductor layer.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2014 / 030589A1 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] Short-circuit withstand and feedback capacitance are well-known electrical characteristics of semiconductor devices with a MISFET structure consisting of a gate, source, and drain. Short-circuit withstand is the time a device can withstand a short-circuit current. Short-circuit current is the current flowing between the source and drain when switching from the on state to the off state. Feedback capacitance is the electrostatic capacitance between the gate and drain.

[0010] The higher the short-circuit withstand capability, the higher the reliability of the semiconductor device. Furthermore, the smaller the feedback capacitance, the higher the switching speed of the semiconductor device. Therefore, by achieving excellent short-circuit withstand capability and excellent feedback capacitance, it is possible to provide a semiconductor device that can be used in a variety of situations.

[0011] However, in a semiconductor device having a structure in which the gate trench and the source trench are formed at substantially the same depth, a p-type deep well region can only be formed in a relatively shallow region of the n-type semiconductor layer.

[0012] In this structure, the depletion layer cannot be fully expanded from the boundary between the semiconductor layer and the deep well region. Consequently, the short-circuit current path caused by the depletion layer is not sufficiently narrowed, and short-circuit withstand capability cannot be adequately improved. Furthermore, the width of the depletion layer is also small, making it impossible to adequately reduce the feedback capacitance.

[0013] One embodiment of the present invention provides a semiconductor device capable of improving short-circuit withstand capability and reducing feedback capacitance.

[0014] Solutions to Problems

[0015] One embodiment of the present invention provides a semiconductor device, characterized in that it includes: a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side; a trench gate structure including a gate trench formed on the first main surface of the semiconductor layer, and a gate electrode buried in the gate trench via a gate insulating layer; a trench source structure including a source trench formed on the first main surface of the semiconductor layer at a distance from the gate trench to be deeper than the gate trench, and a source electrode buried in the source trench. An electrode, and a well region of the second conductive type formed in the region along the source trench in the above-mentioned semiconductor layer, and the ratio of the depth of the above-mentioned trench source structure to the depth of the above-mentioned trench gate structure is greater than 1.5 and less than 4.0; a main region of the second conductive type, which is formed in the region between the above-mentioned gate trench and the above-mentioned source trench in the surface portion of the above-mentioned first main surface of the above-mentioned semiconductor layer; a source region of the first conductive type, which is formed in the surface portion of the above-mentioned main region; and a drain electrode, which is connected to the above-mentioned second main surface of the above-mentioned semiconductor layer.

[0016] According to this semiconductor device, the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 to 4.0, thereby allowing the depletion layer to expand from the boundary between the semiconductor layer and the well region toward the region closer to the second main surface than the bottom wall of the gate trench.

[0017] As a result, the current path of the short-circuit current flowing between the source and drain electrodes can be narrowed. Furthermore, the depletion layer that expands from the boundary between the semiconductor layer and the well region can reduce the feedback capacitance in inverse proportion. Therefore, a semiconductor device with improved short-circuit resistance and reduced feedback capacitance can be provided.

[0018] One embodiment of the present invention provides a semiconductor device, characterized in that it includes: a semiconductor layer of a first conductivity type, which has a first main surface on one side and a second main surface on the other side; a trench gate structure, which includes a gate trench having a first sidewall and a first bottom wall and formed on the first main surface of the semiconductor layer, and a gate electrode buried in the gate trench via a gate insulating layer; a trench source structure, which includes a source trench having a second sidewall and a second bottom wall and formed on the first main surface of the semiconductor layer at a distance from the gate trench, a source electrode buried in the source trench, and a well region of the second conductivity type formed in the semiconductor layer along the region of the source trench; a body region of the second conductivity type, which is formed on the surface of the first main surface of the semiconductor layer The semiconductor layer of the present invention further comprises a first conductive type electrode which is located on a surface of the main body region and a second conductive type electrode which is located on a side of the main body region of the semiconductor layer. The second conductive type electrode is located on a surface of the main body region of the semiconductor layer. The second side wall of the source trench comprises a first wall portion which is located on the first main surface side of the semiconductor layer relative to the first bottom wall of the gate trench, and a second wall portion which is located on the second main surface side of the semiconductor layer relative to the first bottom wall of the gate trench. The well region comprises a first region formed along the first wall portion of the second side wall of the source trench, and a second region which is formed along the second wall portion of the second side wall of the source trench and has a length greater than that of the first region in the thickness direction of the semiconductor layer.

[0019] According to this semiconductor device, the well region includes the first region formed along the first wall portion of the second sidewall of the source trench and the second region formed along the second wall portion of the second sidewall of the source trench.

[0020] The second region of the well region is longer than the first region of the well region in the thickness direction of the semiconductor layer. This allows the depletion layer to extend from the boundary between the semiconductor layer and the well region toward a region closer to the second main surface than the first bottom wall of the gate trench.

[0021] As a result, the current path of the short-circuit current flowing between the source and drain electrodes can be narrowed. Furthermore, the depletion layer that expands from the boundary between the semiconductor layer and the well region can reduce the feedback capacitance in inverse proportion. Thus, a semiconductor device with improved short-circuit resistance and reduced feedback capacitance can be provided.

[0022] The above and other objects, features and effects of the present invention will become more apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1It is a plan view showing a semiconductor device according to a first embodiment of the present invention.

[0024] Figure 2 It is along Figure 1 Cross-sectional view along line II-II.

[0025] Figure 3 Is used to illustrate Figure 1 A cross-sectional view illustrating the operation of a semiconductor device.

[0026] Figure 4 Yes Figure 1 A graph showing the current-voltage characteristics of a semiconductor device.

[0027] Figure 5 Yes Figure 1 A graph showing the capacitance-voltage characteristics of a semiconductor device.

[0028] Figure 6 It is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.

[0029] Figure 7 It is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.

[0030] Figure 8 It is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

[0031] Figure 9 It is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

[0032] Figure 10 It is a plan view showing a semiconductor device according to a sixth embodiment of the present invention.

[0033] Figure 11 It is a plan view showing a semiconductor device according to a seventh embodiment of the present invention.

[0034] Figure 12 yes Figure 11 The enlarged view of the region XII shown is a view for explaining the structure of the first main surface of the SiC semiconductor layer.

[0035] Figure 13 It is along Figure 12 A cross-sectional view taken along line XIII-XIII is shown.

[0036] Figure 14 It is along Figure 12 A cross-sectional view taken along line XIV-XIV is shown.

[0037] Figure 15 This is a graph showing the relationship between the resistivity of polycrystal and the formation temperature.

[0038] Figure 16 It is a graph for explaining sheet resistance.

[0039] Figure 17A Yes Figure 11 A cross-sectional view of an example of a method for manufacturing a semiconductor device shown.

[0040] Figure 17B Yes Figure 17A Cross-sectional view of the subsequent process.

[0041] Figure 17C Yes Figure 17B Cross-sectional view of the subsequent process.

[0042] Figure 17D Yes Figure 17C Cross-sectional view of the subsequent process.

[0043] Figure 17E Yes Figure 17D Cross-sectional view of the subsequent process.

[0044] Figure 17F Yes Figure 17E Cross-sectional view of the subsequent process.

[0045] Figure 17G Yes Figure 17F Cross-sectional view of the subsequent process.

[0046] Figure 17H Yes Figure 17G Cross-sectional view of the subsequent process.

[0047] Figure 17I Yes Figure 17H Cross-sectional view of the subsequent process.

[0048] Figure 17J Yes Figure 17I Cross-sectional view of the subsequent process.

[0049] Figure 17K Yes Figure 17J Cross-sectional view of the subsequent process.

[0050] Figure 17L Yes Figure 17K Cross-sectional view of the subsequent process.

[0051] Figure 18 is with Figure 13 The cross-sectional view of the corresponding region is a cross-sectional view showing the semiconductor device according to the eighth embodiment of the present invention.

[0052] Figure 19 is with Figure 13The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the ninth embodiment of the present invention.

[0053] Figure 20A Yes Figure 19 A cross-sectional view of an example of a method for manufacturing a semiconductor device shown.

[0054] Figure 20B Yes Figure 20A Cross-sectional view of the subsequent process.

[0055] Figure 20C Yes Figure 20B Cross-sectional view of the subsequent process.

[0056] Figure 21 is with Figure 12 The enlarged view of the corresponding region is an enlarged view showing the semiconductor device according to the tenth embodiment of the present invention.

[0057] Figure 22 It is along Figure 21 A cross-sectional view taken along line XXII-XXII is shown.

[0058] Figure 23 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the eleventh embodiment of the present invention.

[0059] Figure 24 is with Figure 12 The enlarged view of the corresponding region is an enlarged view for explaining the structure of the semiconductor device according to the twelfth embodiment of the present invention.

[0060] Figure 25 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the thirteenth embodiment of the present invention.

[0061] Figure 26 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the fourteenth embodiment of the present invention.

[0062] Figure 27 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the fifteenth embodiment of the present invention.

[0063] Figure 28 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the sixteenth embodiment of the present invention.

[0064] Figure 29is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the seventeenth embodiment of the present invention.

[0065] Figure 30 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the eighteenth embodiment of the present invention.

[0066] Figure 31 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the nineteenth embodiment of the present invention.

[0067] Figure 32 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the 20th embodiment of the present invention.

[0068] Figure 33 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device according to the twenty-first embodiment of the present invention.

[0069] Figure 34 It is a top view showing a semiconductor device according to a twenty-second embodiment of the present invention.

[0070] Figure 35 Yes Figure 34 The bottom view of the semiconductor device shown is a bottom view showing a first embodiment of the bump group.

[0071] Figure 36A It is a diagram showing a second embodiment of the raised portion group.

[0072] Figure 36B This is a diagram showing a third embodiment of the raised portion group.

[0073] Figure 36C It is a diagram showing a fourth embodiment of the raised portion group.

[0074] Figure 36D This is a diagram showing a fifth embodiment of the raised portion group.

[0075] Figure 37 yes Figure 34 The enlarged view of region XXXVII shown is a view in which the structure above the first main surface of the SiC semiconductor layer is removed.

[0076] Figure 38 It is along Figure 37 A cross-sectional view taken along line XXXVIII-XXXVIII.

[0077] Figure 39 It is along Figure 37 Cross-sectional view of line XXXIX-XXXIX.

[0078] Figure 40 yes Figure 39 Magnified view of area XL is shown.

[0079] Figure 41A yes Figure 34 FIG. 1 is a top view of a semiconductor wafer used in manufacturing a semiconductor device.

[0080] Figure 41B yes Figure 41A The bottom view of the semiconductor wafer shown shows a state after a polishing step and an annealing treatment.

[0081] Figure 42 Is used to illustrate Figure 34 A flowchart of an example of a semiconductor device is shown.

[0082] Figure 43A Is used to illustrate Figure 42 A cross-sectional view illustrating the manufacturing method.

[0083] Figure 43B Is used to illustrate Figure 43A Cross-sectional view of the subsequent process.

[0084] Figure 43C Is used to illustrate Figure 43B Cross-sectional view of the subsequent process.

[0085] Figure 43D Is used to illustrate Figure 43C Cross-sectional view of the subsequent process.

[0086] Figure 43E Is used to illustrate Figure 43D Cross-sectional view of the subsequent process.

[0087] Figure 43F Is used to illustrate Figure 43E Cross-sectional view of the subsequent process.

[0088] Figure 43G Is used to illustrate Figure 43F Cross-sectional view of the subsequent process.

[0089] Figure 43H Is used to illustrate Figure 43G Cross-sectional view of the subsequent process.

[0090] Figure 43I Is used to illustrate Figure 43H Cross-sectional view of the subsequent process.

[0091] Figure 44 is with Figure 35 The corresponding bottom view is a bottom view of the semiconductor device according to the twenty-third embodiment of the present invention.

[0092] Figure 45 is with Figure 39 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device according to the twenty-fourth embodiment of the present invention.

[0093] Figure 46 Yes Figure 45 Magnified view of area XLVI is shown.

[0094] Figure 47 is with Figure 39 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device according to a twenty-fifth embodiment of the present invention.

[0095] Figure 48 yes Figure 47 An enlarged view of region XLVIII is shown.

[0096] Figure 49 It is a top view of a semiconductor device according to a twenty-sixth embodiment of the present invention.

[0097] Figure 50 Yes Figure 49 The top view of the semiconductor device shown is a top view with the resin layer removed.

[0098] Figure 51 yes Figure 50 The enlarged view of the region LI shown is a diagram for explaining the structure of the first main surface of the SiC semiconductor layer.

[0099] Figure 52 It is along Figure 51 The cross-sectional view taken along line LII-LII is a cross-sectional view showing a first embodiment of the gate trench and a first embodiment of the source trench.

[0100] Figure 53 It is along Figure 51 The cross-sectional view taken along line LIII-LIII is a cross-sectional view showing a first embodiment of the gate wiring layer.

[0101] Figure 54 yes Figure 52 Magnified view of area LIV is shown.

[0102] Figure 55 It is along Figure 50The cross-sectional view along the LV-LV line shown is a cross-sectional view showing the first example of the active side wall, the first example of the outer main surface, the first example of the side wall, the first example of the diode region, the first example of the outer deep well region, the first example of the field limiting structure, and the first example of the anchor hole.

[0103] Figure 56 yes Figure 55 The enlarged view of the region LVI shown is an enlarged view showing the first embodiment of the active sidewall and the first embodiment of the outer main surface.

[0104] Figure 57A is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the second embodiment of the gate trench.

[0105] Figure 57B is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the third embodiment of the gate trench.

[0106] Figure 57C is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fourth embodiment of the gate trench.

[0107] Figure 57D is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fifth embodiment of the gate trench.

[0108] Figure 57E is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the sixth embodiment of the gate trench.

[0109] Figure 58A is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the second embodiment of the source trench.

[0110] Figure 58B is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the third embodiment of the source trench.

[0111] Figure 58C is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing an example of the fourth embodiment of the source trench.

[0112] Figure 58D is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fifth embodiment of the source trench.

[0113] Figure 58E is with Figure 54The cross-sectional view of the corresponding region is a cross-sectional view showing the sixth embodiment of the source trench.

[0114] Figure 58F is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the seventh embodiment of the source trench.

[0115] Figure 58G is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the eighth embodiment of the source trench.

[0116] Figure 58H is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the ninth embodiment of the source trench.

[0117] Figure 58I is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the tenth embodiment of the source trench.

[0118] Figure 58J is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the eleventh embodiment of the source trench.

[0119] Figure 58K is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the twelfth embodiment of the source trench.

[0120] Figure 58L is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the thirteenth embodiment of the source trench.

[0121] Figure 58M is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fourteenth embodiment of the source trench.

[0122] Figure 58N is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fifteenth embodiment of the source trench.

[0123] Figure 58O is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the sixteenth embodiment of the source trench.

[0124] Figure 58P is with Figure 54 The cross-sectional view of the corresponding region is a cross-sectional view showing the seventeenth embodiment of the source trench.

[0125] Figure 58Q is with Figure 54The cross-sectional view of the corresponding region is a cross-sectional view showing the eighteenth embodiment of the source trench.

[0126] Figure 59A is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the second embodiment of the active sidewall.

[0127] Figure 59B is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the third embodiment of the active sidewall.

[0128] Figure 59C is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the fourth embodiment of the active sidewall.

[0129] Figure 60A is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the second embodiment of the outer main surface.

[0130] Figure 60B is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the third embodiment of the outer main surface.

[0131] Figure 60C is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the fourth embodiment of the outer main surface.

[0132] Figure 61A is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the second embodiment of the side wall.

[0133] Figure 61B is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the third embodiment of the side wall.

[0134] Figure 61C is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the fourth embodiment of the side wall.

[0135] Figure 61D is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the fifth embodiment of the side wall.

[0136] Figure 61E is with Figure 56 The enlarged view of the corresponding region is an enlarged view showing the sixth embodiment of the side wall.

[0137] Figure 61F is with Figure 56The enlarged view of the corresponding region is an enlarged view showing the seventh embodiment of the side wall.

[0138] Figure 62A is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the second embodiment of the outer deep well region.

[0139] Figure 62B is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the third embodiment of the outer deep well region.

[0140] Figure 62C is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the fourth embodiment of the outer deep well region.

[0141] Figure 63A is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the second embodiment of the field confinement structure.

[0142] Figure 63B is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the third embodiment of the field confinement structure.

[0143] Figure 63C is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the fourth embodiment of the field confinement structure.

[0144] Figure 63D is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the fifth embodiment of the field confinement structure.

[0145] Figure 64A is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the second embodiment of the anchor hole.

[0146] Figure 64B is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the third embodiment of the anchor hole.

[0147] Figure 64C is with Figure 55 The cross-sectional view of the corresponding region is an enlarged view showing the fourth embodiment of the anchor hole.

[0148] Figure 64D is with Figure 50 The corresponding plan view is a plan view showing the fifth embodiment of the anchor hole.

[0149] Figure 65A is with Figure 54 The enlarged image of the corresponding area shows Figure 49 An enlarged view of an example of a method for manufacturing a semiconductor device shown.

[0150] Figure 65B Yes Figure 65A A magnified view of the subsequent process.

[0151] Figure 65C Yes Figure 65B A magnified view of the subsequent process.

[0152] Figure 65D Yes Figure 65C A magnified view of the subsequent process.

[0153] Figure 65E Yes Figure 65D A magnified view of the subsequent process.

[0154] Figure 65F Yes Figure 65E A magnified view of the subsequent process.

[0155] Figure 65G Yes Figure 65F A magnified view of the subsequent process.

[0156] Figure 65H Yes Figure 65G A magnified view of the subsequent process.

[0157] Figure 65I Yes Figure 65H A magnified view of the subsequent process.

[0158] Figure 65J Yes Figure 65I A magnified view of the subsequent process.

[0159] Figure 65K Yes Figure 65J A magnified view of the subsequent process.

[0160] Figure 65L Yes Figure 65K A magnified view of the subsequent process.

[0161] Figure 65M Yes Figure 65L A magnified view of the subsequent process.

[0162] Figure 65N Yes Figure 65M A magnified view of the subsequent process.

[0163] Figure 65O Yes Figure 65N A magnified view of the subsequent process.

[0164] Figure 65P Yes Figure 65OA magnified view of the subsequent process.

[0165] Figure 65Q Yes Figure 65P A magnified view of the subsequent process.

[0166] Figure 65R Yes Figure 65Q A magnified view of the subsequent process.

[0167] Figure 65S Yes Figure 65R A magnified view of the subsequent process.

[0168] Figure 65T Yes Figure 65S A magnified view of the subsequent process.

[0169] Figure 65U Yes Figure 65T A magnified view of the subsequent process.

[0170] Figure 65V Yes Figure 65U A magnified view of the subsequent process.

[0171] Figure 65W Yes Figure 65V A magnified view of the subsequent process.

[0172] Figure 65X Yes Figure 65W A magnified view of the subsequent process.

[0173] Figure 65Y Yes Figure 65X A magnified view of the subsequent process.

[0174] Figure 65Z Yes Figure 65Y A magnified view of the subsequent process.

[0175] Figure 66A is with Figure 55 The cross-sectional view of the corresponding area is shown Figure 49 A cross-sectional view of an example of a method for manufacturing a semiconductor device shown.

[0176] Figure 66B Yes Figure 66A Cross-sectional view of the subsequent process.

[0177] Figure 66C Yes Figure 66B Cross-sectional view of the subsequent process.

[0178] Figure 66D Yes Figure 66C Cross-sectional view of the subsequent process.

[0179] Figure 66E Yes Figure 66D Cross-sectional view of the subsequent process.

[0180] Figure 66F Yes Figure 66E Cross-sectional view of the subsequent process.

[0181] Figure 66G Yes Figure 66F Cross-sectional view of the subsequent process.

[0182] Figure 66H Yes Figure 66G Cross-sectional view of the subsequent process.

[0183] Figure 66I Yes Figure 66H Cross-sectional view of the subsequent process.

[0184] Figure 66J Yes Figure 66I Cross-sectional view of the subsequent process.

[0185] Figure 66K Yes Figure 66J Cross-sectional view of the subsequent process.

[0186] Figure 66L Yes Figure 66K Cross-sectional view of the subsequent process.

[0187] Figure 66M Yes Figure 66L Cross-sectional view of the subsequent process.

[0188] Figure 66N Yes Figure 66M Cross-sectional view of the subsequent process.

[0189] Figure 66O Yes Figure 66N Cross-sectional view of the subsequent process.

[0190] Figure 66P Yes Figure 66O Cross-sectional view of the subsequent process.

[0191] Figure 66Q Yes Figure 66P Cross-sectional view of the subsequent process.

[0192] Figure 66R Yes Figure 66Q Cross-sectional view of the subsequent process.

[0193] Figure 66S Yes Figure 66R Cross-sectional view of the subsequent process.

[0194] Figure 66T Yes Figure 66S Cross-sectional view of the subsequent process.

[0195] Figure 66U Yes Figure 66T Cross-sectional view of the subsequent process.

[0196] Figure 66V Yes Figure 66U Cross-sectional view of the subsequent process.

[0197] Figure 66W Yes Figure 66V Cross-sectional view of the subsequent process.

[0198] Figure 66X Yes Figure 66W Cross-sectional view of the subsequent process.

[0199] Figure 66Y Yes Figure 66X Cross-sectional view of the subsequent process.

[0200] Figure 66Z Yes Figure 66Y Cross-sectional view of the subsequent process.

[0201] Figure 67 is with Figure 51 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the twenty-seventh embodiment of the present invention.

[0202] Figure 68 It is along Figure 67 A cross-sectional view taken along line LXVIII-LXVIII is shown.

[0203] Figure 69 It is along Figure 67 A cross-sectional view taken along line LXIX-LXIX is shown.

[0204] Figure 70 yes Figure 68 Magnified view of area LXX-LXX is shown.

[0205] Figure 71 This is a graph showing leakage current characteristics when NiSi is used as the low-resistance electrode layer.

[0206] Figure 72 Graph showing leakage current characteristics when CoSi2 is used as the low-resistance electrode layer.

[0207] Figure 73 This is a graph showing leakage current characteristics when TiSi2 is used as a low-resistance electrode layer.

[0208] Figure 74A is with Figure 70 The enlarged image of the corresponding area is used to illustrate Figure 67An enlarged view of an example of a method for manufacturing a semiconductor device shown.

[0209] Figure 74B Yes Figure 74A A magnified view of the subsequent process.

[0210] Figure 74C Yes Figure 74B A magnified view of the subsequent process.

[0211] Figure 74D Yes Figure 74C A magnified view of the subsequent process.

[0212] Figure 74E Yes Figure 74D A magnified view of the subsequent process.

[0213] Figure 74F Yes Figure 74E A magnified view of the subsequent process.

[0214] Figure 74G Yes Figure 74F A magnified view of the subsequent process.

[0215] Figure 75 is with Figure 70 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the twenty-eighth embodiment of the present invention.

[0216] Figure 76A is with Figure 75 The enlarged image of the corresponding area is used to illustrate Figure 75 An enlarged view of an example of a method for manufacturing a semiconductor device shown.

[0217] Figure 76B Yes Figure 76A A magnified view of the subsequent process.

[0218] Figure 76C Yes Figure 76B A magnified view of the subsequent process.

[0219] Figure 76D Yes Figure 76C A magnified view of the subsequent process.

[0220] Figure 76E Yes Figure 76D A magnified view of the subsequent process.

[0221] Figure 76F Yes Figure 76E A magnified view of the subsequent process.

[0222] Figure 76G Yes Figure 76F A magnified view of the subsequent process.

[0223] Figure 77 is with Figure 70 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the twenty-ninth embodiment of the present invention.

[0224] Figure 78A is with Figure 77 The enlarged image of the corresponding area is used to illustrate Figure 77 An enlarged view of an example of a method for manufacturing a semiconductor device shown.

[0225] Figure 78B Yes Figure 78A A magnified view of the subsequent process.

[0226] Figure 78C Yes Figure 78B A magnified view of the subsequent process.

[0227] Figure 78D Yes Figure 78C A magnified view of the subsequent process.

[0228] Figure 78E Yes Figure 78D A magnified view of the subsequent process.

[0229] Figure 78F Yes Figure 78E A magnified view of the subsequent process.

[0230] Figure 79 is with Figure 70 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the 30th embodiment of the present invention.

[0231] Figure 80 is with Figure 69 The cross-sectional view of the corresponding area is shown Figure 79 A cross-sectional view of a semiconductor device is shown.

[0232] Figure 81 is with Figure 55 The cross-sectional view of the corresponding area is shown Figure 79 A cross-sectional view of a semiconductor device is shown.

[0233] Figure 82A is with Figure 79 The enlarged image of the corresponding area is used to illustrate Figure 79 An enlarged view of an example of a method for manufacturing a semiconductor device shown.

[0234] Figure 82B Yes Figure 82A A magnified view of the subsequent process.

[0235] Figure 82C Yes Figure 82B A magnified view of the subsequent process.

[0236] Figure 83 It is a bottom view of a semiconductor device according to a thirty-first embodiment of the present invention, and is a bottom view of a first embodiment of a group of raised portions.

[0237] Figure 84A It is a diagram showing a second embodiment of the raised portion group.

[0238] Figure 84B This is a diagram showing a third embodiment of the raised portion group.

[0239] Figure 84C It is a diagram showing a fourth embodiment of the raised portion group.

[0240] Figure 84D This is a diagram showing a fifth embodiment of the raised portion group.

[0241] Figure 85 is with Figure 68 The cross-sectional view of the corresponding area is shown Figure 83 A cross-sectional view of a semiconductor device is shown.

[0242] Figure 86 is with Figure 69 The cross-sectional view of the corresponding area is shown Figure 83 A cross-sectional view of a semiconductor device is shown.

[0243] Figure 87 Yes Figure 86 Magnified view of region LXXXVII is shown.

[0244] Figure 88 is with Figure 55 The cross-sectional view of the corresponding area is shown Figure 83 A cross-sectional view of a semiconductor device is shown.

[0245] Figure 89 is with Figure 83 The corresponding bottom view is a bottom view of the semiconductor device according to the thirty-second embodiment of the present invention.

[0246] Figure 90 is with Figure 86 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device according to a thirty-third embodiment of the present invention.

[0247] Figure 91 yes Figure 90 Magnified view of region XCI is shown.

[0248] Figure 92 is with Figure 86 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device according to a thirty-fourth embodiment of the present invention.

[0249] Figure 93 Yes Figure 92 An enlarged view of region XCIII is shown.

[0250] Figure 94 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the thirty-fifth embodiment of the present invention.

[0251] Figure 95 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the thirty-sixth embodiment of the present invention.

[0252] Figure 96 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the thirty-seventh embodiment of the present invention.

[0253] Figure 97 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the thirty-eighth embodiment of the present invention.

[0254] Figure 98 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of a semiconductor device according to the thirty-ninth embodiment of the present invention.

[0255] Figure 99 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the 40th embodiment of the present invention.

[0256] Figure 100 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the 41st embodiment of the present invention.

[0257] Figure 101 is with Figure 55 The cross-sectional view of the corresponding region is a cross-sectional view of the semiconductor device according to the 42nd embodiment of the present invention.

[0258] Figure 102 is with Figure 51 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the 43rd embodiment of the present invention.

[0259] Figure 103 It means along Figure 102 A cross-sectional view taken along line CIII-CIII is shown.

[0260] Figure 104 is with Figure 51The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the 44th embodiment of the present invention.

[0261] Figure 105 is with Figure 54 The enlarged view of the corresponding region is an enlarged view of the semiconductor device according to the 45th embodiment of the present invention.

[0262] Figure 106 This is a perspective view showing a semiconductor package into which any of the semiconductor devices according to the first to forty-fifth embodiments described above can be incorporated, with a sealing body being seen through.

[0263] Figure 107 This is a diagram showing a unit cell of a 4H—SiC single crystal to which an embodiment of the present invention is applied.

[0264] Figure 108 Yes Figure 107 A plan view of the silicon surface of a unit cell of a 4H-SiC single crystal is shown. DETAILED DESCRIPTION

[0265] Figure 1 It is a plan view showing a semiconductor device 1 according to the first embodiment of the present invention. Figure 2 It is along Figure 1 Cross-sectional view along line II-II.

[0266] The semiconductor device 1 is a switching device including a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). Figure 1 as well as Figure 2 The semiconductor device 1 includes an n-type SiC semiconductor layer 2 made of SiC (silicon carbide) single crystal.

[0267] The SiC semiconductor layer 2 includes a first principal surface 3 on one side and a second principal surface 4 on the other side. In this embodiment, the SiC semiconductor layer 2 has a stacked structure comprising a SiC semiconductor substrate 5 comprising a SiC single crystal and an n-type SiC epitaxial layer 6 comprising the SiC single crystal. The second principal surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 5. The first principal surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 6.

[0268] A drain electrode 7 is connected to the second main surface 4 of the SiC semiconductor layer 2. The SiC semiconductor substrate 5 is formed as an n+ type drain region. The SiC epitaxial layer 6 is formed as an n- type drain drift region.

[0269] The n-type impurity concentration of the SiC semiconductor substrate 5 is preferably 1.0×10 18 cm －3Above and 1.0×10 21 cm －3 The n-type impurity concentration of the SiC epitaxial layer 6 is preferably 1.0×10 15 cm －3 Above and 1.0×10 17 cm －3 Hereinafter, in this specification, "impurity concentration" refers to the peak value of the impurity concentration.

[0270] Reference Figure 1 as well as Figure 2 A plurality of trench gate structures 10 and a plurality of trench source structures 11 are formed on the first main surface 3 of the SiC semiconductor layer 2. The trench gate structures 10 and the trench source structures 11 are alternately formed along an arbitrary first direction X with spaces therebetween.

[0271] The trench gate structure 10 and the trench source structure 11 are formed in a band shape extending in a second direction Y perpendicular to the first direction X. Preferably, the first direction X is a [11-20] direction, and the second direction Y is a [1-100] direction.

[0272] A stripe structure including a plurality of trench gate structures 10 and a plurality of trench source structures 11 is formed on the first main surface 3 of the SiC semiconductor layer 2. The distance between the trench gate structure 10 and the trench source structure 11 in the first direction X is preferably 0.3 μm to 1.0 μm.

[0273] Each trench gate structure 10 includes a gate trench 12, a gate insulating layer 13, and a gate electrode layer 14. Figure 1 , the gate electrode layer 14 is shown with hatching for clarity.

[0274] The gate trench 12 is formed by digging the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The gate trench 12 includes a first sidewall 15 and a first bottom wall 16.

[0275] Gate insulating layer 13 is formed in a film shape along first sidewall 15, first bottom wall 16, and corner 17 connecting first sidewall 15 and first bottom wall 16 of gate trench 12. Gate insulating layer 13 defines a concave space in gate trench 12.

[0276] The gate insulating layer 13 may also include silicon oxide. In addition to silicon oxide, the gate insulating layer 13 may also include at least one of non-impurity-added silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0277] The gate electrode layer 14 is embedded in the gate trench 12 via the gate insulating layer 13 . More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13 .

[0278] The gate electrode layer 14 may also include conductive polysilicon. In addition to conductive polysilicon, the gate electrode layer 14 may also include at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0279] Each trench source structure 11 includes a source trench 18, a barrier-forming layer 19, a source electrode layer 20, and a p-type deep well region 21. Figure 1 , for the sake of clarity, the source electrode layer 20 is shown by hatching. The deep well region 21 is also referred to as a withstand voltage holding region.

[0280] The source trench 18 is formed by digging the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The source trench 18 includes a second side wall 22 and a second bottom wall 23.

[0281] The second sidewall 22 of the source trench 18 includes a first wall portion 24 and a second wall portion 25. The first wall portion 24 of the source trench 18 is located on the first main surface 3 side of the SiC semiconductor layer 2 relative to the first bottom wall 16 of the gate trench 12. In other words, the first wall portion 24 is a portion that overlaps with the gate trench 12 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2.

[0282] The second wall portion 25 of the source trench 18 is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the second bottom wall 23 of the gate trench 12. In other words, the second wall portion 25 is a portion of the region of the source trench 18 that is located on the second main surface 4 side of the SiC semiconductor layer 2 relative to the second bottom wall 23 of the gate trench 12.

[0283] In the thickness direction of the SiC semiconductor layer 2, the length of the second wall portion 25 of the source trench 18 is greater than the length of the first wall portion 24 of the source trench 18. The second bottom wall 23 of the source trench 18 is located in a region between the first bottom wall 16 of the gate trench 12 and the second main surface 4 of the SiC semiconductor layer 2 in the thickness direction of the SiC semiconductor layer 2.

[0284] In this embodiment, the second bottom wall 23 of the source trench 18 is located in the SiC epitaxial layer 6 . The second bottom wall 23 of the source trench 18 may also be located in the SiC semiconductor substrate 5 .

[0285] The barrier-forming layer 19 is formed in a film shape along the second sidewall 22 and second bottom wall 23 of the source trench 18 and along a corner 26 connecting the second sidewall 22 and second bottom wall 23. The barrier-forming layer 19 defines a concave space in the source trench 18.

[0286] The barrier-forming layer 19 is made of a material different from the conductive material of the source electrode layer 20 . The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the source electrode layer 20 and the deep well region 21 .

[0287] A conductive barrier-forming layer may be used as the barrier-forming layer 19. The conductive barrier-forming layer may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, and molybdenum.

[0288] An insulating barrier forming layer may also be used as the barrier forming layer 19. The insulating barrier forming layer may also contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. Figure 2 , an example in which an insulating barrier-forming layer is formed as the barrier-forming layer 19 is shown.

[0289] More specifically, the barrier-forming layer 19 is silicon oxide. The barrier-forming layer 19 and the gate insulating layer 13 are preferably formed of the same material. In this case, the thickness of the barrier-forming layer 19 and the thickness of the gate insulating layer 13 are preferably the same. When the barrier-forming layer 19 and the gate insulating layer 13 are formed of silicon oxide, the barrier-forming layer 19 and the gate insulating layer 13 can be formed simultaneously using a thermal oxidation process.

[0290] The source electrode layer 20 fills the concave space of the source trench 18 via the barrier-forming layer 19. The source electrode layer 20 may also include conductive polysilicon. The source electrode layer 20 may also be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities.

[0291] The source electrode layer 20 may include at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten, in addition to conductive polysilicon.

[0292] The source electrode layer 20 is formed of the same conductive material as the gate electrode layer 14. In this case, the gate electrode layer 14 and the source electrode layer 20 can be formed simultaneously. Of course, the source electrode layer 20 may be formed of a conductive material different from that of the gate electrode layer 14.

[0293] The deep well region 21 is formed in the region of the SiC semiconductor layer 2 along the source trench 18. The p-type impurity concentration of the deep well region 21 may also be 1.0×10 17 cm －3 Above and 1.0×10 19 cm －3 the following.

[0294] The deep well region 21 is formed in a region of the SiC semiconductor layer 2 along the second sidewall 22 of the source trench 18 . The deep well region 21 is formed in a region of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18 .

[0295] In this embodiment, deep well region 21 is continuously formed in SiC semiconductor layer 2 along second sidewall 22, corner 26, and second bottom wall 23 of source trench 18. Deep well region 21 includes first region 27 and second region 28 along second sidewall 22 of source trench 18.

[0296] First region 27 of deep well region 21 is formed along first wall portion 24 of second sidewall 22 of source trench 18. Second region 28 of deep well region 21 is formed along second wall portion 25 of second sidewall 22 of source trench 18. In the thickness direction of SiC semiconductor layer 2, the length of second region 28 of deep well region 21 is greater than the length of first region 27 of deep well region 21.

[0297] The thickness of the portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 may be greater than the thickness of the portion of the deep well region 21 along the second side wall 22 of the source trench 18 .

[0298] The portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 may cross the boundary region between the SiC semiconductor substrate 5 and the SiC epitaxial layer 6 and be located within the SiC semiconductor substrate 5 .

[0299] In the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18, the p-type impurity is implanted along the normal direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, in the portion of the SiC semiconductor layer 2 along the second side wall 22 of the source trench 18, the p-type impurity is implanted in a state inclined with respect to the first main surface 3 of the SiC semiconductor layer 2.

[0300] Therefore, the p-type impurity is implanted into the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18 at a deeper position than the portion along the second side wall 22 of the source trench 18. As a result, a thickness difference is generated in the deep well region 21 between the portion along the second bottom wall 23 of the source trench 18 and the portion along the second side wall 22 of the source trench 18.

[0301] A p-type body region 30 is formed on the surface of the first main surface 3 of the SiC semiconductor layer 2. The body region 30 is formed in the region between the gate trench 12 and the source trench 18. The body region 30 is formed in a band shape extending in the second direction Y in a plan view.

[0302] The body region 30 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The body region 30 is connected to the first region 27 of the deep well region 21.

[0303] The p-type impurity concentration of the body region 30 may also be 1.0×10 16 cm －3Above and 1.0×10 19 cm －3 The p-type impurity concentration of the body region 30 may be substantially equal to the p-type impurity concentration of the deep well region 21 . The p-type impurity concentration of the body region 30 may be higher than the p-type impurity concentration of the deep well region 21 .

[0304] An n+ type source region 31 is formed in the surface portion of the body region 30. The source region 31 is formed in a region along the first sidewall 15 of the gate trench 12 in the surface portion of the body region 30. The source region 31 is exposed from the first sidewall 15 of the gate trench 12.

[0305] The source region 31 may be formed in a band shape extending in the second direction Y in a plan view. Although not shown, the source region 31 may include a portion exposed from the second side wall 22 of the source trench 18 .

[0306] The width WS of the source region 31 may be greater than or equal to 0.2 μm and less than or equal to 0.6 μm (e.g., approximately 0.4 μm). In this embodiment, the width WS is the width of the source region 31 along the first direction X. The n-type impurity concentration of the source region 31 may also be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0307] A p+ type contact region 32 is formed in the surface portion of the body region 30. The contact region 32 is formed in a region along the second sidewall 22 of the source trench 18 in the surface portion of the body region 30. The contact region 32 is exposed from the second sidewall 22 of the source trench 18.

[0308] The contact region 32 may be connected to the source region 31. The contact region 32 may be formed in a band shape extending in the second direction Y in a plan view. The contact region 32 may include a portion exposed from the first sidewall 15 of the adjacent gate trench 12.

[0309] The width WC of the contact region 32 may be greater than or equal to 0.1 μm and less than or equal to 0.4 μm (e.g., approximately 0.2 μm). In this embodiment, the width WC is the width of the contact region 32 along the first direction X. The p-type impurity concentration of the contact region 32 may also be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0310] An insulating layer 40 is formed on the first main surface 3 of the SiC semiconductor layer 2. The insulating layer 40 covers the plurality of trench gate structures 10. Contact holes 41 are formed in the insulating layer 40. The contact holes 41 selectively expose the trench source structures 11, the source regions 31, and the contact regions 32.

[0311] A main surface source electrode 42 is formed on the insulating layer 40 . The main surface source electrode 42 extends from above the insulating layer 40 into the contact hole 41 . The main surface source electrode 42 is electrically connected to the source electrode layer 20 , the source region 31 , and the contact region 32 in the contact hole 41 .

[0312] The main surface source electrode 42 may be formed of the same conductive material as the source electrode layer 20 . The main surface source electrode 42 may be formed of a conductive material different from that of the source electrode layer 20 .

[0313] In this embodiment, source electrode layer 20 comprises n-type polysilicon or p-type polysilicon, and main surface source electrode 42 comprises aluminum or a metal material containing aluminum as a main component. Main surface source electrode 42 may also comprise at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0314] The main surface source electrode 42 may be constituted by an electrode layer formed integrally with the source electrode layer 20. In this case, the source electrode layer 20 and the main surface source electrode 42 are formed through a common process.

[0315] Hereinafter, the dimensions of the trench gate structure 10 and the dimensions of the trench source structure 11 will be described in detail.

[0316] The trench gate structure 10 has an aspect ratio D1 / W1 . The aspect ratio D1 / W1 of the trench gate structure 10 is defined by the ratio of the depth D1 of the trench gate structure 10 to the width W1 of the trench gate structure 10 .

[0317] In this embodiment, the width W1 is the width of the trench gate structure 10 along the first direction X. The aspect ratio D1 / W1 of the trench gate structure 10 may be the aspect ratio of the gate trench 12 .

[0318] The aspect ratio D1 / W1 of the trench gate structure 10 may be greater than or equal to 0.25 and less than or equal to 15.0. The width W1 of the trench gate structure 10 may be greater than or equal to 0.2 μm and less than or equal to 2.0 μm (e.g., approximately 0.4 μm). The depth D1 of the trench gate structure 10 may be greater than or equal to 0.5 μm and less than or equal to 3.0 μm (e.g., approximately 1.0 μm).

[0319] The trench source structure 11 has an aspect ratio D2 / W2 . The aspect ratio D2 / W2 of the trench source structure 11 is the ratio of the depth D2 of the trench source structure 11 to the width W2 of the trench source structure 11 .

[0320] The width W2 of the trench source structure 11 is the sum of the width WST of the source trench 18 , the first width Wα of the deep well region 21 , and the second width Wβ of the deep well region 21 ( W2 = WST + Wα + Wβ).

[0321] In this embodiment, width WST is the width of the source trench 18 along the first direction X. In this embodiment, width Wα is the width of the portion of the deep well region 21 along the second sidewall 22 on one side of the source trench 18 along the first direction X. In this embodiment, second width Wβ is the width of the portion of the deep well region 21 along the second sidewall 22 on the other side of the source trench 18 along the first direction X.

[0322] The aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 may be greater than or equal to 0.5 and less than or equal to 18.0.

[0323] The ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 may be 1.5 or more and 4.0 or less. Increasing the depth D2 of the trench source structure 11 can also enhance the withstand voltage maintenance effect of the SJ (Super Junction) structure.

[0324] The width W2 of the trench source structure 11 may be greater than or equal to 0.6 μm and less than or equal to 2.4 μm (e.g., approximately 0.8 μm). The depth D2 of the trench source structure 11 may be greater than or equal to 1.5 μm and less than or equal to 11 μm (e.g., approximately 2.5 μm). The width W2 of the trench source structure 11 may be equal to the width W1 of the trench gate structure 10. The width W2 of the trench source structure 11 may also be different from the width W1 of the trench gate structure 10.

[0325] In the trench source structure 11 , the source trench 18 has an aspect ratio DST / WST. The aspect ratio DST / WST of the source trench 18 is a ratio of the depth DST of the source trench 18 to the width WST of the source trench 18.

[0326] The aspect ratio DST / WST of the source trench 18 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio DST / WST of the source trench 18 may be greater than or equal to 0.5 and less than or equal to 18.0.

[0327] The width WST of the source trench 18 may be 0.2 μm or more and 2.0 μm or less (eg, approximately 0.4 μm). The width WST of the source trench 18 may be equal to the width W1 of the gate trench 12 (WST=W1).

[0328] When the width WST of the source trench 18 or the width W1 of the gate trench 12 varies in the depth direction, the width WST and the width W1 are defined as the width of the opening. The depth DST of the source trench 18 may be 1.0 μm to 10 μm (eg, approximately 2.0 μm).

[0329] The ratio of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 (gate trench 12) is preferably greater than 2. The ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 may also exceed 4.0. In this case, it is necessary to pay attention to the durability of the resist mask used when forming the source trench 18 by etching.

[0330] For example, if the depth D1 of the trench gate structure 10 is approximately 3.0 μm and the ratio DST / D1 exceeds 4, the resist mask may approach or exceed the durability limit due to etching. If the resist mask exceeds the durability limit, undesirable etching of the SiC semiconductor layer 2 may occur.

[0331] Therefore, the ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 is preferably greater than 1.0 and equal to or less than 4.0. If the ratio DST / D1 is within this range, the source trench 18 can be appropriately formed.

[0332] Figure 3 Is used to illustrate Figure 1 A cross-sectional view of the operation of the semiconductor device 1. Figure 3 In the Figure 2 The same structure is marked with the same reference numerals.

[0333] In the semiconductor device 1, a pn junction 45 is formed at the boundary region between the SiC semiconductor layer 2 and the deep well region 21. When the semiconductor device 1 is switched from the on state to the off state, a depletion layer 46 expands from the pn junction 45 toward the SiC semiconductor layer 2. Figure 3 In FIG, the depletion layer 46 is shown by a two-dot chain line.

[0334] Deep well region 21 includes a first region 27 and a second region 28. First region 27 is formed along first wall portion 24 of second sidewall 22 of source trench 18. Second region 28 is formed along second wall portion 25 of second sidewall 22 of source trench 18.

[0335] The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 to a region closer to the first main surface 3 than the first bottom wall 16 of the gate trench 12. The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 to a region closer to the second main surface 4 than the first bottom wall 16 of the gate trench 12.

[0336] When the semiconductor device 1 switches from the on state to the off state, the current path of the short-circuit current flowing from the drain electrode 7 to the source electrode layer 20 is narrowed by the depletion layer 46. This can delay the time until the semiconductor device 1 is destroyed.

[0337] In particular, according to semiconductor device 1, aspect ratio D2 / W2 of trench source structure 11 is larger than aspect ratio D1 / W1 of trench gate structure 10. Aspect ratio D2 / W2 of trench source structure 11 is greater than or equal to 0.5 and less than or equal to 18.0.

[0338] Furthermore, a ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 is greater than or equal to 1.5 and less than or equal to 4.0. In the thickness direction of the SiC semiconductor layer 2 , the length of the second region 28 of the deep well region 21 is greater than the length of the first region 27 of the deep well region 21 .

[0339] Therefore, in the SiC semiconductor layer 2, the ratio of the area occupied by the depletion layer 46 extending in the region on the second main surface 4 side can be reliably increased compared to the ratio of the area occupied by the depletion layer 46 extending in the region on the first main surface 3 side. This ensures that the current path of the short-circuit current can be narrowed in the region on the drain electrode 7 side.

[0340] The depletion layer 46 from the pn junction 45 may overlap with the first bottom wall 16 of the gate trench 12 . The depletion layer 46 on the second region 28 side of the deep well region 21 may overlap with the first bottom wall 16 of the gate trench 12 .

[0341] This structure can reliably narrow the current path of the short-circuit current in the region on the drain electrode 7 side. Of course, the depletion layer 46 on the first region 27 side of the deep well region 21 may overlap with the first bottom wall 16 of the gate trench 12 .

[0342] Furthermore, according to the semiconductor device 1 , the depletion layer 46 can be increased in the area occupied by the SiC semiconductor layer 2 , thereby reducing the feedback capacitance Crss in inverse proportion. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 14 and the drain electrode 7 .

[0343] As described above, according to the semiconductor device 1 , the short-circuit withstand capability is improved and the feedback capacitance Crss can be reduced.

[0344] Furthermore, according to the semiconductor device 1 , the barrier-forming layer 19 is formed in the source trench 18 . The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the deep well region 21 and the source electrode layer 20 .

[0345] Therefore, even if depletion layer 46 extending from pn junction 45 between SiC semiconductor layer 2 and deep well region 21 contacts the inner wall surface of source trench 18 , punch-through can be suppressed.

[0346] In the absence of the barrier-forming layer 19 , punch-through tends to be noticeable at the corner 26 of the source trench 18 . This is because the depletion layer 46 extends from the second side wall 22 of the source trench 18 further along the second bottom wall 23 of the source trench 18 .

[0347] Here, in the semiconductor device 1 , the inner wall surface of the source trench 18 including the corner portion 26 is covered by the barrier-forming layer 19 . This effectively suppresses the occurrence of punch-through in the source trench 18 .

[0348] According to the semiconductor device 1 , the depletion layer 46 is formed in a relatively wide region of the SiC semiconductor layer 2 from the viewpoint of designing the short-circuit withstand capability and the feedback capacitance Crss. However, the barrier-forming layer 19 can appropriately suppress leakage current caused by the depletion layer 46 .

[0349] Figure 4 Yes Figure 1 A graph showing the drain current-drain voltage characteristics of the semiconductor device 1. Figure 4 In the figure, the vertical axis represents the drain current ID [A / cm 2 ], and the horizontal axis represents the drain voltage VD [V]. The drain current ID is a current (short-circuit current) flowing between the drain electrode 7 and the source electrode layer 20 .

[0350] Figure 4 Graphs L1 and L2 are shown in FIG. Both graphs L1 and L2 are obtained through simulation. Graphs L1 and L2 represent changes in drain current ID when a drain voltage VD within a predetermined range is applied to drain electrode 7. Drain voltage VD varies within a range of 0V to 1000V.

[0351] Curve L1 represents the drain current-drain voltage characteristics of the semiconductor device of the reference example. Curve L2 represents the drain current-drain voltage characteristics of semiconductor device 1. The semiconductor device of the reference example has the same structure as semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0352] Referring to the curve L1, in the semiconductor device of the reference example, when the drain voltage VD exceeds 200 V, the drain current ID exceeds 15000 A / cm 2 On the other hand, referring to the curve L2, in the semiconductor device 1, the drain voltage VD is in the range of 0V to 1000V, and the drain current ID is less than 15000A / cm2 .

[0353] In the semiconductor device 1, the drain voltage VD is in the range of 400 V to 1000 V, and the drain current ID is 10000 A / cm 2 Above and less than 15000A / cm 2 range.

[0354] When the drain voltage VD is 600 V, the drain current ID of the semiconductor device 1 is reduced by approximately 45% compared to the drain current ID of the semiconductor device of the reference example.

[0355] From the simulation results, it was confirmed that the short-circuit withstand capability can be significantly improved by forming the deep well region 21 along the source trench 18 which is deeper than the gate trench 12 .

[0356] Figure 5 Yes Figure 1 The feedback capacitance-drain voltage characteristic curve of the semiconductor device 1 is shown in FIG. Figure 5 In the figure, the vertical axis represents the feedback capacitance Crss [F / cm 2 ], the horizontal axis represents the drain voltage VD [V].

[0357] exist Figure 5 Graphs L3 and L4 are shown. Both graphs L3 and L4 were obtained through simulation. Graphs L3 and L4 represent changes in feedback capacitance Crss when a drain voltage VD within a predetermined range is applied to drain electrode 7. Drain voltage VD varies within a range of 0V to 1000V.

[0358] Curve L3 represents the feedback capacitance-drain voltage characteristics of the semiconductor device of the reference example. Curve L4 represents the feedback capacitance-drain voltage characteristics of semiconductor device 1. The semiconductor device of the reference example has the same structure as semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0359] Referring to curve L3 , in the semiconductor device of the reference example, the feedback capacitance Crss decreases gradually when the drain voltage VD is in the range of 1 V to 10 V. In the semiconductor device of the reference example, the reduction rate of the feedback capacitance Crss is approximately 25% when the drain voltage VD is in the range of 1 V to 10 V.

[0360] On the other hand, in semiconductor device 1, feedback capacitance Crss decreases dramatically when drain voltage VD is in the range of 1V to 10V. When drain voltage VD is 10V, feedback capacitance Crss of semiconductor device 1 is approximately 95% less than feedback capacitance Crss of the semiconductor device of the reference example. In semiconductor device 1, the reduction rate of feedback capacitance Crss is 95% or more and 99% or less when drain voltage VD is in the range of 1V to 10V.

[0361] The simulation results confirm that the feedback capacitance Crss can be significantly reduced by forming the deep well region 21 along the source trench 18 deeper than the gate trench 12. In other words, it can be confirmed that the switching speed can be significantly improved by reducing the feedback capacitance Crss.

[0362] Figure 6 1 is a cross-sectional view showing a semiconductor device 51 according to a second embodiment of the present invention. Hereinafter, structures corresponding to those described in the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0363] Reference Figure 6 The source region 31 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The contact region 32 is formed in the deep well region 21 in a region along the second bottom wall 23 of the source trench 18. The contact region 32 is exposed from the second bottom wall 23 of the source trench 18.

[0364] The contact region 32 may cover the entire second bottom wall 23 of the source trench. The p-type impurity concentration of the contact region 32 is higher than the p-type impurity concentration of the deep well region 21.

[0365] exist Figure 6 , an example is shown in which the barrier-forming layer 19 is formed of a conductive barrier-forming layer. The barrier-forming layer 19 is formed along the inner wall surface of the source trench 18 so that the contact region 32 is selectively exposed from the second bottom wall 23 of the source trench 18 .

[0366] More specifically, the barrier-forming layer 19 includes a first portion 52 and a second portion 53. The first portion 52 of the barrier-forming layer 19 covers the second sidewall 22 of the source trench 18. The second portion 53 of the barrier-forming layer 19 partially covers the second bottom wall 23 of the source trench 18.

[0367] The second portion 53 of the barrier-forming layer 19 is connected to the first portion 52 of the barrier-forming layer 19. The second portion 53 of the barrier-forming layer 19 extends from the corner 26 of the source trench 18 along the second bottom wall 23.

[0368] The second portion 53 of the barrier-forming layer 19 exposes the central portion of the second bottom wall 23 of the source trench 18. The second portion 53 of the barrier-forming layer 19 may be formed in a shape without discontinuities (annular shape) in a plan view.

[0369] As described above, according to the semiconductor device 51, the same effects as those described for the semiconductor device 1 can be achieved. Furthermore, according to the semiconductor device 51, even if the depletion layer 46 spreads from the corner 26 of the source trench 18 along the second bottom wall 23, the barrier-forming layer 19 can ensure a sufficient distance for the depletion layer 46 to reach the source electrode layer 20. Thus, the occurrence of punch-through can be suppressed near the corner 26 of the source trench 18.

[0370] Figure 7 1 is a cross-sectional view showing a semiconductor device 61 according to a third embodiment of the present invention. Hereinafter, structures corresponding to those of the semiconductor device 51 described above are denoted by the same reference numerals and their descriptions are omitted.

[0371] An exposed portion 62 that selectively exposes the second bottom wall 23 of the source trench 18 is formed in the deep well region 21. More specifically, the second region 28 of the deep well region 21 is formed along the corner 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18. The second region 28 of the deep well region 21 may be formed in a continuous (ring-shaped) shape in a plan view.

[0372] In this embodiment, the contact region 32 is not formed. The contact region 32 may be formed in the surface portion of the body region 30 in a region along the second sidewall 22 of the source trench 18 .

[0373] The source electrode layer 20 forms a heterojunction portion with the SiC semiconductor layer 2 at the exposed portion 62 of the deep well region 21. This forms a heterojunction diode 63 having the source electrode layer 20 as an anode and the SiC semiconductor layer 2 as a cathode.

[0374] The source electrode layer 20 may also include conductive polysilicon. Of course, as long as the heterojunction diode 63 can be formed, the source electrode layer 20 may also include a conductive material other than conductive polysilicon.

[0375] A body diode 64 is formed at the pn junction between the SiC semiconductor layer 2 and the body region 30. The junction barrier of the heterojunction diode 63 is smaller than the diffusion potential of the body diode 64. The junction barrier of the heterojunction diode 63 may be greater than 1.0 eV and less than 1.5 eV. The diffusion potential of the body diode 64 may be greater than 2.8 eV and less than 3.2 eV.

[0376] As described above, semiconductor device 61 can achieve the same effects as those described for semiconductor device 51. Furthermore, in semiconductor device 61, when a reverse bias voltage is applied, current can preferentially flow into heterojunction diode 63. This can suppress the expansion of SiC crystal defects in SiC semiconductor layer 2. As a result, short-circuit withstand capability can be improved, feedback capacitance Crss can be reduced, and an increase in on-resistance can be suppressed.

[0377] Figure 8 1 is a cross-sectional view showing a semiconductor device 71 according to a fourth embodiment of the present invention. Hereinafter, structures corresponding to those of the semiconductor device 51 described above are denoted by the same reference numerals and their descriptions are omitted.

[0378] The barrier-forming layer 19 has a stacked structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 18. In this embodiment, the barrier-forming layer 19 has a stacked structure including an insulating barrier-forming layer 72 and a conductive barrier-forming layer 73 stacked in order from the inner wall of the source trench 18.

[0379] The insulating barrier-forming layer 72 is formed in a film shape along the inner wall surface of the source trench 18 . The insulating barrier-forming layer 72 selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18 .

[0380] More specifically, the insulating barrier-forming layer 72 includes a first portion 74 and a second portion 75 . The first portion 74 covers the second sidewall 22 of the source trench 18 . The second portion 75 selectively covers the second bottom wall 23 of the source trench 18 .

[0381] The second portion 75 is connected to the first portion 74. The second portion 75 extends from the corner 26 of the source trench 18 along the second bottom wall 23 so that the center portion of the second bottom wall 23 of the source trench 18 is exposed.

[0382] The insulating barrier-forming layer 72 may include at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0383] The conductive barrier-forming layer 73 is formed in a film along the insulating barrier-forming layer 72 so as to selectively expose the contact region 32 from the second bottom wall 23 of the source trench 18. The conductive barrier-forming layer 73 includes a conductive material different from that of the source electrode layer 20.

[0384] The conductive barrier-forming layer 73 may be formed of the same conductive material as that of the gate electrode layer 14. The conductive barrier-forming layer 73 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0385] As described above, according to the semiconductor device 71, the same effects as those described for the semiconductor device 51 can be achieved. Furthermore, in the semiconductor device 71, the barrier-forming layer 19 has a stacked structure including the insulating barrier-forming layer 72 and the conductive barrier-forming layer 73. Thus, the occurrence of punch-through can be suppressed by the two layers of the insulating barrier-forming layer 72 and the conductive barrier-forming layer 73.

[0386] If the conductive material of the conductive barrier-forming layer 73 is the same as that of the gate electrode layer 14 , the gate electrode layer 14 and the conductive barrier-forming layer 73 can be formed in the same process, thereby suppressing an increase in man-hours.

[0387] Figure 9 1 is a cross-sectional view showing a semiconductor device 81 according to a fifth embodiment of the present invention. Hereinafter, structures corresponding to those described in relation to the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0388] The barrier-forming layer 19 includes a first portion 82 and a second portion 83 . The first portion 82 of the barrier-forming layer 19 covers the second sidewall 22 of the source trench 18 . The second portion 83 of the barrier-forming layer 19 covers the second bottom wall 23 of the source trench 18 .

[0389] First portion 82 of barrier-forming layer 19 selectively includes sidewall contact hole 84 that exposes SiC semiconductor layer 2 from second sidewall 22 of source trench 18. First portion 82 covers first wall 24 of source trench 18, exposing second wall 25.

[0390] The first portion 82 may be formed across the boundary region between the SiC semiconductor layer 2 and the body region 30 . The end portion of the first portion 82 on the second principal surface 4 side may be formed in a region deeper than the bottom of the body region 30 .

[0391] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region shallower than the bottom of the body region 30. In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the bottom of the body region 30 and the bottom of the contact region 32. In the above case, the source electrode layer 20 is connected to at least the body region 30 within the source trench 18.

[0392] The end portion of first portion 82 on the second principal surface 4 side may be formed in the region between first principal surface 3 of SiC semiconductor layer 2 and the bottom of contact region 32. Barrier-forming layer 19 may also have only second portion 83 without first portion 82. In the above case, source electrode layer 20 is connected to body region 30 and contact region 32 within source trench 18.

[0393] The second portion 83 of the barrier-forming layer 19 is formed at a distance from the first portion 82 of the barrier-forming layer 19. The second portion 83 is separated from the first portion 82. The second portion 83 may cover the corner 26 of the source trench 18.

[0394] The second portion 83 may expose the corner 26 of the source trench 18 . The second portion 83 may cover the corner 26 of the source trench 18 and may also cover a portion of the second sidewall 22 of the source trench 18 .

[0395] Source electrode layer 20 forms a Schottky junction within source trench 18 and between SiC semiconductor layer 2. Thus, a Schottky barrier diode 85 is formed with source electrode layer 20 as an anode and SiC semiconductor layer 2 as a cathode.

[0396] The source electrode layer 20 may be formed of the same conductive material as the main surface source electrode 42. The source electrode layer 20 and the main surface source electrode 42 may be formed of aluminum or a metal material containing aluminum as a main component.

[0397] The source electrode layer 20 and the main surface source electrode 42 may also include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten. In this case, the gate electrode layer 14 is preferably formed of polysilicon (n-type polysilicon or p-type polysilicon).

[0398] A p-type deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18. The deep well region 21 may be formed continuously in the SiC semiconductor layer 2 in a region along the second side wall 22 and corner 26 of the source trench 18 so that the source electrode layer 20 is exposed from the second side wall 22 of the source trench 18.

[0399] That is, the deep well region 21 covers the second bottom wall 23 of the source trench 18. Furthermore, the deep well region 21 covers the corner 26 connecting the second side wall 22 and the second bottom wall 23 of the source trench 18. The deep well region 21 may expose substantially the entire second side wall 22 of the source trench 18 in the SiC semiconductor layer 2.

[0400] The deep well region 21 extends from the second bottom wall 23 of the source trench 18 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2. Thus, the deep well region 21 faces the body region 30 with a portion of the SiC semiconductor layer 2 interposed therebetween in the normal direction to the first main surface 3 of the SiC semiconductor layer 2.

[0401] More specifically, in the normal direction to the first main surface 3 of the SiC semiconductor layer 2 , the source electrode layer 20 is located at a depth between the body region 30 and the deep well region 21 and forms a Schottky junction with the SiC semiconductor layer 2 .

[0402] More specifically, in the normal direction of the first principal surface 3 of the SiC semiconductor layer 2 , the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in a region sandwiched between the body region 30 and the deep well region 21 .

[0403] The width W2 of the trench source structure 11 may be equal to the width WST of the source trench 18. That is, the first width Wα and the second width Wβ of the deep well region 21 may both be zero.

[0404] As described above, semiconductor device 81 can achieve the same effects as those described for semiconductor device 1. Furthermore, in semiconductor device 81, when a reverse bias voltage is applied, current can flow preferentially through Schottky barrier diode 85. This can suppress the expansion of SiC crystal defects in SiC semiconductor layer 2. As a result, short-circuit resistance can be improved, feedback capacitance Crss can be reduced, and an increase in on-resistance can be suppressed.

[0405] In this embodiment, an example is described in which the source electrode layer 20 is within the sidewall contact hole 84 of the barrier-forming layer 19 and forms a Schottky junction with the SiC semiconductor layer 2. However, an embodiment may also be employed in which the barrier-forming layer 19 (the first portion 82 and the second portion 83) is not formed.

[0406] Figure 10 1 is a plan view of a semiconductor device 91 according to a sixth embodiment of the present invention. Hereinafter, structures corresponding to those described in the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0407] Reference Figure 10 In this embodiment, the trench gate structure 10 is formed in a lattice shape in a plan view. The trench source structure 11 may be formed in a region surrounded by the trench gate structure 10 .

[0408] The source region 31 may also be formed along the periphery of the trench gate structure 10 . The contact region 32 may also be formed along the periphery of the trench source structure 11 .

[0409] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1. In addition, the semiconductor device 91 can also increase the density of the current flowing in the SiC semiconductor layer 2.

[0410] The structure of the semiconductor device 91 is also applicable to the above-described embodiments. Specifically, the structure in which the trench gate structure 10 is formed in a lattice pattern in plan view and the trench source structure 11 is formed in the region surrounded by the trench gate structure 10 is also applicable to the above-described embodiments.

[0411] Although the first to sixth embodiments of the present invention have been described, the first to sixth embodiments of the present invention can also be implemented in other forms.

[0412] In the first to sixth embodiments described above, the barrier-forming layer 19 may selectively expose the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. For example, the barrier-forming layer 19 may expose at least one of the contact region 32, the source region 31, and the body region 30 within the source trench 18.

[0413] In the above-described first to sixth embodiments, a structure in which the barrier-forming layer 19 is omitted may be employed.

[0414] In the first to sixth embodiments described above, the gate trench 12 may be formed in a tapered shape in which the area of ​​the first bottom wall 16 is smaller than the opening area in a cross-sectional view.

[0415] In the first to sixth embodiments described above, the first bottom wall 16 of the gate trench 12 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The first bottom wall 16 of the gate trench 12 may be formed in a convexly curved shape extending from the first side wall 15 toward the second main surface 4 of the SiC semiconductor layer 2.

[0416] In the first to sixth embodiments described above, source trench 18 may be formed in a tapered shape in which the area of ​​second bottom wall 23 is smaller than the area of ​​the opening in a cross-sectional view.

[0417] In the first to sixth embodiments described above, second bottom wall 23 of source trench 18 may be formed parallel to first main surface 3 of SiC semiconductor layer 2. Second bottom wall 23 of source trench 18 may be formed in a convexly curved shape extending outward from second side wall 22.

[0418] In the first to sixth embodiments described above, a Si (silicon) Si semiconductor layer (2) may be used instead of a SiC single crystal SiC semiconductor layer 2. That is, the Si semiconductor layer (2) may have a stacked structure including a Si semiconductor substrate (5) made of Si and a Si epitaxial layer (6) made of Si.

[0419] In the first to sixth embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0420] In the first to sixth embodiments described above, a p+ type SiC semiconductor substrate (5) may be used instead of the n+ type SiC semiconductor substrate 5. This structure can provide an IGBT (Insulated Gate Bipolar Transistor) instead of a MISFET.

[0421] In this case, the "source" of the MISFET is replaced by the "emitter" of the IGBT. Furthermore, the "drain" of the MISFET is replaced by the "collector" of the IGBT. Even when an IGBT is used instead of the MISFET, the same effects as those described in the above embodiments can be achieved.

[0422] Figure 11 It is a plan view showing a semiconductor device 101 according to a seventh embodiment of the present invention.

[0423] Reference Figure 11 The semiconductor device 101 includes a SiC semiconductor layer 102 made of SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also include 4H-SiC single crystal.

[0424] 4H-SiC single crystals have an off-angle of less than 10° from the (0001) plane relative to the [11-20] direction. The off-angle can be between 0° and 4°. It can also be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically, within the range of 2°±0.2° or 4°±0.4°.

[0425] In this embodiment, SiC semiconductor layer 102 is formed into a rectangular parallelepiped sheet having a first principal surface 103 on one side, a second principal surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first principal surface 103 and the second principal surface 104 .

[0426] The first main surface 103 and the second main surface 104 are formed into a quadrilateral shape in a plan view (hereinafter referred to as "plan view") as viewed from the normal direction. The side surface 105A faces the side surface 105C. The side surface 105B faces the side surface 105D.

[0427] Side surfaces 105A to 105D extend in a planar manner along the normal direction of first and second principal surfaces 103 and 104. Side surfaces 105A to 105D may each have a length of 1 mm to 10 mm (eg, 2 mm to 5 mm).

[0428] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107 . The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106 .

[0429] Active region 106 is provided in the center of SiC semiconductor layer 102, spaced apart from side surfaces 105A to 105D of SiC semiconductor layer 102 toward the inner region of SiC semiconductor layer 102 in a plan view. Active region 106 is provided in a quadrilateral shape having four sides parallel to side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view.

[0430] The outer region 107 is defined between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is defined in a continuous shape (a square ring shape) surrounding the active region 106 in a plan view.

[0431] On the first main surface 103 of the SiC semiconductor layer 102, a gate pad 108, a gate finger 109, and a source pad 110 are formed as first main surface electrodes. Figure 11 , for clarity, the gate pad 108, the gate fingers 109, and the source pad 110 are shown by hatching. The gate pad 108, the gate fingers 109, and the source pad 110 may also include aluminum or copper.

[0432] Gate pad 108 is formed along side surface 105A of SiC semiconductor layer 102 in a plan view. Gate pad 108 is formed along the central region of side surface 105A of SiC semiconductor layer 102 in a plan view. Gate pad 108 may also be formed along any two corners connecting any of the four side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view.

[0433] The gate pad 108 is formed into a quadrilateral shape in a plan view and extends from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view.

[0434] Gate fingers 109 are formed in outer region 107. Gate fingers 109 extend from gate pad 108 and extend in a stripe shape in outer region 107. In this embodiment, gate fingers 109 are formed along three side surfaces 105A, 105B, and 105D of SiC semiconductor layer 102 to divide active region 106 in three directions.

[0435] Source pad 110 is formed in active region 106 at a distance from gate pad 108 and gate finger 109. Source pad 110 is formed in a concave shape in a plan view so as to cover a concave region defined by gate pad 108 and gate finger 109.

[0436] A gate voltage is applied to gate pad 108 and gate finger 109. The gate voltage may be greater than or equal to 10 V and less than or equal to 50 V (eg, approximately 30 V). A source voltage is applied to source pad 110. The source voltage may be a reference voltage (eg, GND voltage).

[0437] Figure 12 yes Figure 11 The enlarged view of the region XII shown is an enlarged view for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102 . Figure 13 It is along Figure 12 A cross-sectional view taken along line XIII-XIII is shown. Figure 14 It is along Figure 12 A cross-sectional view taken along line XIV-XIV is shown.

[0438] Reference Figures 12 to 14 In this embodiment, the SiC semiconductor layer 102 has a stacked structure including an n+-type SiC semiconductor substrate 111 and an n-type SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 111.

[0439] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 may be a polished surface. The second main surface 104 of the SiC semiconductor layer 102 may have polishing marks.

[0440] The thickness of the SiC semiconductor substrate 111 may be greater than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate 111 may be greater than 5 μm. The thickness of the SiC semiconductor substrate 111 may be greater than 25 μm. The thickness of the SiC semiconductor substrate 111 may be greater than 50 μm. The thickness of the SiC semiconductor substrate 111 may be greater than 100 μm.

[0441] The thickness of the SiC semiconductor substrate 111 may be 700 μm or less. The thickness of the SiC semiconductor substrate 111 may be 500 μm or less. The thickness of the SiC semiconductor substrate 111 may be 400 μm or more. The thickness of the SiC semiconductor substrate 111 may be 300 μm or less.

[0442] The thickness of the SiC semiconductor substrate 111 may be 250 μm or less. The thickness of the SiC semiconductor substrate 111 may be 200 μm or less. The thickness of the SiC semiconductor substrate 111 may be 150 μm or less. The thickness of the SiC semiconductor substrate 111 may be 100 μm or less.

[0443] The thickness of the SiC semiconductor substrate 111 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 111 , the resistance value can be reduced by shortening the current path.

[0444] The thickness of the SiC epitaxial layer 112 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 112 may be 5 μm or more. The thickness of the SiC epitaxial layer 112 may be 10 μm or more.

[0445] The thickness of the SiC epitaxial layer 112 may be 50 μm or less. The thickness of the SiC epitaxial layer 112 may be 40 μm or less. The thickness of the SiC epitaxial layer 112 may be 30 μm or less.

[0446] The thickness of the SiC epitaxial layer 112 may be 20 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 10 μm or less.

[0447] The n-type impurity concentration of the SiC epitaxial layer 112 is lower than the n-type impurity concentration of the SiC semiconductor substrate 111 . More specifically, the n-type impurity concentration of the SiC epitaxial layer 112 is lower than the n-type impurity concentration of the SiC semiconductor substrate 111 .

[0448] The n-type impurity concentration of the SiC semiconductor substrate 111 may be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 The n-type impurity concentration of the SiC epitaxial layer 112 may be 1.0×10 15 cm －3 Above and 1.0×10 18 cm －3 In this embodiment, the SiC epitaxial layer 112 has a plurality of regions having different n-type impurity concentrations along the normal direction of the first main surface 103 of the SiC semiconductor layer 102 .

[0449] More specifically, the SiC epitaxial layer 112 includes a high-concentration region 112a having a relatively high n-type impurity concentration, and a low-concentration region 112b having a lower n-type impurity concentration than the high-concentration region 112a. The high-concentration region 112a is formed in a region on the first main surface 103 side. The low-concentration region 112b is formed in a region on the SiC semiconductor substrate 111 side relative to the high-concentration region 112a.

[0450] The n-type impurity concentration of the high-concentration region 112a may also be 1×10 16 cm －3 Above and 1×10 18 cm －3 The n-type impurity concentration of the low-concentration region 112b may be 1×10 15 cm －3 Above and 1×10 16 The thickness of the high-concentration region 112a is less than the thickness of the low-concentration region 112b. More specifically, the thickness of the high-concentration region 112a is smaller than the thickness of the low-concentration region 112b.

[0451] Drain pad 113 as a second main surface electrode is connected to second main surface 104 of SiC semiconductor layer 102. During the off state, the maximum voltage applicable between source pad 110 and drain pad 113 may be 1000V or more and 10000V or less.

[0452] The SiC semiconductor substrate 111 is formed as the drain region 114 of the MISFET. The SiC epitaxial layer 112 is formed as the drift region 115 of the MISFET.

[0453] In the active region 106, a p-type body region 116 is formed on the surface of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 116 may be 1×10 17 cm －3 Above and 1×10 20 cm －3 Next, the active region 106 is defined by the body region 116 .

[0454] In the active region 106, a plurality of gate trenches 121 are formed in the surface portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 121 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 121 are formed in a strip shape extending along a second direction Y intersecting the first direction X.

[0455] More specifically, the first direction X is a direction along the side surfaces 105B and 105D of the SiC semiconductor layer 102 . The second direction Y is a direction perpendicular to the first direction X. The second direction Y is also a direction along the side surfaces 105A and 105C of the SiC semiconductor layer 102 .

[0456] The plurality of gate trenches 121 are formed in a stripe shape in a plan view. In this embodiment, each gate trench 121 extends in a stripe shape from the peripheral portion on one side (side surface 105B) toward the peripheral portion on the other side (side surface 105D) of the first main surface 103 of the SiC semiconductor layer 102 in a plan view.

[0457] Each gate trench 121 extends across the middle portion between the peripheral portion on one side of the first main surface 103 and the peripheral portion on the other side of the first main surface 103, as viewed from above. One end of each gate trench 121 is located at the peripheral portion on one side of the first main surface 103 of the SiC semiconductor layer 102. The other end of each gate trench 121 is located at the peripheral portion on the other side of the first main surface 103 of the SiC semiconductor layer 102.

[0458] The first direction X may be set to the [11-20] direction ([-1-120] direction). In this case, each gate trench 121 may extend along the [11-20] direction. The first direction X may be set to the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 121 may extend along the [-1100] direction ([1-100] direction).

[0459] Each gate trench 121 has a length of the order of millimeters (a length of 1 mm or more). Figure 14 In the cross section shown, the length of the gate trench 121 is the length from the end portion on the connection side between the gate trench 121 and the gate finger 109 to the end portion on the opposite side.

[0460] The length of each gate trench 121 may also be greater than 0.5 mm. In this embodiment, the length of each gate trench 121 is greater than 1 mm and less than 10 mm (e.g., greater than 2 mm and less than 5 mm). The total extension of one or more gate trenches 121 per unit area may also be 0.5 μm / μm. 2 Above and 0.75μm / μm 2 the following.

[0461] Each gate trench 121 integrally includes an active trench portion 121a and a contact trench portion 121b. The active trench portion 121a is the portion of the gate trench 121 formed in the active region 106. The contact trench portion 121b is the portion of the gate trench 121 extending from the active trench portion 121a to the outer region 107.

[0462] Each gate trench 121 penetrates the body region 116 and reaches the SiC epitaxial layer 112 . The bottom wall of each gate trench 121 is located in the SiC epitaxial layer 112 . More specifically, the bottom wall of each gate trench 121 is located in the high concentration region 112 a of the SiC epitaxial layer 112 .

[0463] The depth of the gate trench 121 may be 0.5 μm to 3 μm (eg, approximately 1 μm) in the normal direction of the first main surface 103 of the SiC semiconductor layer 102. The depth of the gate trench 121 is preferably 0.5 μm to 1.0 μm.

[0464] The width of the gate trench 121 in the first direction may be 0.1 μm or more and 2 μm or less (eg, approximately 0.5 μm). The width of the gate trench 121 in the first direction is preferably 0.1 μm or more and 0.5 μm or less.

[0465] Reference Figure 13 as well as Figure 14 The opening edge portion 124 of each gate trench 121 includes a curved portion 125 that curves inwardly of the gate trench 121 . The opening edge portion 124 of the gate trench 121 is a corner portion connecting the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of the gate trench 121 .

[0466] The electric field of the gate trench 121 with respect to the opening edge portion 124 is dispersed along the curved portion 125. Thus, the electric field concentration of the gate trench 121 with respect to the opening edge portion 124 can be alleviated.

[0467] In the surface portion of the body region 116, an n+ type source region 126 is formed in a region along the sidewall of the gate trench 121. The n-type impurity concentration of the source region 126 may be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0468] A plurality of source regions 126 are formed along one sidewall and the other sidewall of the gate trench 121 in the first direction X. The plurality of source regions 126 are each formed in a band shape extending in the second direction Y. The plurality of source regions 126 are formed in a stripe shape in a plan view.

[0469] In each gate trench 121, a gate insulating layer 131 and a gate electrode layer 132 are formed. Figure 12 In FIG, the gate insulating layer 131 and the gate electrode layer 132 are shown by hatching.

[0470] The gate insulating layer 131 may also include silicon oxide. The gate insulating layer 131 may also include other insulating films such as silicon nitride. The gate insulating layer 131 is formed in a film shape along the inner wall surface of the gate trench 121 so as to define a concave space in the gate trench 121 .

[0471] The gate insulating layer 131 includes a first region 131a, a second region 131b, and a third region 131c. The first region 131a is formed along the sidewalls of the gate trench 121. The second region 131b is formed along the bottom wall of the gate trench 121. The third region 131c is formed along the first main surface 103 of the SiC semiconductor layer 102.

[0472] The thickness T1 of the first region 131a is smaller than the thickness T2 of the second region 131b and the thickness T3 of the third region 131c. The ratio T2 / T1 of the thickness T2 of the second region 131b to the thickness T1 of the first region 131a may be greater than 2 and less than 5. The ratio T3 / T1 of the thickness T3 of the third region 131c to the thickness T1 of the first region 131a may be greater than 2 and less than 5.

[0473] The thickness T1 of the first region 131a may be 0.01 μm to 0.2 μm, the thickness T2 of the second region 131b may be 0.05 μm to 0.5 μm, and the thickness T3 of the third region 131c may be 0.05 μm to 0.5 μm.

[0474] By forming the first region 131a of the gate insulating layer 131 relatively thin, it is possible to suppress an increase in carriers induced in the area near the sidewalls of the gate trench 121 within the body region 116. This can thereby suppress an increase in channel resistance. By forming the second region 131b of the gate insulating layer 131 relatively thick, it is possible to mitigate electric field concentration on the bottom wall of the gate trench 121.

[0475] By forming the third region 131c of the gate insulating layer 131 thickly, the breakdown voltage of the gate insulating layer 131 near the opening edge 124 of the gate trench 121 can be improved. In addition, by forming the third region 131c thickly, it is possible to prevent the third region 131c from disappearing due to etching.

[0476] This can prevent the first region 131 a from being removed by etching due to the disappearance of the third region 131 c . As a result, the gate electrode layer 132 can be appropriately opposed to the SiC semiconductor layer 102 via the gate insulating layer 131 .

[0477] The gate electrode layer 132 is embedded in the gate trench 121 via the gate insulating layer 131. More specifically, the gate electrode layer 132 is embedded in the gate trench 121 so as to fill the concave space defined by the gate insulating layer 131. The gate electrode layer 132 is controlled by a gate voltage.

[0478] Reference Figure 13 as well as Figure 14 The gate electrode layer 132 is formed in a wall shape that extends in a direction normal to the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view and is perpendicular to the extending direction of the gate trench 121 .

[0479] Gate electrode layer 132 has an upper end portion located on the opening side of gate trench 121. The upper end portion of gate electrode layer 132 is formed in a curved shape that is recessed toward the bottom wall of gate trench 121.

[0480] The cross-sectional area of ​​the gate electrode layer 132 (the cross-sectional area perpendicular to the direction in which the gate trench 121 extends) may be 0.05 μm 2 Above and 0.5μm 2 Hereinafter, the cross-sectional area of ​​the gate electrode layer 132 is defined by the product of the depth of the gate electrode layer 132 and the width of the gate electrode layer 132 .

[0481] The depth of the gate electrode layer 132 is the distance from the upper end to the lower end of the gate electrode layer 132. The width of the gate electrode layer 132 is the width of the trench at a position midway between the upper end and the lower end of the gate electrode layer 132. When the upper end is a curved surface (in this embodiment, a curved shape that is concave toward the bottom), the position of the upper end of the gate electrode layer 132 is the middle position in the depth direction of the upper surface of the gate electrode layer 132.

[0482] The gate electrode layer 132 includes p-type polysilicon to which p-type impurities are added. The p-type impurities may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0483] The p-type impurity concentration of the gate electrode layer 132 is equal to or higher than the p-type impurity concentration of the body region 116 . More specifically, the p-type impurity concentration of the gate electrode layer 132 is higher than the p-type impurity concentration of the body region 116 .

[0484] The p-type impurity concentration of the gate electrode layer 132 may also be 1×10 18 cm －3 Above and 1×10 22 cm －3 The sheet resistance of the gate electrode layer 132 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this embodiment).

[0485] Reference Figure 14 A gate wiring layer 133 is formed in the outer region 107 . The gate wiring layer 133 is electrically connected to the gate pad 108 and the gate finger 109 .

[0486] The gate wiring layer 133 is formed on the first main surface 103 of the SiC semiconductor layer 102 . More specifically, the gate wiring layer 133 is formed on the third region 131 c of the gate insulating layer 131 .

[0487] In this embodiment, the gate wiring layer 133 is formed along the gate finger 109. The gate wiring layer 133 is formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to divide the active region 106 in three directions.

[0488] The gate wiring layer 133 is connected to the gate electrode layer 132 exposed from the contact trench portion 121b of each gate trench 121. In this embodiment, the gate wiring layer 133 is formed by a lead portion extending from the gate electrode layer 132 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 133 is connected to the upper end of the gate electrode layer 132.

[0489] Reference Figure 13 A low-resistance electrode layer 134 is formed on the gate electrode layer 132 . The low-resistance electrode layer 134 covers the upper end portion of the gate electrode layer 132 in the gate trench 121 .

[0490] The low-resistance electrode layer 134 includes a conductive material having a sheet resistance smaller than that of the gate electrode layer 132. The sheet resistance of the low-resistance electrode layer 134 may be 0.01 Ω / □ or more and 10 Ω / □ or less.

[0491] The current supplied to the gate trench 121 flows through the low-resistance electrode layer 134, which has a relatively low sheet resistance, and is then transferred to the entire gate electrode layer 132. This allows the entire gate electrode layer 132 (the entire active region 106) to quickly transition from an off state to an on state, thereby suppressing delays in switching response.

[0492] In particular, in the case of a gate trench 121 having a length on the order of millimeters, current propagation requires time. However, the low-resistance electrode layer 134 can appropriately suppress delays in switching response. Specifically, the low-resistance electrode layer 134 is formed within the gate trench 121 as a current spreading electrode layer that spreads current.

[0493] Furthermore, as the cell structure becomes increasingly miniaturized, the width, depth, cross-sectional area, and the like of the gate electrode layer 132 decrease, and thus there is a concern that the resistance in the gate trench 121 may increase, causing a delay in the switching response.

[0494] However, the low-resistance electrode layer 134 allows the entire gate electrode layer 132 to quickly transition from the off state to the on state, and thus it is possible to appropriately suppress a delay in switching response due to miniaturization.

[0495] The low-resistance electrode layer 134 is formed in a film shape. The low-resistance electrode layer 134 includes a connecting portion 134a that is in contact with the upper end of the gate electrode layer 132, and a non-connecting portion 134b opposite thereto. The connecting portion 134a and the non-connecting portion 134b of the low-resistance electrode layer 134 can also be formed in a curved shape, mimicking the upper end of the gate electrode layer 132. The connecting portion 134a and the non-connecting portion 134b of the low-resistance electrode layer 134 can be formed in various forms.

[0496] The entire connection portion 134 a of the low-resistance electrode layer 134 may be located above the first principal surface 103 of the SiC semiconductor layer 102 . The entire connection portion 134 a of the low-resistance electrode layer 134 may be located below the first principal surface 103 of the SiC semiconductor layer 102 .

[0497] The connection portion 134a of the low-resistance electrode layer 134 may include a portion located above the first principal surface 103 of the SiC semiconductor layer 102. The connection portion 134a of the low-resistance electrode layer 134 may include a portion located below the first principal surface 103 of the SiC semiconductor layer 102.

[0498] For example, the central portion of the connection portion 134 a of the low-resistance electrode layer 134 may be located below the first principal surface 103 of the SiC semiconductor layer 102 , and the peripheral portion of the connection portion 134 a of the low-resistance electrode layer 134 may be located above the first principal surface 103 of the SiC semiconductor layer 102 .

[0499] The entire non-connection portion 134 b of the low-resistance electrode layer 134 may be located above the first principal surface 103 of the SiC semiconductor layer 102 . The entire non-connection portion 134 b of the low-resistance electrode layer 134 may be located below the first principal surface 103 of the SiC semiconductor layer 102 .

[0500] The non-connecting portion 134b of the low-resistance electrode layer 134 may include a portion located above the first principal surface 103 of the SiC semiconductor layer 102. The non-connecting portion 134b of the low-resistance electrode layer 134 may include a portion located below the first principal surface 103 of the SiC semiconductor layer 102.

[0501] For example, the central portion of the non-connection portion 134 b of the low-resistance electrode layer 134 may be located below the first principal surface 103 of the SiC semiconductor layer 102 , and the peripheral portion of the non-connection portion 134 b of the low-resistance electrode layer 134 may be located above the first principal surface 103 of the SiC semiconductor layer 102 .

[0502] The low-resistance electrode layer 134 has an edge portion 134c in contact with the gate insulating layer 131. The edge portion 134c of the low-resistance electrode layer 134 is in contact with a corner portion of the gate insulating layer 131 connecting the first region 131a and the second region 131b.

[0503] The edge portion 134 c of the low-resistance electrode layer 134 is formed in a region on the first principal surface 103 side of the SiC semiconductor layer 102 relative to the bottom of the source region 126. In other words, the edge portion 134 c of the low-resistance electrode layer 134 is formed in a region on the first principal surface 103 side of the SiC semiconductor layer 102 relative to the boundary region between the body region 116 and the source region 126.

[0504] Therefore, the edge portion 134c of the low-resistance electrode layer 134 faces the source region 126 via the gate insulating layer 131. The edge portion 134c of the low-resistance electrode layer 134 does not face the body region 116 via the gate insulating layer 131.

[0505] This can prevent a current path from being formed in the region between the low-resistance electrode layer 134 of the gate insulating layer 131 and the body region 116 . The current path can be formed by undesired diffusion of the electrode material of the low-resistance electrode layer 134 into the gate insulating layer 131 .

[0506] In particular, the design of connecting the edge 134 c of the low-resistance electrode layer 134 to the third region 131 c of the relatively thick gate insulating layer 131 (the corner of the gate insulating layer 131 ) is effective in reducing the risk of forming a current path.

[0507] In the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the thickness TR of the low-resistance electrode layer 134 is less than or equal to the thickness TG of the gate electrode layer 132 (TR≤TG). The thickness TR of the low-resistance electrode layer 134 is preferably less than the thickness TG of the gate electrode layer 132 (TR<TG). More specifically, the thickness TR of the low-resistance electrode layer 134 is preferably less than or equal to half the thickness TG of the gate electrode layer 132 (TR≤TG / 2).

[0508] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 134 to the thickness TG of the gate electrode layer 132 is 0.01 to 1. The thickness TG of the gate electrode layer 132 may be 0.5 μm to 3 μm. The thickness TR of the low-resistance electrode layer 134 may be 0.01 μm to 3 μm.

[0509] Reference Figure 14 In this embodiment, the low-resistance electrode layer 134 also covers the upper end of the gate wiring layer 133. The portion of the low-resistance electrode layer 134 covering the upper end of the gate wiring layer 133 is formed integrally with the portion of the low-resistance electrode layer 134 covering the upper end of the gate electrode layer 132. Thus, the low-resistance electrode layer 134 covers the entire region of the gate electrode layer 132 and the entire region of the gate wiring layer 133.

[0510] Therefore, the current supplied from the gate pad 108 and the gate fingers 109 to the gate wiring layer 133 flows through the low-resistance electrode layer 134 having a relatively low sheet resistance and is transferred to the entire gate electrode layer 132 and the gate wiring layer 133 .

[0511] This allows the entire gate electrode layer 132 (the entire active region 106 ) to quickly transition from an off state to an on state via the gate wiring layer 133 , thereby suppressing a delay in switching response.

[0512] In particular, in the case of the gate trench 121 having a length of the order of millimeters, the delay in the switching response can be appropriately suppressed by the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133 .

[0513] The low-resistance electrode layer 134 includes a polycrystalline layer. The polycrystalline layer is formed by silicide of a metal material forming the surface portion of the gate electrode layer 132. More specifically, the polycrystalline layer is composed of a p-type polycrystalline layer containing p-type impurities added to the gate electrode layer 132 (p-type polysilicon).

[0514] In this embodiment, the polycrystalline layer has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. More specifically, the polycrystalline layer includes at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2.

[0515] When low-resistance electrode layer 134 is formed on p-type polysilicon, the sheet resistance within gate trench 121 is less than the sheet resistance of gate electrode layer 132 (p-type polysilicon) alone. The sheet resistance within gate trench 121 is preferably less than the sheet resistance of n-type polysilicon to which n-type impurities have been added.

[0516] The sheet resistance in the gate trench 121 is similar to the sheet resistance of the low-resistance electrode layer 134. That is, the sheet resistance in the gate trench 121 may be greater than 0.01Ω / □ and less than 10Ω / □. The sheet resistance in the gate trench 121 is preferably less than 10Ω / □.

[0517] Figure 15 The results of investigating the resistivity of the polycrystalline layer are shown. Figure 15 This is a graph showing the relationship between the resistivity of polycrystalline and the formation temperature. Figure 15 In the graph, the vertical axis represents the resistivity [μΩ·cm], and the horizontal axis represents the polycrystal formation temperature [°C].

[0518] Reference Figure 15 The resistivity decreases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2. Therefore, the priority of the material used as the polycrystalline layer increases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2.

[0519] In particular, NiSi, CoSi 2 , and TiSi 2 among the above-mentioned materials are suitable as the polycrystalline layer for forming the low-resistance electrode layer 134 because their resistivity values ​​and temperature dependence are relatively small.

[0520] Furthermore, according to the inventors' verification results, when TiSi2 is used as the material for the low-resistance electrode layer 134, an increase in gate-source leakage current is observed when a low electric field is applied. In contrast, when CoSi2 is used, no increase in gate-source leakage current is observed when a low electric field is applied. Considering that NiSi has issues with heat resistance compared to CoSi2, CoSi2 is the most preferred material for the polycrystalline layer forming the low-resistance electrode layer 134.

[0521] Reference Figure 12 as well as Figure 13 In the active region 106 , a plurality of source trenches 141 are formed in the first main surface 103 of the SiC semiconductor layer 102 . Each source trench 141 is formed in a region between two adjacent gate trenches 121 .

[0522] The plurality of source trenches 141 are formed in a stripe shape extending in the second direction Y. The plurality of source trenches 141 are formed in a stripe shape in a plan view. The distance between the center portions of adjacent source trenches 141 in the first direction X may be 1.5 μm or more and 3 μm or less.

[0523] Each source trench 141 penetrates the body region 116 and reaches the SiC epitaxial layer 112 . The bottom wall of each source trench 141 is located in the SiC epitaxial layer 112 . More specifically, the bottom wall of each source trench 141 is located in the high concentration region 112 a of the SiC epitaxial layer 112 .

[0524] The depth of the source trench 141 is substantially equal to the depth of the gate trench 121. The depth of the source trench 141 may be greater than the depth of the gate trench 121. The depth of the source trench 141 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 may be greater than or equal to 0.5 μm and less than or equal to 10 μm (e.g., approximately 1 μm).

[0525] The first-direction width of the source trench 141 may be substantially equal to the first-direction width of the gate trench 121. The first-direction width of the source trench 141 may be greater than the first-direction width of the gate trench 121. The first-direction width of the source trench 141 may be greater than or equal to 0.1 μm and less than or equal to 2 μm (e.g., approximately 0.5 μm).

[0526] Opening edge 142 of each source trench 141 includes a curved portion 143 curved inwardly of source trench 141 . Opening edge 142 of source trench 141 is a corner connecting first principal surface 103 of SiC semiconductor layer 102 and the sidewall of source trench 141 .

[0527] The electric field with respect to the opening edge portion 142 of the source trench 141 is dispersed along the bent portion 143. Thus, the electric field concentration with respect to the opening edge portion 142 of the source trench 141 can be alleviated.

[0528] In the SiC semiconductor layer 102, a p+ type contact region 144 is formed in a region along the sidewall of the source trench 141. The p-type impurity concentration of the contact region 144 may be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 Next, a plurality of contact regions 144 are formed on one side surface and the other side surface of one source trench 141 .

[0529] The plurality of contact regions 144 are formed at intervals along the second direction Y. The plurality of contact regions 144 are formed at intervals along the first direction X from the gate trench 121 .

[0530] In SiC semiconductor layer 102, a p-type deep well region 145 is formed in a region along the inner wall of source trench 141. Deep well region 145 is also referred to as a withstand voltage maintaining region. Deep well region 145 is formed in a band shape extending along source trench 141. Deep well region 145 extends along the inner wall of source trench 141.

[0531] Reference Figure 12 as well as Figure 14 More specifically, the deep well region 145 extends along the sidewalls of the source trench 141 , passes through the edge portion, and covers the bottom wall of the source trench 141 . The deep well region 145 is connected to the body region 116 at the sidewalls of the source trench 141 .

[0532] The deep well region 145 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0533] The p-type impurity concentration of the deep well region 145 may be substantially equal to the p-type impurity concentration of the body region 116. The p-type impurity concentration of the deep well region 145 may also exceed the p-type impurity concentration of the body region 116. The p-type impurity concentration of the deep well region 145 may also be lower than the p-type impurity concentration of the body region 116.

[0534] The p-type impurity concentration of the deep well region 145 may be lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 145 may be lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 21 may be 1.0×10 17 cm －3 Above and 1.0×10 19 cm －3 the following.

[0535] Reference Figure 12 as well as Figure 14 A p-type peripheral deep well region 148 is formed in the outer region 107 . The peripheral deep well region 148 is electrically connected to the deep well region 145 .

[0536] The peripheral deep well region 148 is configured to have the same potential as the deep well region 145. In this embodiment, the peripheral deep well region 148 and the deep well region 145 are formed integrally.

[0537] More specifically, the peripheral deep well region 148 extends in a band shape along the periphery of the active region 106 in the outer region 107. More specifically, the peripheral deep well region 148 is formed in a seamless shape (in this embodiment, a quadrilateral ring shape) surrounding the active region 106.

[0538] Peripheral deep well region 148 is formed in outer region 107 in a region along the surface portion of first main surface 103 of SiC semiconductor layer 102 and the inner wall of contact trench portion 121b of gate trench 121. Peripheral deep well region 148 extends along the sidewalls of contact trench portion 121b, passes through the edge portion, and covers the bottom wall of contact trench portion 121b.

[0539] The peripheral deep well region 148 overlaps with the gate wiring layer 133 in a plan view. That is, the peripheral deep well region 148 faces the gate wiring layer 133 via the gate insulating layer 131 (third region 131c).

[0540] The peripheral deep well region 148 has a bottom portion located closer to the second main surface 104 of the SiC semiconductor layer 102 than the bottom wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0541] Peripheral deep well region 148 includes lead portion 148a extending from outer region 107 toward the periphery of active region 106 in a plan view. Lead portion 148a of peripheral deep well region 148 covers the end portion of source trench 141 located on the outer region 107 side in a plan view.

[0542] The lead portion 148a of the peripheral deep well region 148 covers the inner wall of the active trench portion 121a at the peripheral portion of the active region 106. The lead portion 148a of the peripheral deep well region 148 extends along the sidewall of the active trench portion 121a, passes through the edge portion, and covers the bottom wall of the active trench portion 121a. The lead portion 148a of the peripheral deep well region 148 is connected to the deep well region 145 in the active region 106.

[0543] The lead portion 148a of the peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the active trench portion 121a of the gate trench 121. The lead portion 148a of the peripheral deep well region 148 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0544] The p-type impurity concentration of the peripheral deep well region 148 may be substantially equal to the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may also exceed the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may also be lower than the p-type impurity concentration of the body region 116.

[0545] The p-type impurity concentration of peripheral deep well region 148 may be substantially equal to the p-type impurity concentration of deep well region 145. The p-type impurity concentration of peripheral deep well region 148 may also exceed the p-type impurity concentration of deep well region 145. The p-type impurity concentration of peripheral deep well region 148 may also be lower than the p-type impurity concentration of deep well region 145.

[0546] The p-type impurity concentration of the peripheral deep well region 148 may be lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be 1.0×10 17 cm －3 Above and 1.0×10 19 cm －3 the following.

[0547] A source insulating layer 146 and a source electrode layer 147 are formed in each source trench 141. Figure 12 In FIG, the source insulating layer 146 and the source electrode layer 147 are shown by hatching.

[0548] The source insulating layer 146 may also include silicon oxide. The source insulating layer 146 is formed in a film shape along the inner wall surface of the source trench 141 so as to define a concave space in the source trench 141 .

[0549] Source insulating layer 146 includes a first region 146a and a second region 146b. First region 146a is formed along the sidewalls of source trench 141. Second region 146b is formed along the bottom wall of source trench 141. Thickness T11 of first region 146a is smaller than thickness T12 of second region 146b.

[0550] The ratio T12 / T11 of the thickness T12 of the second region 146b to the thickness T11 of the first region 146a may be 2 to 5. The thickness T11 of the first region 146a may be 0.01 μm to 0.2 μm. The thickness T12 of the second region 146b may be 0.05 μm to 0.5 μm.

[0551] The thickness T11 of the first region 146a may be substantially equal to the thickness T1 of the first region 131a of the gate insulating layer 131 . The thickness T12 of the second region 146b may be substantially equal to the thickness T2 of the second region 131b of the gate insulating layer 131 .

[0552] The source insulating layer 146 exposes the opening edge portion 142 of the source trench 141 . More specifically, the source insulating layer 146 exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141 .

[0553] More specifically, the first region 146 a of the source insulating layer 146 has an upper end portion located on the opening side of the source trench 141 . The upper end portion of the first region 146 a is formed below the first main surface 103 of the SiC semiconductor layer 102 .

[0554] The upper end of the first region 146a exposes the sidewall of the source trench 141 on the opening side of the source trench 141. Thus, the first region 146a exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0555] The source electrode layer 147 is embedded in the source trench 141 via the source insulating layer 146. More specifically, the source electrode layer 147 is embedded in the source trench 141 so as to fill the concave space defined by the source insulating layer 146. The source electrode layer 147 is controlled by the source voltage.

[0556] Source electrode layer 147 has an upper end portion located on the opening side of source trench 141. The upper end portion of source electrode layer 147 is formed below first main surface 103 of SiC semiconductor layer 102. The upper end portion of source electrode layer 147 may be formed on the same surface as the upper end portion of source insulating layer 146.

[0557] The upper end of the source electrode layer 147 may protrude further upward than the upper end of the source insulating layer 146. The upper end of the source electrode layer 147 may be located lower than the upper end of the source insulating layer 146. The thickness of the source electrode layer 147 may be greater than or equal to 0.5 μm and less than or equal to 10 μm (e.g., approximately 1 μm).

[0558] The source electrode layer 147 is preferably made of polycrystalline silicon, which has properties similar to those of SiC. This can reduce stress generated within the SiC semiconductor layer 102. The source electrode layer 147 is preferably made of p-type polycrystalline silicon to which p-type impurities are added. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 132.

[0559] The p-type impurity concentration of the source electrode layer 147 is greater than or equal to the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the source electrode layer 147 is greater than the p-type impurity concentration of the body region 116. The p-type impurity of the source electrode layer 147 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0560] The p-type impurity concentration of the source electrode layer 147 may also be 1×10 18 cm －3 Above and 1×10 22 cm －3 The sheet resistance of the source electrode layer 147 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this embodiment).

[0561] The p-type impurity concentration of the source electrode layer 147 may be substantially equal to the p-type impurity concentration of the gate electrode layer 132 . The sheet resistance of the source electrode layer 147 may be substantially equal to the sheet resistance of the gate electrode layer 132 .

[0562] The source electrode layer 147 may include n-type polysilicon instead of p-type polysilicon. The source electrode layer 147 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of p-type polysilicon.

[0563] Thus, semiconductor device 101 has trench gate structure 151 and trench source structure 152. Trench gate structure 151 includes gate trench 121, gate insulating layer 131, gate electrode layer 132, and low-resistance electrode layer 134. Trench source structure 152 includes source trench 141, source insulating layer 146, and source electrode layer 147.

[0564] Reference Figure 13 as well as Figure 14 An interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 . The interlayer insulating layer 153 covers the trench gate structure 151 in the active region 106 and the gate wiring layer 133 in the outer region 107 .

[0565] The interlayer insulating layer 153 may also include silicon oxide or silicon nitride. A gate contact hole 154 and a source contact hole 155 are formed in the interlayer insulating layer 153 .

[0566] Gate contact hole 154 exposes gate wiring layer 133 (low-resistance electrode layer 134) in outer region 107. Source contact hole 155 exposes source region 126, contact region 144, and trench source structure 152 in active region 106. Gate pad 108, gate fingers 109, and source pad 110 are formed on interlayer insulating layer 153.

[0567] Gate finger 109 extends from above interlayer insulating layer 153 into gate contact hole 154. Gate finger 109 is electrically connected to low-resistance electrode layer 134 within gate contact hole 154. Thus, an electrical signal from gate pad 108 is transmitted to gate electrode layer 132 via low-resistance electrode layer 134 having a relatively low resistance value.

[0568] Source pad 110 extends from above interlayer insulating layer 153 into source contact hole 155. Source pad 110 is electrically connected to source region 126, contact region 144, and source electrode layer 147 within source contact hole 155. Source electrode layer 147 may also be formed using a portion of source pad 110.

[0569] Figure 16is a graph used to illustrate sheet resistance. Figure 16 In the table, the vertical axis represents the sheet resistance [Ω / □] and the horizontal axis represents the item. Figure 16 , a first histogram L1 , a second histogram L2 , and a third histogram L3 are shown.

[0570] The first bar graph L1 shows the sheet resistance of n-type polycrystalline silicon. The second bar graph L2 shows the sheet resistance of p-type polycrystalline silicon. The third bar graph L3 shows the sheet resistance when a low-resistance electrode layer 134 is formed on the p-type polycrystalline silicon. Here, the low-resistance electrode layer 134 comprises TiSi2 (p-type titanium silicide).

[0571] Referring to the first bar graph L1, the sheet resistance of n-type polycrystalline silicon is 10Ω / □. Referring to the second bar graph L2, the sheet resistance of p-type polycrystalline silicon is 200Ω / □. Referring to the third bar graph L3, the sheet resistance when a low-resistance electrode layer 134 is formed on the p-type polycrystalline silicon is 2Ω / □.

[0572] P-type polysilicon has a different work function from n-type polysilicon. Simply by burying p-type polysilicon in the gate trench 121 , the gate threshold voltage Vth can be increased by approximately 1 V.

[0573] However, p-type polysilicon has a sheet resistance several dozen times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for gate electrode layer 132, energy loss significantly increases as the parasitic resistance within gate trench 121 (hereinafter referred to as "gate resistance") increases.

[0574] In contrast, in a structure having a low-resistance electrode layer 134 on p-type polysilicon, the sheet resistance can be reduced by less than 1 / 100 compared to a structure without the low-resistance electrode layer 134. In a structure having the low-resistance electrode layer 134, the sheet resistance can be reduced by less than 1 / 5 compared to a structure having a gate electrode layer 132 composed of n-type polysilicon.

[0575] As described above, according to semiconductor device 101 , trench gate structure 151 is formed in which gate electrode layer 132 is embedded in gate trench 121 via gate insulating layer 131 . In trench gate structure 151 , gate electrode layer 132 is covered by low-resistance electrode layer 134 in a limited space called gate trench 121 .

[0576] The gate electrode layer 132 includes p-type polysilicon. This can increase the gate threshold voltage Vth. The low-resistance electrode layer 134 includes a conductive material having a sheet resistance lower than that of p-type polysilicon.

[0577] This reduces gate resistance and, as a result, allows current to be efficiently diffused along the trench gate structure 151 , shortening switching delay.

[0578] In particular, the structure in which the gate electrode layer 132 is covered by the low-resistance electrode layer 134 eliminates the need to increase the p-type impurity concentration in the body region 116. Therefore, an increase in channel resistance can be prevented while increasing the gate threshold voltage Vth.

[0579] Furthermore, according to the semiconductor device 101, the gate wiring layer 133 is covered with the low-resistance electrode layer 134 in the outer region 107. This also enables the gate resistance of the gate wiring layer 133 to be reduced.

[0580] In particular, in a structure where the gate electrode layer 132 and the gate wiring layer 133 are covered by the low-resistance electrode layer 134, current can be efficiently diffused along the trench gate structure 151. Therefore, switching delay can be appropriately shortened.

[0581] Figures 17A to 17L Yes Figure 11 A cross-sectional view of an example of a method for manufacturing the semiconductor device 101 is shown. Figures 17A to 17L is with Figure 12 Cross-sectional view of the corresponding part.

[0582] Reference Figure 17A First, an n+ type SiC semiconductor substrate 111 is prepared. Next, a SiC epitaxial layer 112 is formed on the main surface of the SiC semiconductor substrate 111. The SiC epitaxial layer 112 is formed by growing SiC on the main surface of the SiC semiconductor substrate 111 using an epitaxial growth method.

[0583] In this embodiment, the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed. Thus, the SiC semiconductor layer 102 including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 is formed.

[0584] Next, a p-type body region 116 is formed on the surface portion of the first main surface 103 of the SiC semiconductor layer 102 . The body region 116 is formed by introducing p-type impurities into the first main surface 103 of the SiC semiconductor layer 102 .

[0585] The body region 116 may be formed in the surface portion of the first main surface 103 of the SiC semiconductor layer 102 by ion implantation through an ion implantation mask (not shown). The active region 106 is defined by the body region 116 .

[0586] Next, refer to Figure 17BAn n+ type source region 126 is formed in the surface portion of the body region 116. The source region 126 is formed by introducing n-type impurities into the surface portion of the body region 116. The source region 126 can also be formed in the surface portion of the body region 116 by ion implantation through an ion implantation mask 161.

[0587] Next, refer to Figure 17C A p+ type contact region 144 is formed on the surface of the body region 116. The contact region 144 is formed by introducing p-type impurities into the surface of the body region 116. The contact region 144 can also be formed on the surface of the body region 116 by ion implantation through an ion implantation mask 162.

[0588] Next, refer to Figure 17D A mask 163 having a predetermined pattern is formed on the first main surface 103 of the SiC semiconductor layer 102. The mask 163 has a plurality of openings 164 that expose regions where the gate trenches 121 and the source trenches 141 are to be formed.

[0589] Next, unnecessary portions of the SiC semiconductor layer 102 are removed. The unnecessary portions of the SiC semiconductor layer 102 can also be removed by etching (for example, wet etching) through the mask 163. Thus, the gate trench 121 and the source trench 141 are formed. The mask 163 is then removed.

[0590] Next, the deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The deep well region 145 may also be formed in the SiC semiconductor layer 102 by ion implantation through an ion implantation mask (not shown).

[0591] Furthermore, in the outer region 107, a peripheral deep well region 148 is formed in a region along the surface portion of the first main surface 103 of the SiC semiconductor layer 102 and the inner wall of the contact trench portion 121b of the gate trench 121. In this step, the peripheral deep well region 148 including the lead portion 148a extending from the outer region 107 to the peripheral portion of the active region 106 is formed.

[0592] The peripheral deep well region 148 may also be formed in the SiC semiconductor layer 102 by ion implantation through an ion implantation mask (not shown). A portion or all of the peripheral deep well region 148 may also be formed simultaneously with the deep well region 145 by the process of forming the deep well region 145. A portion of the peripheral deep well region 148 may also be formed simultaneously with the body region 116 by the process of forming the body region 116.

[0593] Next, refer to Figure 17EThe SiC semiconductor layer 102 is subjected to an annealing process. The annealing process may be a high-temperature hydrogen annealing process. The annealing temperature may be 1400° C. or higher.

[0594] As a result, a bent portion 125 is formed at the opening edge portion 124 of the gate trench 121 . Furthermore, a bent portion 143 is formed at the opening edge portion 142 of the source trench 141 .

[0595] Next, refer to Figure 17F The base insulating layer 165, which serves as a base for the gate insulating layer 131 and the source insulating layer 146, is formed to cover the first main surface 103 of the SiC semiconductor layer 102. The base insulating layer 165 can also be formed by CVD (chemical vapor deposition) and can include silicon oxide.

[0596] In this step, in the base insulating layer 165 , the portion covering the side wall of the gate trench 121 and the portion covering the side wall of the source trench 141 are formed to be thinner than the other portions.

[0597] The base insulating layer 165 is formed using a CVD method by adjusting predetermined conditions such as gas flow rate, gas type, gas ratio, and gas supply time. Alternatively, the base insulating layer 165 may be formed using an oxidation method, such as thermal oxidation or wet oxidation, instead of CVD.

[0598] Next, refer to Figure 17G The base conductive layer 166 serving as a base for the gate electrode layer 132 , the gate wiring layer 133 , and the source electrode layer 147 is formed on the first main surface 103 of the SiC semiconductor layer 102 .

[0599] The base conductor layer 166 may include p-type polysilicon to which p-type impurities are added. The base conductor layer 166 may also be formed by CVD. The CVD method may be LP-CVD (Low Pressure-CVD).

[0600] Next, refer to Figure 17H , removing unnecessary portions of the base conductor layer 166. The unnecessary portions of the base conductor layer 166 are removed by etching (eg, wet etching) through a mask (not shown) having a predetermined pattern.

[0601] This mask (not shown) covers the region where the gate wiring layer 133 is to be formed. Unnecessary portions of the base conductive layer 166 are removed until at least the portion covering the first main surface 103 of the SiC semiconductor layer 102 is exposed in the base insulating layer 165. Thus, the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 are formed.

[0602] When the source electrode layer 147 is made of an electrode material different from that of the gate electrode layer 132, the electrode material of the source electrode layer 147 is separately subjected to the same Figures 17G to 17H Source electrode layer 147 may be formed by the same process as that of . In the case where source electrode layer 147 is formed using a portion of source pad 110 , source electrode layer 147 is formed when source pad 110 is formed.

[0603] Next, refer to Figure 17I A metal material layer 167 is formed on the gate electrode layer 132. In this embodiment, the metal material layer 167 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover both the gate electrode layer 132 and the source electrode layer 147.

[0604] The metal material layer 167 includes a metal material capable of polycrystallization between p-type polysilicon layers and may include at least one of Mo, W, Ni, Co, or Ti.

[0605] Next, a p-type polycrystalline layer is formed on the surface portion of the gate electrode layer 132 and the surface portion of the gate wiring layer 133. In this embodiment, a p-type polycrystalline layer is also formed on the surface portion of the source electrode layer 147.

[0606] The p-type polycrystalline layer is formed by polycrystallizing the surface portions of the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 by heat treating the metal material layer 167. The heat treatment of the metal material layer 167 may be performed by RTA (Rapid Thermal Annealing).

[0607] Thus, p-type polycrystalline containing at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, or WSi2 is formed according to the metal material of the metal material layer 167. The low-resistance electrode layer 134 is formed from this p-type polycrystalline layer.

[0608] Next, refer to Figure 17J , removing the unreacted portion of the metal material layer 167 that is not combined with the p-type polysilicon. The unreacted portion of the metal material layer 167 can also be removed by etching (eg, wet etching).

[0609] When the low-resistance electrode layer 134 (p-type polycrystalline) includes at least one of TiSi and CoSi, the low-resistance electrode layer 134 may be subjected to heat treatment as needed after removing the unreacted portion of the metal material layer 167 .

[0610] The heat treatment for the low-resistance electrode layer 134 may be an RTA method. In this way, TiSi is modified into TiSi2 and CoSi is modified into CoSi2, thereby achieving a lower resistance.

[0611] Next, refer to Figure 17K An interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the trench gate structure 151 and the gate wiring layer 133. The interlayer insulating layer 153 includes silicon oxide or silicon nitride. The interlayer insulating layer 153 can also be formed using a CVD method.

[0612] Next, a mask 168 having a predetermined pattern is formed over the interlayer insulating layer 153. The mask 168 has a plurality of openings 169 that expose regions where the gate contact holes 154 and the source contact holes 155 are to be formed.

[0613] Next, unnecessary portions of the interlayer insulating layer 153 are removed. The unnecessary portions of the interlayer insulating layer 153 can also be removed by etching (eg, dry etching) through the mask 168. Thus, the gate contact hole 154 and the source contact hole 155 are formed.

[0614] Next, refer to Figure 17L Gate pad 108, gate fingers 109, and source pad 110 are formed on interlayer insulating layer 153. Gate pad 108, gate fingers 109, and source pad 110 are formed using a mask (not shown) having a predetermined pattern. Furthermore, drain pad 113 is formed on second main surface 104 of SiC semiconductor layer 102. Semiconductor device 101 is manufactured through the above-mentioned steps.

[0615] Figure 18 is with Figure 13 The cross-sectional view of the corresponding region is a cross-sectional view showing a semiconductor device 171 according to an eighth embodiment of the present invention. Hereinafter, structures corresponding to those described in the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0616] Reference Figure 18In the semiconductor device 171, the gate insulating layer 131 includes a bulging portion 172 that bulges from the opening edge 124 of the gate trench 121 toward the inside of the gate trench 121. The bulging portion 172 is formed at a corner of the gate insulating layer 131 connecting the first region 131a and the third region 131c.

[0617] The bulging portion 172 extends in a curved shape toward the inside of the gate trench 121. The bulging portion 172 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0618] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulged portion 172 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this embodiment, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulged portion 172 of the gate insulating layer 131.

[0619] In the above Figure 17F In the process, the shape of the bulged portion 172 of the gate insulating layer 131 is also considered, and the bulged portion 172 of the gate insulating layer 131 is formed by setting predetermined conditions of the CVD method (gas flow rate, gas type, gas ratio, gas supply time, etc.).

[0620] As described above, according to semiconductor device 171 , edge 134c of low-resistance electrode layer 134 contacts bulged portion 172 of gate insulating layer 131 , thereby appropriately preventing a current path from forming in the region between low-resistance electrode layer 134 and SiC semiconductor layer 102 .

[0621] Furthermore, according to semiconductor device 171, opening edge portion 124 of gate trench 121 includes curved portion 125 and bulged portion 172. This further improves the dielectric strength of gate insulating layer 131 in opening edge portion 124 of gate trench 121.

[0622] Figure 19 is with Figure 13 The cross-sectional view of the corresponding region is a cross-sectional view showing a semiconductor device 181 according to a ninth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0623] Reference Figure 19 In the semiconductor device 181 , the opening edge portion 124 of the gate trench 121 has an inclined portion 182 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the sidewall of the gate trench 121 .

[0624] According to the inclined portion 182 of the gate trench 121 , the electric field can be dispersed along the inclined portion 182 , and thus the electric field concentration on the opening edge portion 124 of the gate trench 121 can be alleviated.

[0625] The gate insulating layer 131 includes a bulging portion 183 bulging from the inclined portion 182 of the gate trench 121 toward the inside of the gate trench 121. The bulging portion 183 is formed at a corner of the gate insulating layer 131 connecting the first region 131a and the third region 131c.

[0626] The bulging portion 183 extends in a curved shape toward the inside of the gate trench 121. The bulging portion 183 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0627] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulged portion 183 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this embodiment, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulged portion 183 of the gate insulating layer 131.

[0628] The opening edge portion 142 of the source trench 141 has an inclined portion 184 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the sidewall of the source trench 141. The inclined portion 184 of the source trench 141 disperses the electric field along the inclined portion 184, thereby concentrating the electric field relative to the opening edge portion 142 of the source trench 141.

[0629] Figures 20A to 20C Yes Figure 19 A cross-sectional view of an example of a method for manufacturing a semiconductor device 181 is shown.

[0630] First, refer to Figure 20A , ready to go through Figures 17A to 17D In the step of forming the SiC semiconductor layer 102 having the gate trench 121 and the source trench 141 on the first main surface 103 .

[0631] Next, refer to Figure 20B The first main surface 103 of the SiC semiconductor layer 102 is thermally oxidized to form a sacrificial oxide film 185. In this step, oxidation is uniformly initiated from both the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of the gate trench 121.

[0632] The oxide film extending from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film extending from the sidewall of the gate trench 121 are integrated at the opening edge portion 124 of the gate trench 121 .

[0633] The integration of these oxide films accelerates oxidation of the opening edge portion 124 of the gate trench 121. Furthermore, an inclined portion 182 is formed below the oxide film integrated with the opening edge portion 124 of the gate trench 121.

[0634] The oxide film extending from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film extending from the sidewall of the source trench 141 are integrated at the opening edge portion 142 of the source trench 141 .

[0635] The integration of these oxide films accelerates oxidation of the opening edge portion 142 of the source trench 141 . Furthermore, an inclined portion 184 is formed below the oxide film integrated with the opening edge portion 142 of the source trench 141 .

[0636] Next, refer to Figure 20C , remove the sacrificial oxide film 185. The sacrificial oxide film 185 can also be removed by etching (such as wet etching). Then, perform Figures 17F to 17L process.

[0637] exist Figure 17F In the above steps, the shape of the bulged portion 183 of the gate insulating layer 131 is also taken into consideration, and predetermined CVD conditions (gas flow rate, gas type, gas ratio, gas supply time, etc.) are set to form the bulged portion 183 of the gate insulating layer 131. Through the steps including the above steps, the semiconductor device 181 is manufactured.

[0638] As described above, according to semiconductor device 181 , edge 134 c of low-resistance electrode layer 134 contacts bulged portion 183 of gate insulating layer 131 , thereby appropriately preventing a current path from forming in the region between low-resistance electrode layer 134 and SiC semiconductor layer 102 .

[0639] Furthermore, according to semiconductor device 181, opening edge portion 124 of gate trench 121 has inclined portion 182 and bulged portion 183. This further improves the dielectric strength of gate insulating layer 131 in opening edge portion 124 of gate trench 121.

[0640] In this embodiment, an example of a mode in which the gate insulating layer 131 having the bulging portion 183 is formed in the semiconductor device 181 is described. However, the gate insulating layer 131 without the bulging portion 183 may be formed in the semiconductor device 181 .

[0641] Figure 21 is with Figure 12 The enlarged view of the corresponding region is an enlarged view showing the semiconductor device 191 according to the tenth embodiment of the present invention. Figure 22 It is along Figure 21 Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0642] Reference Figure 21 as well as Figure 22 In the semiconductor device 191 , an outer gate trench 192 is formed in the outer region 107 and on the first main surface 103 of the SiC semiconductor layer 102 . The outer gate trench 192 extends in a stripe shape in the outer region 107 .

[0643] The outer gate trench 192 is formed in a region directly below the gate finger 109 on the first main surface 103 of the SiC semiconductor layer 102 . The outer gate trench 192 extends along the gate finger 109 .

[0644] More specifically, outer gate trench 192 is formed along three side surfaces 105A, 105B, and 105D of SiC semiconductor layer 102 to divide active region 106 in three directions. Outer gate trench 192 may also be formed in a continuous shape (e.g., a quadrilateral ring shape) surrounding active region 106.

[0645] The outer gate trench 192 communicates with the contact trench portion 121b of each gate trench 121. Thus, the outer gate trench 192 and the gate trench 121 are formed by a single trench.

[0646] The gate wiring layer 133 is embedded in the outer gate trench 192. The gate wiring layer 133 is connected to the gate electrode layer 132 at the outer gate trench 192 and the communicating portion contacting the trench portion 121b.

[0647] In this embodiment, the low resistance electrode layer 134 covers the upper end of the gate wiring layer 133 in the outer gate trench 192. Therefore, the low resistance electrode layer 134 covering the gate electrode layer 132 and the low resistance electrode layer 134 covering the gate wiring layer 133 are both located in one trench.

[0648] In this embodiment, the peripheral deep well region 148 covers the inner wall of the outer gate trench 192 in the outer region 107. The peripheral deep well region 148 extends along the sidewall of the outer gate trench 192 and passes through the edge portion to the bottom wall of the outer gate trench 192.

[0649] That is, the peripheral deep well region 148 is located along the inner wall of the outer gate trench 192 and faces the gate wiring layer 133 via the gate insulating layer 131. Furthermore, the peripheral deep well region 148 is located along the inner wall of the gate trench 121 and faces the gate electrode layer 132 via the gate insulating layer 131.

[0650] As described above, the semiconductor device 191 can also achieve the same effects as those described for the semiconductor device 101 . In addition, the semiconductor device 191 does not require the gate wiring layer 133 to be extended onto the first main surface 103 of the SiC semiconductor layer 102 .

[0651] This prevents gate wiring layer 133 from facing SiC semiconductor layer 102 via gate insulating layer 131 at the opening edges of gate trench 121 and outer gate trench 192. Consequently, electric field concentration at the opening edge of gate trench 121 can be suppressed.

[0652] Figure 23 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 201 according to the 11th embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0653] Reference Figure 23 In the semiconductor device 201, each source trench 141 is formed deeper than the gate trench 121. Therefore, the bottom wall of each source trench 141 is located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom of the gate trench 121. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0654] The ratio of the depth of the source trench 141 to the depth of the gate trench 121 may be 1.5 or greater. The ratio of the depth of the source trench 141 to the depth of the gate trench 121 is preferably 2 or greater.

[0655] The depth of the gate trench 121 may be greater than or equal to 0.5 μm and less than or equal to 3 μm (eg, approximately 1 μm). The depth of the source trench 141 may be greater than or equal to 0.75 μm and less than or equal to 10 μm (eg, approximately 2 μm).

[0656] As in the case of semiconductor device 101, deep well region 145 extends along the inner wall of source trench 141 and has a bottom portion located on the second main surface 104 side of SiC semiconductor layer 102 relative to the bottom wall of gate trench 121. Deep well region 145 is formed in high concentration region 112a of SiC epitaxial layer 112.

[0657] As described above, according to the semiconductor device 201 , the same effects as those described for the semiconductor device 101 can be achieved.

[0658] Figure 24 is with Figure 12The plan view of the corresponding region is a plan view for explaining the structure of the semiconductor device 211 according to the twelfth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0659] Reference Figure 24 In this embodiment, the gate trenches 121 are formed in a lattice shape that integrally includes a plurality of gate trenches 121 extending in the first direction X and a plurality of gate trenches 121 extending in the second direction Y in a plan view.

[0660] On the first main surface 103 of the SiC semiconductor layer 102, a plurality of cell regions 212 are partitioned in rows and columns by gate trenches 121. Each cell region 212 is formed into a quadrilateral shape in a plan view. Source trenches 141 are formed in each of the plurality of cell regions 212. Source trenches 141 may also be formed into a quadrilateral shape in a plan view.

[0661] along Figure 24 The cross-sectional view of the XIII-XIII line and Figure 13 The cross-sectional views shown are substantially the same. Figure 24 The cross-sectional view of the XIV-XIV line and Figure 14 The cross-sectional views shown are generally the same.

[0662] As described above, the semiconductor device 211 can also achieve the same effects as those described for the semiconductor device 101. Other embodiments can also be applied, such as the gate trench 121 having a lattice-shaped structure instead of a stripe-shaped structure.

[0663] Figure 25 is with Figure 13 The cross-sectional views of the corresponding regions are plan views for explaining the structure of the semiconductor device 221 according to the 13th embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0664] Reference Figure 25 In the semiconductor device 221, the SiC semiconductor layer 102 includes a p+-type SiC semiconductor substrate 222 instead of the n+-type SiC semiconductor substrate 111. The p+-type SiC semiconductor substrate 222 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0665] In the description of the semiconductor device 101 , the description of the semiconductor device 221 is applied by replacing the “source” of the MISFET with the “emitter” of the IGBT and replacing the “drain” of the MISFET with the “collector” of the IGBT.

[0666] That is, the source pad 110 and the source region 126 are replaced by the emitter pad (110) and the emitter region (126), respectively. In addition, the drain pad 113 and the drain region 114 are replaced by the collector electrode layer (113) and the collector region (114), respectively.

[0667] As described above, according to the semiconductor device 221 , the same effects as those described for the semiconductor device 101 can be achieved.

[0668] Figure 26 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 231 according to the fourteenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0669] Reference Figure 26 The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141 . The contact region 144 is exposed from the bottom wall of the source trench 141 .

[0670] The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0671] More specifically, the source insulating layer 146 includes a first portion 232 and a second portion 233 . The first portion 232 covers the sidewalls of the source trench 141 , while the second portion 233 partially covers the bottom wall of the source trench 141 .

[0672] The second portion 233 is connected to the first portion 232. The second portion 233 extends from a corner of the source trench 141 along the bottom wall so as to expose the center portion of the bottom wall of the source trench 141. The second portion 233 may be formed in a continuous shape (ring shape) in a plan view.

[0673] As described above, the semiconductor device 231 can achieve the same effects as those described for the semiconductor device 101 . In addition, the semiconductor device 231 forms a pn junction in the boundary region between the SiC semiconductor layer 102 and the deep well region 145 .

[0674] Even if the depletion layer spreads from the corner of source trench 141 along the bottom wall at the pn junction, the source insulating layer 146 can ensure a sufficient distance for the depletion layer to reach source electrode layer 147. This prevents punch-through from occurring near the corner of source trench 141.

[0675] Figure 27 is with Figure 13The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 241 according to the fifteenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0676] Reference Figure 27 In the deep well region 145 , an exposed portion 242 is formed to selectively expose the bottom wall of the source trench 141 . The exposed portion 242 exposes the center portion of the bottom wall of the source trench 141 .

[0677] In this embodiment, the source insulating layer 146 includes a first portion 243 and a second portion 244 . The first portion 243 covers the sidewalls of the source trench 141 , and the second portion 244 partially covers the bottom wall of the source trench 141 .

[0678] The second portion 244 is connected to the first portion 243. The second portion 244 extends from a corner of the source trench 141 along the bottom wall so as to expose the center portion of the bottom wall of the source trench 141. The second portion 244 may be formed in a continuous shape (ring shape) in a plan view.

[0679] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 at the exposed portion 242 of the deep well region 145. This forms a heterojunction diode 245 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode. The source electrode layer 147 may include a conductive material other than polysilicon as long as it can form the heterojunction diode 245.

[0680] A body diode 246 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116 . The junction barrier of the heterojunction diode 245 is smaller than the diffusion potential of the body diode 246 .

[0681] The junction barrier of the heterojunction diode 245 may be 1.0 eV to 1.5 eV, and the diffusion potential of the body diode 246 may be 2.8 eV to 3.2 eV.

[0682] As described above, the semiconductor device 241 can achieve the same effects as those described for the semiconductor device 101. In the semiconductor device 241, when a reverse bias voltage is applied, current flows preferentially into the junction diode 245.

[0683] This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, the short-circuit withstand capability can be improved and the feedback capacitance Crss can be reduced, while suppressing an increase in on-resistance.

[0684] Figure 28is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 251 according to the sixteenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0685] Reference Figure 28 The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141 . The contact region 144 is exposed from the bottom wall of the source trench 141 .

[0686] Source insulating layer 146 has a stacked structure including a plurality of barrier-forming layers formed along the inner wall of source trench 141. In this embodiment, source insulating layer 146 has a stacked structure including an insulating barrier-forming layer 252 and a conductive barrier-forming layer 253 stacked in order from the inner wall of source trench 141.

[0687] The insulating barrier-forming layer 252 may include at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0688] The insulating barrier-forming layer 252 is formed in a film shape along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0689] More specifically, the insulating barrier-forming layer 252 includes a first portion 254 and a second portion 255 . The first portion 254 covers the sidewalls of the source trench 141 , while the second portion 255 selectively covers the bottom wall of the source trench 141 .

[0690] The second portion 255 is connected to the first portion 254. The second portion 255 extends from a corner portion of the source trench 141 along the bottom wall so that the center portion of the bottom wall of the source trench 141 is exposed.

[0691] The conductive barrier-forming layer 253 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier-forming layer 253 includes a conductive material different from the conductive material of the source electrode layer 147 .

[0692] The conductive barrier-forming layer 253 is formed in a film shape along the insulating barrier-forming layer 252 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0693] The source insulating layer 146 may include an insulating barrier-forming layer made of an insulating material different from that of the insulating barrier-forming layer 252, instead of the conductive barrier-forming layer 253. The source insulating layer 146 may include an insulating barrier-forming layer made of the same insulating material as that of the insulating barrier-forming layer 252, instead of the conductive barrier-forming layer 253.

[0694] As described above, according to the semiconductor device 251, the same effects as those described for the semiconductor device 101 can be achieved. Furthermore, in the semiconductor device 251, the source insulating layer 146 has a stacked structure including the insulating barrier-forming layer 252 and the conductive barrier-forming layer 253. Thus, the occurrence of punch-through can be suppressed by both the insulating barrier-forming layer 252 and the conductive barrier-forming layer 253.

[0695] Figure 29 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 261 according to the seventeenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and their descriptions are omitted.

[0696] Reference Figure 29 The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141 . The contact region 144 is exposed from the bottom wall of the source trench 141 .

[0697] The source insulating layer 146 includes a first portion 262 and a second portion 263 . The first portion 262 covers the sidewalls of the source trench 141 , and the second portion 263 covers the bottom wall of the source trench 141 .

[0698] The first portion 262 selectively includes a sidewall contact hole 264 that exposes the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 262 may be formed to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0699] The lower end of the first portion 262 (the end on the bottom wall side of the source trench 141) may be located on the bottom wall side of the source trench 141 relative to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0700] The lower end of the first portion 262 may be located on the first main surface 103 side relative to the bottom of the body region 116. The lower end of the first portion 262 may also be formed in the region between the bottom of the body region 116 and the bottom of the source region 126. In the above case, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0701] The lower end of first portion 262 may be formed in the region between first main surface 103 of SiC semiconductor layer 102 and the bottom of source region 126. Source insulating layer 146 may also have only second portion 263 without first portion 262. In this case, source electrode layer 147 is connected to body region 116 and contact region 144 within source trench 141.

[0702] The second portion 263 of the source insulating layer 146 is formed at a distance from the first portion 262 of the source insulating layer 146. That is, the second portion 263 is separated from the first portion 262. The second portion 263 may cover the corner of the source trench 141.

[0703] The second portion 263 may expose the corner of the source trench 141 . The second portion 263 may cover the corner of the source trench 141 and a portion of the sidewall of the source trench 141 .

[0704] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115 ) within the source trench 141 , thereby forming a Schottky barrier diode 265 with the source electrode layer 147 as an anode and the SiC semiconductor layer 102 as a cathode.

[0705] P-type deep well region 145 is formed in the SiC semiconductor layer 102 along the bottom wall of source trench 141. In this embodiment, deep well region 145 is formed in high concentration region 112a of SiC epitaxial layer 112. The entire deep well region 145 is formed in high concentration region 112a.

[0706] The deep well region 145 may be continuously formed in the SiC semiconductor layer 102 in a region along the sidewalls and corners of the source trench 141 so that the source electrode layer 147 is exposed from the sidewalls of the source trench 141 .

[0707] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the connecting sidewalls and the corner of the bottom wall of the source trench 141. The deep well region 145 may expose substantially the entire area of ​​the sidewall of the source trench 141 in the SiC semiconductor layer 102.

[0708] The deep well region 145 is extended from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the body region 116 in the normal direction to the first main surface 103 of the SiC semiconductor layer 102, across a portion of the SiC semiconductor layer 102 (drift region 115).

[0709] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115 ) in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 and at a depth between the body region 116 and the deep well region 145 .

[0710] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115 ) in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 and in a region sandwiched between the body region 116 and the deep well region 145 in the SiC semiconductor layer 102 .

[0711] The source electrode layer 147 may have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0712] The first electrode layer may also be a barrier electrode layer comprising a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may also have a stacked structure in which a Ti (titanium) film and a TiN (titanium nitride) film are stacked in this order from the SiC semiconductor layer 102 side. The first electrode layer may also have a single-layer structure consisting of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may also contain aluminum or tungsten.

[0713] As described above, the semiconductor device 261 can achieve the same effects as those described for the semiconductor device 101. In addition, in the semiconductor device 261, when a reverse bias voltage is applied, current can flow preferentially into the Schottky barrier diode 265.

[0714] This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, the short-circuit withstand capability can be improved, the feedback capacitance Crss can be reduced, and an increase in on-resistance can be suppressed.

[0715] In this embodiment, the source electrode layer 147 is located within the sidewall contact hole 264 of the source insulating layer 146 and forms a Schottky junction with the SiC semiconductor layer 102. However, an embodiment may be employed in which the source insulating layer 146 (the first portion 262 and the second portion 263) is not formed.

[0716] Figure 30 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 271 according to the eighteenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals and their descriptions are omitted.

[0717] Reference Figure 30 The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141. The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141.

[0718] More specifically, the source insulating layer 146 includes a first portion 272 and a second portion 273 . The first portion 272 covers the sidewalls of the source trench 141 , while the second portion 273 partially covers the bottom wall of the source trench 141 .

[0719] The second portion 273 is connected to the first portion 272. The second portion 273 extends from a corner of the source trench 141 along the bottom wall so as to expose the center portion of the bottom wall of the source trench 141. The second portion 273 may be formed in a continuous shape (ring shape) in a plan view.

[0720] As described above, the semiconductor device 271 can achieve the same effects as those described for the semiconductor device 201 . In addition, the semiconductor device 271 forms a pn junction in the boundary region between the SiC semiconductor layer 102 and the deep well region 145 .

[0721] Even if the depletion layer spreads from the corner of source trench 141 along the bottom wall from the pn junction, the source insulating layer 146 can ensure a sufficient distance for the depletion layer to reach source electrode layer 147. This prevents punch-through from occurring near the corner of source trench 141.

[0722] Figure 31 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 281 according to the nineteenth embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals and their descriptions are omitted.

[0723] Reference Figure 31 An exposed portion 282 that selectively exposes the bottom wall of the source trench 141 is formed in the deep well region 145 . The exposed portion 282 exposes the center portion of the bottom wall of the source trench 141 .

[0724] In this embodiment, the source insulating layer 146 includes a first portion 283 and a second portion 284 . The first portion 283 covers the sidewalls of the source trench 141 , and the second portion 284 partially covers the bottom wall of the source trench 141 .

[0725] The second portion 284 is connected to the first portion 283. The second portion 284 extends from a corner of the source trench 141 along the bottom wall so as to expose the center portion of the bottom wall of the source trench 141. The second portion 284 may be formed in a continuous shape (ring shape) in a plan view.

[0726] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 at the exposed portion 282 of the deep well region 145. This forms a heterojunction diode 285 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode. The source electrode layer 147 may include a conductive material other than polysilicon as long as it can form the heterojunction diode 285.

[0727] A body diode 286 is formed at a pn junction between the SiC semiconductor layer 102 and the body region 116 . The junction barrier of the heterojunction diode 285 is smaller than the diffusion potential of the body diode 286 .

[0728] The junction barrier of the heterojunction diode 285 may be 1.0 eV to 1.5 eV, and the diffusion potential of the body diode 286 may be 2.8 eV to 3.2 eV.

[0729] As described above, the semiconductor device 281 can achieve the same effects as those described for the semiconductor device 201. In addition, in the semiconductor device 281, when a reverse bias voltage is applied, current can flow preferentially into the heterojunction diode 285.

[0730] This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, the short-circuit withstand capability can be improved and the feedback capacitance Crss can be reduced, while suppressing an increase in on-resistance.

[0731] Figure 32 is with Figure 13 The cross-sectional views of the corresponding regions are used to describe the structure of the semiconductor device 291 according to the 20th embodiment of the present invention.

[0732] Reference Figure 32 The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141 . The contact region 144 is exposed from the bottom wall of the source trench 141 .

[0733] Source insulating layer 146 has a stacked structure including a plurality of barrier-forming layers formed along the inner wall of source trench 141. In this embodiment, source insulating layer 146 has a stacked structure including an insulating barrier-forming layer 292 and a conductive barrier-forming layer 293 stacked in order from the inner wall of source trench 141.

[0734] The insulating barrier-forming layer 292 may include at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0735] The insulating barrier-forming layer 292 is formed in a film shape along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0736] More specifically, the insulating barrier-forming layer 292 includes a first portion 294 and a second portion 295 . The first portion 294 covers the sidewalls of the source trench 141 , while the second portion 295 selectively covers the bottom wall of the source trench 141 .

[0737] The second portion 295 is connected to the first portion 294. The second portion 295 extends from a corner portion of the source trench 141 along the bottom wall so that the center portion of the bottom wall of the source trench 141 is exposed.

[0738] The conductive barrier-forming layer 293 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier-forming layer 293 includes a conductive material different from the conductive material of the source electrode layer 147 .

[0739] The conductive barrier-forming layer 293 is formed in a film shape along the insulating barrier-forming layer 292 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0740] As described above, semiconductor device 291 can achieve the same effects as those described for semiconductor device 201. Furthermore, in semiconductor device 291, source insulating layer 146 has a stacked structure including insulating barrier-forming layer 292 and conductive barrier-forming layer 293. Thus, the occurrence of punch-through can be suppressed by both insulating barrier-forming layer 292 and conductive barrier-forming layer 293.

[0741] Figure 33 is with Figure 13 The cross-sectional views of the corresponding regions are cross-sectional views for explaining the structure of the semiconductor device 301 according to the 21st embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals and their descriptions are omitted.

[0742] Reference Figure 33The contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141 . The contact region 144 is exposed from the bottom wall of the source trench 141 .

[0743] The source insulating layer 146 includes a first portion 302 and a second portion 303 . The first portion 302 covers the sidewalls of the source trench 141 , and the second portion 303 covers the bottom wall of the source trench 141 .

[0744] The first portion 302 selectively includes a sidewall contact hole 304 that exposes the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 302 may be formed to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0745] The lower end of the first portion 302 (end on the source trench 141 side) may be located closer to the bottom wall of the source trench 141 than the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0746] The lower end of the first portion 302 may be located on the first main surface 103 side relative to the bottom of the body region 116. The lower end of the first portion 302 may also be formed in the region between the bottom of the body region 116 and the bottom of the source region 126. In the above case, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0747] The lower end of first portion 302 may be formed in the region between first main surface 103 of SiC semiconductor layer 102 and the bottom of source region 126. Source insulating layer 146 may also have only second portion 303 without first portion 302. In this case, source electrode layer 147 is connected to body region 116 and contact region 144 within source trench 141.

[0748] The second portion 303 of the source insulating layer 146 is formed at a distance from the first portion 302 of the source insulating layer 146. That is, the second portion 303 is separated from the first portion 302. The second portion 303 may cover the corner of the source trench 141.

[0749] The second portion 303 may expose the corner of the source trench 141 . The second portion 303 may cover the corner of the source trench 141 and may cover a portion of the sidewall of the source trench 141 .

[0750] Source electrode layer 147 forms a Schottky junction with SiC semiconductor layer 102 (drift region 115 ) within source trench 141 , thereby forming a Schottky barrier diode 305 with source electrode layer 147 as an anode and SiC semiconductor layer 102 as a cathode.

[0751] P-type deep well region 145 is formed in the SiC semiconductor layer 102 along the bottom wall of source trench 141. In this embodiment, deep well region 145 is formed in high concentration region 112a of SiC epitaxial layer 112. The entire deep well region 145 is formed in high concentration region 112a.

[0752] The deep well region 145 may be continuously formed in the SiC semiconductor layer 102 in a region along the sidewalls and corners of the source trench 141 so that the source electrode layer 147 is exposed from the sidewalls of the source trench 141 .

[0753] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the connecting sidewalls and the corner of the bottom wall of the source trench 141. The deep well region 145 may expose substantially the entire area of ​​the sidewall of the source trench 141 in the SiC semiconductor layer 102.

[0754] The deep well region 145 is extended from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the body region 116 across a portion of the SiC semiconductor layer 102 (drift region 115) in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0755] The deep well region 145 is extended from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the body region 116 across a portion of the SiC semiconductor layer 102 (drift region 115) in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0756] More specifically, the source electrode layer 147 is located at a depth between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 , and forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115 ).

[0757] More specifically, the source electrode layer 147 is located in a region of the SiC semiconductor layer 102 sandwiched between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 , and forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115 ).

[0758] The source electrode layer 147 may have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer stacked in this order from the SiC semiconductor layer 102 side.

[0759] The first electrode layer may also be a barrier electrode layer comprising a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may also have a stacked structure in which a Ti (titanium) film and a TiN (titanium nitride) film are stacked in this order from the SiC semiconductor layer 102 side. The first electrode layer may also have a single-layer structure consisting of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may also contain aluminum or tungsten.

[0760] As described above, the semiconductor device 301 can achieve the same effects as those described for the semiconductor device 201. In addition, in the semiconductor device 301, when a reverse bias voltage is applied, current can flow preferentially into the Schottky barrier diode 305.

[0761] This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, the short-circuit withstand capability can be improved, the feedback capacitance Crss can be reduced, and an increase in on-resistance can be suppressed.

[0762] In this embodiment, an example is described in which the source electrode layer 147 is within the sidewall contact hole 264 of the source insulating layer 146 and forms a Schottky junction with the SiC semiconductor layer 102. However, an embodiment may also be employed in which the source insulating layer 146 (the first portion 302 and the second portion 303) is not formed.

[0763] Although the seventh to twenty-first embodiments of the present invention have been described, the seventh to twenty-first embodiments of the present invention can also be implemented in other forms.

[0764] In the seventh to twenty-first embodiments described above, an example of forming the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b by epitaxial growth has been described. However, the SiC epitaxial layer 112 may also be formed by the following steps.

[0765] First, a SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface of the SiC epitaxial layer 112 by ion implantation. This forms the SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0766] In the seventh to twenty-first embodiments described above, the SiC semiconductor layer 102 has been described as having a stacked structure including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112. However, the SiC semiconductor layer 102 may also have a single-layer structure consisting of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may also have a single-layer structure consisting of the SiC epitaxial layer 112.

[0767] In the seventh to twenty-first embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, a p-type portion may be n-type, and an n-type portion may be p-type.

[0768] In the seventh to twenty-first embodiments described above, examples are described in which the gate electrode layer 132 and gate wiring layer 133 are formed of p-type polysilicon doped with p-type impurities. However, if increasing the gate threshold voltage Vth is not important, the gate electrode layer 132 and gate wiring layer 133 may be formed of n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0769] The low-resistance electrode layer 134 can also be formed by silicideing the surface portion of the gate electrode layer 132 (n-type polysilicon) using a metal material. In other words, the low-resistance electrode layer 134 can also be composed of n-type polycrystalline. With this structure, gate resistance can be reduced.

[0770] The structure of the semiconductor device 221 can also be used in the seventh to twenty-first embodiments described above. That is, in the seventh to twenty-first embodiments described above, a p+-type SiC semiconductor substrate 222 can be used instead of the n+-type SiC semiconductor substrate 111. In this case, in the description of the seventh to thirteenth embodiments described above, "source" is replaced by "emitter," and "drain" is replaced by "collector."

[0771] Figure 34 It is a top view showing a semiconductor device 311 according to a twenty-second embodiment of the present invention. Figure 35 yes Figure 34 FIG. 3 is a bottom view of the semiconductor device 311. Hereinafter, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and described.

[0772] Reference Figure 34 The semiconductor device 311 includes a SiC semiconductor layer 102 made of SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also include 4H-SiC single crystal.

[0773] 4H-SiC single crystal has an off-angle of less than 10° from the

[0001] plane to the [11-20] direction. The off-angle can be between 0° and 4°. It can also be greater than 0° and less than 4°. Typically, the off-angle is set within the range of 2° or 4°, more specifically, within the range of 2° ± 0.2° or 4° ± 0.4°.

[0774] In this embodiment, SiC semiconductor layer 102 is formed into a rectangular parallelepiped sheet. SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting first main surface 103 and second main surface 104. First main surface 103 and second main surface 104 are formed into a quadrilateral shape (a rectangular shape in this embodiment) when viewed from above (hereinafter referred to as "top view") as viewed from the normal direction described above.

[0775] Side surface 105A faces side surface 105C. Side surface 105B faces side surface 105D. Four side surfaces 105A to 105D extend in a planar manner along the normal direction of first principal surface 103 and second principal surface 104, respectively. The lengths of side surfaces 105A to 105D may each be greater than 1 mm and less than 10 mm (e.g., greater than 2 mm and less than 5 mm).

[0776] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107 . The active region 106 is a region where vertical MISFETs are formed. The outer region 107 is a region outside the active region 106 .

[0777] Active region 106 is provided in the center of SiC semiconductor layer 102, spaced inward from side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view. Active region 106 is provided in a quadrilateral shape (a rectangular shape in this embodiment) having four sides parallel to side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view.

[0778] The outer region 107 is defined between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is defined in a continuous shape (a square ring shape) surrounding the active region 106 in a plan view.

[0779] A gate pad 108, gate fingers 109, and a source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102. The gate pad 108, gate fingers 109, and source pad 110 may also include aluminum and / or copper.

[0780] Gate pad 108 is formed along side surface 105A of SiC semiconductor layer 102 in a plan view. Gate pad 108 is formed along the central region of side surface 105A of SiC semiconductor layer 102 in a plan view. Gate pad 108 may also be formed along a corner connecting any two of the four side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view.

[0781] The gate pad 108 is formed in a quadrilateral shape in a plan view and is drawn from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view.

[0782] The gate fingers 109 include outer gate fingers 109A and inner gate fingers 109B. The outer gate fingers 109A extend from the gate pad 108 toward the outer region 107. The outer gate fingers 109A extend in a ribbon shape in the outer region 107.

[0783] In this embodiment, the outer gate fingers 109A may be formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to divide the active region 106 in three directions.

[0784] The inner gate finger 109B is extended from the gate pad 108 toward the active region 106. The inner gate finger 109B extends in a stripe shape in the active region 106. The inner gate finger 109B extends from the side surface 105A toward the side surface 105C.

[0785] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate finger 109. The source pad 110 covers the C-shaped region (in the region 106) defined by the gate pad 108 and the gate finger 109. Figure 34 In the manner of forming an inverted C-shape in the region, the region is formed into a C-shape in a plan view (in Figure 34 Inverted C shape in the middle).

[0786] A gate voltage is applied to gate pad 108 and gate finger 109. The gate voltage may be 10 V or higher and 50 V or lower (eg, approximately 30 V). A source voltage is applied to source pad 110. The source voltage may be a reference voltage (eg, GND voltage).

[0787] A resin layer 312 is formed on the first main surface 103 of the SiC semiconductor layer 102 (more specifically, on the interlayer insulating layer 153). Figure 34 , for clarity, the resin layer 312 is shown by hatching. The resin layer 312 covers the gate pad 108, the gate fingers 109, and the source pad 110.

[0788] The resin layer 312 may include a negative or positive photosensitive resin. In this embodiment, the resin layer 312 includes polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 312 may also include polyimide, which is an example of a negative photosensitive resin.

[0789] The peripheral edge of the resin layer 312 is formed at intervals inward from the side surfaces 105A to 105D of the SiC semiconductor layer 102. Thus, the peripheral edge of the resin layer 312 exposes the first principal surface 103 of the SiC semiconductor layer 102. More specifically, the peripheral edge of the resin layer 312 exposes the interlayer insulating layer 153.

[0790] A gate pad opening 313 and a source pad opening 314 are formed in the resin layer 312. The gate pad opening 313 exposes the gate pad 108. The source pad opening 314 exposes the source pad 110.

[0791] Reference Figure 35 as well as Figure 35 , a raised portion group 316 including a plurality of raised portions 315 is formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of raised portions 315 are portions raised on the second main surface 104 of the SiC semiconductor layer 102 along the normal direction of the second main surface 104 of the SiC semiconductor layer 102.

[0792] The plurality of raised portions 315 are formed at intervals from one another along an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one direction of the first main surface 103 of the SiC semiconductor layer 102 .

[0793] In this embodiment, the first direction X is set to be parallel to the side surfaces 105B and 105D of the SiC semiconductor layer 102. More specifically, the second direction Y is a direction perpendicular to the first direction X. That is, in this embodiment, the second direction Y is set to be parallel to the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0794] The raised portion group 316 includes a first portion 317 in which some of the raised portions 315 among the plurality of raised portions 315 overlap in the first direction X when viewed from the first direction X.

[0795] Furthermore, the raised portion group 316 includes second portions 318 that are formed away from the first portion 317 from some of the raised portions 315 among the plurality of raised portions 315 and that overlap in the first direction X when viewed in the first direction.

[0796] The plurality of raised portions 315 are continuously formed along the first direction X. More specifically, the plurality of raised portions 315 have a distribution pattern in which the raised portions 315 are distributed along the first direction X and the second direction Y at intervals.

[0797] The plurality of raised portions 315 maintains this distribution pattern and is continuously formed in the first direction X. In this embodiment, the plurality of raised portions 315 are formed from the periphery of one side surface 105A to the periphery of the other side surface 105C of the SiC semiconductor layer 102 in a plan view.

[0798] In the ridge group 316 , the distances between the ridges 315 formed at intervals in the first direction X may be different from each other. The distances between the ridges 315 formed at intervals in the second direction Y may be different from each other.

[0799] The plurality of raised portions 315 are formed in non-uniform shapes, sizes, and thicknesses. The thickness of a raised portion 315 is the distance from the base to the top (front end) of the raised portion 315 in the normal direction of the second main surface 104 of the SiC semiconductor layer 102 .

[0800] Each of the plurality of raised portions 315 may have a size greater than 0 μm and less than 10 μm. Each raised portion 315 may have a thickness less than 500 nm (eg, greater than 1 nm and less than 250 nm).

[0801] The ridge group 316 is formed on the second main surface 104 of the SiC semiconductor layer 102 in a range narrower than the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer 102 .

[0802] The ridge group 316 is formed, for example, in a range of not less than 1 / 1000 and not more than 1 / 5 of the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer 102 .

[0803] The ridge group 316 may be formed in a range of not less than 1 / 200 and not more than 1 / 10 of the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer 102 .

[0804] The raised portion group 316 may be formed in a range of 10 μm to 200 μm in the second direction Y. The raised portion group 316 may be formed in a range of 50 μm to 150 μm in the second direction Y. The raised portion group 316 may be formed in a range of 80 μm to 120 μm in the second direction Y.

[0805] The raised portion group 316 has a layout in which the plurality of raised portions 315 overlap in the first direction X when viewed from the first direction X. Thus, the raised portion group 316 forms a raised portion group region 319 extending in a band shape along the first direction X by the collective pattern of the plurality of raised portions 315 continuously distributed along the first direction X.

[0806] In other words, the raised portion group region 319 includes a plurality of raised portions 315 (raised portion group 316 ) formed in a band-shaped region extending in the first direction X on the second main surface 104 of the SiC semiconductor layer 102 .

[0807] A plurality of raised portion groups 316 (raised portion group regions 319 ) having such a morphology are formed at intervals along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102 .

[0808] That is, the distribution pattern of the plurality of protrusions 315 is formed intermittently when viewed from the second direction Y. The distance between the plurality of protrusion groups 316 may be greater than or equal to 1% and less than or equal to 25% of the range in which the protrusion groups 316 are formed.

[0809] The distance between adjacent protrusion groups 316 in the second direction Y may be 100 μm or less. The distance between protrusion groups 316 may be 5 μm or more and 50 μm or less. The distance between protrusion groups 316 may be 20 μm or less.

[0810] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. In other words, the raised portion group 316 may be formed as a band-shaped raised portion group region 319 extending approximately parallel to or parallel to the [11-20] direction, with a plurality of raised portion groups formed at intervals along the [1-100] direction.

[0811] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. In other words, the raised portion group 316 may be formed as a band-shaped raised portion group region 319 extending approximately parallel to or parallel to the [1-100] direction, with a plurality of raised portion group regions spaced apart along the [11-20] direction.

[0812] In the region between the groups of protrusions 316 adjacent to each other in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102 , a space 320 having no distribution pattern of the plurality of protrusions 315 is defined.

[0813] The spaces 320 are divided into stripes extending parallel to the first direction X by the adjacent ridge groups 316 (ridge group regions 319 ). Thus, a stripe pattern in which the ridge groups 316 and the spaces 320 are alternately formed along the second direction Y is formed on the second main surface 104 of the SiC semiconductor layer 102 .

[0814] A plurality of grooves 321 are formed on the second main surface 104 of the SiC semiconductor layer 102. Figure 35 as well as Figure 35 In the enlarged view of FIG, the groove 321 is shown by a line. The groove 321 is formed in the protrusion group 316 and the space 320.

[0815] The grooves 321 include polishing marks generated by polishing the second wafer main surface 333 of the SiC semiconductor wafer 331 , which will be described later. Therefore, the extending direction of the grooves 321 varies depending on the position where the SiC semiconductor layer 102 is cut out of the SiC semiconductor wafer 331 .

[0816] The groove 321 may extend substantially parallel to or parallel to each of the protrusion groups 316. The groove 321 may include a portion intersecting the protrusion groups 316. The groove 321 may extend in a direction intersecting or perpendicular to each of the protrusion groups 316. The groove 321 may extend in a straight line or in an arc shape.

[0817] Some of the plurality of raised portions 315 included in each raised portion group 316 are formed at intervals along the groove 321. That is, each raised portion group 316 includes a third portion 322 in which some of the plurality of raised portions 315 are formed at intervals along the groove 321 in a plan view.

[0818] Each of the raised portion groups 316 is formed by, for example, annealing. The plurality of raised portions 315 may be laser processing marks formed by laser annealing.

[0819] The plurality of raised portions 315 along the groove 321 (the third portion 322 of the raised portion group 316 ) can also be formed by annealing the unevenness divided by the groove 321 on the second main surface 104 of the SiC semiconductor layer 102 (the second wafer main surface 333 of the SiC semiconductor wafer 331 ).

[0820] like Figures 36A to 36D As shown, each ridge group 316 can adopt various forms by adjusting the annealing conditions (here, laser annealing conditions).

[0821] Figure 36A 1 and 2 are diagrams showing a second embodiment of each protrusion group 316 .

[0822] like Figure 36AAs shown, the protrusion group 316 may also include a protrusion group extending in the first direction X in a top view and extending in the second direction Y (in the Figure 36A The convex curved protrusion 315 protrudes from the side surface 105B. The protrusion 315 may be formed by a plurality of protrusions 315 overlapping each other.

[0823] The distance between the two most distant points in the raised portion 315 may be 1 μm or greater and 200 μm or less (approximately 50 μm in this embodiment). The distance between adjacent raised portions 315 in the first direction X is set to a value that is at least 10% of the size of the raised portion 315. The raised portions 315 are formed by staggering adjacent laser irradiation positions in the first direction X.

[0824] Figure 36B This is a diagram showing a third embodiment of the protrusion group 316 .

[0825] like Figure 36B As shown, the protrusion group 316 may include a concavely curved protrusion 315 extending in the second direction Y in a plan view and recessed in the first direction X. The protrusion 315 may be formed of a plurality of protrusions 315 overlapping each other.

[0826] The distance between the two most distant points in each raised portion 315 may be 1 μm to 200 μm (about 50 μm in this embodiment). The plurality of raised portions 315 are formed by overlapping adjacent laser irradiation positions by 50% to 70%.

[0827] Figure 36C This is a diagram showing a fourth embodiment of the protrusion group 316 .

[0828] like Figure 36C As shown, the raised portion group 316 may include linear raised portions 315 extending in the second direction Y and recessed in the first direction X when viewed from above. The raised portions 315 may also include protrusions protruding in the first direction X. The raised portion 315 may also be formed by a plurality of raised portions 315 overlapping each other.

[0829] The distance between the two most distant points in protrusion 315 may be 1 μm to 200 μm (about 50 μm in this embodiment). Multiple protrusions 315 are formed by overlapping adjacent laser irradiation positions by 70% to 90%.

[0830] Figure 36D This is a diagram showing a fifth embodiment of the protrusion group 316 .

[0831] like Figure 36DAs shown, the raised portion group 316 may have a layout in which raised portion rows including a plurality of raised portions 315 arranged at intervals in the second direction Y are formed at intervals in the first direction X.

[0832] The distance between the two most distant points in protrusion 315 may be 1 μm to 200 μm (about 5 μm in this embodiment). Multiple protrusions 315 are formed by overlapping adjacent laser irradiation positions by 90% to 100%.

[0833] Figure 37 yes Figure 34 The enlarged view of the region XXXVII shown is a view in which the structure above the first main surface 103 of the SiC semiconductor layer 102 is removed. Figure 38 It is along Figure 37 A cross-sectional view taken along line XXXVIII-XXXVIII. Figure 39 It is along Figure 37 Cross-sectional view of line XXXIX-XXXIX. Figure 40 yes Figure 39 Magnified view of area XL is shown.

[0834] Reference Figures 37 to 39 The semiconductor device 311 has the same planar structure and cross-sectional structure as the semiconductor device 101 , except that a protrusion group 316 is formed on the second main surface 104 of the SiC semiconductor layer 102 .

[0835] Reference Figure 40 , a group of raised portions 316 (plural raised portions 315) and a groove 321 are formed in the SiC semiconductor substrate 111. A modified layer 323 is formed on the surface of the second main surface 104 of the SiC semiconductor layer 102. The modified layer 323 is formed by partially modifying the SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 111) to have other properties. This modified layer 323 is formed by annealing the second main surface 104 of the SiC semiconductor layer 102.

[0836] The modified layer 323 contains Si atoms and C atoms. More specifically, the modified layer 323 has a carbon density in the SiC semiconductor layer 102 (SiC semiconductor substrate 111 ) that is lower than the carbon density of a region outside the modified layer 323 .

[0837] Furthermore, the modified layer 323 has a higher silicon density than a carbon density. That is, the modified layer 323 includes a Si modified layer in which SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified into Si. The Si modified layer may also be a Si amorphous layer.

[0838] The modified layer 323 may include lattice defects caused by modification of SiC. In other words, the modified layer 323 may include lattice defect regions having defect levels introduced by modification of SiC.

[0839] In this embodiment, the modified layer 323 is formed in the surface portion of the second main surface 104 of the SiC semiconductor layer 102 in a region along the ridge group 316 .

[0840] In this embodiment, the modified layer 323 further extends from the protrusion group 316 toward the space 320 . That is, the annealing treatment performed on the second main surface 104 of the SiC semiconductor layer 102 extends to the space 320 .

[0841] The thickness of the portion of modified layer 323 along protrusion group 316 is greater than the thickness of the portion of modified layer 323 along space 320 due to the presence of protrusion 315. More specifically, the thickness of the portion of modified layer 323 along protrusion group 316 is greater than the thickness of the portion of modified layer 323 along space 320.

[0842] The thickness of the modified layer 323 may also be greater than 1 nm and less than 1000 nm. The thickness Ta of the region of the modified layer 323 where the raised portion 315 is formed may also be greater than 50 nm and less than 1000 nm. The thickness Tb of the region of the modified layer 323 outside the raised portion 315 may also be greater than 1 nm and less than 300 nm.

[0843] The thickness Ta may be greater than or equal to 50 nm and less than or equal to 100 nm. The thickness Ta may be greater than or equal to 100 nm and less than or equal to 150 nm. The thickness Ta may be greater than or equal to 150 nm and less than or equal to 200 nm. The thickness Ta may be greater than or equal to 200 nm and less than or equal to 250 nm.

[0844] The thickness Ta may be greater than or equal to 250 nm and less than or equal to 300 nm. The thickness Ta may be greater than or equal to 300 nm and less than or equal to 350 nm. The thickness Ta may be greater than or equal to 350 nm and less than or equal to 400 nm. The thickness Ta may be greater than or equal to 400 nm and less than or equal to 450 nm. The thickness Ta may be greater than or equal to 450 nm and less than or equal to 500 nm.

[0845] The thickness Ta may be greater than or equal to 500 nm and less than or equal to 600 nm. The thickness Ta may be greater than or equal to 600 nm and less than or equal to 700 nm. The thickness Ta may be greater than or equal to 700 nm and less than or equal to 800 nm. The thickness Ta may be greater than or equal to 800 nm and less than or equal to 900 nm. The thickness Ta may be greater than or equal to 900 nm and less than or equal to 1000 nm.

[0846] The thickness Tb may be greater than or equal to 1 nm and less than or equal to 10 nm. The thickness Tb may be greater than or equal to 10 nm and less than or equal to 50 nm. The thickness Tb may be greater than or equal to 50 nm and less than or equal to 100 nm.

[0847] The thickness Tb may be greater than or equal to 100 nm and less than or equal to 150 nm. The thickness Tb may be greater than or equal to 150 nm and less than or equal to 200 nm. The thickness Tb may be greater than or equal to 200 nm and less than or equal to 250 nm. The thickness Tb may be greater than or equal to 250 nm and less than or equal to 300 nm.

[0848] The thickness Tb may also be less than 1 / 2, less than 1 / 3, less than 1 / 4, less than 1 / 5, less than 1 / 6, less than 1 / 7, less than 1 / 8, less than 1 / 9, less than 1 / 10, less than 1 / 11, less than 1 / 12, less than 1 / 13, less than 1 / 14, less than 1 / 15, less than 1 / 16, less than 1 / 17, less than 1 / 18, less than 1 / 19 or less than 1 / 20 of the thickness Ta.

[0849] The resistance value of the second main surface 104 of the SiC semiconductor layer 102 when no protrusion group 316 is present is greater than the resistance value of the second main surface 104 when the protrusion group 316 is present.

[0850] That is, as an electrical characteristic, the plurality of bump groups 316 have a resistance value that is lower than the resistance value of a SiC single crystal alone. More specifically, the plurality of bump groups 316 have a resistance value that is lower than the resistance value of a SiC single crystal alone.

[0851] Furthermore, the plurality of protrusion groups 316 have a resistance value that is lower than the resistance value of the space 320 . More specifically, the plurality of protrusion groups 316 have a resistance value that is lower than the resistance value of the space 320 .

[0852] The resistance of protrusion group 316 is reduced by modified layer 323. Specifically, the resistance of protrusion group 316 is reduced to a value lower than that of SiC single crystal by modified layer 323, which modifies the properties of SiC. Furthermore, the resistance of space 320 is also reduced by modified layer 323.

[0853] In this embodiment, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the bump group 316 on the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers a plurality of bump groups 316 at a time.

[0854] Drain pad 113 is formed into a film-like shape, conforming to the outer surface of bump group 316 (the outer surfaces of multiple bumps 315) and the inner surface of groove 321. Consequently, a portion of drain pad 113's outer surface that covers bump group 316 (multiple bumps 315) is formed with a bump 113a that rises away from second main surface 104. Furthermore, a portion of drain pad 113's outer surface that covers groove 321 is formed with a recessed portion 113b that is recessed toward second main surface 104.

[0855] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 . More specifically, the drain pad 113 forms an ohmic contact with the ridge group 316 .

[0856] More specifically, drain pad 113 forms ohmic contact with a plurality of bump groups 316. In this embodiment, drain pad 113 also forms ohmic contact with space 320.

[0857] Drain pad 113 has a stacked structure including a plurality of electrode layers stacked on second principal surface 104 of SiC semiconductor layer 102. In this embodiment, drain pad 113 has a four-layer structure including a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 stacked in this order from second principal surface 104 of SiC semiconductor layer 102.

[0858] Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 are formed into films, respectively, to mimic the outer surfaces of bump group 316 (the outer surfaces of bumps 315) and the inner surfaces of groove 321. Bump 113a and recess 113b of drain pad 113 are formed on the outer surface of Ag layer 327.

[0859] Ti layer 324 is directly connected to second main surface 104 of SiC semiconductor layer 102. Ti layer 324 also covers the plurality of protrusion groups 316 and forms ohmic contact with second main surface 104 of SiC semiconductor layer 102. In this embodiment, Ti layer 324 also forms ohmic contact with space 320.

[0860] The Ni layer 325 covers substantially the entire region or the entire region of the Ti layer 324. The Au layer 326 covers substantially the entire region or the entire region of the Ni layer 325. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0861] The thickness of the Ti layer 324 may be 0.01 μm to 5 μm (eg, approximately 0.07 μm). The thickness of the Ni layer 325 may be 0.1 μm to 40 μm (eg, approximately 1.2 μm).

[0862] The thickness of Au layer 326 can be between 0.1 μm and 40 μm (e.g., approximately 0.07 μm). The thickness of Ag layer 327 can also be between 0.1 μm and 40 μm (e.g., approximately 0.3 μm). Of course, drain pad 113 can also have a single-layer structure consisting of Ti layer 324, Ni layer 325, Au layer 326, or Ag layer 327.

[0863] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without intervening the silicide layer mainly containing silicide. The drain pad 113 forms ohmic contact with each of the ridge groups 316 without intervening the silicide layer mainly containing silicide.

[0864] The drain pad 113 forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without passing through the carbon layer mainly containing carbon. The drain pad 113 forms ohmic contact with each ridge group 316 without passing through the carbon layer mainly containing carbon.

[0865] The drain pad 113 does not include a region where a material mainly containing silicide is formed in a layered form. In addition, the drain pad 113 does not include a region where a material mainly containing carbon is formed in a layered form.

[0866] Figure 41A Yes Figure 34 FIG. 3 is a top view of a SiC semiconductor wafer 331 used in manufacturing a semiconductor device 311 . Figure 41B yes Figure 41A The bottom view of the SiC semiconductor wafer 331 shows a state where the second wafer main surface 333 of the SiC semiconductor wafer 331 has undergone a polishing process and an annealing process.

[0867] Reference Figure 41A as well as Figure 41B The SiC semiconductor wafer 331 is formed of a disk-shaped SiC single crystal. The SiC semiconductor wafer 331 serves as a base for the SiC semiconductor substrate 111 .

[0868] The SiC semiconductor wafer 331 has a first wafer main surface 332 on one side, a second wafer main surface 333 on the other side, and a wafer side surface 334 connecting the first wafer main surface 332 and the second wafer main surface 333 .

[0869] The SiC semiconductor wafer 331 may also include a 4H-SiC single crystal. The first wafer main surface 332 of the SiC semiconductor wafer 331 has an off angle within 10° from the (0001) plane to the [11-20] direction.

[0870] The deflection angle may be greater than 0° and less than 4°. The deflection angle may be greater than 0° and less than 4°. Typically, the deflection angle is set within the range of 2° or 4°, more specifically, within the range of 2°±0.2° or 4°±0.4°.

[0871] One or more (in this embodiment, one) orientation flats 335 are formed on the wafer side surface 334 of the SiC semiconductor wafer 331, indicating the crystal orientation. Orientation flats 335 are cutouts formed on the periphery of the SiC semiconductor wafer 331. In this embodiment, orientation flats 335 extend linearly along the [11-20] direction.

[0872] The first wafer main surface 332 is an element formation surface where MISFETs are formed. A plurality of device formation regions 336 corresponding to the semiconductor devices 311 are defined on the first wafer main surface 332 .

[0873] In this embodiment, the plurality of device formation regions 336 are arranged in rows and columns along the [11-20] direction ([-1-120] direction) and the [-1100] direction ([1-100] direction).

[0874] The grid-shaped regions that divide the plurality of device formation regions 336 are dicing lines 337. The semiconductor devices 311 are cut out by cutting the SiC semiconductor wafer 331 along the peripheries of the plurality of device formation regions 336 (dicing lines 337).

[0875] Reference Figure 41B After the second wafer main surface 333 of the SiC semiconductor wafer 331 has been polished and annealed, a plurality of protrusion groups 316 and a plurality of polishing marks 338 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 .

[0876] The plurality of ridge groups 316 are formed in stripes that are substantially parallel to or parallel to the orientation plane 335. The plurality of ridge groups 316 may also be formed in stripes that intersect or are perpendicular to the orientation plane 335.

[0877] The plurality of polishing marks 338 extend in an arc shape from the center toward the periphery of the SiC semiconductor wafer 331. The plurality of polishing marks 338 generally include polishing marks 338 intersecting the [11-20] direction and the [1-100] direction.

[0878] The plurality of polishing marks 338 include polishing marks 338 extending approximately parallel to or parallel to the [11-20] or [1-100] directions at portions of the tangent lines of the arcs extending along the [11-20] or [1-100] directions. Grooves 321 formed in the second principal surface 104 of the SiC semiconductor layer 102 may also be formed from portions of the polishing marks 338.

[0879] Figure 42 Is used to illustrate Figure 34 Flowchart of an example of a method for manufacturing a semiconductor device 311 shown.

[0880] Figures 43A to 43I Applicable instructions Figure 34 A cross-sectional view illustrating a method for manufacturing a semiconductor device 311 is shown.

[0881] In the method for manufacturing the semiconductor device 311, in the step of forming the drain pad 113 of the method for manufacturing the semiconductor device 101 (see Figure 17L ), the processing step of the second wafer main surface 333 is performed before the step of forming the second wafer main surface 333. The processing step of the second wafer main surface 333 may also be performed after the step of forming the gate pad 108, the gate finger 109, and the source pad 110.

[0882] Reference Figure 43A First, implement Figures 17A to 17L In the process, a SiC semiconductor wafer 331 is prepared in which MISFETs are formed on a first wafer main surface 332. The second wafer main surface 333 of the SiC semiconductor wafer 331 is in an unprocessed state.

[0883] Next, refer to Figure 43B , grinding the second wafer main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 In this step, the second wafer main surface 333 of the SiC semiconductor wafer 331 is polished using abrasive grains having a grit size of 500 or greater.

[0884] The particle size of the abrasive grains is preferably not less than 1000 and not more than 5000. Thus, a plurality of grinding marks 338 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (also refer to Figure 41B ). In addition, thereby, the second wafer main surface 333 of the SiC semiconductor wafer 331 is flattened and the SiC semiconductor wafer 331 is thinned.

[0885] Next, refer to Figure 43C A metal layer 341 ( Figure 42 In this method, the metal layer 341 is formed by a Ni layer. The Ni layer can also be formed by sputtering. The thickness of the Ni layer can also be Above and the following.

[0886] Next, refer to Figure 43D , an annealing treatment method is performed on the second wafer main surface 333 of the SiC semiconductor wafer 331 ( Figure 42In this step, laser annealing is performed as an example of an annealing method.

[0887] In the laser annealing method, a laser having a diameter of 50 μm or more and 200 μm (for example, about 100 μm) is used. Pulsed laser. Pulsed laser is UV laser with a wavelength in the ultraviolet region. The energy of the pulsed laser can also be 1.0 J / cm 2 Above and 4.0J / cm 2 Below (e.g. 3.0 J / cm 2 about).

[0888] The pulse laser enters the second wafer main surface 333 of the SiC semiconductor wafer 331 through the metal layer 341 . In this method, the pulse laser enters the second wafer main surface 333 of the SiC semiconductor wafer 331 while moving the irradiation position along the orientation flat surface 335 .

[0889] On the second wafer main surface 333 of the SiC semiconductor wafer 331 , in a region where the pulse laser enters, one or more protrusions 315 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 .

[0890] Furthermore, on the second wafer main surface 333 of the SiC semiconductor wafer 331, in the region where the pulsed laser enters, a modified layer 323 is formed, in which the SiC of the SiC semiconductor wafer 331 is modified to have other properties. More specifically, the SiC of the SiC semiconductor wafer 331 is modified to Si by heating, causing carbon atoms to be removed from the SiC and / or sublimated.

[0891] Thus, a modified layer 323 including a Si modified layer is formed. The modified layer 323 may also include an amorphous silicon layer. The modified layer 323 may also include C atoms. The one or more raised portions 315 formed on the second wafer main surface 333 may also be formed from the modified layer 323.

[0892] Then, the pulsed laser continuously enters in the direction along the orientation flat 335, forming a plurality of protrusions 315 along the orientation flat 335. Thus, a protrusion group 316 including the plurality of protrusions 315 and extending along the [11-20] direction is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0893] When one ridge group 316 is formed, the pulse laser irradiation position moves in the [1-100] direction. Then, the pulse laser enters the second wafer main surface 333 of the SiC semiconductor wafer 331 while again moving the irradiation position along the orientation flat 335 .

[0894] As a result, another group of protrusions 316 extending substantially parallel to or in parallel with the one group of protrusions 316 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 .

[0895] In the laser annealing method, such steps are repeated until a plurality of protrusion groups 316 are formed over substantially the entire area or the entire area of ​​the second wafer main surface 333 of the SiC semiconductor wafer 331 (also refer to Figure 41B ).

[0896] In this embodiment, the laser annealed metal layer 341 has a stacked structure including a carbon layer 342 , a NiSi (nickel silicide) layer 343 , and a Ni layer 344 stacked in this order from the second wafer principal surface 333 side of the SiC semiconductor wafer 331 .

[0897] That is, the laser annealing method includes a step of reacting the metal layer 341 with the SiC semiconductor wafer 331 to form a silicide. More specifically, the laser annealing method includes a step of forming the NiSi layer 343 .

[0898] In the laser annealing method, in addition to the NiSi layer 343, a carbon layer 342 containing carbon atoms is formed as a by-product in the metal layer 341. The carbon layer 342 is formed by precipitation of carbon atoms constituting SiC.

[0899] In metal layer 341, carbon layer 342 and NiSi layer 343 can serve as delamination starting points. While metal layer 341 can be used as drain pad 113 without modification, it can lead to poor connection and increased resistance. Therefore, it is preferable to form a metal layer different from preferred metal layer 341 as drain pad 113.

[0900] The temperature applied to metal layer 341 during the formation of NiSi layer 343 is equal to or higher than the melting points of gate pad 108 , gate finger 109 , and source pad 110 (eg, equal to or higher than 1000° C.).

[0901] The laser annealing method can locally increase the temperature of the second wafer main surface 333 of the SiC semiconductor wafer 331, thereby preventing the gate pad 108, gate fingers 109, and source pad 110 from heating up. Therefore, melting of the gate pad 108, gate fingers 109, and source pad 110 can be appropriately suppressed.

[0902] Next, refer to Figure 43E , a step of removing the metal layer 341 is performed. The step of removing the metal layer 341 is performed until the second wafer main surface 333 of the SiC semiconductor wafer 331 is exposed.

[0903] In this process, first, the NiSi layer 343 and the Ni layer 344 in the metal layer 341 are removed. Figure 42 The NiSi layer 343 and the Ni layer 344 may also be removed by wet etching.

[0904] Next, refer to Figure 43F , remove the carbon layer 342 in the metal layer 341 ( Figure 42 The carbon layer 342 may also be removed by dry etching.

[0905] Next, refer to Figure 43G , removing the residue of the NiSi layer 343 and the residue of the Ni layer 344 attached to the second wafer main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 The NiSi layer 343 and the Ni layer 344 may also be removed by wet etching.

[0906] Next, refer to Figure 43H , removing the residue of the carbon layer 342 attached to the second wafer main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 The carbon layer 342 may also be removed by dry etching.

[0907] Next, the natural oxide film ( Figure 42 The natural oxide film can also be removed by wet etching.

[0908] As described above, in this embodiment, the step of removing the layer containing Ni (NiSi layer 343 and Ni layer 344 ) and the step of removing the layer containing carbon (carbon layer 342 ) are repeated twice.

[0909] This allows for appropriate removal of the metal layer 341. After the metal layer 341 removal step, the second wafer main surface 333 of the SiC semiconductor wafer 331, whose resistance value has been reduced by the laser annealing process, is appropriately exposed.

[0910] Next, refer to Figure 43I , a drain pad 113 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 Step S9).

[0911] This process includes forming Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 in order from the second wafer main surface 333 of SiC semiconductor wafer 331. Ti layer 324, Ni layer 325, Au layer 326, and Ag layer 327 can all be formed by sputtering.

[0912] In the drain pad 113 , the Ti layer 324 is directly connected to the second wafer main surface 333 of the SiC semiconductor wafer 331 . The Ti layer 324 also covers the plurality of protrusion groups 316 , forming ohmic contacts between the plurality of protrusion groups 316 and between the plurality of spaces 320 .

[0913] Next, the SiC semiconductor wafer 331 is cut along the periphery (dicing lines 337) of the plurality of device formation regions 336. Thus, a plurality of semiconductor devices 311 are cut out from the SiC semiconductor wafer 331. Through the steps including the above steps, the semiconductor device 311 is manufactured.

[0914] As described above, semiconductor device 311 can achieve the same effects as those described for semiconductor device 101. Furthermore, semiconductor device 311 can increase the connection area of ​​drain pad 113 to second main surface 104 of SiC semiconductor layer 102 through bump group 316. This can improve electrical characteristics.

[0915] More specifically, drain pad 113 forms ohmic contact with bump group 316. This allows for good ohmic characteristics to be obtained between SiC semiconductor layer 102 and drain pad 113, thereby improving electrical characteristics.

[0916] Furthermore, in semiconductor device 311, drain pad 113 is directly connected to second main surface 104 of SiC semiconductor layer 102. More specifically, drain pad 113 forms ohmic contact with bump group 316 without a carbon layer interposed therebetween. Furthermore, drain pad 113 forms ohmic contact with bump group 316 without a silicide layer interposed therebetween.

[0917] Therefore, by directly connecting the drain pad 113 to the second main surface 104 of the SiC semiconductor layer 102, it is possible to appropriately suppress poor connection or an increase in resistance caused by the poor connection.

[0918] Figure 44 is with Figure 35 The corresponding bottom view is a bottom view showing a semiconductor device 351 according to a twenty-third embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 311 are denoted by the same reference numerals and their descriptions are omitted.

[0919] Reference Figure 44 The semiconductor device 351 includes a plurality of bump groups 316 including a first bump group 316A and a second bump group 316B.

[0920] First raised portion group 316A includes a plurality of first raised portions 315A formed on second principal surface 104 of SiC semiconductor layer 102. First raised portions 315A are portions raised on second principal surface 104 of SiC semiconductor layer 102 in a direction normal to second principal surface 104 of SiC semiconductor layer 102.

[0921] The plurality of first raised portions 315A are formed at intervals along the first direction X and a second direction Y intersecting the first direction X. The first raised portion 315A has a first portion 317A, which is a portion where some of the plurality of first raised portions 315A overlap in the first direction X when viewed from the first direction X.

[0922] Furthermore, the first raised portion 315A includes a second portion 318A in which some of the plurality of first raised portions 315A are separated from the first portion 317A and overlap in the first direction X when viewed in the first direction.

[0923] The plurality of first raised portions 315A are continuously formed along the first direction X. More specifically, the plurality of first raised portions 315A have a distribution pattern in which the plurality of first raised portions 315A are distributed along the first direction X and the second direction Y at intervals.

[0924] The plurality of first raised portions 315A maintains this distribution pattern and is continuously formed in the first direction X. In this embodiment, the distribution pattern of the plurality of first raised portions 315A extends from the periphery of one side surface 105A to the periphery of the other side surface 105C of the SiC semiconductor layer 102 in a plan view.

[0925] When viewed from the first direction X, the first raised portion group 316A has a layout in which a plurality of raised portions 315 overlap in the first direction X. Thus, the first raised portion group 316A is formed by a collective pattern of the plurality of raised portions 315 continuously distributed in the first direction X, forming a first raised portion group region 319A extending in a band shape in the first direction X.

[0926] In other words, the first raised portion group region 319A includes a plurality of first raised portions 315A (first raised portion group 316A) formed in a band-shaped region extending in the first direction X on the second main surface 104 of the SiC semiconductor layer 102 .

[0927] Second raised portion group 316B includes a plurality of second raised portions 315B formed on second principal surface 104 of SiC semiconductor layer 102. Second raised portions 315B are portions raised on second principal surface 104 of SiC semiconductor layer 102 in a direction normal to second principal surface 104 of SiC semiconductor layer 102.

[0928] The plurality of second raised portions 315B are formed at intervals along the first direction X and a second direction Y intersecting the first direction X. The second raised portion group 316B includes a first portion 317B where some of the plurality of second raised portions 315B overlap in the second direction Y when viewed from the second direction Y.

[0929] The second raised portion group 316B includes a second portion 318B in which some of the second raised portions 315B are formed separately from the first portion 317B and overlap in the second direction Y when viewed in the second direction.

[0930] The plurality of second raised portions 315B are continuously formed along the second direction Y. More specifically, the plurality of second raised portions 315B have a distribution pattern in which the plurality of second raised portions 315B are distributed along the first direction X and the second direction Y at intervals.

[0931] The plurality of second raised portions 315B maintain this distribution pattern and are continuously formed along the second direction Y. In this embodiment, the distribution pattern of the plurality of second raised portions 315B is formed from the periphery of one side surface 105B to the periphery of the other side surface 105D of the SiC semiconductor layer 102 in a plan view.

[0932] When viewed from the second direction Y, the second raised portion group 316B has a layout in which a plurality of second raised portions 315B overlap in the second direction Y. Thus, the second raised portion group 316B is formed by a collective pattern of a plurality of second raised portions 315B continuously distributed in the second direction Y, forming a second raised portion group region 319B extending in a band shape in the second direction Y.

[0933] In other words, the second raised portion group region 319B includes a plurality of second raised portions 315B (second raised portion group 316B) formed in a band-shaped region extending in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102 .

[0934] The second raised portion group 316B (second raised portion group region 319B) crosses the first raised portion group 316A (first raised portion group region 319A). As a result, an intersection region 352 is formed on the second main surface 104 of the SiC semiconductor layer 102, where the first raised portion group 316A (first raised portion group region 319A) and the second raised portion group 316B (second raised portion group region 319B) intersect.

[0935] In this embodiment, a plurality of first raised portion groups 316A are formed on the second main surface 104 of the SiC semiconductor layer 102 at intervals along the second direction Y. In other words, the distribution pattern of the plurality of first raised portions 315A is formed intermittently with respect to the second direction Y.

[0936] In this embodiment, a plurality of second raised portion groups 316B are formed on the second main surface 104 of the SiC semiconductor layer 102 at intervals along the first direction X. That is, the distribution pattern of the plurality of second raised portions 315B is formed intermittently with respect to the first direction X.

[0937] Therefore, in this embodiment, the intersection region 352 is formed in a matrix arrangement with spaces between them along the first direction X and the second direction Y. Furthermore, the first raised portion group 316A and the second raised portion group 316B define a space 320. The space 320 is formed in a matrix arrangement with spaces between them along the first direction X and the second direction Y.

[0938] The plurality of first raised portions 315A and the plurality of second raised portions 315B may overlap each other in the intersection region 352. The thickness of the plurality of first raised portions 315A and the plurality of second raised portions 315B formed in the intersection region 352 may be greater than the thickness of the first raised portions 315A and the second raised portions 315B formed in the region outside the intersection region 352.

[0939] Furthermore, the number of the plurality of first raised portions 315A and the plurality of second raised portions 315B formed in the intersection region 352 may be greater than the number of the first raised portions 315A and the second raised portions 315B formed in the region outside the intersection region 352 .

[0940] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. That is, the first raised portion group 316A (first raised portion group region 319A) may be formed substantially parallel to or parallel to the [11-20] direction, and the second raised portion group 316B (second raised portion group region 319B) may be formed substantially parallel to or parallel to the [1-100] direction.

[0941] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. That is, the first raised portion group 316A (first raised portion group region 319A) is formed substantially parallel to or parallel to the [1-100] direction, and the second raised portion group 316B (second raised portion group region 319B) is formed substantially parallel to or parallel to the [11-20] direction.

[0942] The first raised portion 315A and the first raised portion group 316A correspond to the raised portion 315 and the raised portion group 316 of the twenty-second embodiment. The description of the raised portion 315 and the raised portion group 316 of the twenty-second embodiment refers to the description of the first raised portion 315A and the first raised portion group 316A, and other specific descriptions of the first raised portion 315A and the first raised portion group 316A are omitted.

[0943] The second raised portion 315B and the second raised portion group 316B correspond to the raised portion 315 and the raised portion group 316 of the twenty-second embodiment. The description of the raised portion 315 and the raised portion group 316 of the twenty-second embodiment refers to the other descriptions of the second raised portion 315B and the second raised portion group 316B, and other specific descriptions of the second raised portion 315B and the second raised portion group 316B are omitted.

[0944] In this embodiment, drain pad 113 covers first and second ridge groups 316A and 316B on second main surface 104 of SiC semiconductor layer 102. In this embodiment, drain pad 113 covers both first and second ridge groups 316A and 316B.

[0945] Drain pad 113 is formed in a film shape to follow the outer surface of first bump group 316A (outer surface of first bump 315A), the outer surface of second bump group 316B (outer surface of second bump 315B), and the inner surface of groove 321 .

[0946] Thus, although not shown, a raised portion 113a is formed on the outer surface of drain pad 113 in a portion covering first raised portion group 316A (first raised portion 315A) and second raised portion group 316B (second raised portion 315B). Furthermore, a recessed portion 113b is formed on the outer surface of drain pad 113 in a portion covering groove 321.

[0947] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the first ridge group 316A and the second ridge group 316B.

[0948] More specifically, drain pad 113 forms ohmic contact with first ridge group 316A and second ridge group 316B. In this embodiment, drain pad 113 also forms ohmic contact with space 320.

[0949] The portion of drain pad 113 covering first ridge group 316A and second ridge group 316B meshes with the concave and convex portions defined by first ridge groups 316A, second ridge groups 316B, and grooves 321 .

[0950] That is, the contact area of ​​drain pad 113 with second main surface 104 of SiC semiconductor layer 102 is increased by first ridge groups 316A, second ridge groups 316B, and grooves 321. This improves the adhesion of drain pad 113 with second main surface 104 of SiC semiconductor layer 102.

[0951] The semiconductor device 351 of this structure is subjected to the above-mentioned laser annealing process ( Figure 42 In step S3), the following steps are implemented to manufacture.

[0952] First, a plurality of first protrusion groups 316A are formed by laser annealing in a direction substantially parallel to or parallel to the orientation flat 335. Next, a plurality of second protrusion groups 316B are formed in a direction intersecting (orthogonal to) the orientation flat 335 by laser annealing.

[0953] In this process, a plurality of first protrusion groups 316A are formed in a direction intersecting (orthogonal) with the orientation plane 335, and a plurality of second protrusion groups 316B may be formed in a direction substantially parallel or parallel to the orientation plane 335. Figure 42 The semiconductor device 351 is manufactured through the processes of steps S4 to S9.

[0954] The first and second ridge groups 316A and 316B may be formed in any order. Thus, the first ridge groups 316A may be formed after the second ridge groups 316B are formed. Alternatively, the first and second ridge groups 316A and 316B may be formed alternately.

[0955] As described above, according to the semiconductor device 351 , the same effects as those described for the semiconductor device 311 can be achieved.

[0956] Figure 45 is with Figure 39 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device 361 according to the twenty-fourth embodiment of the present invention. Figure 46 yes Figure 45 Hereinafter, structures corresponding to those described for the semiconductor device 311 are denoted by the same reference numerals and their descriptions are omitted.

[0957] In the semiconductor device 361, the drain pad 113 has a three-layer structure including a Ni layer 325, an Au layer 326, and an Ag layer 327 stacked in this order from the second main surface 104 of the SiC semiconductor layer 102. Figure 42 The Ti layer 324 is formed without forming the Ti layer in step S9.

[0958] The Ni layer 325 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ni layer 325 also covers the plurality of protrusion groups 316.

[0959] The Ni layer 325 forms ohmic contact with the protrusion group 316 and with the space 320. The Au layer 326 covers substantially the entire region or the entire region of the Ni layer 325. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0960] As described above, semiconductor device 361 can achieve the same effects as those described for semiconductor device 311. In semiconductor device 361, drain pad 113 may have a single-layer structure composed of Ni layer 325.

[0961] Figure 47 is with Figure 39 The corresponding cross-sectional view is a cross-sectional view showing a semiconductor device 371 according to the twenty-fifth embodiment of the present invention. Figure 48 yes Figure 47 Hereinafter, structures corresponding to those described for the semiconductor device 311 are denoted by the same reference numerals and their descriptions are omitted.

[0962] In semiconductor device 371, drain pad 113 includes metal layer 341, Au layer 326, and Ag layer 327. In this embodiment, metal layer 341 has a stacked structure including carbon layer 342, NiSi layer 343, and Ni layer 344 stacked in this order from second principal surface 104 side of SiC semiconductor layer 102.

[0963] The metal layer 341 is connected to the second main surface 104 of the SiC semiconductor layer 102. The metal layer 341 also covers the plurality of protrusion groups 316.

[0964] The metal layer 341 forms ohmic contact with the protrusion group 316 and with the space 320. The Au layer 326 covers substantially the entire region or the entire region of the metal layer 341. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0965] The semiconductor device 371 is Figure 42 The metal layer 341 removal step is omitted (see Figure 42In the semiconductor device 371, in the above-mentioned steps S4 to S8) Figure 42 In step S9 , the Au layer 326 and the Ag layer 327 are formed on the metal layer 341 .

[0966] As described above, according to semiconductor device 371, drain pad 113 includes carbon layer 342 and NiSi layer 343. Although semiconductor device 371 cannot improve the connection strength of drain pad 113 as much as semiconductor device 311, it can achieve substantially the same effects as those described for semiconductor device 311. In semiconductor device 371, drain pad 113 may also be formed solely of metal layer 341.

[0967] As mentioned above, although the 22nd to 25th embodiments of the present invention have been described, the 22nd to 25th embodiments of the present invention can also be implemented in other forms.

[0968] In the above-described 22nd to 25th embodiments, examples have been described in which the SiC semiconductor layer 102 has a stacked structure including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 .

[0969] However, the SiC semiconductor layer 102 may have a single-layer structure composed of the SiC semiconductor substrate 111 . The SiC semiconductor layer 102 may have a single-layer structure composed of the SiC epitaxial layer 112 .

[0970] In the above-described 22nd to 25th embodiments, an example of forming the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b by epitaxial growth has been described. However, the SiC epitaxial layer 112 can also be formed by the following steps.

[0971] First, a SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface of the SiC epitaxial layer 112 by ion implantation. This forms the SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0972] In the 22nd to 25th embodiments described above, examples are described in which the gate electrode layer 132 and gate wiring layer 133 are formed of p-type polysilicon doped with p-type impurities. However, if increasing the gate threshold voltage Vth is not important, the gate electrode layer 132 and gate wiring layer 133 may be formed of n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0973] In other words, the low-resistance electrode layer 134 may also include n-type polysilicon. The low-resistance electrode layer 134 may also be formed by silicideing the surface portion of the gate electrode layer 132 (n-type polysilicon) using a metal material. In this case, the gate resistance can be reduced.

[0974] In the above-mentioned 22nd to 25th embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, a p-type portion may be changed to an n-type portion, and an n-type portion may be changed to a p-type portion.

[0975] In the above-mentioned 22nd to 25th embodiments, a p+ type SiC semiconductor substrate (111) may be used instead of the n+ type SiC semiconductor substrate 111. In this case, in the description of the above-mentioned 22nd to 25th embodiments, "source" is replaced by "emitter" and "drain" is replaced by "collector".

[0976] Figure 49 It is a top view showing a semiconductor device 401 according to a twenty-sixth embodiment of the present invention. Figure 50 Yes Figure 49 The top view of the semiconductor device 401 shown is a top view from which the resin layer 416 is removed.

[0977] Reference Figure 49 as well as Figure 50 The semiconductor device 401 includes a SiC semiconductor layer 402 made of SiC (silicon carbide) single crystal. The SiC semiconductor layer 402 may also include 4H-SiC single crystal.

[0978] 4H-SiC single crystals have an off-angle of less than 10° from the

[0001] plane to the [11-20] direction. The off-angle can be between 0° and 4°. It can also be greater than 0° and less than 4°. Typically, the off-angle is set within the range of 2° or 4°, more specifically, within the range of 2° ± 0.2° or 4° ± 0.4°.

[0979] In this embodiment, the SiC semiconductor layer 402 is formed into a rectangular parallelepiped sheet. The SiC semiconductor layer 402 has a first main surface 403 on one side, a second main surface 404 on the other side, and side surfaces 405A, 405B, 405C, and 405D connecting the first main surface 403 and the second main surface 404. The first main surface 403 and the second main surface 404 are formed into a quadrilateral shape (a rectangular shape in this embodiment) when viewed from above (hereinafter referred to as "top view") as viewed from the direction normal to the first and second main surfaces 403 and 404.

[0980] Side surface 405A faces side surface 405C. Side surface 405B faces side surface 405D. Side surfaces 405A to 405D extend in a planar manner along the normal direction of first principal surface 403 and second principal surface 404, respectively. The length of each side surface 405A to 405D may be greater than 1 mm and less than 10 mm (e.g., greater than 2 mm and less than 5 mm).

[0981] The SiC semiconductor layer 402 includes an active region 406 and an outer region 407 . The active region 406 is a region where vertical MISFETs are formed, and the outer region 407 is a region outside the active region 406 .

[0982] Active region 406 is provided in the center of SiC semiconductor layer 402, spaced inward from side surfaces 405A to 405D of SiC semiconductor layer 402 in a plan view. Active region 406 is provided in a quadrilateral shape (a rectangular shape in this embodiment) having four sides parallel to side surfaces 405A to 405D of SiC semiconductor layer 402 in a plan view.

[0983] The outer region 407 is defined between the side surfaces 405A to 405D of the SiC semiconductor layer 402 and the periphery of the active region 406. The outer region 407 is defined in a seamless shape (a square ring shape) surrounding the active region 406 in a plan view.

[0984] A main-surface gate electrode 408 and a main-surface source electrode 409 are formed on the first main surface 403 of the SiC semiconductor layer 402 .

[0985] The main surface gate electrode 408 includes a gate pad 410 and gate fingers 411. In this embodiment, the gate pad 410 and the gate fingers 411 are arranged in the active region 406.

[0986] The gate pad 410 is formed along the side surface 405A of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed along the central region of the side surface 405A of the SiC semiconductor layer 402 in a plan view.

[0987] The gate pad 410 may be formed along a corner portion connecting any two of the side surfaces 405A to 405D of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed in a quadrilateral shape in a plan view.

[0988] The gate fingers 411 include outer gate fingers 411A and inner gate fingers 411B.

[0989] Outer gate fingers 411A extend from gate pad 410 and extend in a stripe shape along the periphery of active region 406. In this embodiment, outer gate fingers 411A are formed along three side surfaces 405A, 405B, and 405D of SiC semiconductor layer 402 to divide the inner region of active region 406 in three directions.

[0990] The outer gate finger 411A has a pair of open ends 412A and 412B. The pair of open ends 412A and 412B of the outer gate finger 411A are formed in a region facing the gate pad 410 across the inner region of the active region 406. In this embodiment, the pair of open ends 412A and 412B of the outer gate finger 411A are formed along the side surface 405C of the SiC semiconductor layer 402.

[0991] The inner gate finger 411B is extended from the gate pad 410 to the inner region of the active region 406. The inner gate finger 411B extends in a stripe shape in the inner region of the active region 406. The inner gate finger 411B extends from the side surface 405A to the side surface 405C.

[0992] In this embodiment, the main surface source electrode 409 includes a source pad 413 , a source pull-back line 414 , and a source connection portion 415 .

[0993] The source pad 413 is formed in the active area 406 at a distance from the gate pad 410 and the gate finger 411. The source pad 413 is formed to cover the C-shaped portion (at the bottom) defined by the gate pad 410 and the gate finger 411. Figure 49 as well as Figure 50 In the manner of forming an inverted C-shape in the region, the region is formed into a C-shape in a plan view (in Figure 49 as well as Figure 50 It is an inverted C shape).

[0994] The source pull-back line 414 is formed in the outer region 407. The source pull-back line 414 extends in a ribbon shape along the active region 406. In this embodiment, the source pull-back line 414 is formed in a continuous shape (a four-sided ring shape) surrounding the active region 406 in a plan view. The source pull-back line 414 is electrically connected to the SiC semiconductor layer 402 in the outer region 407.

[0995] Source connection portion 415 connects source pad 413 and source pull-back line 414. Source connection portion 415 is provided in the region between a pair of open ends 412A and 412B of outer gate finger 411A. Source connection portion 415 extends from source pad 413 across the boundary between active region 406 and outer region 407 and connects to source pull-back line 414.

[0996] The MISFET formed in the active region 406 includes an npn-type parasitic bipolar transistor in its structure. If the avalanche current generated in the outer region 407 flows into the active region 406, the parasitic bipolar transistor turns on. In this case, there is a possibility that the control of the MISFET will become unstable due to latchup, for example.

[0997] Here, in the semiconductor device 401 , the structure of the main surface source electrode 409 forms an avalanche current absorbing structure that absorbs an avalanche current generated in a region outside the active region 406 .

[0998] More specifically, the avalanche current generated in the outer region 407 is absorbed by the source pull-back wiring 414. Thus, the avalanche current reaches the source pad 413 via the source connection portion 415. When a wire for external connection (e.g., a bonding wire) is connected to the source pad 413, the avalanche current is output through the wire.

[0999] This can prevent the parasitic bipolar transistor from being turned on due to an unintended current generated in the outer region 407. Therefore, latch-up can be suppressed, thereby improving the stability of the control of the MISFET.

[1000] A gate voltage is applied to gate pad 410 and gate finger 411. The gate voltage may be greater than 10 V and less than 50 V (eg, approximately 30 V). A source voltage is applied to source pad 413. The source voltage may be a reference voltage (eg, GND voltage).

[1001] A resin layer 416 is formed on the first main surface 403 of the SiC semiconductor layer 402 (more specifically, on the interlayer insulating layer 491 described later). Figure 49 , for clarity, the resin layer 416 is shown by hatching. The resin layer 416 covers the gate pad 410, the gate finger 411, and the source pad 413.

[1002] The resin layer 416 may include a negative or positive photosensitive resin. In this embodiment, the resin layer 416 includes polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 416 may also include polyimide, which is an example of a negative photosensitive resin.

[1003] A gate pad opening 417 and a source pad opening 418 are formed in the resin layer 416. The gate pad opening 417 exposes the gate pad 410. The source pad opening 418 exposes the source pad 413.

[1004] The peripheral portion 419 of the resin layer 416 is formed at intervals inward from the side surfaces 405A to 405D of the SiC semiconductor layer 402. Thus, the resin layer 416 exposes the peripheral portion of the SiC semiconductor layer 402 (more specifically, the interlayer insulating layer 491 described later).

[1005] The peripheral edge 419 of the resin layer 416 forms a dicing street when the semiconductor device 401 is cut out of a SiC semiconductor wafer. By exposing the peripheral edge of the SiC semiconductor layer 402 from the resin layer 416, the resin layer 416 does not need to be physically cut.

[1006] Therefore, semiconductor devices 401 can be smoothly cut out from a single SiC semiconductor wafer. Side surfaces 405A to 405D of SiC semiconductor layer 402 may also be cut surfaces (polished surfaces). Side surfaces 405A to 405D of SiC semiconductor layer 402 may also have polishing marks.

[1007] Figure 51 yes Figure 50 The enlarged view of the region LI shown is a diagram for explaining the structure of the first main surface 403 of the SiC semiconductor layer 402 . Figure 52 It is along Figure 51 The cross-sectional view taken along line LII-LII is a cross-sectional view showing a first embodiment of the gate trench 431 and a first embodiment of the source trench 441 . Figure 53 It is along Figure 51 The cross-sectional view taken along line LIII-LIII is a cross-sectional view showing a first embodiment of the gate wiring layer 436 . Figure 54 yes Figure 52 Magnified view of area LIV is shown.

[1008] Figure 55 It is along Figure 50 The cross-sectional view taken along the LV-LV line shown is a cross-sectional view showing a first example of the active side wall 464, a first example of the outer main surface 462, a first example of the side wall 482, a first example of the diode region 471, a first example of the outer deep well region 472, a first example of the field limiting structure 473, and a first example of the anchor hole 495. Figure 56 yes Figure 55 The enlarged view of the region LVI shown is an enlarged view showing a first embodiment of the active sidewall 464 and a first embodiment of the outer main surface 462 .

[1009] Reference Figures 51 to 55 In this embodiment, the SiC semiconductor layer 402 has a stacked structure including an n+-type SiC semiconductor substrate 421 and an n-type SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 is formed by the SiC semiconductor substrate 421.

[1010] The first main surface 403 of the SiC semiconductor layer 402 is formed by the SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 may be a polished surface. The second main surface 404 of the SiC semiconductor layer 402 may have polishing marks.

[1011] The thickness of the SiC semiconductor substrate 421 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 421 may be 5 μm or more. The thickness of the SiC semiconductor substrate 421 may be 25 μm or more. The thickness of the SiC semiconductor substrate 421 may be 50 μm or more. The thickness of the SiC semiconductor substrate 421 may be 100 μm or more.

[1012] The thickness of the SiC semiconductor substrate 421 may be 700 μm or less. The thickness of the SiC semiconductor substrate 421 may be 500 μm or less. The thickness of the SiC semiconductor substrate 421 may be 400 μm or less. The thickness of the SiC semiconductor substrate 421 may be 300 μm or less.

[1013] The thickness of the SiC semiconductor substrate 421 may be 250 μm or less. The thickness of the SiC semiconductor substrate 421 may be 200 μm or less. The thickness of the SiC semiconductor substrate 421 may be 150 μm or less. The thickness of the SiC semiconductor substrate 421 may be 100 μm or less.

[1014] The thickness of the SiC semiconductor substrate 421 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 421 , the resistance value can be reduced by shortening the current path.

[1015] The thickness of the SiC epitaxial layer 422 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 422 may be 5 μm or more. The thickness of the SiC epitaxial layer 422 may be 10 μm or more.

[1016] The thickness of the SiC epitaxial layer 422 may be 50 μm or less. The thickness of the SiC epitaxial layer 422 may be 40 μm or less. The thickness of the SiC epitaxial layer 422 may be 30 μm or less.

[1017] The thickness of the SiC epitaxial layer 422 may be 20 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 10 μm or less.

[1018] The n-type impurity concentration of the SiC epitaxial layer 422 is lower than the n-type impurity concentration of the SiC semiconductor substrate 421. The n-type impurity concentration of the SiC epitaxial layer 6 may be 1.0×1015 cm －3 Above 1.0×10 18 cm －3 the following.

[1019] In this embodiment, the SiC epitaxial layer 422 includes a plurality of regions having different n-type impurity concentrations along a direction normal to the first main surface 403 of the SiC semiconductor layer 402. More specifically, the SiC epitaxial layer 422 includes a high-concentration region 422a having a relatively high n-type impurity concentration, and a low-concentration region 422b having a lower n-type impurity concentration than the high-concentration region 422a.

[1020] The high-concentration region 422a is formed in a region on the first main surface 403 side. The low-concentration region 422b is formed in a region on the second main surface 404 side of the SiC semiconductor layer 402 relative to the high-concentration region 422a.

[1021] The n-type impurity concentration of the high-concentration region 422a may also be 1×10 16 cm －3 Above and 1×10 18 cm －3 The n-type impurity concentration of the low-concentration region 422b may be 1×10 15 cm －3 Above and 1×10 16 cm －3 the following.

[1022] The thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. More specifically, the thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. In other words, the thickness of the high-concentration region 422a is less than half the total thickness of the SiC epitaxial layer 422.

[1023] A drain pad 423 serving as a second main surface electrode is connected to second main surface 404 of SiC semiconductor layer 402. During the off state, the maximum voltage applicable between source pad 413 and drain pad 423 may be 1000V or higher and 10000V or lower.

[1024] The drain pad 423 may include at least one of a Ti layer, a Ni layer, an Au layer, and an Ag layer. The drain pad 423 has a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order from the second main surface 404 of the SiC semiconductor layer 402 .

[1025] The SiC semiconductor substrate 421 is formed as the drain region 424 of the MISFET. The SiC epitaxial layer 422 is formed as the drift region 425 of the MISFET.

[1026] In the active region 406 , a p-type body region 426 is formed on the surface portion of the first main surface 403 of the SiC semiconductor layer 402 . The body region 426 defines the active region 406 .

[1027] That is, in this embodiment, the body region 426 is formed in the entire region where the active region 406 is formed on the first main surface 403 of the SiC semiconductor layer 402. The p-type impurity concentration of the body region 426 may be 1×10 17 cm －3 Above and 1×10 20 cm －3 the following.

[1028] In the active region 406, a plurality of gate trenches 431 are formed in the surface portion of the first main surface 403 of the SiC semiconductor layer 402. The plurality of gate trenches 431 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 431 are formed in a strip shape extending along a second direction Y intersecting the first direction X.

[1029] More specifically, the first direction X is a direction along the side surfaces 405B and 405D of the SiC semiconductor layer 402 . The second direction Y is a direction perpendicular to the first direction X. The second direction Y is also a direction along the side surfaces 405A and 405C of the SiC semiconductor layer 402 .

[1030] The plurality of gate trenches 431 are formed in a stripe shape in a plan view. In this embodiment, each gate trench 431 extends in a stripe shape from the peripheral portion on one side (side surface 405B) toward the peripheral portion on the other side (side surface 405D) of the active region 406 .

[1031] Each gate trench 431 traverses a portion midway between one peripheral portion and the other peripheral portion of the active region 406. One end of each gate trench 431 is located at one peripheral portion of the active region 406. The other end of each gate trench 431 is located at the other peripheral portion of the active region 406.

[1032] The first direction X may be set to the [11-20] direction ([-1-120] direction). In this case, each gate trench 431 may extend along the [11-20] direction. The first direction X may be set to the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 431 may extend along the [-1100] direction ([1-100] direction).

[1033] Each gate trench 431 has a length of the order of millimeters. Figure 53In the cross section shown, the length of the gate trench 431 is the length from the end portion on the connection side between the gate trench 431 and the gate finger 411 to the end portion on the opposite side.

[1034] The length of each gate trench 431 may also be greater than 0.5 mm. In this embodiment, the length of each gate trench 431 is greater than 1 mm and less than 10 mm (e.g., greater than 2 mm and less than 5 mm). The total extension of one or more gate trenches 431 per unit area may also be 0.5 μm / μm. 2 Above and 0.75μm / μm 2 the following.

[1035] Each gate trench 431 integrally includes an active trench portion 431 a and a contact trench portion 431 b. The active trench portion 431 a is a portion of the active region 406 along the channel region of the MISFET.

[1036] The contact trench portion 431b is a portion of the gate trench 431 intended to contact the gate finger 411. The contact trench portion 431b extends from the active trench portion 431a toward the periphery of the active region 406. The contact trench portion 431b is formed directly below the gate finger 411. The extension length of the contact trench portion 431b is optional.

[1037] Each gate trench 431 passes through the main body region 426 and reaches the SiC epitaxial layer 422 . The bottom wall of each gate trench 431 is located in the SiC epitaxial layer 422 .

[1038] More specifically, the bottom wall of each gate trench 431 is located in the high-concentration region 422 a of the SiC epitaxial layer 422 . The bottom wall of the gate trench 431 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402 .

[1039] The sidewalls of the gate trench 431 may extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402 . That is, the sidewalls of the gate trench 431 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402 .

[1040] The depth of the gate trench 431 may be 0.5 μm to 3 μm (eg, approximately 1 μm) in the normal direction of the first main surface 403 of the SiC semiconductor layer 402. The depth of the gate trench 431 is preferably 0.5 μm to 1.0 μm.

[1041] The width of the gate trench 431 in the first direction may be greater than or equal to 0.1 μm and less than or equal to 2 μm (eg, approximately 0.5 μm). The width of the gate trench 431 in the first direction is preferably greater than or equal to 0.1 μm and less than or equal to 0.5 μm.

[1042] Reference Figure 54 The opening edge portion 432 of each gate trench 431 includes an inclined portion 433 that slopes downward from the first main surface 403 of the SiC semiconductor layer 402 toward the interior of the gate trench 431. The opening edge portion 432 of the gate trench 431 is a corner portion connecting the first main surface 403 of the SiC semiconductor layer 402 and the sidewall of the gate trench 431.

[1043] In this embodiment, the inclined portion 433 is formed in a concavely curved shape toward the inside of the SiC semiconductor layer 402. The inclined portion 433 may be formed in a convexly curved shape toward the inside of the gate trench 431.

[1044] The electric field with respect to the opening edge portion 432 of the gate trench 431 is dispersed along the inclined portion 433. Thus, the electric field concentration with respect to the opening edge portion 432 of the gate trench 431 can be alleviated.

[1045] A gate insulating layer 434 and a gate electrode layer 435 are formed in each gate trench 431. Figure 51 The gate insulating layer 434 and the gate electrode layer 435 are shown by hatching.

[1046] The gate insulating layer 434 includes silicon oxide. The gate insulating layer 434 may also include other insulating films such as silicon nitride. The gate insulating layer 434 is formed in a film shape along the inner wall surface of the gate trench 431 so as to define a concave space in the gate trench 431.

[1047] The gate insulating layer 434 includes a first region 434a, a second region 434b, and a third region 434c. The first region 434a is formed along the sidewalls of the gate trench 431. The second region 434b is formed along the bottom wall of the gate trench 431. The third region 434c is formed along the first main surface 403 of the SiC semiconductor layer 402.

[1048] The thickness T1 of the first region 434a is smaller than the thickness T2 of the second region 434b and the thickness T3 of the third region 434c. The ratio T2 / T1 of the thickness T2 of the second region 434b to the thickness T1 of the first region 434a may be greater than 2 and less than 5. The ratio T3 / T1 of the thickness T3 of the third region 434c to the thickness T1 of the first region 434a may be greater than 2 and less than 5.

[1049] The thickness T1 of the first region 434a may be 0.01 μm to 0.2 μm, the thickness T2 of the second region 434b may be 0.05 μm to 0.5 μm, and the thickness T3 of the third region 434c may be 0.05 μm to 0.5 μm.

[1050] By forming the first region 434a of the gate insulating layer 434 relatively thinly, an increase in carriers induced in the area near the sidewalls of the gate trench 431 in the body region 426 can be suppressed. This can thereby suppress an increase in channel resistance. By forming the second region 434b of the gate insulating layer 434 relatively thickly, electric field concentration relative to the bottom wall of the gate trench 431 can be alleviated.

[1051] By forming the third region 434c of the gate insulating layer 434 thickly, the breakdown voltage of the gate insulating layer 434 near the opening edge 432 of the gate trench 431 can be improved. In addition, by forming the third region 434c thickly, the third region 434c can be prevented from disappearing due to etching.

[1052] This can prevent the first region 434a from being removed by etching due to the disappearance of the third region 434c. As a result, the gate electrode layer 435 can be appropriately opposed to the SiC semiconductor layer 402 (body region 426) via the gate insulating layer 434.

[1053] The gate insulating layer 434 further includes a bulging portion 434d bulging into the gate trench 431 at the opening edge 432 of the gate trench 431. The bulging portion 434d is formed at a corner of the gate insulating layer 434 connecting the first region 434a and the third region 434c.

[1054] The bulging portion 434d extends in a curved shape toward the inside of the gate trench 431. The bulging portion 434d narrows the opening of the gate trench 431 at the opening edge portion 432 of the gate trench 431.

[1055] The bulge 434d can improve the dielectric breakdown voltage of the gate insulating layer 434 in the opening edge portion 432. Of course, the gate insulating layer 434 may be formed without the bulge 434d. The gate insulating layer 434 may also be formed to have a uniform thickness.

[1056] The gate electrode layer 435 is embedded in the gate trench 431 via the gate insulating layer 434. More specifically, the gate electrode layer 435 is embedded in the gate trench 431 so as to fill the concave space defined by the gate insulating layer 434. The gate electrode layer 435 is controlled by a gate voltage.

[1057] The gate electrode layer 435 is formed as a wall extending in a direction normal to the first main surface 403 of the SiC semiconductor layer 402 in a cross-sectional view perpendicular to the extending direction of the gate trench 431 . The gate electrode layer 435 has an upper end located on the opening side of the gate trench 431 .

[1058] The upper end portion of the gate electrode layer 435 is formed in a curved shape recessed toward the bottom wall of the gate trench 431 . The upper end portion of the gate electrode layer 435 has a constricted portion constricted along the bulged portion 434 d of the gate insulating layer 434 .

[1059] The cross-sectional area of ​​the gate electrode layer 435 (the cross-sectional area perpendicular to the direction in which the gate trench 431 extends) may be 0.05 μm 2 Above and 0.5μm 2 In the following, the cross-sectional area of ​​the gate electrode layer 435 is defined by the product of the depth of the gate electrode layer 435 and the width of the gate electrode layer 435 .

[1060] The depth of the gate electrode layer 435 is the distance from the upper end to the lower end of the gate electrode layer 435. The width of the gate electrode layer 435 is the width of the trench at a position midway between the upper end and the lower end of the gate electrode layer 435. When the upper end is a curved surface (in this embodiment, a curved shape that is concave toward the lower side), the position of the upper end of the gate electrode layer 435 is the middle position in the depth direction of the upper surface of the gate electrode layer 435.

[1061] The gate electrode layer 435 may also include conductive polysilicon. The gate electrode layer 435 may also include n-type polysilicon or p-type polysilicon, which are examples of conductive polysilicon. Instead of polysilicon, the gate electrode layer 435 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy.

[1062] Reference Figure 51 as well as Figure 53 A gate wiring layer 436 is formed in the active region 406. The gate wiring layer 436 is electrically connected to the gate pad 410 and the gate finger 411. Figure 53 , the gate wiring layer 436 is shown by hatching for clarity.

[1063] The gate wiring layer 436 is formed on the first main surface 403 of the SiC semiconductor layer 402 . More specifically, the gate wiring layer 436 is formed on the third region 434 c of the gate insulating layer 434 .

[1064] In this embodiment, the gate wiring layer 436 is formed along the gate finger 411. More specifically, the gate wiring layer 436 is formed along the three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to divide the inner region of the active region 406 into three directions.

[1065] The gate wiring layer 436 is connected to the gate electrode layer 435 exposed from the contact trench portion 431b of each gate trench 431. In this embodiment, the gate wiring layer 436 is formed by a lead portion extending from the gate electrode layer 435 to the first main surface 403 of the SiC semiconductor layer 402. The upper end of the gate wiring layer 436 is connected to the upper end of the gate electrode layer 435.

[1066] Reference Figure 51 、 Figure 52 as well as Figure 54 In the active region 406 , a plurality of source trenches 441 are formed in the first main surface 403 of the SiC semiconductor layer 402 . Each source trench 441 is formed in a region between two adjacent gate trenches 431 .

[1067] The plurality of source trenches 441 are formed in a band shape extending in the second direction Y. The plurality of source trenches 441 are formed in a stripe shape in a plan view. The distance between the center portions of adjacent source trenches 441 in the first direction X may be 1.5 μm or more and 3 μm or less.

[1068] Each source trench 441 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each source trench 441 is located in the SiC epitaxial layer 422. More specifically, the bottom wall of each source trench 441 is located in the high-concentration region 422a.

[1069] In this embodiment, the depth of the source trench 441 is greater than or equal to the depth of the gate trench 431. More specifically, the depth of the source trench 441 is greater than the depth of the gate trench 431. The bottom wall of the source trench 441 is located closer to the second main surface 404 of the SiC semiconductor layer 402 than the bottom wall of the gate trench 431.

[1070] The bottom wall of the source trench 441 is located between the bottom wall of the gate trench 431 and the low-concentration region 422 b . The bottom wall of the source trench 441 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402 .

[1071] The sidewalls of the source trench 441 may extend in the normal direction to the first main surface 403 of the SiC semiconductor layer 402 . That is, the sidewalls of the source trench 441 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402 .

[1072] The depth of the source trench 441 in the normal direction of the first main surface 403 of the SiC semiconductor layer 402 may be 0.5 μm or more and 10 μm or less (e.g., approximately 2 μm). The ratio of the depth of the source trench 441 to the depth of the gate trench 431 may be 1.5 or more. The ratio of the depth of the source trench 441 to the depth of the gate trench 431 is preferably 2 or more.

[1073] The width of the source trench 441 in the first direction may be substantially equal to the width of the gate trench 431 in the first direction. The width of the source trench 441 in the first direction may be greater than the width of the gate trench 431 in the first direction. The width of the source trench 441 in the first direction may be greater than or equal to 0.1 μm and less than or equal to 2 μm (e.g., approximately 0.5 μm).

[1074] A source insulating layer 442 and a source electrode layer 443 are formed in each source trench 441. Figure 51 , for clarity, the source insulating layer 442 and the source electrode layer 443 are shown by hatching.

[1075] The source insulating layer 442 may also include silicon oxide. The source insulating layer 442 is formed in a film shape along the inner wall surface of the source trench 441 so as to define a concave space in the source trench 441 .

[1076] The source insulating layer 442 includes a first region 442a and a second region 442b. The first region 442a is formed along the sidewalls of the source trench 441. The second region 442b is formed along the bottom wall of the source trench 441. The thickness T11 of the first region 442a is smaller than the thickness T12 of the second region 442b.

[1077] The ratio T12 / T11 of the thickness T12 of the second region 442b to the thickness T11 of the first region 442a may be 2 to 5. The thickness T11 of the first region 442a may be 0.01 μm to 0.2 μm. The thickness T12 of the second region 442b may be 0.05 μm to 0.5 μm.

[1078] The thickness T11 of the first region 442a may be substantially equal to the thickness T1 of the first region 434a of the gate insulating layer 434. The thickness T12 of the second region 442b may be substantially equal to the thickness T2 of the second region 434b of the gate insulating layer 434. Of course, the source insulating layer 442 may be formed to have a uniform...

Claims

1. A semiconductor device, characterized in that: include: a first conductivity type semiconductor layer having a first main surface on one side and a second main surface on the other side; A trench gate structure including a gate trench formed on the first main surface of the semiconductor layer, and a gate electrode buried in the gate trench via a gate insulating layer; A trench source structure, comprising a source trench formed on the first main surface of the semiconductor layer at a distance from the gate trench to be deeper than the gate trench, a source electrode buried in the source trench, and a well region of the second conductivity type formed in the semiconductor layer along the source trench, wherein the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 or more and 4.0 or less; a second conductivity type body region formed in a region between the gate trench and the source trench in a surface portion of the first main surface of the semiconductor layer; A source region of the first conductivity type formed in a surface portion of the body region; as well as a drain electrode connected to the second main surface of the semiconductor layer, The trench source structure further includes a barrier forming layer, the barrier forming layer being located between the source trench and the source electrode and having a potential barrier higher than a potential barrier between the well region and the source electrode. The barrier-forming layer includes an insulating barrier-forming layer formed of an insulating material. The insulating barrier forming layer includes a first portion covering a side wall of the source trench and a second portion connected to the first portion and covering a bottom wall of the source trench. The second portion covers a portion of the bottom wall of the source trench, leaving the remaining portion exposed.

2. The semiconductor device according to claim 1, wherein: The aspect ratio of the trench source structure is greater than the aspect ratio of the trench gate structure.

3. The semiconductor device according to claim 1, wherein: The aspect ratio of the trench source structure is greater than or equal to 0.5 and less than or equal to 18.

0.

4. The semiconductor device according to claim 1, wherein: In the semiconductor layer, a depletion layer extends from a boundary region between the semiconductor layer and the well region toward a region closer to the second main surface than a bottom wall of the gate trench.

5. The semiconductor device according to claim 4, wherein: The depletion layer overlaps with a bottom wall of the gate trench.

6. The semiconductor device according to claim 1, wherein: The well region is formed in a region of the semiconductor layer along a sidewall of the source trench.

7. The semiconductor device according to claim 1, wherein: The well region is formed in a region of the semiconductor layer along a bottom wall of the source trench.

8. The semiconductor device according to claim 1, wherein: The well region is continuously formed in the semiconductor layer along the sidewalls, the bottom wall, and the corner connecting the sidewalls and the bottom wall of the source trench.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The well region is connected to the body region.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that The barrier-forming layer further includes a conductive barrier-forming layer formed of a conductive material different from a conductive material of the source electrode.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that: The barrier-forming layer is formed along the sidewalls, the bottom wall, and the corner connecting the sidewalls and the bottom wall of the source trench.

12. The semiconductor device according to any one of claims 1 to 8, characterized in that: The method further includes a second conductivity type contact region, which is formed in a region of the semiconductor layer along a sidewall of the source trench and has a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the body region.

13. The semiconductor device according to any one of claims 1 to 8, characterized in that: It also includes a second conductivity type contact region, which is formed in the semiconductor layer along the bottom wall of the source trench and has a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the body region.

14. A semiconductor device, characterized in that: include: a first conductivity type semiconductor layer having a first main surface on one side and a second main surface on the other side; A trench gate structure including a gate trench having a first side wall and a first bottom wall and formed on the first main surface of the semiconductor layer, and a gate electrode buried in the gate trench via a gate insulating layer; A trench source structure comprising a source trench having a second side wall and a second bottom wall and formed on the first main surface of the semiconductor layer at a distance from the gate trench, a source electrode buried in the source trench, and a well region of a second conductivity type formed in the semiconductor layer in a region along the source trench; a second conductivity type body region formed in a region between the gate trench and the source trench in a surface portion of the first main surface of the semiconductor layer; A source region of the first conductivity type formed in a surface portion of the body region; as well as a drain electrode connected to the second main surface of the semiconductor layer, The second side wall of the source trench includes a first wall portion located on the first main surface side of the semiconductor layer relative to the first bottom wall of the gate trench, and a second wall portion located on the second main surface side of the semiconductor layer relative to the first bottom wall of the gate trench. The well region includes a first region formed along the first wall portion of the second side wall of the source trench, and a second region formed along the second wall portion of the second side wall of the source trench and having a length greater than that of the first region in a thickness direction of the semiconductor layer. The trench source structure further includes a barrier forming layer, the barrier forming layer being located between the source trench and the source electrode and having a potential barrier higher than a potential barrier between the well region and the source electrode. The barrier-forming layer includes an insulating barrier-forming layer formed of an insulating material. The insulating barrier forming layer includes a first portion covering the second side wall and a second portion connected to the first portion and covering the second bottom wall. The second portion covers a portion of the second bottom wall, leaving the remaining portion exposed.

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