Latch-up Immunity Technology for Integrated Circuits

Abstract

The present disclosure relates to latch-up immunity techniques for integrated circuits. For example, in integrated circuits supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a thermal n-well with an n-well band, wherein the n-well band is separated from the thermal n-well by a specified distance according to design rules. The n-well band is located between the thermal n-well and other n-wells or n-type diffusion structures.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 691,024, filed on June 28, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates generally to integrated circuits and, more particularly, to integrated circuit designs that provide improved immunity to latch-up. Background Art

[0004] Latch-up is an operating condition within an integrated circuit where a low impedance path is formed between a power node and a ground node, and a large current can flow through the low impedance path, causing damage to the integrated circuit. A triggering event (such as a current injection or an overvoltage condition) causes the low impedance path to form. Once formed, feedback causes the low impedance path to continue to be valid, even though the triggering event itself has dissipated. A cycle of power is usually required to eliminate the low impedance path.

[0005] Integrated circuits of the complementary metal oxide semiconductor (CMOS) type use n-channel transistors (nMOS) and p-channel transistors (pMOS) to form circuit functions. Inherent parasitic transistors and diodes are created near the PN junctions of these nMOS and pMOS transistors. These parasitic circuit structures can form PNPN thyristors (i.e., silicon controlled rectifiers—SCRs) that are triggered by current or voltage pulses applied to any of the input nodes, output nodes, or power supply nodes. A triggering event (such as an overshoot or undershoot outside of the normal operating voltage and / or current level) turns on the thyristor and allows current to pass through a low impedance path between the power supply and ground nodes.

[0006] Figure 1A cross section of a CMOS inverter circuit 10 is shown. A semiconductor well 12 (e.g., doped with an n-type dopant) is formed within a semiconductor substrate 14 (e.g., doped with a p-type dopant). A pMOS transistor 20 of the CMOS inverter circuit 10 is formed in and on the well 12 and includes a source region 22 and a drain region 24 doped with a p-type dopant, respectively, and an insulated gate electrode 26 located above a channel region between the source region 22 and the drain region 24. An nMOS transistor 30 of the CMOS inverter circuit 10 is formed in and on the substrate 14 and includes a source region 32 and a drain region 34 doped with an n-type dopant, respectively, and an insulated gate electrode 36 located above a channel region between the source region 32 and the drain region 34. The source region 22 is connected to a power supply node 40, and the source region 32 is connected to a ground node 42. The gate electrodes 26 and 36 are electrically connected together to form an input node 44 of the CMOS inverter circuit 10. Drain regions 24 and 34 are electrically connected together to form an output node 46 of CMOS inverter circuit 10 .

[0007] The pMOS transistor 20 forms a parasitic vertical PNP bipolar transistor 50 having an emitter at the p-type doped source and drain regions 22 and 24, a base at the n-type doped well 12, and a collector at the p-type doped substrate 14. The nMOS transistor 30 forms a parasitic lateral NPN bipolar transistor 52 having an emitter at the n-type doped source and drain regions 32 and 34, a base at the p-type doped substrate 14, and a collector at the n-type doped well 12. Figure 2 The equivalent circuit diagram of these parasitic structures is shown in Figure 2 Also shown are the resistance Rwell provided by the n-type doped well 12 between the power supply node 40 and the base of the PNP 50 and the resistance Rsub provided by the p-type doped substrate 14 between the ground node 42 and the base of the NPN 52 .

[0008] For example, the latch-up phenomenon may be triggered by a current pulse at the drain 24 of the pMOS transistor 20, which causes the PN junction between the drain 24 and the well 12 to become forward biased. If the current pulse is high enough (e.g., lasts long enough), the carriers injected into the substrate 14 cause an electric drop across the substrate resistance Rsub. Then, the bias across the PN junction between the substrate 14 and the drain 34 of the nMOS transistor 30 may become high enough to turn on the NPN transistor 52. Then, the collector current in the NPN transistor 52 flows into the base of the PNP transistor 50, causing the PNP transistor 50 to further turn on. At this point, the latch-up becomes self-sustaining due to the positive feedback. The only way to release the latch-up is to remove power from the power supply node 40.

[0009] As the number of nMOS and pMOS devices within an integrated circuit increases, the risk of latch-up also increases due to the creation of more parasitic bipolar transistors and associated PNPN thyristors. Making integrated circuits immune to latch-up is a key design goal. Known latch-up immunity techniques include: spacing of circuit elements, adding guard rings around specific circuit points, using substrate constraints and well taps, and controlling substrate doping. Summary of the invention

[0010] In one embodiment, an integrated circuit includes: a semiconductor substrate doped with a first conductivity type; a first semiconductor well doped with a second conductivity type within the semiconductor substrate (which includes: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad); a second semiconductor well doped with the second conductivity type within the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a ground node; a third semiconductor well doped with the second conductivity type within the semiconductor substrate; and a fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to the integrated circuit pad via a resistor; wherein the third semiconductor well is located within the semiconductor substrate between the first semiconductor well and the second semiconductor well.

[0011] In one embodiment, an integrated circuit includes: a semiconductor substrate doped with a first conductivity type; a first semiconductor well doped with a second conductivity type within the semiconductor substrate (which includes: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad); a second semiconductor well doped with the second conductivity type within the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to the integrated circuit pad through a resistor; and a fourth region heavily doped with the second conductivity type within the semiconductor substrate, wherein the fourth region is connected to a ground node; wherein the second semiconductor well is located within the semiconductor substrate between the fourth region and the first semiconductor well.

[0012] In one embodiment, an integrated circuit includes: a semiconductor substrate doped with a first conductivity type; a first semiconductor well doped with a second conductivity type within the semiconductor substrate (which includes: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to a first integrated circuit pad); a second semiconductor well doped with the second conductivity type within the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a second integrated circuit pad; a third semiconductor well doped with the second conductivity type within the semiconductor substrate; and a fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to the first integrated circuit pad via a resistor; wherein the third semiconductor well is located within the semiconductor substrate between the first semiconductor well and the second semiconductor well.

[0013] In one embodiment, an integrated circuit includes: a semiconductor substrate doped with a first conductivity type; a first semiconductor well doped with a second conductivity type within the semiconductor substrate (which includes: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to a first integrated circuit pad); a second semiconductor well doped with the second conductivity type within the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a second integrated circuit pad; a third semiconductor well doped with the second conductivity type within the semiconductor substrate; and a fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to a power supply node; wherein the third semiconductor well is located within the semiconductor substrate between the first semiconductor well and the second semiconductor well.

[0014] In one embodiment, an integrated circuit includes: a semiconductor substrate doped with a first conductivity type; a first semiconductor well doped with a second conductivity type within the semiconductor substrate (which includes: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad); a second semiconductor well doped with the second conductivity type within the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a ground node; a third semiconductor well doped with the second conductivity type within the semiconductor substrate; and a fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to a power supply node; wherein the third semiconductor well is located within the semiconductor substrate between the first semiconductor well and the second semiconductor well. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0016] Figure 1 is a cross-sectional view of an integrated circuit implementation of a CMOS inverter;

[0017] Figure 2 yes Figure 1 Schematic diagram of an equivalent circuit showing the parasitic bipolar transistor forming a thyristor;

[0018] Figure 3 is a cross-sectional view of an integrated circuit;

[0019] Figure 4 yes Figure 3 Schematic diagram of an equivalent circuit showing a parasitic bipolar transistor forming a thyristor immune to latch-up;

[0020] Figure 5 is a cross-sectional view of an integrated circuit;

[0021] Figure 6 yes Figure 5 Schematic diagram of an equivalent circuit showing a parasitic bipolar transistor forming a thyristor immune to latch-up;

[0022] Figure 7 is a cross-sectional view of an integrated circuit;

[0023] Figure 8 yes Figure 7 Schematic diagram of an equivalent circuit showing a parasitic bipolar transistor forming a thyristor immune to latch-up;

[0024] Fig. 9 is a cross-sectional view of an integrated circuit;

[0025] Fig.10 yes Fig. 9 Schematic diagram of an equivalent circuit showing a parasitic bipolar transistor forming a thyristor immune to latch-up;

[0026] Fig.11 is a cross-sectional view of an integrated circuit;

[0027] Fig.12 yes Fig.11 Schematic diagram of an equivalent circuit showing a parasitic bipolar transistor forming a thyristor immune to latch-up;

[0028] Fig.13 is a cross-sectional view of an integrated circuit; and

[0029] Fig.14 yes Fig.13 Schematic diagram of an equivalent circuit showing the parasitic bipolar transistor forming a thyristor immune to latch-up.

[0030] It will be appreciated that the cross-sectional views are not drawn to scale. DETAILED DESCRIPTION

[0031] Reference now Figure 3 , which shows a cross section of an integrated circuit 100 that incorporates design techniques and structures for providing latch-up immunity. The integrated circuit 100 includes an n-type doped well 102 located within a p-type doped substrate 104. The well 102 is referred to herein as a "hot n-well," which is defined in this example as an n-type doped well that includes a heavily doped p-type region 108 that forms a source / drain region of a pMOS transistor that is directly connected to an integrated circuit pad (Pad). A hot n-well can also be defined as a bulk of a PMOS transistor whose drain is directly connected to an integrated circuit pad or a base of a PNP transistor whose emitter is connected to an integrated circuit pad. The well 102 also includes a heavily doped n-type region 106 that is connected to a power supply node Vdd. For example, the heavily doped n-type region 106 can form a guard ring structure surrounding the heavily doped p-type region 108. The heavily doped p-type region 108 can be isolated from the heavily doped n-type region 106 by a shallow trench isolation (STI) structure 116.

[0032] The circuit 100 also includes a heavily doped p-type region 120 located within the p-type doped substrate 104 to form a connection to a ground node (Gnd) through a resistance Rmetal formed due to the inherent resistance of the metallization layer of the integrated circuit. For example, the heavily doped p-type region 120 can form a guard ring structure around the well 102. The heavily doped p-type region 120 can be isolated from the heavily doped n-type region 106 by the STI structure 116.

[0033] The heavily doped n-type region 124 within the p-type doped substrate 104 is also connected to the ground node Gnd. The heavily doped n-type region 124 may be isolated from the heavily doped p-type region 120 by the STI structure 116.

[0034] Circuit 100 also includes an n-type doped well 130 including a heavily doped n-type region 132 to form a connection to a ground node Gnd. Well 130 is referred to herein as a “grounded n-well.” Heavily doped n-type region 132 may be isolated from heavily doped p-type region 120 by STI structure 116 .

[0035] To provide latch-up immunity, heavily doped n-type region 124 is spaced from well 102 by a distance A specified by a design rule controlling the spacing between heavily doped n-type regions in a p-type substrate and a thermal n-well. In addition, n-type doped well 130 is spaced from well 102 by a distance B specified by a design rule controlling the spacing between any n-well in a p-type substrate and a thermal n-well. As an example, for a given voltage greater than or equal to a threshold from Pad or Vdd to Gnd, distances A and B are set to ensure a high impedance state of the PNPN thyristor and reduce the gain of the parasitic bipolar transistor.

[0036] Latch-up immunity is further enhanced by enclosing the heavily doped p-type region 108 within the n-well 102 with a double guard ring formed by the heavily doped n-type region 106 within the well 102 and the heavily doped p-type region 120 within the p-doped substrate 104 .

[0037] exist Figure 4 An equivalent circuit diagram of a parasitic structure presented by integrated circuit 100 is shown in FIG.

[0038] The spacing requirements of distance A and distance B have an adverse effect on the area occupied by the integrated circuit 100. In order to provide the necessary latch-up immunity, the area occupied by these integrated circuits must be increased to support the minimum spacing requirements and guard ring structures required by the design rules. Figure 3 The latch-up immunity of the circuit configuration shown would be advantageous.

[0039] Reference now Figure 5 , Figure 5 A cross section of an integrated circuit 200 incorporating design techniques and structures for providing latch-up immunity is shown. The integrated circuit 200 includes an n-type doped well 202 located within a p-type doped substrate 204. The well 202 is referred to herein as a "hot n-well," which is defined in this example as an n-type doped well that includes a heavily doped p-type region 208 that forms a source / drain region of a pMOS transistor that is directly connected to an integrated circuit pad (Pad). A hot n-well may also be defined as a bulk of a PMOS transistor whose drain is directly connected to an integrated circuit pad or a base of a PNP transistor whose emitter is connected to an integrated circuit pad. The well 202 also includes a heavily doped n-type region 206 that is connected to a power supply node Vdd. For example, the heavily doped n-type region 206 may form a guard ring structure surrounding the heavily doped p-type region 208. The heavily doped p-type region 208 may be isolated from the heavily doped n-type region 206 by a shallow trench isolation (STI) structure 216.

[0040] The circuit 200 also includes a heavily doped p-type region 220 located within the p-type doped substrate 204 to form a connection to a ground node (Gnd) through a resistance Rmetal1 formed by the inherent resistance of the metallization layer. For example, the heavily doped p-type region 220 can form a guard ring structure around the well 202. The heavily doped p-type region 220 can be separated from the heavily doped n-type region 206 by an STI structure 216.

[0041] The heavily doped n-type region 224 within the p-type doped substrate 204 is also connected to the ground node Gnd.

[0042] Circuit 200 also includes an n-type doped well 230, which includes a heavily doped n-type region 232 to form a connection to a ground node Gnd. Well 230 is referred to herein as a "grounded n-well."

[0043] Circuit 200 also includes a first n-type doped well 240, which includes a heavily doped n-type region 242 to form a connection with an integrated circuit pad (Pad) through a resistor Rmetal2. In one embodiment, resistor Rmetal2 may have a resistance value of 20-50Ohm (which may vary with design and technical limitations), wherein the resistance of Rmetal1 may be, for example, in the range of 1-20Ohm. Well 240 is referred to as an "n-well strip" herein. Well 240 and its heavily doped n-type region 242 are located between well 202 and well 230 and may be isolated from heavily doped p-type region 220 by STI structure 216. The lateral width D of well 240 is set by design rules and is separated from each of well 202 and well 230 by a design-specific spacing E between adjacent n-wells set by the design rules.

[0044] The circuit 200 also includes a second n-type doped well 250, which includes a heavily doped n-type region 252 to form a connection with an integrated circuit pad (Pad) through a resistor Rmetal2. The well 250 is referred to herein as an "n-well strip". The heavily doped n-type region 252 can be isolated from the heavily doped p-type region 220 and the heavily doped n-type region 224 by the STI structure 216, and is located between the well 202 and the heavily doped n-type region 224. The well 250 has a lateral width D set by the design rules, and is separated from the well 202 by a design-specific spacing E between adjacent n-wells set by the design rules, and is further separated from the heavily doped n-type region 224 by a design-specific spacing F between an n-well and a heavily doped n-type region in a p-type substrate set by the design rules.

[0045] The circuit 200 also includes a heavily doped p-type region 260 located within the p-type doped substrate 204 to form a connection to a ground node (Gnd) through a resistance Rmetal1 formed by the inherent resistance of the metallization layer. The heavily doped p-type region is located between the wells 230 and 240 and can be isolated from both the heavily doped n-type region 232 and the heavily doped n-type region 242 by the STI structure 216.

[0046] The circuit 200 also includes a heavily doped p-type region 270 located within the p-type doped substrate 204 to form a connection to a ground node (Gnd) through a resistance Rmetal1 formed by the inherent resistance of the metallization layer. The heavily doped p-type region is located between the well 250 and the heavily doped n-type region 224 and can be isolated from both the heavily doped n-type region 252 and the heavily doped n-type region 224 by the STI structure 216.

[0047] The n-well strip that provides electrical connection to the integrated circuit pad (Pad) through resistor Rmetal2 provides the necessary latch-up immunity by isolating the bipolar transistors from each other and thereby preventing regeneration. The advantage of circuit 200 over circuit 100 is that the distance A' separated from the well 202 by the heavily doped n-type region 224 is less than the distance A, where A'=E+D+F. In addition, the distance B' separated from the well 202 by the n-type doped well 230 is less than the distance B, where B'=2*E+D. As a result, circuit 200 will occupy a smaller area than circuit 100 while still providing the necessary latch-up immunity. For example, for a first voltage from Pad or Vdd to Gnd, the area of ​​circuit 200 is 37% smaller than the area of ​​circuit 100, and for a second voltage from Pad or Vdd to Gnd, the area of ​​circuit 200 is 68% smaller than the area of ​​circuit 100, where the second voltage is greater than the first voltage. Other advantages of circuit 200 over circuit 100 include: there is no voltage dependency in the design structure (meaning that the spacing between adjacent n-wells does not need to change based on the voltage amplitude), and the effectiveness of latch-up immunity no longer depends on the efficiency of the double guard ring formed by the heavily doped n-type region 206 within the well 202 and the heavily doped p-type region 220 within the p-type doped substrate 204.

[0048] In one embodiment, the first n-type doped well 240 and the second n-type doped well 250 may be connected and form a well ring around the well 202 and separated therefrom by a minimum distance E. Then, the heavily doped n-type regions 242 and 252 will also be connected and form a guard ring. However, it should be understood that it is not necessary to form a ring structure with the wells 240 and 250, and in some circuit implementations, only the n-type doped well 240 with the heavily doped n-type region 242 is required because the latch-up problem mainly exists on the left side of the circuit.

[0049] exist Figure 6 An equivalent circuit schematic diagram of a parasitic structure exhibited by integrated circuit 200 is shown.

[0050] Reference now Figure 7 , Figure 7A cross section of an integrated circuit 400 is shown, which is combined with design techniques and structures for providing latch-up immunity. The integrated circuit 400 includes an n-type doped well 402 located in a p-type doped substrate 404. The well 402 is referred to herein as a "hot n-well", which is defined in this example as an n-type doped well, including a heavily doped p-type region 408 that forms a source / drain region of a pMOS transistor directly connected to a first integrated circuit pad (Pad1). The hot n-well can also be defined as a bulk of a PMOS transistor with a drain directly connected to the integrated circuit pad or a base of a PNP transistor with an emitter directly connected to the first integrated circuit pad (Pad1). The well 402 also includes a heavily doped n-type region 406 connected to a power supply node Vdd. For example, the heavily doped n-type region 406 can form a guard ring structure surrounding the heavily doped p-type region 408. The heavily doped p-type region 408 can be isolated from the heavily doped n-type region 406 by a shallow trench isolation (STI) structure 416.

[0051] The circuit 400 also includes a heavily doped p-type region 420 located within the p-type doped substrate 404 to form a connection to a ground node (Gnd) through a resistance Rmetal formed by the inherent resistance of the metallization layer. For example, the heavily doped p-type region 420 can form a guard ring structure around the well 402. The heavily doped p-type region 420 can be isolated from the heavily doped n-type region 406 by the STI structure 416.

[0052] Circuit 400 also includes an n-type doped well 430 including a heavily doped n-type region 432 to form a connection with a second integrated circuit pad (Pad2). Well 430 is referred to herein as an "emitter n-well". Well 430 and heavily doped n-type region 432 may be isolated from heavily doped p-type region 420 by STI structure 416.

[0053] To provide latch-up immunity, n-type doped well 430 is spaced a distance C from well 402, which is specified by the design rules for any n-type well and thermal n-well in a p-type substrate. As an example, for a given voltage greater than or equal to the threshold from Pad or Vdd to Gnd, distance C is set to ensure a high impedance state of the PNPN thyristor and reduce the gain of the parasitic bipolar transistor.

[0054] Latch-up immunity is enhanced by enclosing the heavily doped p-type region 408 in the well 402 with a double guard ring formed by the heavily doped n-type region 406 in the well 402 and the heavily doped p-type region 420 in the p-type doped substrate 404 .

[0055] exist Figure 8 An equivalent circuit diagram of a parasitic structure presented by integrated circuit 400 is shown in FIG.

[0056] The spacing requirement of distance C has an adverse effect on the area occupied by the integrated circuit 400. In order to provide the necessary latch-up immunity, the area occupied by these integrated circuits must be increased to support the minimum spacing requirements and guard ring structures required by the design rules. Figure 7 The latch-up immunity of the circuit configuration shown is advantageous.

[0057] Reference now Fig. 9 , Fig. 9 A cross section of an integrated circuit 500 incorporating design techniques and structures for providing latch-up immunity is shown. The integrated circuit 500 includes an n-type doped well 502 located within a p-type doped substrate 504. The well 502 is referred to herein as a "hot n-well," which is defined in this example as an n-type doped well, containing a heavily doped p-type region 508 forming a source / drain region of a pMOS transistor directly connected to a first integrated circuit pad (Pad1). A hot n-well may also be defined as a bulk of a PMOS transistor having a drain directly connected to an integrated circuit pad or a base of a PNP transistor having an emitter connected to a first integrated circuit pad (Pad1). The well 502 also includes a heavily doped n-type region 506 connected to a power supply node Vdd. For example, the heavily doped n-type region 506 may form a guard ring structure surrounding the heavily doped p-type region 508. The heavily doped p-type region 508 may be isolated from the heavily doped n-type region 506 by a shallow trench isolation (STI) structure 516.

[0058] The circuit 500 also includes a heavily doped p-type region 520 located within the p-type doped substrate 504 to form a connection to a ground node (Gnd) through a resistance Rmetal1 formed by the inherent resistance of the metallization layer. For example, the heavily doped p-type region 520 can form a guard ring structure around the well 502. The heavily doped p-type region 520 can be isolated from the heavily doped n-type region 506 by the STI structure 516.

[0059] Circuit 500 also includes an n-type doped well 530, which includes a heavily doped n-type region 532 to form a connection to a second integrated circuit pad (Pad2). Well 530 is referred to herein as an "emitter n-well."

[0060] Circuit 500 also includes a first n-type doped well 540, which includes a heavily doped n-type region 542 to form a connection with a first integrated circuit pad (Pad1) through a resistor Rmetal2. In one embodiment, resistor Rmetal2 may have a resistance value of 20-50Ohm (which may vary with design and technical limitations), wherein resistor Rmetal1 may be in the range of 1-20Ohm. Well 540 is referred to as an "n-well strip" herein. Well 540 and its heavily doped n-type region 542 are located between well 502 and well 530, and may be isolated from heavily doped p-type region 520 by STI structure 516. The lateral width D of well 540 is set by design rules, and is separated from each of wells 502 and 530 by a design-specific spacing E between adjacent n-wells set by design rules.

[0061] Circuit 500 also includes a second n-type doped well 550, which includes a heavily doped n-type region 552 to form a connection to the first integrated circuit pad (Pad1) through resistor Rmetal2. Well 550 is referred to herein as an "n-well strip". Well 550 and its heavily doped n-type region 552 can be isolated from heavily doped p-type region 520 by STI structure 516. Well 550 is separated from well 502 by a design-specific spacing E between adjacent n-wells set by design rules.

[0062] The circuit 500 also includes a heavily doped p-type region 560 located within the p-type doped substrate 504 to form a connection to a ground node (Gnd) through a resistance Rmetal1 formed by the inherent resistance of the metallization layer. The heavily doped p-type region 560 is located between the n-well 530 and the n-well 540 and is isolated from each of the heavily doped n-type region 532 and the heavily doped n-type region 542 by the STI structure 516.

[0063] The n-well strap that provides electrical connection to the first integrated circuit pad (Pad1) through resistor Rmetal2 provides the necessary latch-up immunity by isolating the bipolar transistors from each other and thereby preventing regeneration. An advantage of circuit 500 over circuit 400 is that the distance C' separating n-well 530 from n-well 502 is less than the distance C, where C' = 2*E+D. As a result, circuit 500 will occupy a smaller area than circuit 400 while still providing the necessary latch-up immunity. For example, for a first voltage from Pad1 or Vdd to Pad2, the area of ​​circuit 500 is 70% smaller than the area of ​​circuit 400, and for a second voltage from Pad1 or Vdd to Pad2, the area of ​​circuit 500 is 81% smaller than the area of ​​circuit 400, where the second voltage is greater than the first voltage. Other advantages of circuit 500 over circuit 400 include: there is no voltage dependency in the design structure (meaning that the spacing between adjacent n-wells does not vary with voltage amplitude), and the effectiveness of latch-up immunity no longer depends on the efficiency of the double guard ring formed by the heavily doped n-type region 506 within the well 502 and the heavily doped p-type region 520 within the p-doped substrate 504.

[0064] In one embodiment, the first n-type doped well 540 and the second n-type doped well 550 can be connected and form a well ring around the well 502 and separated from the well 502 by a minimum distance E. Then, the heavily doped n-type regions 542 and 552 will also be connected and form a guard ring. However, it should be understood that it is not necessary to form a ring structure using wells 540 and 550.

[0065] exist Fig.10 An equivalent circuit schematic of the parasitic structures exhibited by integrated circuit 500 is shown.

[0066] Reference now Fig.11 , Fig.11 A cross section of an integrated circuit 600 incorporating design techniques and structures for providing latch-up immunity is shown. The integrated circuit 600 includes an n-type doped well 602 located within a p-type doped substrate 604. The well 602 is referred to herein as a "hot n-well," which is defined in this example as an n-type doped well, containing a heavily doped p-type region 608 forming a source / drain region of a pMOS transistor directly connected to a first integrated circuit pad (Pad1). A hot n-well may also be defined as a bulk of a PMOS transistor having a drain directly connected to an integrated circuit pad or a base of a PNP transistor having an emitter connected to an integrated circuit pad. The well 602 also includes a heavily doped n-type region 606 connected to a power supply node Vdd. For example, the heavily doped n-type region 606 may form a guard ring structure surrounding the heavily doped p-type region 608. The heavily doped p-type region 608 may be isolated from the heavily doped n-type region 606 by a shallow trench isolation (STI) structure 616.

[0067] The circuit 600 also includes a heavily doped p-type region 620 located within the p-type doped substrate 604 to form a connection to a ground node (Gnd) through a resistance Rmetal formed by the inherent resistance of the metallization layer. For example, the heavily doped p-type region 620 can form a guard ring structure around the well 602. The heavily doped p-type region 620 can be isolated from the heavily doped n-type region 606 by the STI structure 616.

[0068] Circuit 600 also includes an n-type doped well 630, which includes a heavily doped n-type region 632 to form a connection to a second integrated circuit pad (Pad2). Well 630 is referred to herein as an "emitter n-well."

[0069] Circuit 600 also includes a first n-type doped well 640, which includes a heavily doped n-type region 642 to form a connection with a power supply node Vdd. Well 640 is referred to herein as an "n-well strip". Well 640 and its heavily doped n-type region 642 are located between well 602 and well 630. The heavily doped n-type region 642 can be isolated from the heavily doped p-type region 620 by STI structure 616. Well 640 has a lateral width D set by design rules and is separated from each of well 602 and well 630 by a design-specific spacing E between the n-well and the thermal n-well set by the design rules.

[0070] Circuit 600 also includes a second n-type doped well 650, which includes a heavily doped n-type region 652 to form a connection to the power supply node Vdd. Well 650 is referred to herein as an "n-well strip". The heavily doped n-type region 652 can be isolated from the heavily doped p-type region 620 by the STI structure 616. Well 650 is separated from well 602 by a design-specific spacing E between the n-well and the thermal n-well set by the design rules.

[0071] The circuit 600 may further include a heavily doped p-type region 660 located within the p-type doped substrate 604 to form a connection to a ground node (Gnd) through a resistance Rmetal formed by the inherent resistance of the metallization layer. The heavily doped p-type region 660 is located between the n-well 630 and the n-well 640 and is isolated from each of the heavily doped n-type region 632 and the heavily doped n-type region 642 by the STI structure 616.

[0072] The n-well strip that provides electrical connection to the power supply node Vdd provides the necessary latch-up immunity by isolating the bipolar transistors from each other and thereby preventing regeneration. An advantage of circuit 600 over circuit 400 is that the distance C' separating n-well 630 from n-well 602 is less than the distance C, where C'=2*E+D. As a result, circuit 600 will occupy a smaller area than circuit 400 while still providing the necessary latch-up immunity. For example, for a first voltage from Pad1 or Vdd to Pad2, the area of ​​circuit 600 is 55% smaller than the area of ​​circuit 400, and for a second voltage from Pad1 or Vdd to Pad2, the area of ​​circuit 600 is 73% smaller than the area of ​​circuit 400, where the second voltage is greater than the first voltage. Other advantages of circuit 600 over circuit 400 include: there is no voltage dependency in the design structure (meaning that the spacing between adjacent n-wells does not vary with voltage amplitude), and the effectiveness of latch-up immunity no longer depends on the efficiency of the double guard ring formed by the heavily doped n-type region 606 within the well 602 and the heavily doped p-type region 620 within the p-type doped substrate 604.

[0073] In one embodiment, the first n-type doped well 640 and the second n-type doped well 650 may be connected and form a well ring around the well 602 and separated from the well 602 by a design-specific distance E. Then, the heavily doped n-type regions 642 and 652 will also be connected and form a guard ring. However, it should be understood that it is not necessary to form a ring structure using wells 640 and 650, and in some circuit implementations, since the latch-up problem mainly exists on the left side of the circuit, only the n-type doped well 640 with the heavily doped n-type region 642 is required.

[0074] exist Fig.12 An equivalent circuit diagram of the parasitic structure presented by the integrated circuit 600 is shown in FIG.

[0075] Reference now Fig.13 , Fig.13A cross section of an integrated circuit 700 incorporating design techniques and structures for providing latch-up immunity is shown. The integrated circuit 700 includes an n-type doped well 702 located within a p-type doped substrate 704. The well 702 is referred to herein as a "hot n-well," which is defined in this example as an n-type doped well, containing a heavily doped p-type region 708 forming a source / drain region of a pMOS transistor directly connected to an integrated circuit pad (Pad). A hot n-well may also be defined as a bulk of a PMOS transistor having a drain directly connected to an integrated circuit pad or a base of a PNP transistor having an emitter connected to an integrated circuit pad (Pad). The well 702 also includes a heavily doped n-type region 706 connected to a power supply node Vdd. For example, the heavily doped n-type region 706 may form a guard ring structure surrounding the heavily doped p-type region 708. The heavily doped p-type region 708 may be isolated from the heavily doped n-type region 706 by a shallow trench isolation (STI) structure 716.

[0076] The circuit 700 also includes a heavily doped p-type region 720 located within the p-type doped substrate 704 to form a connection to a ground node (Gnd) through a resistance Rmetal formed by the inherent resistance of the metallization layer. For example, the heavily doped p-type region 720 can form a guard ring structure around the well 702. The heavily doped p-type region 720 can be isolated from the heavily doped n-type region 706 by the STI structure 716.

[0077] Circuit 700 also includes an n-type doped well 730, which includes a heavily doped n-type region 732 to form a connection to a ground node (Gnd). Well 730 is referred to herein as a "grounded n-well."

[0078] Circuit 700 also includes a first n-type doped well 740, which includes a heavily doped n-type region 742 to form a connection with a power supply node Vvdd. Well 740 is referred to herein as an "n-well strip". Well 740 and its heavily doped n-type region 742 are located between well 702 and well 730. The heavily doped n-type region 742 can be isolated from the heavily doped p-type region 720 by STI structure 716. Well 740 has a lateral width D set by design rules and is separated from each of well 792 and well 730 by a design-specific spacing E between an n-well and a hot n-well or a ground n-well set by design rules.

[0079] Circuit 700 also includes a second n-type doped well 750, which includes a heavily doped n-type region 752 to form a connection to the power supply node Vdd. Well 750 is referred to herein as an "n-well strip". Well 750 and its heavily doped n-type region 752 can be isolated from heavily doped p-type region 720 by STI structure 716. Well 750 is separated from well 702 by a design-specific spacing E between the n-well and the thermal n-well set by the design rules.

[0080] The circuit 700 may further include a heavily doped p-type region 760 located within the p-type doped substrate 704 to form a connection to a ground node (Gnd) through a resistance Rmetal formed by an intrinsic resistance of the metallization layer. The heavily doped p-type region 760 is located between the n-well 730 and the n-well 740 and is isolated from each of the heavily doped n-type region 732 and the heavily doped n-type region 742 by the STI structure 716.

[0081] The n-well strip that provides electrical connection to the power supply node Vdd provides the necessary latch-up immunity by isolating the bipolar transistors from each other and thereby preventing regeneration. An advantage of circuit 700 over circuit 100 is that the distance C' separating n-well 730 from n-well 702 is less than the distance C, where C'=2*E+D. As a result, circuit 700 will occupy a smaller area than circuit 100 while still providing the necessary latch-up immunity. For example, for a first voltage from Pad or Vdd to Gnd, the area of ​​circuit 700 is 25% smaller than the area of ​​circuit 100, and for a second voltage from Pad or Vdd to Gnd, the area of ​​circuit 700 is 60% smaller than the area of ​​circuit 100, where the second voltage is greater than the first voltage. Other advantages of circuit 700 over circuit 100 include: there is no voltage dependency in the design structure (meaning that the spacing between adjacent n-wells does not change with voltage amplitude), and the effectiveness of latch-up immunity no longer depends on the efficiency of the double guard ring formed by the heavily doped n-type region 706 within the well 702 and the heavily doped p-type region 720 within the p-type doped substrate 704.

[0082] In one embodiment, the first n-type doped well 740 and the second n-type doped well 750 may be connected and form a well ring around the well 702, and separated from the well 702 by a specific design distance E. Then, the heavily doped n-type regions 742 and 752 will also be connected and form a guard ring. However, it should be understood that it is not necessary to form a ring structure using wells 740 and 750, and in some circuit implementations, since the latch-up problem mainly exists on the left side of the circuit, only the n-type doped well 740 with the heavily doped n-type region 742 is required.

[0083] exist Fig.14 An equivalent circuit diagram of a parasitic structure presented by integrated circuit 700 is shown in FIG.

[0084] Although the present invention has been shown and described in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Various modifications to the disclosed embodiments may be understood and effected by those skilled in the art in practicing the described invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. An integrated circuit, comprising: a semiconductor substrate doped with a first conductivity type; A first semiconductor well is doped with a second conductivity type in the semiconductor substrate and comprises: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad; a second semiconductor well doped with the second conductivity type in the semiconductor substrate; a third region heavily doped with the second conductivity type in the second semiconductor well, wherein the third region is connected to a ground node; a third semiconductor well doped with the second conductivity type in the semiconductor substrate; and a fourth region heavily doped with the second conductivity type in the third semiconductor well, wherein the fourth region is connected to the integrated circuit pad via a resistor; The third semiconductor well is located in the semiconductor substrate between the first semiconductor well and the second semiconductor well.

2. The integrated circuit of claim 1, wherein the third semiconductor well is laterally spaced from the first semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

3. The integrated circuit of claim 1, wherein the third semiconductor well is laterally spaced from the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

4. The integrated circuit of claim 1 , wherein the third semiconductor well is laterally separated from each of the first semiconductor well and the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit. The integrated circuit of claim 1 , wherein the third semiconductor well surrounds the first semiconductor well. The integrated circuit of claim 1 , wherein the third semiconductor well does not surround the first semiconductor well.

7. The integrated circuit of claim 1 , further comprising: A fifth region is heavily doped with the first conductivity type in the semiconductor substrate, and the fifth region is located between the first semiconductor well and the third semiconductor well. The integrated circuit of claim 7 , wherein the fifth region surrounds the first semiconductor well.

9. The integrated circuit of claim 7, wherein the fifth region is connected to the ground node through a metallization layer having an intrinsic metallization resistance. 10 . The integrated circuit of claim 7 , wherein the fifth region is isolated from both the first region and the fourth region by shallow trench isolation.

11. The integrated circuit of claim 7, further comprising: A sixth region is heavily doped with the second conductivity type in the semiconductor substrate, and the third semiconductor well is located between the sixth region and the fifth region. 12 . The integrated circuit of claim 11 , wherein the sixth region is connected to the ground node.

13. The integrated circuit of claim 1, wherein the first region surrounds the second region.

14. The integrated circuit of claim 11, further comprising: A seventh region is heavily doped with the first conductivity type in the semiconductor substrate, and the seventh region is located between the fourth region and the sixth region.

15. The integrated circuit of claim 14, wherein the seventh region is connected to the ground node through a metallization layer having an intrinsic metallization resistance. 16 . The integrated circuit of claim 14 , wherein the seventh region is isolated from both the fourth region and the sixth region by shallow trench isolation.

17. The integrated circuit of claim 1, further comprising: An eighth region is heavily doped with the first conductivity type in the semiconductor substrate, and the eighth region is located between the third semiconductor well and the second semiconductor well.

18. The integrated circuit of claim 17, wherein the eighth region is connected to the ground node through a metallization layer having an intrinsic metallization resistance.

19. The integrated circuit of claim 17, wherein the eighth region is isolated from both the third region and the fourth region by shallow trench isolation.

20. An integrated circuit comprising: a semiconductor substrate doped with a first conductivity type; A first semiconductor well is doped with a second conductivity type in the semiconductor substrate and comprises: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad; a second semiconductor well doped with the second conductivity type in the semiconductor substrate; a third region heavily doped with the second conductivity type in the second semiconductor well, wherein the third region is connected to the integrated circuit pad via a resistor; and a fourth region heavily doped with the second conductivity type in the semiconductor substrate, wherein the fourth region is connected to a ground node; The second semiconductor well is located in the semiconductor substrate between the fourth region and the first semiconductor well. The integrated circuit of claim 20 , wherein the fourth region is connected to a ground node.

22. The integrated circuit of claim 20, wherein the second semiconductor well is laterally spaced from the first semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

23. The integrated circuit of claim 20, wherein the second semiconductor well surrounds the first semiconductor well.

24. The integrated circuit of claim 20, wherein the second semiconductor well does not surround the first semiconductor well.

25. The integrated circuit of claim 20, further comprising: A fifth region is heavily doped with the first conductivity type in the semiconductor substrate, and the fifth region is located between the first semiconductor well and the second semiconductor well.

26. The integrated circuit of claim 25, wherein the fifth region surrounds the first semiconductor well.

27. The integrated circuit of claim 25, wherein the fifth region is connected to the ground node through a metallization layer having a metallization resistance.

28. The integrated circuit of claim 25, wherein the fifth region is isolated from the first region and the third region by shallow trench isolation.

29. The integrated circuit of claim 20, wherein the first region surrounds the second region.

30. The integrated circuit of claim 20, further comprising: A sixth region is heavily doped with the first conductivity type in the semiconductor substrate, and the sixth region is located between the third region and the fourth region.

31. The integrated circuit of claim 30, wherein the sixth region is connected to the ground node through a metallization layer having an intrinsic metallization resistance.

32. The integrated circuit of claim 30, wherein the sixth region is isolated from both the third region and the fourth region by shallow trench isolation.

33. An integrated circuit comprising: a semiconductor substrate doped with a first conductivity type; A first semiconductor well is doped with a second conductivity type in the semiconductor substrate and comprises: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to a first integrated circuit pad; a second semiconductor well doped with the second conductivity type in the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a second integrated circuit pad; a third semiconductor well doped with the second conductivity type in the semiconductor substrate; and a fourth region heavily doped with the second conductivity type in the third semiconductor well, wherein the fourth region is connected to the first integrated circuit pad via a resistor; The third semiconductor well is located in the semiconductor substrate between the first semiconductor well and the second semiconductor well.

34. The integrated circuit of claim 33, wherein the third semiconductor well is laterally spaced from the first semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

35. The integrated circuit of claim 33, wherein the third semiconductor well is laterally spaced from the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

36. The integrated circuit of claim 33, wherein the third semiconductor well is laterally separated from each of the first semiconductor well and the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

37. The integrated circuit of claim 33, wherein the third semiconductor well surrounds the first semiconductor well.

38. The integrated circuit of claim 33, wherein the third semiconductor well does not surround the first semiconductor well.

39. The integrated circuit of claim 33, further comprising: A fifth region is heavily doped with the first conductivity type in the semiconductor substrate, and the fifth region is located between the first semiconductor well and the third semiconductor well.

40. The integrated circuit of claim 39, wherein the fifth region surrounds the first semiconductor well.

41. The integrated circuit of claim 39, wherein the fifth region is connected to a ground node through a metallization layer having an intrinsic metallization resistance.

42. The integrated circuit of claim 39, wherein the fifth region is isolated from the first region and the fourth region by shallow trench isolation.

43. The integrated circuit of claim 33, further comprising: A sixth region is heavily doped with the first conductivity type in the semiconductor substrate, and the sixth region is located between the second semiconductor well and the third semiconductor well.

44. The integrated circuit of claim 43, wherein the sixth region is connected to a ground node through a further metallization layer having an intrinsic metallization resistance.

45. The integrated circuit of claim 43, wherein the sixth region is isolated from each of the third region and the fourth region by shallow trench isolation.

46. ​​The integrated circuit of claim 33, wherein the first region surrounds the second region.

47. An integrated circuit comprising: a semiconductor substrate doped with a first conductivity type; A first semiconductor well is doped with a second conductivity type in the semiconductor substrate and comprises: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to a first integrated circuit pad; a second semiconductor well doped with the second conductivity type in the semiconductor substrate; a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a second integrated circuit pad; a third semiconductor well doped with the second conductivity type in the semiconductor substrate; and a fourth region heavily doped with the second conductivity type in the third semiconductor well, wherein the fourth region is connected to a power node; The third semiconductor well is located in the semiconductor substrate between the first semiconductor well and the second semiconductor well.

48. The integrated circuit of claim 47, wherein the third semiconductor well is laterally spaced from the first semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

49. The integrated circuit of claim 47, wherein the third semiconductor well is laterally spaced from the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

50. The integrated circuit of claim 47, wherein the third semiconductor well is laterally separated from each of the first semiconductor well and the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by design rules for the integrated circuit.

51. The integrated circuit of claim 47, wherein the third semiconductor well surrounds the first semiconductor well.

52. The integrated circuit of claim 47, wherein the third semiconductor well does not surround the first semiconductor well.

53. The integrated circuit of claim 47, further comprising: A fifth region is heavily doped with the first conductivity type in the semiconductor substrate, and the fifth region is located between the first semiconductor well and the third semiconductor well.

54. The integrated circuit of claim 53, wherein the fifth region surrounds the first semiconductor well.

55. The integrated circuit of claim 53, wherein the fifth region is connected to a ground node through a metallization layer having an intrinsic metallization resistance.

56. The integrated circuit of claim 53, wherein the fifth region is isolated from the first region and the fourth region by shallow trench isolation.

57. The integrated circuit of claim 47, further comprising: A sixth region is heavily doped with the first conductivity type in the semiconductor substrate, and the sixth region is located between the second semiconductor well and the third semiconductor well.

58. The integrated circuit of claim 57, wherein the sixth region is connected to a ground node through a metallization layer having an intrinsic metallization resistance.

59. The integrated circuit of claim 57, wherein the sixth region is isolated from each of the third region and the fourth region by shallow trench isolation.

60. The integrated circuit of claim 47, wherein the first region surrounds the second region.

61. An integrated circuit comprising: a semiconductor substrate doped with a first conductivity type; A first semiconductor well is doped with a second conductivity type in the semiconductor substrate and comprises: a first region heavily doped with the second conductivity type, wherein the first region is connected to a power supply node; and a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad; a second semiconductor well doped with the second conductivity type in the semiconductor substrate; a third region heavily doped with the second conductivity type in the second semiconductor well, wherein the third region is connected to a ground node; a third semiconductor well doped with the second conductivity type in the semiconductor substrate; and a fourth region heavily doped with the second conductivity type in the third semiconductor well, wherein the fourth region is connected to a power node; The third semiconductor well is located in the semiconductor substrate between the first semiconductor well and the second semiconductor well.

62. The integrated circuit of claim 61, wherein the third semiconductor well is laterally spaced from the first semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

63. The integrated circuit of claim 61, wherein the third semiconductor well is laterally spaced from the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by a design rule for the integrated circuit.

64. An integrated circuit as claimed in claim 61, wherein the third semiconductor well is laterally separated from each of the first semiconductor well and the second semiconductor well by a designed distance between adjacent wells of the same conductivity type specified by design rules for the integrated circuit.

65. The integrated circuit of claim 61, wherein the third semiconductor well surrounds the first semiconductor well.

66. The integrated circuit of claim 61, wherein the third semiconductor well does not surround the first semiconductor well.

67. The integrated circuit of claim 61 , further comprising: A fifth region is heavily doped with the first conductivity type in the semiconductor substrate, and the fifth region is located between the first semiconductor well and the third semiconductor well.

68. The integrated circuit of claim 67, wherein the fifth region surrounds the first semiconductor well.

69. The integrated circuit of claim 67, wherein the fifth region is connected to the ground node through a metallization layer having an intrinsic metallization resistance.

70. The integrated circuit of claim 67, wherein the fifth region is isolated from the first region and the fourth region by shallow trench isolation.

71. The integrated circuit of claim 61 , further comprising: A sixth region is heavily doped with the first conductivity type in the semiconductor substrate, and the sixth region is located between the second semiconductor well and the third semiconductor well.

72. The integrated circuit of claim 71, wherein the sixth region is connected to the ground node through a metallization layer having an intrinsic metallization resistance.

73. The integrated circuit of claim 71, wherein the sixth region is isolated from each of the third region and the fourth region by shallow trench isolation.

74. The integrated circuit of claim 61, wherein the first region surrounds the second region.

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