Silicon carbide semiconductor device

Abstract

The present invention provides a silicon carbide semiconductor device capable of improving current controllability based on gate voltage control at high temperature. A p-type base region extension portion (23') is provided on the outer side of the active region of the p-type base region (23). + In a first direction X parallel to the front surface of the semiconductor substrate, at p + Type high concentration area (51) and n + The type source region (24) and in a second direction Y parallel to the front surface of the semiconductor substrate (10) and orthogonal to the first direction X are + The portion between the p-type high concentration region and the outermost trench (26) is a p-type silicon carbide epitaxial layer constituting a p-type base region extension portion (23') and is exposed on the front surface (13a) of the semiconductor substrate. + Type high concentration area to n + The first distance X1 of the type source region is greater than 0.6 μm. + The second distance Y1 from the high concentration region to the outermost trench is greater than 0.6 μm.

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device. Background Art

[0002] Silicon carbide (SiC) is highly anticipated as a semiconductor material that can achieve higher withstand voltage, lower on-resistance, lower loss, higher speed, and higher temperature characteristics than silicon (Si). In addition, in semiconductor devices with MOS gate structures such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor with an insulated gate composed of a three-layer structure of metal-oxide film-semiconductor) and / or IGBT (Insulated Gate Bipolar Transistor: an insulated gate bipolar transistor), a trench gate structure is used.

[0003] Among the trench gate structures, there is a MOS gate structure in which a MOS gate is buried in a trench formed on the front side of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the side wall of the trench in a direction orthogonal to the front side of the semiconductor substrate. Therefore, compared with a planar gate structure in which a channel is formed along the front side of the semiconductor substrate, the density of unit cells (structural units of elements) per unit area can be increased, and since the current density per unit area can be increased, it is advantageous in terms of cost. The planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front side of a semiconductor substrate.

[0004] The structure of a conventional silicon carbide semiconductor device (a semiconductor device using silicon carbide as a semiconductor material) will be described using MOSFET as an example. Fig.21 FIG. 1 is a plan view showing the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate. Fig. 22 Yes means Fig.21 A cross-sectional view of the cross-sectional structure at the cutting line AA-AA'. Fig. 22 , a cross-sectional structure of a region 103 between the active region 101 and the edge termination region 102 (hereinafter referred to as a boundary region) is shown. Fig.23 It is magnified Fig.21 A top view of a portion of. Fig.24 , Fig.25 It means respectively Fig.23 Cross-sectional view of the cross-sectional structure at the cutting line CC-CC' and the cutting line DD-DD'.

[0005] exist Fig.23, the state near the boundary between the active region 101 and the boundary region 103 near the corner of the semiconductor substrate (semiconductor chip) 110 surrounded by a rectangular frame with vertices BB and BB' as diagonal vertices is shown. The vertex BB of the rectangular frame is on the corner side of the semiconductor substrate 110, and the vertex BB' is on the center side of the semiconductor substrate 110. The corner of the semiconductor substrate 110 refers to the vertex of the semiconductor substrate 110 having a substantially rectangular planar shape. Fig.23 n + Type source region 124, p + Type contact region 125, trench 126 and p + The layout of the type high concentration region 151 is shown, and the gate insulating film 127 and the gate electrode 128 are omitted.

[0006] Figure 21 to Figure 25 The conventional silicon carbide semiconductor device shown in FIG. 1 has a p-type semiconductor layer between the active region 101 and the edge termination region 102. + The active region 101 is configured in the central part of the semiconductor substrate 110 made of silicon carbide. A plurality of unit cells of a vertical MOSFET with a trench gate structure are configured in the active region 101, and a main current flows in the active region 101 when the MOSFET is turned on. The trench gate structure (the gate electrode 128 buried in the inside of the trench 126 via the gate insulating film 127) is configured in a stripe shape extending in the direction X parallel to the front surface of the semiconductor substrate 110.

[0007] The edge termination region 102 is a region between the boundary region 103 and the end of the semiconductor substrate 110, and surrounds the periphery of the active region 101 via the boundary region 103. The edge termination region 102 has the function of alleviating the electric field concentration at the end of the active region 101 and maintaining a predetermined withstand voltage (voltage resistance). The withstand voltage refers to the limit voltage at which the voltage between the source and the drain does not increase even if avalanche breakdown occurs at the pn junction and the current between the source and the drain increases. For example, a plurality of p-type transistors are arranged in the edge termination region 102, and the impurity concentration decreases as it is arranged on the outside (the end side of the semiconductor substrate 110). - Type region 141 and p -- The junction termination (JTE: Junction Termination Extension) structure 140 formed by the type region 142 is a voltage-resistant structure.

[0008] The boundary region 103 is formed by a p-type semiconductor substrate 110 disposed on the entire front surface between the active region 101 and the edge termination region 102. + Type high concentration region 151. +The high concentration region 151 is provided at a portion (hereinafter referred to as a p-type base region extension portion) 123' of the p-type base region 123 of the MOSFET extending from the boundary region 103, and is connected to the n-type base region 151. + Type source region 124 and p + In addition, p + The p-type high concentration region 151 and the innermost side (central side of the semiconductor substrate 110) of the JTE structure 140 are - The type region 141 is in contact. + The impurity concentration of the p-type high concentration region 151 is higher than the impurity concentration of the p-type base region 123 .

[0009] p + The p-type high concentration region 151 has a function of reducing the resistance of the p-type base region 123. By reducing the resistance of the p-type base region 123, the potential of the p-type base region 123 is prevented from rising when the hole current 162 generated at the end or edge termination region 102 of the active region 101, which applies a high electric field due to avalanche breakdown 161 at the time of shutdown, is drawn to the source 131. For example, if the potential of the p-type base region 123 rises too much, the electric field applied to the thin gate insulating film 127 becomes large near the contact portion where the hole current 162 is drawn, thereby shortening the life of the gate insulating film 127 and / or causing insulation breakdown.

[0010] In addition, in order to reduce the sheet resistance of the p-type base region 123 of the MOSFET, the p + The high concentration region 151 and the n-type MOSFET + The p type source region 124 is arranged adjacent to the p + The p-type high concentration region 151 is usually formed by ion implantation of p-type impurities such as aluminum (Al) and heat treatment for impurity activation (hereinafter referred to as activation annealing) performed after the ion implantation. + The ion implantation conditions of the p-type high concentration region 151 are, for example, a maximum acceleration energy of 350 keV and a total dose of 5.15×10 15 / cm 2 .

[0011] Reference numerals 121, 111, and 112 denote silicon carbide epitaxial layers constituting the semiconductor substrate 110. Reference numerals 122, 122', 129, 132, 133, 143, and 144 denote silicon carbide epitaxial layers, respectively. - The reference numeral 130 denotes a metal film that makes ohmic contact with the semiconductor portion. The reference numerals 152 and 153 denote a conductive layer of the gate potential and a gate runner, respectively. The reference numerals 137 and 138 denote p-type drift region, n-type JFET region, interlayer insulating film, gate pad, drain, n-type channel stop region, and field oxide film. The reference numeral 130 denotes a metal film that makes ohmic contact with the semiconductor portion. The reference numerals 152 and 153 denote a conductive layer of the gate potential and a gate runner, respectively. The reference numerals 137 and 138 denote p-type +Symbol Y is the direction in which the trenches 126 are arranged side by side. Symbol Z is the depth direction of the semiconductor substrate 110.

[0012] As such a conventional silicon carbide semiconductor device, a trench gate MOSFET having a plurality of unit cells in which a MOS gate is constituted by a gate electrode inside a trench is proposed. + The device has a p-type contact region extending to the edge termination region and contacting the innermost p-type region of the JTE structure (for example, see the following patent document 1 (paragraph 0044)). In the following patent document 1, the n-type contact region in the mesa region is extended to the edge termination region and contacted with the innermost p-type region of the JTE structure. + The type source region and the p + The p-type contact area or the end of the trench + type contact area, so that all n + The source regions are fixed at the same potential.

[0013] Prior art literature

[0014] Patent Literature

[0015] Patent Document 1: Japanese Patent Application Publication No. 2018-019045 Summary of the invention

[0016] Technical issues

[0017] However, in the above-mentioned conventional silicon carbide semiconductor device (refer to Figures 21 to 25 ), when the semiconductor substrate 110 is kept in the off state under high temperature (e.g., above 125°C), a gate voltage Vg (gate voltage Vg < 0: hereinafter referred to as negative gate bias) with respect to the potential of the source 131 is applied to the gate electrode 128 for a long time. At this time, the gate threshold voltage Vth changes greatly in the negative direction (in the direction of decreasing) compared with the initial state, and the leakage current Id begins to flow when the gate voltage Vg is lower than the initial state. Therefore, the gain curve of the leakage current Id (refer to Fig.26 ) changes significantly toward the negative direction of the gate voltage Vg compared to the initial state.

[0018] The initial state refers to the state in which the total time of the negative gate bias voltage applied to the gate electrode 128 is 0 (zero) V. The drain current Id refers to the current flowing from n when power is turned on. + Type drain region (n + Type starting substrate 121) toward n +The gain curve of the drain current Id refers to the increase curve of the drain current Id that starts to flow when a gate voltage Vg (gate voltage Vg ≥ 0: hereinafter referred to as a gate positive bias) with respect to the potential of the source 131 is applied to the gate electrode 128 to increase the gate voltage Vg, and increases with the increase of the gate voltage Vg.

[0019] The change of the gate voltage Vg corresponding to the predetermined current amount of the drain current Id relative to the initial state has no regularity, and the change amount ΔVg is the largest in the negative direction at any application time of the gate negative bias voltage applied to the gate electrode 128. Moreover, compared with the change amount ΔVg of the gate voltage Vg in the initial state, the change amount ΔVg of the gate voltage Vg does not change in the positive direction. Therefore, when the application time of the gate negative bias voltage applied to the gate electrode 128 is used as the time axis, the change amount ΔVg of the gate voltage Vg changes irregularly between the maximum value in the initial state when the change amount ΔVg is the smallest and the minimum value at any application time when the change amount ΔVg is the largest.

[0020] This phenomenon is particularly evident in the rising region of the drain current Id in the gain curve. The results of verifying this phenomenon are shown in Fig.26 , Fig. 27 . Fig.26 1 is a characteristic diagram showing a region at the initial stage of current rise of a gain curve of the drain current Id of a conventional silicon carbide semiconductor device. Fig.26 The horizontal axis of is the gate voltage Vg (gate forward bias) [V] applied to the gate electrode 128 when power is applied. Fig.26 The vertical axis is the normalized drain current obtained by dividing the rated current I0 by the drain current Id. Usually, the gate threshold voltage Vth is defined as the value when the normalized drain current (=Id / I0) becomes 10 -3 The gate voltage Vg at this time.

[0021] Fig.26 The annotation is the application time of the negative gate bias applied to the gate electrode 128. When the negative gate bias is applied to the gate electrode 128, the voltage between the drain 133 and the source 131 (source-drain voltage) is 0 (zero) V. In addition, Fig.26 The sample of "0h" shown in the comment corresponds to the above-mentioned initial state. Fig. 27 Yes means Fig.26 A characteristic diagram showing the relationship between the change ΔVg of the gate voltage Vg (gate positive bias) relative to the initial state and the application time of the gate voltage Vg (gate negative bias) when turned off. Fig. 27The horizontal axis is the application time of the negative gate bias [hours (h: hour)], and the vertical axis is the change ΔVg of the positive gate bias relative to the initial state.

[0022] First, a conventional silicon carbide semiconductor device (see Figure 21 to Figure 25 ) structure MOSFET, a plurality of samples were prepared in which a negative gate bias was applied to the gate electrode 128 under the condition of a high temperature of 200°C on the semiconductor substrate 110. The negative gate bias applied to the gate electrode 128 of these samples was -5V (gate voltage Vg = -5V), and the application time of the negative gate bias varied in the range of 0h to 2500h. For these samples, a positive gate bias was applied to the gate electrode 128 at room temperature (e.g., about 25°C), and then the positive gate bias was increased, and the current amount [A] of the leakage current Id was measured. The results are shown in FIG. Fig.26 .

[0023] In addition, the predetermined current amounts Id1 / I0 and Id2 / I0 ( Fig.26 The change ΔVg of the gate forward bias voltage relative to the initial state corresponding to the position indicated by the dotted line with the symbols 171 and 172 in FIG. Fig. 27 .exist Fig. 27 For example, the leakage current Id is one thousandth of the rated current I0, which is Id1 / I0 (=10 -3 ) (hereinafter referred to as the first measurement point 171') and the current amount of the leakage current Id is the current amount Id2 / I0 (=10 -9 ) (hereinafter referred to as the second measurement point 172') is a change ΔVg of the gate forward bias voltage relative to the initial state.

[0024] like Fig. 27 As shown, the gate forward bias corresponding to the current amount of the drain current Id at the first measurement point 171' is 5.2 V in all samples with different application times of the gate negative bias applied to the gate electrode 128. That is, the change amount ΔVg of the gate forward bias corresponding to the current amount of the drain current Id at the first measurement point 171' relative to the initial state is almost 0 (zero) V regardless of whether the gate negative bias is applied. On the other hand, the change amount ΔVg of the gate forward bias corresponding to the current amount of the drain current Id at the second measurement point 172' in the state where the gate forward bias applied to the gate electrode 128 is closer to the gate threshold voltage Vth than the first measurement point 171' is -1.2 V at most.

[0025] According to the Fig. 27The results shown show that in the rising region of the drain current Id (specifically, near the second measurement point 172'), the characteristics of the gate threshold voltage Vth become unstable due to the adverse effects of high temperature and the application of a negative gate bias, which is called NBTI (Negative Bias Temperature Instability). Thus, the gain curve of the drain current Id is greatly shifted to the negative direction of the gate voltage Vg compared to the initial state only in the rising region of the drain current Id.

[0026] Such a shift in the gain curve of the leakage current Id may cause an increase in the reverse leakage current when a gate voltage Vg of 0 V or less is applied to the gate electrode 128 to maintain the off state, or may cause excessive heat and device destruction due to excessive leakage current.

[0027] The present invention aims to solve the above-mentioned problems of the prior art and to provide a silicon carbide semiconductor device having improved current controllability by gate voltage control at high temperatures (about 200° C. or higher).

[0028] Technical Solution

[0029] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the semiconductor device of the present invention has the following characteristics. An active area for main current flow is provided in a semiconductor substrate of a first conductivity type having a first main surface and a second main surface. The terminal area surrounds the periphery of the above-mentioned active area. The second conductivity type epitaxial layer constitutes a part of the above-mentioned semiconductor substrate and forms the above-mentioned first main surface of the above-mentioned semiconductor substrate. In the above-mentioned active area, a first semiconductor region of the first conductivity type is selectively provided in the surface layer on the above-mentioned first main surface side of the above-mentioned second conductivity type epitaxial layer. In the boundary area between the above-mentioned active area and the above-mentioned terminal area, a second semiconductor region of the second conductivity type is selectively provided in the surface layer on the above-mentioned first main surface side of the above-mentioned second conductivity type epitaxial layer. The impurity concentration of the above-mentioned second semiconductor region is higher than the impurity concentration of the above-mentioned second conductivity type epitaxial layer. The third semiconductor region of the second conductivity type is the part of the above-mentioned second conductivity type epitaxial layer other than the above-mentioned first semiconductor region and the above-mentioned second semiconductor region. The fourth semiconductor region of the first conductivity type is the part of the above-mentioned semiconductor substrate other than the above-mentioned second conductivity type epitaxial layer. The trench penetrates the above-mentioned first semiconductor region and the above-mentioned third semiconductor region and reaches the above-mentioned fourth semiconductor region. The gate electrode is arranged inside the trench through a gate insulating film. The first electrode is electrically connected to the first semiconductor region and the third semiconductor region. The second electrode is arranged on the second main surface of the semiconductor substrate. The second semiconductor region is configured to be separated from the first semiconductor region. Between the second semiconductor region and the first semiconductor region, a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate.

[0030] In the semiconductor device of the present invention, in the above invention, the trench extends linearly in a first direction parallel to the first main surface of the semiconductor substrate, and the second semiconductor region is arranged near an end of the trench so as to be separated from the first semiconductor region in the first direction.

[0031] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the above grooves are arranged in a stripe shape extending from the above active region to the above boundary region in the above first direction. The above first semiconductor region is arranged between adjacent above grooves. The above second semiconductor region is arranged in a manner separated from the outermost trench closest to the above boundary region in the second direction parallel to the above first main surface of the above semiconductor substrate and orthogonal to the above first direction among the plurality of above grooves. Between the above second semiconductor region and the above outermost trench, a portion of the above third semiconductor region of the above second conductive type epitaxial layer is exposed on the above first main surface of the above semiconductor substrate.

[0032] Furthermore, in the semiconductor device of the present invention, in the above invention, a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate is arranged in the boundary region and surrounds the active region.

[0033] Furthermore, in the semiconductor device of the present invention, in the above invention, a first distance from the second semiconductor region to the first semiconductor region in the first direction is greater than or equal to 0.6 μm.

[0034] Furthermore, in the semiconductor device of the present invention, in the above invention, a second distance from the second semiconductor region to the outermost trench in the second direction is greater than or equal to 0.6 μm.

[0035] Furthermore, in the semiconductor device of the present invention, in the above invention, a first distance from the second semiconductor region to the first semiconductor region in the first direction is greater than or equal to 9.35 μm.

[0036] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the above grooves are arranged in a stripe shape extending from the above active region to the above boundary region in a first direction parallel to the above first main surface of the above semiconductor substrate. The above first semiconductor region is arranged between adjacent above grooves. The above second semiconductor region is arranged separately from the outermost trench closest to the above boundary region in a second direction parallel to the above first main surface of the above semiconductor substrate and orthogonal to the above first direction among the plurality of above grooves. Between the above second semiconductor region and the above outermost trench, a portion of the above third semiconductor region of the above second conductive type epitaxial layer is exposed on the above first main surface of the above semiconductor substrate.

[0037] Furthermore, in the semiconductor device of the present invention, in the above invention, a second distance from the second semiconductor region to the outermost trench in the second direction is greater than or equal to 0.6 μm.

[0038] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the impurity concentration of the second semiconductor region is 6.4×10 14 / cm 2 the following.

[0039] Furthermore, in the semiconductor device of the present invention, in the above invention, the trench extends from the active region to the boundary region and terminates at a position closer to the active region than the second semiconductor region.

[0040] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, it further comprises a second conductivity type fifth semiconductor region selectively provided in a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate. The impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the third semiconductor region. The third semiconductor region is electrically connected to the first electrode via the fifth semiconductor region.

[0041] Furthermore, in the semiconductor device of the present invention, in the above invention, the fifth semiconductor region is a diffusion region formed by ion implantation of second conductivity type impurities into the second conductivity type epitaxial layer.

[0042] Furthermore, in the semiconductor device of the present invention, in the above invention, the second semiconductor region is a diffusion region formed by ion implantation of second conductivity type impurities into the second conductivity type epitaxial layer.

[0043] According to the above invention, it is possible to suppress the accumulation of holes at the interface between the third semiconductor region and the gate insulating film when a negative gate bias is applied to the gate electrode under high temperature conditions. Thus, it is possible to suppress the gain curve of the current flowing from the fourth semiconductor region to the first semiconductor region from shifting in the negative direction of the gate voltage compared to the initial state when a positive gate bias greater than the gate threshold voltage is applied to the gate electrode.

[0044] Effects of the Invention

[0045] According to the silicon carbide semiconductor device of the present invention, there is an effect of being able to improve the current controllability by gate voltage control at high temperatures (approximately 200° C. or higher). BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 FIG. 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment when viewed from the front surface side of the semiconductor substrate.

[0047] Figure 2 Yes means Figure 1 Cross-sectional view of the cross-sectional structure at the cutting line AA'.

[0048] Figure 3 It is magnified Figure 1 A top view of a portion of.

[0049] Figure 4 Yes means Figure 3 Cross-sectional view of the cross-sectional structure at the cutting line CC'.

[0050] Figure 5 Yes means Figure 3 Cross-sectional view of the cross-sectional structure at the cutting line D-D'.

[0051] Figure 6 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0052] Figure 7 This is a cross-sectional view showing a state of the silicon carbide semiconductor device according to the first embodiment during the manufacturing process.

[0053] Figure 8 3 is a characteristic diagram showing the results of verification for the first distance of Example 1.

[0054] Fig. 9 This is a plan view showing the layout of a portion of the silicon carbide semiconductor device according to the second embodiment as viewed from the front surface side of the semiconductor substrate.

[0055] Fig.10 3 is a characteristic diagram showing the results of verification for the first distance of Example 2.

[0056] Fig.11 This is a plan view showing the layout of a portion of the silicon carbide semiconductor device according to the third embodiment as viewed from the front surface side of the semiconductor substrate.

[0057] Fig.12 is p for Example 3 + The dose in the high concentration area was verified in the characteristic diagram.

[0058] Fig.13 1 is a plan view showing a layout of a portion of the silicon carbide semiconductor device according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate.

[0059] Fig.14 is p for Example 4 + The dose in the high concentration area was verified in the characteristic diagram.

[0060] Fig.15 It is a plan view showing the layout of a part of the silicon carbide semiconductor device according to the fifth embodiment as viewed from the front surface side of the semiconductor substrate.

[0061] Fig.16 Yes means Fig.15 Cross-sectional view of the cross-sectional structure at the cutting line EE'.

[0062] Fig.17 It is a plan view showing the layout of a part of the silicon carbide semiconductor device according to the sixth embodiment as viewed from the front surface side of the semiconductor substrate.

[0063] Fig.18 Yes means Fig.17 Cross-sectional view of the cross-sectional structure at the cutting line F-F'.

[0064] Fig.19 It is a plan view showing the layout of the silicon carbide semiconductor device according to the seventh embodiment as viewed from the front surface side of the semiconductor substrate.

[0065] Fig. 20 3 is a characteristic diagram showing the relationship between the first distance and the avalanche current Iav in Example 6.

[0066] Fig.21 FIG. 1 is a plan view showing the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate.

[0067] Fig. 22 Yes means Fig.21 Cross-sectional view of the cross-sectional structure at the cutting line AA-AA'.

[0068] Fig.23 It is magnified Fig.21 A top view of a portion of.

[0069] Fig.24 Yes means Fig.23 Cross-sectional view of the cross-sectional structure at the cutting line CC-CC'.

[0070] Fig.25 Yes means Fig.23 Cross-sectional view of the cross-sectional structure at the cutting line DD-DD'.

[0071] Fig.26 1 is a characteristic diagram showing a region at the initial stage of current rise of a gain curve of the drain current Id of a conventional silicon carbide semiconductor device.

[0072] Fig. 27 Yes means Fig.26 14 is a characteristic diagram showing the relationship between the change ΔVg of the gate voltage Vg and the application time of the gate voltage Vg at the time of shutdown.

[0073] Explanation of symbols

[0074] 1: Active area

[0075] 2: Edge terminal area

[0076] 3: Border area

[0077] 4: Invalid area

[0078] 10: Semiconductor substrate

[0079] 11:n - Silicon Carbide Epitaxial Layer

[0080] 12: p-type silicon carbide epitaxial layer

[0081] 13: Step difference on the front side of the semiconductor substrate

[0082] 13a, 13a': front side of semiconductor substrate

[0083] 13b: Inclined portion of the step difference on the front surface of the semiconductor substrate

[0084] 13c: Corner of step difference on the front surface of semiconductor substrate

[0085] 21:n + Type starting substrate

[0086] 22:n - Drift zone

[0087] 22': n-type JFET region

[0088] 23: p-type base region

[0089] 23': p-type base region extension

[0090] 24:n + Type source region

[0091] 25, 25': p + Type contact area

[0092] 26, 26': Groove

[0093] 27: Gate insulation film

[0094] 28: Gate electrode

[0095] 29: Interlayer insulation film

[0096] 29a~29c:Contact hole

[0097] 30: Metal film

[0098] 31: Source

[0099] 32: Gate pad

[0100] 33: Drain

[0101] 37: p just below the groove + Type Area

[0102] 38: p of the countertop area + Type Area

[0103] 40: JTE structure

[0104] 41, 42: p-type region of JTE structure

[0105] 43: n-type channel cutoff region

[0106] 44: Field oxide film

[0107] 51, 51': p + High concentration area

[0108] 52: Conductive layer

[0109] 53: Gate runner

[0110] 61: Oxide film

[0111] 61a: p + Type contact area formation area

[0112] 61b:p + Type high concentration area formation area

[0113] 62: Ion implantation

[0114] t1: p just below the groove + Thickness of the molded area

[0115] t2: p of the table area + Thickness of the molded area

[0116] t3: p in the boundary area + Thickness of high concentration area

[0117] t11:n - The thickness of the SiC epitaxial layer

[0118] t12: thickness of p-type silicon carbide epitaxial layer

[0119] X: Direction parallel to the front surface of the semiconductor substrate (first direction)

[0120] X1, X1', X11: The first direction from p + Type high concentration area to n + Distance to the source region (first distance)

[0121] Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction)

[0122] Y1: The second direction from p + The distance from the high concentration area to the outermost trench (the second distance)

[0123] Z: Depth direction DETAILED DESCRIPTION

[0124] Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, in the layers and regions prefixed with n or p, it is indicated that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration of the layer or region not marked with + and -. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same structures, and repeated descriptions are omitted.

[0125] (Implementation Method 1)

[0126] The structure of the silicon carbide semiconductor device (a semiconductor device using silicon carbide (SiC) as a semiconductor material) according to the first embodiment will be described using MOSFET as an example. Figure 1 FIG. 1 is a plan view showing the layout of the silicon carbide semiconductor device according to the first embodiment when viewed from the front surface side of the semiconductor substrate. Figure 2 Yes means Figure 1 A cross-sectional view of the cross-sectional structure at the cutting line A-A'. Figure 2 , a cross-sectional structure of a region (boundary region) 3 between an active region 1 and an edge termination region 2 is shown. Figure 3 It is magnified Figure 1 A top view of a portion of. Figure 4 , Figure 5 It means respectively Figure 3Cross-sectional view of the cross-sectional structure at the cutting line CC' and the cutting line DD'.

[0127] exist Figure 3 In the figure, Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate (semiconductor chip) 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The vicinity of vertex B of the rectangular frame is the part on the corner side of the semiconductor substrate 10, and the vicinity of vertex B' is the part on the central side of the semiconductor substrate 10. The corner of the semiconductor substrate 10 refers to the vertex of the semiconductor substrate 10 having a substantially rectangular planar shape. Figure 3 n + Type source region (first semiconductor region) 24, p + Type contact region 25, trench 26 and p + The layout of the type high concentration region (second semiconductor region) 51 is shown, and the gate insulating film 27 and the gate electrode 28 are omitted.

[0128] Figure 1 to Figure 5 The silicon carbide semiconductor device of the first embodiment shown in the figure has a p-type semiconductor layer between the active region 1 and the edge termination region 2. + A vertical MOSFET having a trench gate structure in the boundary region 3 of the high concentration region 51. The active region 1 is arranged in the central part of the semiconductor substrate 10 made of silicon carbide. A plurality of unit cells (structural units of the element) of the vertical MOSFET having a trench gate structure are arranged in the active region 1, and a main current (drain current Id) flows in the active region 1 when the MOSFET is turned on (energized). The trench gate structure has a MOS gate composed of a gate electrode 28 buried through a gate insulating film 27 in a trench 26 reaching a predetermined depth from the front surface 13a of the semiconductor substrate 10.

[0129] The active region 1 is larger than the n + The region of the outer periphery of the source region 24 close to the inner side (the center side of the semiconductor substrate 10) has, for example, a substantially rectangular planar shape. + The periphery of the type source region 24 refers to the n-type source region extending linearly along the trenches 26 in the first direction X between adjacent trenches 26. + The end of the first direction X of the type source region 24. The second direction Y described later + The periphery of the type source region 24 refers to the inner side wall of the outermost trench (outermost trench) 26 in the second direction Y (the end side of the semiconductor substrate 10) and the n + The edge termination region 2 is larger than the p + The high concentration region 51 and the p-type JTE structure 40 described later are - The area on the outside of the boundary of the type area 41.

[0130] The semiconductor substrate 10 is formed by + The drain region is made of silicon carbide. + The front surface of the starting substrate 21 is made into n - The semiconductor substrate 10 is an epitaxial substrate formed by epitaxially growing the p-type silicon carbide epitaxial layers 11 and 12 of the p-type drift region (fourth semiconductor region) 22 and the p-type base region (third semiconductor region) 23. In the semiconductor substrate 10, the main surface (first main surface) where the p-type silicon carbide epitaxial layer (second conductivity type epitaxial layer) 12 is exposed is the front surface 13a, and the n-type silicon carbide epitaxial layer 12 is exposed is the front surface 13a. + The main surface (second main surface) exposed on the back side of the type starting substrate 21 is used as the back side. - The first p-type silicon carbide epitaxial layer 11 is selectively provided with + Type region 37, second p + Type area 38. n - The silicon carbide epitaxial layer 11 has a first p + Type region 37, second p + The portion outside the type region 38 is n - Type drift region 22.

[0131] In the active region 1, n-type silicon carbide epitaxial layer 12 is selectively provided on the surface region (surface layer of the front surface 13a of the semiconductor substrate 10). + Type 24 source region and p + Type contact area 25. + The p-type source region 24 is formed by ion implanting n-type impurities such as phosphorus (P) into the p-type silicon carbide epitaxial layer 12. + Type contact area 25 and p + The p-type high concentration region 51 is formed by ion implantation of p-type impurities such as aluminum (Al) into the p-type silicon carbide epitaxial layer 12. + Type source region 24, p + Type contact area 25 and p + The portion other than the p-type high concentration region 51 is the p-type base region 23 .

[0132] The p-type base region 23 extends outward from the active region 1 and terminates at an inclined portion 13b of a step 13 described later, which is located near the boundary between the boundary region 3 and the edge termination region 2. Hereinafter, the portion of the p-type base region 23 that is outward from the active region 1 is referred to as a p-type base region extension portion 23'. Specifically, the p-type base region extension portion 23' is a portion of the p-type base region 23 that is outward from the active region 1 in the first direction X described later. +The p-type base region extension 23' is a portion of the p-type base region 23 that is outside the outermost trench 26 in the second direction Y described later. The p-type base region extension 23' surrounds the active region 1 in a substantially rectangular shape.

[0133] The trench 26 penetrates the semiconductor substrate 10 from the front surface 13a in the depth direction Z. + type source region 24 and p-type base region 23 to reach n - The trench 26 is arranged in a stripe shape extending in a direction (hereinafter referred to as a first direction) X parallel to the front surface 13a of the semiconductor substrate 10, with both ends located near the opposite sides of the semiconductor substrate 10. The ends of the trench 26 extend outward from the active region 1 and terminate at the boundary region 3. The ends of the trench 26 can reach the p + Type high concentration area 51 (refer to Figure 3 ). The groove 26 may have a substantially annular planar shape in which both ends are connected to the ends of other adjacent grooves 26 .

[0134] A gate electrode 28 is provided inside the trench 26 via a gate insulating film 27. A unit cell of the MOSFET is formed by the gate electrode 28 disposed inside one trench 26 and the adjacent mesa region separated by the trench 26. The region provided in the mesa region is electrically insulated from the gate electrode 28 by the gate insulating film 27. The mesa region refers to the region between adjacent trenches 26. The unit cells of the MOSFET are arranged in a plurality of stripes extending in the first direction X. That is, the p-type base region 23, the n-type base region 24, and the n-type base region 25 are arranged in a plurality of stripes extending in the first direction X. + The source region 24 , the trench 26 , the gate insulating film 27 , and the gate electrode 28 are arranged in a stripe shape extending along the first direction X.

[0135] n + The type source region 24 is provided in the entire mesa region in the active region 1 so as to extend from the side wall of the trench 26 through the mesa region to the side wall of another trench 26 adjacent to the trench 26. + The type contact regions 25 may be dispersedly arranged at n positions at predetermined intervals in the first direction X. + The interior of the type source region 24. + The contact region 25 has a function of reducing the metal film 30 described later and the n + Type 24 source region and p + The contact resistance of the p-type contact area 25 is + The type contact region 25 makes the voltage-current characteristic of the contact (electrical contact) between the metal film 30 and the semiconductor part show ohmic characteristics (linearity). Therefore, the potential difference between the source (first electrode) 31 and the semiconductor part can be reduced.

[0136] By reducing the potential difference between the source electrode 31 and the semiconductor portion, it is possible to prevent the + The gate insulating film 27 is broken due to the npn parasitic bipolar action of the p-type source region 24, the p-type base region 23 and the n-type drift region 22. + The position of the starting substrate 21 side deeper than the bottom surface of the groove 26 is n - The interior of the drift region 22 is selectively provided with a first p + Type region 37, second p + Type region 38. The first p + The type region 37 is arranged in the direction n + The bottom surface of the groove 26 is located at a position deeper than the bottom surface of the groove 26 on the side of the first starting substrate 21 and faces the bottom surface of the groove 26 in the depth direction Z. The bottom surface of the groove 26 may be located at a position deeper than the bottom surface of the groove 26 on the side of the first starting substrate 21 and faces the bottom surface of the groove 26 in the depth direction Z. + The internal terminal of type area 37.

[0137] Second p + The type region 38 is arranged in the mesa region toward n + The second p-type starting substrate 21 is located deeper than the p-type base region 23 and in contact with the p-type base region 23. + The first p-type region 38 is disposed separately from the trench 26. + Type region 37, second p + The type regions 38 are alternately and repeatedly arranged in a direction (hereinafter referred to as a second direction) Y that is orthogonal to the first direction X and parallel to the front surface 13a of the semiconductor substrate 10. + Type region 37, second p + The first p-type region 38 can suppress the electric field applied to the gate insulating film 27 and improve the withstand voltage when the MOSFET is turned off. + Type region 37 and the second p + The impurity concentration of the n-type JFET region 22′ between the n-type regions 38 is greater than that of the n-type JFET region 22′. - The impurity concentration of the type drift region 22 is high.

[0138] In addition, the first + Type region 37, second p + The molded area 38 extends outward in the first direction X to a corner 13c of the step 13 described later, and covers the corner 13c of the step 13. + type high concentration region 51. In addition, the second p + The type region 38 is arranged outside the outermost groove 26 in the second direction Y. The second p-type region 38 is arranged outside the outermost groove 26 in the second direction Y. + The type region 38 is arranged in the direction n +The second p-type starting substrate 21 is located deeper than the p-type base region extension 23' and is in contact with the p-type base region extension 23'. + The type region 38 also extends outward in the second direction Y to the corner 13c of the step difference 13, and covers the corner 13c of the step difference 13. + Type high concentration area 51.

[0139] The interlayer insulating film 29 is provided on the entire front surface 13a of the semiconductor substrate 10 and covers the gate electrode 28. A first contact hole 29a is provided which penetrates the interlayer insulating film 29 in the depth direction Z. In the first contact hole 29a, the mesa region (i.e., n + Type 24 source region and p + Each mesa region is exposed in a different first contact hole 29a. The first contact holes 29a are, for example, dispersedly arranged at predetermined intervals in the first direction X, respectively exposing different p + Type contact region 25. Inside each first contact hole 29a, a metal film 30 is provided on the front surface 13a of the semiconductor substrate 10.

[0140] Metal film 30 and n + Type 24 source region and p + The source electrode 31 contacts the n type contact region 25, forming a contact with an ohmic voltage-current characteristic. The metal film 30 is, for example, a nickel silicide (NiSi) film. + Type source region 24, p + The source electrode 31 is electrically connected to the p-type contact region 25 and the p-type base region 23. The source electrode 31 covers almost the entire surface of the active region 1 on the front surface 13a of the semiconductor substrate 10. The source electrode 31 also serves as a source pad. The source electrode 31 can extend on the interlayer insulating film 29 and terminate at the boundary region 3. The source electrode 31 can be, for example, an aluminum-silicon (Al-Si) film.

[0141] In addition, a gate pad 32 is provided on the interlayer insulating film 29 of the active region 1, for example, in a manner separated from the source 31, near the boundary between the active region 1 and the boundary region 3. The gate pad 32 has, for example, a substantially rectangular planar shape. The gate pad 32 is formed of, for example, the same material as the source 31. The gate pad 32 is electrically connected to all gate electrodes 28 via a conductive layer 52 and a gate runner 53 to be described later. The drain (second electrode) 33 is provided on the entire back side of the semiconductor substrate 10 from the active region 1 to the edge termination region 2. The drain 33 is connected to the n + n-type drain region + The back side contact of the starting substrate 21 is formed to form an ohmic contact with respect to the voltage-current characteristics.

[0142] The edge termination region 2 is a region between the boundary region 3 and the end of the semiconductor substrate 10, and surrounds the active region 1 in a roughly rectangular shape with the boundary region 3 interposed therebetween. The edge termination region 2 has the function of alleviating the electric field concentration at the end of the active region 1 and maintaining a predetermined withstand voltage (voltage resistance). The withstand voltage refers to the limit voltage at which the leakage current does not increase excessively and the element does not malfunction and / or break down. By removing the p-type silicon carbide epitaxial layer 12 from the entire edge termination region 2, the edge termination region 2 is formed on the front surface 13a of the semiconductor substrate 10, which is lower than the active region 1 (towards n). + The step difference 13 is formed by a recess on the side of the semiconductor substrate 21. The front surface 13a' of the semiconductor substrate 10 is newly formed in the edge termination region 2 by utilizing the step difference 13.

[0143] The front surface 13a' of the semiconductor substrate 10 in the edge termination region 2 is exposed. - When forming the step difference 13, the p-type silicon carbide epitaxial layer 12 and the n-type silicon carbide epitaxial layer 11 can be removed at a predetermined depth. - The step 13 has an inclined portion 13b located in the boundary region 3. The inclined portion 13b of the step 13 is a surface connecting the front surface 13a (the upper surface) of the inner portion of the semiconductor substrate 10 and the front surface 13a' (the lower surface) of the outer portion of the semiconductor substrate 10. The p-type silicon carbide epitaxial layer 11 is exposed in the inclined portion 13b of the step 13. + The front surface 13 a ′ of the outer portion of the semiconductor substrate 10 , which is the lower surface of the step 13 , may extend to the boundary region 3 .

[0144] In the edge termination region 2, a voltage-resistant structure such as a junction termination (JTE) structure 40 is arranged on the surface layer of the front surface 13a' of the semiconductor substrate 10. The innermost p-type region of the JTE structure 40 is composed of a plurality of p-type regions with lower impurity concentrations as they are arranged outward (here, for example, two p-type regions are marked with reference numerals 41 and 42 in sequence from the inner side). - The p-type region 41 surrounds the active region 1 via the boundary region 3. -- Type region 42 and p - The p-type region 41 is adjacently arranged outside and surrounds the p-type region 41. - For example, the second p + Type region 38 vs p - Type region 41 and p -- The molded area 42 is deep.

[0145] Through these p - Type region 41 and p -- The inner extension of the type region 42 is from the second p+ Type region 38 and n - The depletion layer extending outward from the end of the pn junction surface of the type drift region 22 ensures the withstand voltage at the edge termination region 2. In addition, in the edge termination region 2, an n-type channel stop region 43 is selectively provided on the surface layer of the front surface 13a' of the semiconductor substrate 10, which is outside the JTE structure 40 and separated from the JTE structure 40. The n-type channel stop region 43 is exposed at the end of the semiconductor substrate 10 (the side of the semiconductor substrate 10). In the edge termination region 2, the front surface 13a' of the semiconductor substrate 10 is covered by a field oxide film 44 provided between the semiconductor substrate 10 and the interlayer insulating film 29.

[0146] The boundary region 3 is composed of a layer of a surface layer of the front surface 13a of the semiconductor substrate 10 disposed between the active region 1 and the edge termination region 2. + Type high concentration region 51. + The p-type high concentration region 51 is formed in the surface region of the p-type base region extension portion 23' by ion implantation of p-type impurities such as aluminum. + The type high concentration region 51 is in the first direction X with the active region 1 at n + The p-type source region 24 is arranged in a manner separated from the outer sidewall of the outermost trench 26 in the second direction Y. + No n type high concentration region 51 is provided between the outermost trench 26. + Type 24 source region and p + Type contact area 25.

[0147] In the first direction X, + Type high concentration region 51 and n + The portion sandwiched by the type source region 24 and the portion sandwiched by the type source region 24 in the second direction Y + The portion sandwiched between the p-type high concentration region 51 and the outermost trench 26 is a portion of the p-type base region extension 23' formed of the p-type silicon carbide epitaxial layer 12, and is exposed on the front surface 13a of the semiconductor substrate 10 along the boundary between the active region 1 and the boundary region 3 ( Figure 3 The unshaded part (in Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 That is, the p-type base region extension portion 23' is exposed on the front surface 13a of the semiconductor substrate 10 along the boundary between the active region 1 and the boundary region 3 in a substantially straight line extending along a pair of opposite sides of the active region 1 having a substantially rectangular planar shape, or in a substantially rectangular shape surrounding the active region 1 having a substantially rectangular planar shape.

[0148] exist Figure 3Only the corner of the semiconductor substrate 10 is shown in FIG. 1 , but the opposite side parallel to the second direction Y along the boundary between the active region 1 and the boundary region 3 is parallel to the n + The p-type source region 24 is separately configured + The p-type high concentration region 51 is formed along the opposite side of the boundary between the active region 1 and the boundary region 3 parallel to the first direction X, and is separated from the outermost trench 26. + Thus, the p-type base region extension 23' formed by the p-type silicon carbide epitaxial layer 12 having no crystal defects in the first direction X is formed. + Type high concentration region 51 and n + The portion sandwiched by the type source region 24, or formed by the p + The portion sandwiched between the type high concentration region 51 and the outermost trench 26, or constitutes these two portions.

[0149] In the first direction X from p + Type high concentration area 51 to n + The first distance X1 of the type source region 24 can be set to, for example, 0.6 μm or more. + The second distance Y1 from the p-type high concentration region 51 to the outermost trench 26 can be set to, for example, a degree of not less than 0.6 μm. As long as at least one of the conditions of the first distance X1 and the second distance Y1 is satisfied, the effect of the present invention described later can be obtained. When the conditions of the first distance X1 and the second distance Y1 are satisfied, the first distance X1 and the second distance Y1 are equal (X1=Y1). When viewed from the front surface 13a side of the semiconductor substrate 10, the active region 1 is surrounded by a p-type base region extension portion 23' having a width of not less than 0.6 μm, and the p-type base region extension portion 23' is surrounded by a p-type base region extension portion 23'. + The type high concentration region 51 is surrounded.

[0150] Thus, in the source region 1 and p + A p-type base region extension 23' composed of a p-type silicon carbide epitaxial layer 12 is arranged between the p-type high concentration region 51. Therefore, even if a gate voltage Vg (gate voltage Vg < 0: gate negative bias) with respect to the potential of the source 31 is applied to the gate electrode 28 for a long time under high temperature conditions (for example, above 125°C), the change ΔVg of the gate voltage Vg corresponding to a predetermined current amount of the drain current Id relative to the initial state can be reduced. Therefore, by applying a gate negative bias under high temperature conditions, the period during which the characteristics of the gate threshold voltage Vth are unstable, that is, the period of NBTI, can be shortened. In addition, even if a gate negative bias is applied to the gate electrode 28 for a long time under high temperature conditions, the current amount of the drain cutoff current (drain current) Idss can be made close to that in the initial state.

[0151] The change ΔVg of the gate voltage Vg relative to the initial state refers to the value (difference) obtained by subtracting the gate voltage Vg in the state where the gate negative bias is applied from the gate voltage Vg in the initial state. When power is turned on, it means that a gate voltage Vg (gate voltage Vg ≥ 0: gate positive bias) with respect to the potential of the source 31 is applied to the gate electrode 28 to increase the gate voltage Vg, and the gate voltage Vg becomes greater than the gate threshold voltage Vth. The leakage current Id starts to flow after power is turned on, and increases with the increase of the gate voltage Vg. The initial state refers to a state in which a negative gate bias is not applied to the gate electrode 28, that is, a state in which the total time of applying the negative gate bias to the gate electrode 28 is 0 (zero) V.

[0152] In addition, + The type high concentration region 51 is exposed on the front surface 13a of the semiconductor substrate 10 in the boundary region 3. + The high concentration region 51 is exposed from the inclined portion 13b and the corner 13c of the step 13 to the front surface 13a' of the outer portion of the semiconductor substrate 10, which is the lower surface of the step 13. The corner 13c of the step 13 refers to the boundary between the front surface 13a' of the outer portion of the semiconductor substrate 10, which is the lower surface of the step 13, and the inclined portion 13b of the step 13. + The high concentration region 51 is located at the corner 13c of the step 13 and is adjacent to the n in the first direction X. - type drift region 22 and the first p + Type region 37, second p + The type region 38 contacts the second p + Type area 38 contacts.

[0153] p + The type high concentration region 51 is adjacent to the innermost p-type region of the JTE structure 40 in the first direction X and the second direction Y. - Type region 41 is in contact. + The high concentration region 51 may be higher than the first p + Type region 37, second p + The p-type region 38 extends to a position further outside. + The high concentration region 51 is in the first p + Type region 37, second p + The p-type region 38 and the JTE structure 40 - Type region 41 and n - The drift region 22 is in contact with the p + The entire surface of the p-type high concentration region 51 is covered by an insulating film composed of the gate insulating film 27, the interlayer insulating film 29 and the field oxide film 44. + The high concentration region 51 may be in direct contact with the metal film 30. +The p-type high concentration region 51 is electrically connected to the source 31 via the p-type base region extension 23 ′ (ie, the p-type base region 23 ).

[0154] In addition, + The impurity concentration of the p-type high concentration region 51 is higher than the impurity concentration of the p-type base region 23. + The p-type high concentration region 51 has the function of reducing the resistance of the p-type base region 23. By reducing the resistance of the p-type base region 23, it is possible to prevent the potential of the p-type base region extension 23' (i.e., the p-type base region 23) from rising when the hole current generated near the boundary of the edge termination region 2 and the boundary region 3 or the end of the active region 1 where the electric field is concentrated due to avalanche breakdown at the time of shutdown is drawn to the source 31. In this way, the electric field applied to the thin gate insulating film 27 can be alleviated, the life of the gate insulating film 27 can be extended, or the insulation breakdown of the gate insulating film 27 can be prevented.

[0155] In the boundary region 3, a conductive layer 52 made of polysilicon (poly-Si:) and a gate runner 53 made of, for example, the same material as the source 31 are provided on the field oxide film 44 (see Figure 2 ). The conductive layer 52 is electrically connected to all gate electrodes 28 in the portion not shown. The conductive layer 52 is covered by the interlayer insulating film 29. The gate runner 53 is connected to the conductive layer 52 via a second contact hole 29b that penetrates the interlayer insulating film 29 in the depth direction. The conductive layer 52 and the gate runner 53 surround the source region 1 in a substantially rectangular shape. The gate runner 53 is connected to the gate pad 32 (see Figure 1 )connect.

[0156] Although not particularly limited, for example, when the MOSFET of the first embodiment is of a 1200V withstand voltage class, the dimensions and impurity concentrations of the various components are as follows. + The impurity concentration of the starting substrate 21 is, for example, 1×10 18 / cm 3 Around. - The thickness t11 of the silicon carbide epitaxial layer 11 is, for example, 10 μm. - Type silicon carbide epitaxial layer 11 (n - The impurity concentration of the drift region 22 is, for example, 5×10 15 / cm 3 Above and 2×10 16 / cm 3 The impurity concentration of the n-type JFET region 22' is, for example, 1×10 17 / cm 3 about.

[0157] First p + The thickness t1 of the type region 37 may be, for example, about 0.5 μm. +The second p-type region 37 reaches a depth of about 2 μm from the front surface 13 a of the semiconductor substrate 10 , for example. + The thickness t2 of the type region 38 may be, for example, about 1 μm. + The first p-type region 38 reaches a depth of about 2 μm from the front surface 13 a of the semiconductor substrate 10 . + Type region 37, second p + The impurity concentration of the type region 38 is, for example, 1×10 17 / cm 3 Above and 1×10 19 / cm 3 The following degree, for example, can be 1×10 18 / cm 3 about.

[0158] The thickness t12 of the p-type silicon carbide epitaxial layer 12 is, for example, about 1 μm. The impurity concentration of the p-type silicon carbide epitaxial layer 12 (p-type base region 23) is, for example, 1×10 16 / cm 3 Above and 3×10 18 / cm 3 The following degree, for example, can be 1×10 17 / cm 3 Around. + The impurity concentration of the source region 24 is, for example, 1×10 21 / cm 3 Around. + The thickness t3 of the high concentration region 51 is, for example, about 0.5 μm. + The impurity concentration of the high concentration region 51 is, for example, 5×10 18 / cm 3 Above 1×10 21 / cm 3 The following degree.

[0159] Next, the operation of the silicon carbide semiconductor device of Embodiment 1 is described. In a state where a positive voltage (source-drain voltage) is applied to the drain 33 relative to the source 31, a gate voltage Vg less than the gate threshold voltage Vth is applied to the gate electrode 28. As a result, since the pn junction between the p-type base region 23 and the n-type drift region 22 is reverse biased, the reverse withstand voltage of the source region 1 is ensured, and the leakage current Id does not flow. That is, the MOSFET maintains the off state. At this time, for example, by applying a negative gate bias to the gate electrode 28, the MOSFET can be reliably turned off.

[0160] On the other hand, when a gate voltage Vg equal to or higher than the gate threshold voltage Vth is applied to the gate electrode 28 while the source-drain voltage is applied, the p-type base region 23 is n-type.+ Type source region 24 and n - An n-type inversion layer (channel) is formed in the portion along the trench 26 sandwiched by the n-type drift region 22. + Type starting substrate 21, n - The surface inversion layer of the p-type drift region 22, the p-type base region 23 and the n-type + The MOSFET is turned on by the path of the source region 24. Thus, the switching operation of the MOSFET can be performed by controlling the gate voltage Vg.

[0161] A method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. Figure 6 , Figure 7 1 is a cross-sectional view showing a state of the silicon carbide semiconductor device in the manufacturing process according to the first embodiment. + The front side of the starting substrate 21 is n - Next, by photolithography and ion implantation, a silicon carbide epitaxial layer 11 is grown. - A first p-type silicon carbide epitaxial layer 11 is selectively formed inside + Type region 37, second p + Next, n is increased by epitaxial growth. - The thickness of the silicon carbide epitaxial layer 11 is n - The type silicon carbide epitaxial layer 11 is thickened to a predetermined thickness t11.

[0162] Next, photolithography and ion implantation were used to - The surface layer of the silicon carbide epitaxial layer 11 is formed as the second p + Type region 38 p + type region, so that the second p + The molded area 38 is thickened to a predetermined thickness t2. - The silicon carbide epitaxial layer 11 has a first p + Type region 37, second p + type region 38 and the p - Type region 41, p -- The portion other than the n-type region 42 and the n-type channel stop region 43 is n-type. - type drift region 22. Next, in n - On the surface of the p-type silicon carbide epitaxial layer 11 , a p-type silicon carbide epitaxial layer 12 is epitaxially grown.

[0163] Next, the p-type silicon carbide epitaxial layer 12 is removed from the entire region of the edge termination region 2, and a step 13 is formed on the front surface 13a of the semiconductor substrate 10 so that the edge termination region 2 is lower than the active region 1. Thus, the front surface 13a' of the semiconductor substrate 10 in the edge termination region 2 exposes the n-type silicon carbide epitaxial layer 12.- Next, ion implantation is performed using different oxide film masks, thereby selectively forming n type silicon carbide epitaxial layer 11 in the above-mentioned predetermined regions. + Type source region 24, p + Type contact area 25, p + Type high concentration region 51, JTE structure 40 (p - Type region 41, p -- type region 42) and an n-type channel stop region 43.

[0164] n + Type source region 24, p + Type contact area 25, p + The formation order of the n-type high concentration region 51, the JTE structure 40, and the n-type channel stop region 43 may be changed in various ways. + The high concentration region 51 can be connected to the p + The n type contact region 25 is formed at the same time. For example, when forming n + The p-type source region 24, the JTE structure 40 and the n-type channel stop region 43 are then formed. + Type contact area 25 and p + In the case of the high concentration region 51, first, as Figure 6 As shown, an oxide film 61 is deposited on the entire front surface of the semiconductor substrate 10 (ie, the front surfaces 13 a and 13 a ′ of the semiconductor substrate 10 and the inclined portion 13 b of the step 13 ).

[0165] Next, the oxide film 61 and the p + The formation area 61a and p + Next, the remaining portion of the oxide film 61 is used as a mask to perform ion implantation 62 of p-type impurities such as aluminum. Figure 6 ). By the ion implantation 62, a p-type active region 1 is formed in a predetermined region. + A p-type contact region 25 is formed in a predetermined area of ​​the boundary region 3. + Type high concentration area 51 ( Figure 7 ). The conditions for the ion implantation 62 can be the same as in the past, with the maximum acceleration energy being 350 keV and the total dose of the p-type impurity being 5.15×10 15 / cm 2 .

[0166] Next, a heat treatment (activation annealing) is performed at a temperature of, for example, about 1700°C for about 10 minutes to activate all the impurities that have been ion-implanted. Next, a trench gate structure is formed by the trench 26, the gate insulating film 27, and the gate electrode 28 using a conventional method. After the gate insulating film 27 is formed by, for example, thermal oxidation, a POA (Post Oxidation Anneal) for improving the interface characteristics between the gate insulating film 27 and the semiconductor portion may be performed. Then, a field oxide film 44, an interlayer insulating film 29, a metal film 30, a conductive layer 52, a source electrode 31, a gate pad 32, a gate runner 53, and a drain electrode 33 are formed using a conventional method, thereby completing Figure 1 to Figure 5 MOSFET shown.

[0167] Next, the active region 1 and p + The reason why the p-type base region extension portion 23' composed of the p-type silicon carbide epitaxial layer 12 is arranged between the p-type high concentration regions 51 is described. First, the conventional silicon carbide semiconductor device (see Figures 21 to 25 , hereinafter referred to as the existing structure) of the leakage current Id gain curve (refer to Fig.26 ) is explained below with reference to the following description of the mechanism by which the gate voltage Vg is greatly shifted to the negative direction compared to the initial state. It is estimated that the shift of the gain curve of the drain current Id is caused by the following five factors.

[0168] The first item is to form a p-type silicon carbide epitaxial layer 112 by forming a p-type silicon carbide epitaxial layer 112. + The second point defect in the p-type silicon carbide epitaxial layer 112 is caused by the ion implantation of the p-type impurity into the p-type high concentration region 151. + The formation area of ​​the type high concentration region 151 diffuses to the p + The outer side of the high concentration region 151 spreads over a range of several μm in a direction parallel to the front surface of the semiconductor substrate 10 (ie, radially including the first direction X and the second direction Y).

[0169] The third matter is that, by thermal oxidation (including POA) for forming the gate insulating film 127, point defects in the p-type silicon carbide epitaxial layer 112 become hole traps in the gate insulating film 127. The fourth matter is that, by applying a negative gate bias (for example, gate voltage Vg=-5V) to the gate electrode 128 of the MOSFET manufactured by the process including these matters under the condition that the semiconductor substrate 110 becomes a high temperature (for example, 125°C or above), holes are accumulated at the interface between the p-type base region 123 and the gate insulating film 127.

[0170] The fifth event is that some of the holes accumulated at the interface between the p-type base region 123 and the gate insulating film 127 are tunneled and captured by hole traps in the gate insulating film 127. As a result, the gain curve of the drain current Id is greatly shifted to the negative direction of the gate voltage Vg compared to the initial state. These five events are near the electrical connection position between the gate electrode 128 and the gate runner 153 that applies the gate voltage Vg to the gate electrode 128, that is, n + The type source region 124 is significantly manifested near its periphery.

[0171] Since the above five items are + The gain curve of the drain current Id is shifted only in the rising region of the drain current Id because the point defects are not diffused into the gate insulating film 27 in the third item. For the diffusion length of the point defects listed in the second item, the p-type source region 124 is significantly reflected, and the gain curve of the drain current Id is shifted only in the rising region of the drain current Id. Therefore, in the third item, the point defects can be prevented from diffusing into the gate insulating film 27, and the diffusion length of the point defects listed in the second item can be reduced as in the present invention. + Type high concentration region 51 and n + The type source region 24 is fully separated, and the active region 1 and the p + A p-type silicon carbide epitaxial layer 12 having no crystal defects is arranged between the p-type high concentration regions 51 .

[0172] (Example 1)

[0173] Next, the first distance X1 and the second distance Y1 of the silicon carbide semiconductor device n according to the first embodiment are verified. Figure 8 3 is a characteristic diagram showing the results of verification of the first distance of Example 1. Figure 8 The horizontal axis is the first direction X from p + Type high concentration area 51 to n + The vertical axis is the maximum value of the change in the gate forward bias voltage ΔVg generated within a predetermined time period while observing the change in the gate forward bias voltage over time. First, a plurality of n-channel MOSFETs having a trench gate structure having the structure of the silicon carbide semiconductor device of the first embodiment described above are prepared (hereinafter referred to as Example 1). The first distance X1 of each sample of Example 1 is different. + The aluminum dosage of the high concentration region 51' is set to 5.15×10 15 / cm 2 .

[0174] For each sample of Example 1, a gate voltage Vg (negative gate bias) of -5V was applied to the gate electrode 28 for a predetermined application time in a high temperature atmosphere of 200°C with the source 31 and the drain 33 grounded. Then, a negative gate bias was applied to the gate electrode 28 for an arbitrary application time, and a positive gate bias was applied to the gate electrode 28 at room temperature to conduct the power-on and measure the positive gate bias, and the time-dependent change of the positive gate bias from the initial state for 1000 hours was observed. The application time of the negative gate bias applied to the gate electrode 28 was increased at a predetermined time from 0 hours (initial state) to 1000 hours.

[0175] When the leakage current Id reaches one thousandth of the rated current Id1 / I0 (=10 -3 ) of the first measurement point (equivalent to Fig.26 The symbol 171) and the current amount of the leakage current Id become the current amount Id2 / I0 (=10 -9 ) of the second measurement point (equivalent to Fig.26 The change of the gate forward bias voltage over time from the initial state is observed by comparing the maximum value of the change ΔVg of the gate forward bias voltage corresponding to the current amount of the drain current Id at the first measurement point and the second measurement point relative to the initial state. Figure 8 .exist Figure 8 The sample with the first distance X1 set to 0.0 μm is equivalent to p + Type high concentration region 151 and n + The existing structure of the source region 124 contact type (refer to Figure 21 to Figure 25 ).

[0176] according to Figure 8 The results shown in the figure confirm that at the first measurement point and the second measurement point, by + Type high concentration area 51 to n +The first distance X1 of the source region 24 is set to be greater than 0.6 μm, which can reduce the change ΔVg of the gate forward bias voltage relative to the initial state corresponding to the current amount of the leakage current Id compared to the existing structure. Reducing the change ΔVg of the gate forward bias voltage relative to the initial state means reducing the absolute value of the change ΔVg of the gate forward bias voltage relative to the initial state. Specifically, if the first distance X1 is set to be greater than 0.6 μm, for example, even at the second measurement point where the gate forward bias voltage is closer to the gate threshold voltage Vth than the first measurement point, the change ΔVg of the gate forward bias voltage relative to the initial state corresponding to the current amount of the leakage current Id can be reduced from -1.45 V (the sample of the data point represented by the symbol 71) of the existing structure to about -0.8 V (the sample of the data point surrounded by the circle of the symbol 72).

[0177] Although the illustration is omitted, even if the second direction Y is from p + When the second distance Y1 from the high concentration region 51 to the outermost trench 26 is set to 0.6 μm or more, the same Figure 8 The results shown are the same results.

[0178] As described above, according to Embodiment 1, in the first direction, + The p-type source region is separated from the outermost trench in the second direction, or is separated from both of them to form a boundary region between the active region and the edge termination region. + Type high concentration region. In the first direction, it is p + Type high concentration area and n + The portion sandwiched by the type source region, or the portion sandwiched by the p + The portion sandwiched between the p-type high concentration region and the outermost trench, or both portions, is the portion of the p-type silicon carbide epitaxial layer exposed on the front surface of the semiconductor substrate. As a result, the portion of the p-type base region extension adjacent to the gate insulating film is a p-type silicon carbide epitaxial layer without crystal defects. Therefore, it is possible to suppress the generation of hole traps caused by crystal defects in the gate insulating film during thermal oxidation of the gate insulating film.

[0179] By suppressing the generation of hole traps in the gate insulating film in this way, when a negative gate bias is applied to the gate electrode under high temperature conditions, it is possible to suppress the accumulation of holes at the interface between the p-type base region and the gate insulating film. Thus, even if a negative gate bias is applied to the gate electrode to maintain the off state under high temperature conditions, the change in the gate positive bias corresponding to the predetermined current amount of the leakage current relative to the initial state can be reduced. In addition, when a gate voltage of less than 0V is applied to the gate electrode to maintain the off state, the current amount of the drain cutoff current can be made close to that in the initial state. Therefore, it is possible to suppress the gain curve of the leakage current from shifting in the negative direction of the gate voltage compared to the initial state, and the current controllability based on the gate voltage control can be improved.

[0180] (Implementation Method 2)

[0181] Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. Fig. 9 FIG. 1 is a plan view showing a layout of a portion of a silicon carbide semiconductor device according to Embodiment 2, as viewed from the front side of a semiconductor substrate. Fig. 9 In the figure, Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in the first embodiment. Fig. 9 The cross-sectional structure at the cutting line C-C' is Figure 4 The structure obtained by replacing the symbol X1 with X1'. Fig. 9 The cross-sectional structure at the cutting line D-D' is Figure 5 same.

[0182] The silicon carbide semiconductor device of the second embodiment is different from the silicon carbide semiconductor device of the first embodiment in the following two points. The first difference is that the silicon carbide semiconductor device in the first direction X is + Type high concentration area 51 to n + The first distance X1′ of the type source region 24 is greater than the distance from the p + The second distance Y1 from the high concentration region 51 to the outermost trench 26 is wider (X1'>Y1). The second difference is that the p is arranged so that the conditions of the first distance X1' and the second distance Y1 are satisfied. + Type high concentration region 51. The first distance X1' can be set to, for example, 9.35 μm or more, and the second distance Y1 can be set to, for example, 0.6 μm or more.

[0183] (Example 2)

[0184] Next, the first distance X1 ′ and the second distance Y1 of the silicon carbide semiconductor device according to the second embodiment are verified. Fig.103 is a characteristic diagram showing the results of verifying the first distance of Example 2. Fig.10 The horizontal axis is the first direction X from p + Type high concentration area 51 to n + The vertical axis is the maximum value of the change in the gate forward bias voltage ΔVg generated within a predetermined time period when the change in the gate forward bias voltage over time is observed. First, a plurality of n-channel MOSFETs having a trench gate structure having the structure of the silicon carbide semiconductor device of the second embodiment described above are fabricated (hereinafter referred to as Example 2).

[0185] The first distance X1' of each sample of Example 2 is different. The second distance Y1 of all samples of Example 2 is set to 1.6 μm. The rated current of each sample of Example 2 is the same as that of Example 1. + The dosage of the high concentration region 51 is the same as that of Example 1. Then, for each sample of Example 2, the time-dependent change of the gate forward bias voltage from the initial state is observed at the first measurement point and the second measurement point, respectively, as in Example 1, and the maximum value of the change ΔVg of the gate forward bias voltage from the initial state corresponding to the predetermined current amount of the drain current Id is compared. The results are shown in FIG. Fig.10 .

[0186] according to Fig.10 The results shown confirm that in Example 2, in the sample in which the second distance Y1 is set to 1.6μm and the first distance X1' is set to 9.35μm or more, even at the second measurement point where the gate forward bias is closer to the gate threshold voltage Vth than the first measurement point, the change ΔVg of the gate forward bias corresponding to the current amount of the leakage current Id at the second measurement point relative to the initial state can be reduced to the level of -0.75V (sample of the data point represented by symbol 73) to -0.4V (sample of the data point surrounded by the circle of symbol 74).

[0187] As described above, if the second distance Y1 is 0.6 μm or more, the effect of reducing the change ΔVg of the gate forward bias voltage relative to the initial state corresponding to the predetermined current amount of the drain current Id is obtained (see Fig. 9 ). Therefore, it can be seen that in Example 2, if the first distance X1' is greater than 9.35 μm and the second distance Y1 is greater than 0.6 μm, then Fig.10 Similarly to the results shown, the change ΔVg of the gate forward bias voltage corresponding to the current amount of the drain current Id at the second measurement point from the initial state can be reduced to approximately -0.4V.

[0188] As described above, according to the second embodiment, even when the first distance is wider than the second distance, the same effects as those of the first embodiment can be obtained.

[0189] (Implementation method 3)

[0190] Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. Fig.11 FIG. 1 is a plan view showing a layout of a portion of a silicon carbide semiconductor device according to Embodiment 3, as viewed from the front side of a semiconductor substrate. Fig.11 It is shown in Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in the first embodiment. Fig.11 The cross-sectional structures at the cutting line C-C' and the cutting line D-D' are Figure 4 , Figure 5 The structure obtained by replacing the symbol 51 with 51'.

[0191] The silicon carbide semiconductor device of the third embodiment is different from the silicon carbide semiconductor device of the first embodiment in that the p + The dose of the high concentration area 51'. + Type high concentration area 51' to n + When the first distance X1 of the type source region 24 is, for example, 0.6 μm or more, p + The dosage of the high concentration region 51', for example, with aluminum as the dopant, can be 6.4×10 14 / cm 2 The following degree.

[0192] In p + The dosage of the high concentration region 51' is, for example, 3.4×10 14 / cm 2 In the case of the following degree, p + The high concentration region 51' can be combined with the existing structure (refer to Figure 21 to Figure 25 ) Similarly with n + Type source region 24 is in contact.

[0193] (Example 3)

[0194] Next, the silicon carbide semiconductor device according to the third embodiment is + The dosage of the high concentration area 51' is verified. Fig.12 is the p of Example 3 + The dose in the high concentration area was verified in the characteristic diagram. Fig.12 The horizontal axis is the first direction X from p + Type high concentration area 51' to n +The vertical axis is the maximum value of the change in the gate forward bias voltage ΔVg generated within a predetermined time period while observing the time-dependent change in the gate forward bias voltage. First, a plurality of n-channel MOSFETs having a trench gate structure having the structure of the silicon carbide semiconductor device of the third embodiment described above are fabricated (hereinafter referred to as Example 3).

[0195] In each first sample 81 of Example 3, the first distance X1 is 0.6 μm or more and is different from that in Example 1. Based on the mechanism of the shift of the gain curve of the leakage current Id described above, it is inferred that the shift of the gain curve of the leakage current Id also depends on the point defect density. Therefore, the p of each first sample 81 of Example 3 is + The aluminum dosage of the high concentration region 51' is set to p + The aluminum dose of the high concentration region 51 (=5.15×10 15 / cm 2 ) (=6.4×10 14 / cm 2 The rated current of each first sample 81 of Example 3 is the same as that of Example 1.

[0196] In addition, it will make p + Type high concentration region 51' and n + The structure of the first distance X1 = 0 μm, and p + The aluminum dosage of the high concentration region 51' is set to p + The aluminum dosage of the high concentration region 51 is 1 / 15 (=3.4×10 14 / cm 2 ) is used as the second sample 82 of Example 3. The second sample 82 of Example 3 has the following characteristics except for the first distance X1 and p + The configuration other than the dosage of the type high concentration region 51 is the same as that of the first sample 81 of Example 3.

[0197] For each of the first sample 81 and the second sample 82 of Example 3, the time-dependent change of the gate forward bias voltage from the initial state was observed at the first measurement point and the second measurement point, respectively, as in Example 1, and the maximum values ​​of the change ΔVg of the gate forward bias voltage corresponding to the current amount of the drain current Id at the first measurement point and the second measurement point from the initial state were compared. The results are shown in FIG. Fig.12 .exist Fig.12 In the example 1, the results (refer to Figure 8 ) as the “first measurement point, second measurement point”, and the results of the first sample 81 and the second sample 82 of Example 3 are taken as the “first measurement point, second measurement point (dose reduction)”.

[0198] according to Fig.12As shown in the results, in the conventional structure, the change ΔVg of the gate forward bias voltage corresponding to the current amount of the leakage current Id at the second measurement point relative to the initial state is -1.45V (data point 71). In contrast, it was confirmed that even in the second sample 82 of Example 3 in which the first distance X1 is 0μm, the change ΔVg of the gate forward bias voltage corresponding to the current amount of the leakage current Id at the second measurement point relative to the initial state can be reduced to -0.095V. In addition, in the first sample 81 of Example 3 in which the first distance X1 is set to 0.6μm or more, it was confirmed that by + The dose of the high concentration region 51' is set to p + By using a dose of 1 / 8 of the dose of the type high concentration region 51, the change ΔVg of the gate forward bias voltage corresponding to the current amount of the drain current Id at the second measurement point relative to the initial state can be reduced to -0.090V to 0.098V.

[0199] As described above, according to Embodiment 3, even when p is reduced + Even in the case of a type high concentration region with a dosage, the same effects as those in embodiments 1 and 2 can be obtained.

[0200] (Implementation 4)

[0201] Next, the structure of the silicon carbide semiconductor device according to the fourth embodiment will be described. Fig.13 FIG. 1 is a plan view showing a layout of a portion of a silicon carbide semiconductor device according to Embodiment 4 as viewed from the front side of a semiconductor substrate. Fig.13 It is shown in Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in the first embodiment. Fig.13 The cross-sectional structure at the cutting line C-C' is Figure 4 The structure is obtained by replacing the symbols 51 and X1 with 51' and X1' respectively. Fig.13 The cross-sectional structure at the cutting line D-D' is Figure 5 The structure obtained by replacing the symbol 51 with 51'.

[0202] The silicon carbide semiconductor device of the fourth embodiment is different from the silicon carbide semiconductor device of the second embodiment in that the p-type semiconductor layer constituting the boundary region 3 is + The dosage of the type high concentration region 51' is lower than that of the second embodiment. That is, the silicon carbide semiconductor device of the fourth embodiment is obtained by applying the p-type high concentration region 51' of the third embodiment to the structure of the silicon carbide semiconductor device of the second embodiment. +When the first distance X1' is set to, for example, 9.35 μm or more, and the second distance Y1 is set to, for example, 0.6 μm or more, p + The dosage of the high concentration region 51' can be, for example, 1.03×10 15 / cm 2 The following degree.

[0203] (Example 4)

[0204] Next, the silicon carbide semiconductor device of the fourth embodiment is + The dosage of the high concentration area 51' is verified. Fig.14 is the p of Example 4 + The dose in the high concentration area was verified in the characteristic diagram. Fig.14 The horizontal axis is the first direction X from p + Type high concentration area 51' to n + The vertical axis is the maximum value of the change in the gate forward bias voltage ΔVg generated within a predetermined time period when the time-dependent change in the gate forward bias voltage is observed. First, a plurality of n-channel MOSFETs having a trench gate structure having the structure of the silicon carbide semiconductor device of the fourth embodiment described above are fabricated (hereinafter referred to as Example 4).

[0205] The first distance X1' of the first sample 83 of Example 4 is the same as that of the sample of data point 73 of Example 2. The second distance Y1 of the first sample 83 of Example 4 is set to 1.6 μm. + The dose of the high concentration region 51' is set to p + The dose of the high concentration area 51 (=5.15×10 15 / cm 2 ) (=6.4×10 14 / cm 2 ). The rated current of the first sample 83 of Example 4 is the same as that of Example 2. + The dopant of the ion implantation 62 of the high concentration region 51 ′ is the same as that of the second embodiment.

[0206] In addition, the p + The dose of the high concentration region 51' is p + 1 / 5 of the dose in the high concentration region 51 (=1.03×10 15 / cm 2 ) is used as the second sample 84 of Example 4. Each second sample 84 of Example 4 is different from each sample of the data point 74 of Example 2. The second sample 84 of Example 4 has the following characteristics except for the first distance X1′ and p+ The configuration other than the dosage of the type high concentration region 51 ′ is the same as that of the first sample 83 of Example 4.

[0207] For each of the first sample 83 and the second sample 84 of Example 4, the time-dependent change of the gate forward bias voltage relative to the initial state was observed at the first measurement point and the second measurement point, respectively, as in Example 2, and the maximum values ​​of the change ΔVg of the gate forward bias voltage relative to the initial state corresponding to the current amount of the drain current Id at the first measurement point and the second measurement point were compared. The results are shown in FIG. Fig.14 .exist Fig.14 In the example 2, the results (refer to Fig.10 ) as the “first measurement point, second measurement point”, and the results of the first sample 83 and the second sample 84 of Example 4 as the “first measurement point, second measurement point (dose reduction)”.

[0208] according to Fig.14 The results shown confirm that in the second sample 84, the change ΔVg of the gate positive bias voltage corresponding to the current amount of the leakage current Id at the second measurement point relative to the initial state is reduced from about -0.4V (the sample with the data point surrounded by the circle of symbol 74) where the maximum reduction effect is obtained in Example 2 to the level of -0.085V to 0.098V.

[0209] As described above, according to the fourth embodiment, even if the p + When the conditions of the type high concentration region are applied to the configuration of the silicon carbide semiconductor device of the second embodiment, the same effects as those of the first and second embodiments can be obtained.

[0210] (Implementation method 5)

[0211] Next, the structure of the silicon carbide semiconductor device according to the fifth embodiment will be described. Fig.15 FIG. 1 is a top view showing the layout of a portion of a silicon carbide semiconductor device according to Embodiment 5, as viewed from the front side of a semiconductor substrate. Fig.15 It is shown in Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in the first embodiment. Fig.15 The cross-sectional structure at the cutting line D-D' is Figure 5 same. Fig.16 Yes means Fig.15 Cross-sectional view of the cross-sectional structure at the cutting line EE'.

[0212] The silicon carbide semiconductor device of the fifth embodiment is different from the silicon carbide semiconductor device of the second embodiment in that the trench 26 extending outward from the active region 1 in the first direction X does not reach the p + That is, the end of the trench 26 is located in the first direction X at the p-type base region extension portion 23'. + Type high concentration region 51 and n + The length of the trench 26 extending from the active region 1 to the outside in the first direction X can be varied so that the trench 26 does not reach the p-type source region 24. + type high concentration region 51, so that from p + Type high concentration area 51 to n + The first distance X11 of the source region 24 may be extended by an amount that allows the trench 26 to extend outward in the first direction X.

[0213] The structure of the silicon carbide semiconductor device of the fourth embodiment can be applied to the structure of the silicon carbide semiconductor device of the fifth embodiment. + Type high concentration area conditions.

[0214] As described above, according to the fifth embodiment, regardless of the terminal position of the trench extending outward from the active region in the first direction, the same effects as those of the first to fourth embodiments can be obtained.

[0215] (Implementation 6)

[0216] Next, the structure of the silicon carbide semiconductor device according to the sixth embodiment will be described. Fig.17 FIG. 1 is a plan view showing a layout of a portion of a silicon carbide semiconductor device according to Embodiment 6, as viewed from the front side of a semiconductor substrate. Fig.17 It is shown in Figure 1 The state of the active region 1 and the boundary region 3 near the corner of the semiconductor substrate 10 surrounded by a rectangular frame with vertices B and B' as diagonal vertices. The positions of the vertices B and B' corresponding to the semiconductor substrate 10 are the same as those in the first embodiment. Fig.15 The cross-sectional structure at the cutting line C-C' is Figure 4 same. Fig.18 Yes means Fig.17 Cross-sectional view of the cross-sectional structure at the cutting line F-F'.

[0217] The silicon carbide semiconductor device of the sixth embodiment is different from the silicon carbide semiconductor device of the first embodiment in that a second p-type base region extension 23' is provided at a portion exposed at the front surface 13a of the semiconductor substrate 10. + Specifically, the p-type base region extension portion 23' is formed by the p-type contact region (fifth semiconductor region) 25' in the first direction X. + Type high concentration region 51 and n +The portion sandwiched by the type source region 24, or the portion sandwiched by the p + The portion sandwiched between the type high concentration region 51 and the outermost trench 26, or the two portions are selectively provided with a second p + Type contact area 25'.

[0218] exist Fig.17 FIG. 2 shows that only the p-type base region extension 23′ is p-type in the second direction Y. + The portion sandwiched between the type high concentration region 51 and the outermost trench 26 is provided with second p-type high concentration regions dispersedly arranged in the first direction X at predetermined intervals. + Although not shown in the figure, the p-type base region extension portion 23' is p-type in the first direction X. + Type high concentration region 51 and n + The portion sandwiched by the type source region 24 is configured as a second p + In the case of the p-type contact region 25', for example, the active region 1 + Type contact area (hereinafter referred to as the first p + The second p-type contact areas) 25 are dispersedly arranged in the first direction X at the same predetermined intervals. + Type contact area 25' is sufficient.

[0219] Second p + The contact area 25' can be connected to the p + The second p + The conditions (impurity concentration and / or size, etc.) of the first p + The second p + The type contact region 25' is exposed in the boundary region 3 through a third contact hole 29c penetrating the interlayer insulating film 29 in the depth direction Z. The second p-type contact region 25' is exposed in the third contact hole 29c. + Type contact area 25'. The second p + The first p-type contact region 25' is + The type contact region 25 is similarly formed in the third contact hole 29c to make ohmic contact with the metal film 30.

[0220] The source electrode 31 is connected to the second p electrode via the metal film 30 in the third contact hole 29c. + The type contact region 25' is electrically connected via the second p + The p-type contact region 25' is electrically connected to the p-type base region extension 23'. +The p-type contact region 25' is formed, so that the effect of reducing the change ΔVg of the gate voltage Vg corresponding to the predetermined current amount of the drain current Id relative to the initial state is slightly reduced, but since the p-type impurity concentration of the p-type base region extension 23' is increased and the resistance is reduced, the avalanche resistance can be improved. Therefore, the second p-type base region is appropriately configured so that the change ΔVg of the gate voltage Vg corresponding to the predetermined current amount of the drain current Id relative to the initial state and the avalanche resistance both reach predetermined values. + Type contact area 25' is sufficient.

[0221] The second p of Embodiment 6 may also be + The structure of the type contact region is applicable to the structure of the silicon carbide semiconductor device of Embodiments 2 to 5.

[0222] As described above, according to the sixth embodiment, even if the second p-type base region is disposed in the portion of the p-type base region extension exposed on the front surface of the semiconductor substrate, + In the case of a p-type base region, the same effects as those of the first to fifth embodiments can be obtained. In addition, according to the sixth embodiment, by providing a second p-type base region extension portion, + Thus, the hole current (hereinafter referred to as avalanche current) flowing from the edge termination region to the active region side due to avalanche breakdown during the turn-off can also flow from the second p + The avalanche resistance can be improved.

[0223] (Implementation 7)

[0224] Next, the structure of the silicon carbide semiconductor device according to the seventh embodiment will be described. Fig.19 1 is a plan view showing the layout of the silicon carbide semiconductor device of the seventh embodiment as viewed from the front side of the semiconductor substrate. The silicon carbide semiconductor device of the seventh embodiment is different from the silicon carbide semiconductor device of the first embodiment in that one end of the trench 26' terminates in the active region 1. For example, the groups of the trenches 26' extending in a stripe shape in the first direction X may be arranged in two groups separated from each other in the active region 1 so as to be adjacent to each other in the first direction X.

[0225] One end of the trench 26' terminates at, for example, the central portion of the active region 1, and the other end terminates at the boundary region 3. The central portion of the active region 1 is formed by p + The ineffective region 4 is composed of a high concentration region. The region other than the ineffective region 4 of the active region 1 is the effective region. The ineffective region 4 is a region that does not function as a MOSFET, and the effective region is a region that functions as a MOSFET. + The formation method of the high concentration region and the p-type boundary region 3 +The type is the same as the high concentration area.

[0226] In the vicinity H of one end portion of the trench 26' which terminates in the active region 1, the same as in the first embodiment is also connected to n. + The p-type source region is separated from the ineffective region 4. + The first direction X from the ineffective area 4 p + Type high concentration area to n + The distance between the source region and the p-type source region in the first direction X from the boundary region 3 + Type high concentration area to n + The configuration of the trench 26' near the other end portion where the boundary region 3 ends is the same as that of the first embodiment.

[0227] The structure of the trench in the seventh embodiment can also be applied to the structures of the silicon carbide semiconductor devices in the second to sixth embodiments.

[0228] As described above, according to Embodiment 7, by + In the method of source region separation, a p-type gate is configured at the end of the trench constituting the trench gate structure. + type high concentration region, thereby being able to obtain the same effects as in embodiments 1 to 6.

[0229] (Example 5)

[0230] Next, the drain cutoff current (leakage current) Idss of the silicon carbide semiconductor device of Embodiment 3 is verified. The drain cutoff current Idss refers to the drain current Id when the source-drain voltage Vd is applied in a state where the gate-source is short-circuited (i.e., the gate voltage Vg=0V). First, a trench gate structured n-channel MOSFET having the structure of the silicon carbide semiconductor device of Embodiment 3 described above is fabricated (hereinafter referred to as Example 5).

[0231] In the fifth embodiment, the first distance X1 is fully extended to about 0.6 μm, so that p + The aluminum dosage of the high concentration region 51' is lower than that of the existing structure and is 6.4×10 14 / cm 2 , the gate threshold voltage Vth is reduced to 3V. For this Example 5, the drain cutoff current Idss is measured when the gate voltage Vg is 0V and the source-drain voltage Vd is 600V. In addition, as a comparison, the same conditions as in Example 5 are also used for the conventional structure (refer to Figure 21 to Figure 25 )Measure the drain cutoff current Idss.

[0232] In the conventional structure, it was confirmed that the drain cutoff current Idss greatly deviated over time within the range of 100pA to 100μA. In contrast, in Example 5, the drain cutoff current Idss varied over time within the range of 100pA to 1nA. That is, it was confirmed that even if p was reduced, + The aluminum dosage of the type high concentration region 51' can also reduce the drain off current Idss to a level that does not cause problems.

[0233] The silicon carbide semiconductor device of the fourth embodiment also achieves the same effects as those of the fifth embodiment.

[0234] (Example 6)

[0235] Next, the amount of hole current (avalanche current) Iav flowing from the edge termination region 2 toward the active region 1 side due to avalanche breakdown generated when the silicon carbide semiconductor device according to the second embodiment described above is turned off is verified. Fig. 20 1 is a characteristic diagram showing the relationship between the avalanche current Iav / I0 (I0 is the rated current) normalized to the first distance of Example 6. Fig. 20 The horizontal axis is the first direction X from p + Type high concentration area 51 to n + The first distance X1′ of the type source region 24, the vertical axis is the normalized avalanche current Iav / I0.

[0236] First, a plurality of n-channel MOSFETs having a trench gate structure having the structure of the silicon carbide semiconductor device of the second embodiment described above were produced (hereinafter referred to as Example 6). The first distance X1' of each sample of Example 6 was set to 0 μm, 9.35 μm, and 26 μm, respectively. For each sample of Example 6, the avalanche current Iav generated by avalanche breakdown at the time of shutdown was measured. The results are shown in Fig. 20 .exist Fig. 20 Among them, the sample in which the first distance X1' is 0.0 μm corresponds to the conventional structure.

[0237] according to Fig. 20 As shown in the results, in Example 6, although the normalized avalanche current Iav / I0 is reduced from 3.16 (the sample with the data points surrounded by the circle of symbol 75) of the existing structure to 2.84 (the sample with the data points surrounded by the circle of symbol 76), it is more than twice the rated current and is a level that does not cause problems in actual use.

[0238] Although not shown in the figure, the silicon carbide semiconductor devices of Embodiments 1 and 3 to 7 also achieve the same effects as those of Example 6.

[0239] As mentioned above, the present invention is not limited to the above-mentioned embodiments, and various changes can be made within the scope of the main purpose of the present invention. For example, in the above-mentioned embodiments, MOSFET is used as an example, but it can also be applied to MOS-type silicon carbide semiconductor devices such as IGBTs having a trench gate structure. In addition, the present invention also makes the conductivity type (n-type, p-type) inverted.

[0240] Industrial Applicability

[0241] As described above, the silicon carbide semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices such as various industrial machines, and / or ignition devices for automobiles, and is particularly suitable for n-channel silicon carbide semiconductor devices.

Claims

1. A silicon carbide semiconductor device, characterized in that: have: An active region, which is provided on a semiconductor substrate of a first conductivity type having a first main surface and a second main surface and through which a main current flows; a termination region surrounding the active region; A second conductivity type epitaxial layer, which constitutes a part of the semiconductor substrate and forms the first main surface of the semiconductor substrate; A first semiconductor region of a first conductivity type, which is selectively provided in a surface layer on the first main surface side of the second conductivity type epitaxial layer in the active region; A second semiconductor region of the second conductivity type, which is selectively disposed in a surface layer on the first main surface side of the second conductivity type epitaxial layer in a boundary region between the active region and the terminal region, and has an impurity concentration higher than that of the second conductivity type epitaxial layer; A third semiconductor region of the second conductivity type, which is a portion of the second conductivity type epitaxial layer excluding the first semiconductor region and the second semiconductor region; A fourth semiconductor region of the first conductivity type, which is a portion of the semiconductor substrate excluding the second conductivity type epitaxial layer; a voltage-resistant structure, wherein, in the terminal region, the second conductivity type region is selectively provided on the surface layer of the first main surface side of the first conductivity type fourth semiconductor region, a trench penetrating the first semiconductor region and the third semiconductor region and reaching the fourth semiconductor region; a gate electrode disposed inside the trench via a gate insulating film; a first electrode electrically connected to the first semiconductor region and the third semiconductor region; as well as a second electrode provided on the second main surface of the semiconductor substrate, The second semiconductor region is configured in a manner separated from the first semiconductor region, extends from the active region side to the boundary between the terminal region and the boundary region and is directly connected to the voltage-resistant structure, and the entire surface of the second semiconductor region is covered by an insulating film provided on the first main surface of the semiconductor substrate, Between the second semiconductor region and the first semiconductor region, a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate.

2. The silicon carbide semiconductor device according to claim 1, wherein: The groove extends linearly in a first direction parallel to the first main surface of the semiconductor substrate. The second semiconductor region is arranged near an end portion of the trench so as to be separated from the first semiconductor region in the first direction.

3. The silicon carbide semiconductor device according to claim 2, wherein: A plurality of the trenches are arranged in a stripe shape extending from the active region to the boundary region in the first direction, The first semiconductor region is arranged between adjacent trenches. The second semiconductor region is arranged so as to be separated from the outermost trench of the plurality of trenches which is closest to the boundary region in a second direction which is parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction. Between the second semiconductor region and the outermost trench, a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate.

4. The silicon carbide semiconductor device according to claim 3, wherein: A portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate is arranged in the boundary region and surrounds the active region.

5. The silicon carbide semiconductor device according to claim 2, wherein: The first distance from the second semiconductor region to the first semiconductor region in the first direction is 0.6 μ m or more.

6. The silicon carbide semiconductor device according to claim 3 or 4, characterized in that: The second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μ m or more.

7. The silicon carbide semiconductor device according to claim 6, wherein: The first distance from the second semiconductor region to the first semiconductor region in the first direction is 9.35 μ m or more.

8. The silicon carbide semiconductor device according to claim 1, wherein: A plurality of the trenches are arranged in a stripe shape extending from the active region to the boundary region in a first direction parallel to the first main surface of the semiconductor substrate. The first semiconductor region is arranged between adjacent trenches. The second semiconductor region is arranged so as to be separated from the outermost trench of the plurality of trenches which is closest to the boundary region in a second direction which is parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction. Between the second semiconductor region and the outermost trench, a portion of the third semiconductor region of the second conductivity type epitaxial layer is exposed on the first main surface of the semiconductor substrate.

9. The silicon carbide semiconductor device according to claim 8, wherein: The second distance from the second semiconductor region to the outermost trench in the second direction is 0.6 μ m or more.

10. The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein: The impurity concentration of the second semiconductor region is 6.4×10 14 / cm 2 the following.

11. The silicon carbide semiconductor device according to claim 2, wherein: The trench extends from the active region to the boundary region and terminates at a position closer to the active region than the second semiconductor region.

12. The silicon carbide semiconductor device according to any one of claims 1 to 11, characterized in that: The silicon carbide semiconductor device further includes a fifth semiconductor region of the second conductivity type, the fifth semiconductor region being selectively provided in a portion of the third semiconductor region exposed on the first main surface of the semiconductor substrate and having an impurity concentration higher than that of the third semiconductor region. The third semiconductor region is electrically connected to the first electrode via the fifth semiconductor region.

13. The silicon carbide semiconductor device according to claim 12, wherein: The fifth semiconductor region is a diffusion region formed by ion implantation of second conductivity type impurities into the second conductivity type epitaxial layer.

14. The silicon carbide semiconductor device according to any one of claims 1 to 13, wherein: The second semiconductor region is a diffusion region formed by ion implantation of second conductivity type impurities into the second conductivity type epitaxial layer.

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