A chip structure and its fabrication and testing method

Abstract

This application provides a chip structure and its fabrication and testing method, relating to the field of semiconductor technology. The chip structure includes multiple functional layers and functional electrodes connected layer by layer to a substrate; the functional electrodes are disposed on the side of the functional layers away from the substrate; wherein any one of the multiple functional layers has a via; the chip structure also includes a detection electrode mounted in the via. The chip structure and its fabrication and testing method provided in this application are capable of distinguishing the defect properties, physical mechanisms, and impacts on chip characteristics of different functional layers.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a chip structure and its fabrication and testing method. Background Technology

[0002] The epitaxial structure of a high electron mobility transistor (HEMT) contains many functional layers, each with different band structures, doping characteristics, defect distributions, and other properties, resulting in a highly complex electrical mechanism. These properties can affect HEMT device characteristics, such as threshold stability, dynamic resistance, reverse leakage current, and breakdown characteristics.

[0003] Therefore, HEMT devices need to be tested and analyzed to determine the impact of each functional layer on device parameters.

[0004] Currently, the impact of bulk material defects on devices is generally analyzed by applying an external back potential, which involves applying a test voltage to the substrate. However, this type of test makes it difficult to distinguish the nature and impact mechanism of defects at different locations in the epitaxial layer. Summary of the Invention

[0005] The purpose of this invention is to provide a chip structure and its fabrication and testing method to solve the problem of difficulty in distinguishing the defect nature and impact mechanism of different functional layers in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, this application provides a chip structure, the chip structure comprising:

[0008] Substrate;

[0009] A plurality of functional layers and functional electrodes are connected layer by layer to the substrate; the functional electrodes are disposed on the side of the functional layer away from the substrate; wherein, any one of the plurality of functional layers is provided with a through hole;

[0010] A detection electrode is mounted in the through hole.

[0011] Furthermore, each of the multiple functional layers has through holes around its perimeter, and the detection electrodes are laid on the surface of each through hole.

[0012] Furthermore, the plurality of functional layers include a buffer layer, a stress relief layer, a high-resistivity layer, a channel layer, a barrier layer, and a capping layer, wherein the substrate, the buffer layer, the stress relief layer, the high-resistivity layer, the channel layer, the barrier layer, and the capping layer are stacked layer by layer.

[0013] Furthermore, all of the multiple functional layers are nitride functional layers.

[0014] Furthermore, the material used to fabricate the buffer layer includes AlN, the material used to fabricate the stress relief layer includes AlGaN, the material used to fabricate the high-resistivity layer includes GaN, the material used to fabricate the channel layer includes GaN, the material used to fabricate the barrier layer includes AlGaN, and the material used to fabricate the capping layer includes GaN.

[0015] Secondly, this application also provides a method for fabricating a chip structure, the method comprising:

[0016] Provide a substrate;

[0017] Multiple functional layers are sequentially epitaxially grown along the substrate;

[0018] A through-hole is fabricated in any one of the plurality of functional layers;

[0019] A detection electrode is fabricated on the via, and a functional electrode is fabricated in one of the plurality of functional layers away from the substrate.

[0020] Furthermore, the step of creating a through-hole in any one of the plurality of functional layers includes:

[0021] Multiple functional layers around the chip structure are etched to reach the target functional layer.

[0022] Thirdly, this application also provides a chip performance testing method, which is applied to the above-mentioned chip structure, and the method includes:

[0023] Control the chip structure to be in different working states;

[0024] A detection voltage is applied to the detection electrode to test the operating characteristics of the chip structure.

[0025] Further, the step of applying a detection voltage to the detection electrode to test the operating characteristics of the chip structure includes:

[0026] A detection voltage is applied to both the detection electrode and the substrate to test the operating characteristics of the chip structure.

[0027] Compared with the prior art, this application has the following advantages:

[0028] This application provides a chip structure and its fabrication and testing method. The chip structure includes a substrate and multiple functional layers and functional electrodes connected layer by layer to the substrate. The functional electrodes are disposed on the side of the functional layers away from the substrate. Any one of the multiple functional layers has a via. A detection electrode is mounted in the via. Because a via can be disposed in any functional layer in the chip structure provided by this application, when the chip structure is in a conductive or cutoff state, a test voltage can be applied to the test electrode of any functional layer to distinguish the defect nature and influence mechanism of different functional layers.

[0029] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a cross-sectional view of the chip structure provided in an embodiment of this application.

[0032] Figure 2 This is a schematic flowchart illustrating a chip structure fabrication method provided in an embodiment of this application.

[0033] Figure 3 This is another illustrative flowchart of a chip structure fabrication method provided in an embodiment of this application.

[0034] Figure 4 This is a schematic flowchart of a chip performance testing method provided in an embodiment of this application.

[0035] Figure 5 Another illustrative flowchart of the chip performance testing method provided in the embodiments of this application.

[0036] In the diagram: 100 - chip structure; 110 - substrate; 120 - buffer layer; 130 - stress relief layer; 140 - high resistivity layer; 150 - channel layer; 160 - barrier layer; 170 - capping layer; 180 - functional electrode; 190 - detection electrode; 200 - via. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0039] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0043] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0044] First Embodiment

[0045] As described in the background section, current analysis of chip structures generally involves using an external back potential to analyze the impact of bulk material defects on the device, i.e., applying a test voltage to the substrate for testing. However, this type of test makes it difficult to distinguish the nature and impact mechanism of defects at different locations in the epitaxial layer.

[0046] When the device is in the reverse turn-off state, the high electric field will also extend vertically into the entire epitaxial layer. Dislocations, defects and heterojunction structures in the material will cause charge charging and discharging, which will affect the device performance.

[0047] Understandably, different epitaxial layers have varying crystal quality, defect distribution, doping concentration, bandgap, surface roughness, polarization, and other factors, resulting in a complex superposition effect on the operating characteristics of HEMT devices. Therefore, applying voltage to different functional layers will affect device performance to varying degrees.

[0048] In view of this, this application provides a chip structure that, by setting vias and detection electrodes on different functional layers, enables the application of voltage on different electrodes, and then analyzes the defect distribution and physical mechanism of different epitaxial layers by detecting changes in the characteristics of the detection device.

[0049] As one possible implementation of this application, please refer to Figure 1 The chip structure 100 includes a substrate 110, multiple functional layers, functional electrodes 180, and detection electrodes 190. The substrate 110 is connected to the multiple functional layers one by one, and the functional electrodes 180 are disposed on the side of the functional layer away from the substrate 110. Any one of the multiple functional layers is provided with a through-hole 200, and the detection electrode 190 is mounted in the through-hole 200.

[0050] In fabricating the chip structure 100, a functional layer is first epitaxially layered on the substrate 110, and vias 200 are fabricated, along with corresponding electrodes. This allows for the study of defect properties and influence mechanisms at different locations of the epitaxial layer by applying voltages to different functional layers, facilitating the operation for staff.

[0051] It should be noted that, as a possible implementation of this application, the substrate 110 described in this application can be any one of sapphire substrate, silicon substrate, silicon carbide substrate, diamond substrate, and gallium nitride homopolymer substrate, and various functional layers are epitaxially grown on the substrate 110. This application does not impose any limitations on this.

[0052] Furthermore, the chip structure 100 provided in this application can be a HEMT structure, that is, the multiple functional layers described in this application include a buffer layer 120, a stress relief layer 130, a high resistivity layer 140, a channel layer 150, a barrier layer 160, and a capping layer 170. The substrate 110, the buffer layer 120, the stress relief layer 130, the high resistivity layer 140, the channel layer 150, the barrier layer 160, and the capping layer 170 are stacked layer by layer, and a gate electrode, a source electrode, and a drain electrode are disposed on the capping layer 170.

[0053] In one possible implementation of this application, the multiple functional layers provided are all nitride functional layers. For example, the buffer layer 120 is made of AlN, the stress relief layer 130 is made of AlGaN, the high-resistivity layer 140 is made of GaN, the channel layer 150 is made of GaN, the barrier layer 160 is made of AlGaN, and the capping layer 170 is made of GaN. Of course, it is understood that the various functional layers of this application can also be made of other materials, such as binary to quaternary compounds of Al, In, Ga, or N. This application does not limit the materials of each functional layer, as long as the normal operation of the chip structure 100 can be achieved.

[0054] Furthermore, when fabricating the via 200, etching is actually performed along the direction from the capping layer 170 to the substrate 110 to expose the target layer. For example, when it is necessary to determine the effect of applying voltage to the channel layer 150 on device performance, part of the capping layer 170 and the barrier layer 160 can be etched away to expose the channel layer 150, and a detection electrode 190 can be fabricated on the channel layer 150. However, when the chip is in a conducting or cut-off state, a voltage is applied to the detection electrode 190 to detect the effect of applying voltage to the channel layer 150 on device performance.

[0055] As one possible implementation of this application, to test the effect of different functional layers on device performance after applying voltage, multiple chip structures 100 can be fabricated simultaneously, and the vias 200 of each chip structure 100 are disposed on different functional layers. For example, the vias 200 can be disposed on any one of the following layers: buffer layer 120, stress relief layer 130, high-resistivity layer 140, channel layer 150, and barrier layer 160. This allows for a comparison of the effect of applying voltage to different functional layers on device performance.

[0056] Furthermore, as one implementation of this application, in order to achieve more uniform voltage application, when fabricating the vias 200, vias 200 are provided around the perimeter of any one of the multiple functional layers, and detection electrodes 190 are laid on the surface of each via 200. That is, the vias 200 are located around the perimeter of the chip structure 100, so that when voltage is applied, voltage can be applied evenly around the perimeter of the chip, resulting in more accurate results.

[0057] Furthermore, the study of the leakage mechanism of each functional layer and its impact on the device by applying voltages on different functional layers as described in this application includes, but is not limited to:

[0058] 1. Apply a high voltage to the detection electrode of the through hole to test the operating characteristics of the device.

[0059] 2. Apply a high voltage to the detection electrode of the via to test the substrate leakage current.

[0060] 3. Apply a scanning voltage to the detection electrode of the through hole, and change the scanning speed, polarity, and other conditions to test the working characteristics of the device.

[0061] 4. Test the capacitance-voltage (CV) curves between the detection electrode and the device electrode of the through hole, and analyze the device characteristics.

[0062] 5. Test the capacitance-voltage (CV) curve between the detection electrode and the substrate of the through hole to analyze the material properties.

[0063] 6. Conduct various tests under varying temperature conditions.

[0064] Second Embodiment

[0065] Please see Figure 2 This application also provides a method for fabricating a chip structure, the method comprising:

[0066] S101 provides a substrate.

[0067] S102, multiple functional layers are sequentially epitaxially grown along the substrate.

[0068] S103, create a through-hole in any of the multiple functional layers.

[0069] S104, a detection electrode is fabricated on the via, and a functional electrode is fabricated in one of the multiple functional layers away from the substrate.

[0070] Please refer to Figure 3 S103 may include:

[0071] S1031 etches multiple functional layers around the chip structure to etch down to the target functional layer.

[0072] Of course, when fabricating functional electrodes and detection electrodes, the following can be considered:

[0073] Deposit source and drain metals and alloys to form ohmic contacts, deposit gate dielectric layer, deposit gate metal layer, deposit through-hole metal and form contacts.

[0074] Furthermore, the method also includes depositing a passivation layer, which is not limited in this application.

[0075] It should be noted that in some other embodiments, the steps of the chip structure fabrication method may be changed. In this regard, the present embodiment does not limit the steps of the chip structure fabrication method. Any changes to the steps made in other embodiments should be included within the protection scope of the present invention.

[0076] Third Embodiment

[0077] Please see Figure 4 This application also provides a chip performance testing method, which is applied to the chip structure described in the first embodiment, and the method includes:

[0078] S201, control the chip structure to be in different working states.

[0079] S202, a detection voltage is applied to the detection electrode to test the operating characteristics of the chip structure.

[0080] The chip structure's operating states include on and off states. When the chip structure is in different operating states, voltages can be applied to different functional layers or substrates to test the impact on device performance. The operating characteristics of the chip structure include, but are not limited to, the chip's leakage current, threshold voltage, and turn-on current.

[0081] Furthermore, since the current can flow towards the capping layer or the substrate after a voltage is applied functionally, when analyzing the effect of the voltage on the device, it is only necessary to use the current direction as flowing towards the capping layer.

[0082] In view of this, in order to reduce the impact of current flowing to the substrate, please refer to the following in this application: Figure 5 S202 can be:

[0083] A detection voltage is applied to both the detection electrode and the substrate to test the operating characteristics of the chip structure.

[0084] By applying a detection voltage to both the detection electrode and the substrate simultaneously, an equipotential can be formed between the functional layer on which the detection electrode is located and the substrate. Consequently, when a voltage is applied to the detection electrode, the current flows only towards the capping layer, resulting in better performance.

[0085] In summary, this application provides a chip structure and its fabrication and testing method. The chip structure includes a substrate and multiple functional layers and functional electrodes connected layer by layer to the substrate. The functional electrodes are disposed on the side of the functional layers away from the substrate. Any one of the multiple functional layers has a via. A detection electrode is mounted in the via. Because a via can be disposed in any functional layer in the chip structure provided by this application, when the chip structure is in a conductive or cutoff state, a test voltage can be applied to the test electrode of any functional layer to distinguish the defect nature and influence mechanism of different functional layers.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0087] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A chip structure, characterized by The chip structure comprises: a substrate; a plurality of functional layers and functional electrodes connected to the substrate layer by layer; the functional electrodes are arranged on the side of the functional layers away from the substrate; wherein at least one of the plurality of functional layers is provided with a through hole; the plurality of functional layers comprises a buffer layer, a stress release layer, a high resistance layer, a channel layer, a barrier layer and a cap layer, and the substrate, the buffer layer, the stress release layer, the high resistance layer, the channel layer, the barrier layer and the cap layer are stacked layer by layer; a detection electrode is installed in the through hole, the through hole is arranged on one side of the chip structure, the surface of the through hole is paved with the detection electrode, and when a voltage is applied, the voltage can be applied to the whole side of the chip; the functional electrodes are drain, gate and source, and the detection electrode is an electrode independent of the functional electrodes; when the through hole is made, etching is performed in the direction from the cap layer to the substrate to expose a target layer, and the detection electrode is made on the target layer; by arranging the through hole and the detection electrode on different functional layers, a voltage can be applied to different detection electrodes, and by detecting the change of device characteristics, the defect distribution and physical mechanism of different epitaxial layers can be analyzed.

2. The chip structure of claim 1, wherein, The plurality of functional layers are nitride functional layers.

3. The chip structure of claim 2, wherein, The material for making the buffer layer includes AlN, the material for making the stress release layer includes AlGaN, the material for making the high resistance layer includes GaN, the material for making the channel layer includes GaN, the material for making the barrier layer includes AlGaN, and the material for making the cap layer includes GaN.

4. A method of fabricating a chip structure, characterized by, The method is used for making the chip structure of any one of claims 1 to 3, and the method comprises: providing a substrate; extending a plurality of functional layers on the substrate layer by layer; the plurality of functional layers comprises a buffer layer, a stress release layer, a high resistance layer, a channel layer, a barrier layer and a cap layer, and the substrate, the buffer layer, the stress release layer, the high resistance layer, the channel layer, the barrier layer and the cap layer are stacked layer by layer; making a through hole in at least one of the plurality of functional layers; when the through hole is made, etching is performed in the direction from the cap layer to the substrate to expose a target layer; making a detection electrode in the through hole, the detection electrode is made on the target layer, and a functional electrode is made on a layer of the plurality of functional layers away from the substrate; the functional electrode is drain, gate and source, the detection electrode is an electrode independent of the functional electrode, the through hole is arranged on one side of the chip structure, the surface of the through hole is paved with the detection electrode, and when a voltage is applied, the voltage can be applied to the whole side of the chip.

5. A method of testing the performance of a chip, characterized by, The method is applied to the chip structure of any one of claims 1 to 3, and the method comprises: controlling the chip structure to be in different working states; applying a detection voltage to the detection electrode to test the working characteristics of the chip structure.

6. The method of claim 5, wherein the test signal is a pulse signal. The step of applying a detection voltage to the detection electrode to test the working characteristics of the chip structure comprises: A detection voltage is applied to both the detection electrode and the substrate to test the operating characteristics of the chip structure.

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