A CMOS image sensor pixel circuit and pixel matrix

Abstract

The present application proposes a CMOS image sensor pixel circuit and a pixel matrix. The CMOS image sensor pixel circuit includes a detection unit, which is electrically connected to a node FD to detect whether the charge amount on the node FD reaches a preset threshold value. If it is detected that the charge amount on the node FD reaches the set threshold value, the connection with the node FD is electrically disconnected, and the node FD always maintains the original charge amount until the next recovery signal is triggered to restore the electrical connection between the detection unit and the node FD. Such a design reduces the risk of overexposure of the CMOS image sensor pixel circuit.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a pixel circuit and a pixel matrix of a CMOS image sensor. Background Art

[0002] In recent years, the application scope of image sensors has become increasingly wide. In addition to conventional applications such as telescopes or digital cameras, image sensors are also being used in many fields such as security monitoring, face recognition, and 3D image modeling. Compared with traditional CCD image sensors, the advantages of CMOS image sensors (CIS) in terms of low power consumption and high integration have become increasingly obvious due to the increasingly mature development of semiconductor process technology.

[0003] CMOS image sensors are essentially a matrix composed of a large number of single-point pixels. The structure of a single-point pixel is as follows: Figure 1 As shown. The photosensitive element at each pixel converts the light signal sensed by that point into an electrical signal, which is then collected and amplified by the reading circuit and converted into a digital signal through the analog-to-digital converter (ADC). In order to improve the output signal-to-noise ratio of the ADC, a larger signal amplification factor is usually selected or the exposure time of the photosensitive element is increased, thereby achieving the purpose of increasing the amplitude of the ADC input signal.

[0004] Because CMOS image sensors are composed of a large number of single-point pixels, pixels at different locations perceive different amplitudes of light signals. Even for the same pixel, the amplitude of the perceived light signal will change with the change of the ambient light intensity. If all pixels use a unified and fixed magnification and exposure time, it is difficult to ensure that every pixel in the pixel matrix will not be overwhelmed by ADC noise at every moment due to too small amplification, nor will it cause the photosensitive element to be overexposed due to too long exposure time. As the size of the pixel matrix increases, if the magnification or exposure time of each pixel is not uniform, then the hardware configuration required to store (store) this information and realize single-point control is often so large that the system is unacceptable, and the complexity of the matrix connection will also increase exponentially.

[0005] Therefore, the industry is in urgent need of a more efficient CMOS sensor solution. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a CMOS image sensor pixel circuit and a pixel matrix equipped with the pixel circuit, wherein the CMOS image sensor pixel circuit has an anti-overexposure function. The pixel circuit can flexibly control each pixel point to accumulate as much charge as possible without overexposure, thereby effectively improving the output signal-to-noise ratio of the CMOS image sensor.

[0007] In order to achieve the above object, the present invention adopts the following technical scheme:

[0008] A CMOS image sensor pixel circuit, characterized in that it includes a detection unit, which is electrically connected to a node FD and is used to detect whether the charge amount on the node FD reaches a preset threshold value. If it is detected that the charge amount on the node FD reaches the set threshold value, the connection with the FD is electrically disconnected, and the original charge amount on the FD is always maintained until the electrical connection with the FD is restored when a recovery signal is triggered next time.

[0009] Preferably, the detection unit comprises at least one switch, wherein the switch has a first end, a second end, and a third end.

[0010] The first end is electrically connected to the node FD, the second end is electrically connected to the drain end of the MOS switch M14, the third end is electrically connected to the control end, and the third end electrically disconnects the first end from the second end based on the received signal until it receives the next recovery signal.

[0011] Preferably, the detection unit comprises a MOS switch M15 and a capacitor C2, wherein:

[0012] The gate terminal of the MOS switch M15 is electrically connected to a node pdb, and the node pdb is electrically connected to one end of the capacitor C2.

[0013] The drain terminal of the MOS switch M15 is electrically connected to the source terminal of the MOS switch M13 and the node FD. The node FD is electrically connected to one end of the capacitor C1 and the gate terminal of the MOS switch M11.

[0014] The source terminal of the MOS switch M15 is electrically connected to the drain terminal of the MOS switch M14.

[0015] The other end of capacitor C2 is electrically connected to the equipotential terminal.

[0016] The MOS switch M15 is turned on or off based on a signal received at its gate terminal.

[0017] Preferably, the CMOS image sensor pixel circuit further comprises a MOS switch M16, a MOS switch M17, and a MOS switch M18, wherein:

[0018] The gate terminal of the MOS switch M15 is electrically connected to a node pdb, and the node pdb is electrically connected to a source terminal of the MOS switch M16, one end of the capacitor C2, and a drain terminal of the MOS switch M17.

[0019] The drain terminal of the MOS switch M15 is electrically connected to the node FD.

[0020] The drain terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M13 and the power supply terminal.

[0021] The source terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M17 and one end of the capacitor C2.

[0022] The gate terminal of the MOS switch M16 is electrically connected to the control module to receive a signal sent by the control module.

[0023] The source terminal of the MOS switch M17 is electrically connected to the drain terminal of the MOS switch M18.

[0024] The gate terminal of the MOS switch M17 is electrically connected to the control module to receive the marking signal sent by the control module.

[0025] The gate terminal of the MOS switch M18 is electrically connected to the control module to receive a signal sent by the control module.

[0026] Preferably, the capacitance of the capacitor C2 is positively correlated with the process leakage current of the pixel circuit of the CMOS image sensor.

[0027] Preferably, the pixel circuit of the CMOS image sensor includes a node pdb, at which the gate end of the MOS switch M16 receives a high-level rst signal, and after the charge of the pixel circuit is cleared, the node pdb is at a high level and the switch tube M15 is turned on.

[0028] Preferably, when the TX signal received by the gate terminal of the MOS switch M14 is high, the charge converted by the photosensitive element D is transferred to the node FD by the MOS switch tube M15.

[0029] Preferably, when the flag signal received by the gate end of the MOS switch tube M17 and the S signal received by the gate end of the MOS switch tube M18 are both high level, the switch tubes M17 and M18 are turned on at the same time, the pdb node is pulled to a low level, and the switch tube M15 is turned off and remains in the off state until the next reset rst signal becomes high level and can be turned on again.

[0030] Preferably, the pixel circuit of the CMOS image sensor is one of 4T-APS, 5T-APS, 6T-APS, 7T-APS, 8T-APS, and 9T-APS.

[0031] The embodiment of the present application further provides a pixel matrix, characterized in that it comprises a plurality of regularly arranged CMOS image sensor pixel circuits as described above, and each column of pixel units is configured with an identification signal flagi, where i=1, 2, ..., i is the number of columns.

[0032] Beneficial Effects

[0033] Compared with the solutions in the prior art, the advantages of the present invention are as follows: the pixel circuit of the CMOS image sensor of the present application does not require an additional hardware storage unit to record the state of each pixel point. By adding a control signal to the interface of each pixel point, once the pixel point is detected to have too much charge, its corresponding control line (flag) will send a pulse signal, and then the charge transmission path on the pixel point will always remain closed until the overall charge of the entire pixel matrix is ​​cleared, and the channel will be reopened. In addition, the pixel circuit of the CMOS image sensor proposed in the present application can reuse the same control line for pixel units in different rows / columns, and such a design simplifies the layout connection of the pixel matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings required for use in the embodiments or the prior art description are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor:

[0035] Figure 1 Shown is a schematic diagram of a photosensitive component of an existing CMOS image sensor;

[0036] Figure 2a Shown is a schematic diagram of the existing CMOS pixel circuit topology;

[0037] Figure 2b The figure shows a schematic diagram of the topology of a CMOS pixel circuit according to an embodiment of the present invention;

[0038] Figure 3a Shown is a topological schematic diagram of an existing CMOS pixel matrix;

[0039] Figure 3b FIG. 1 is a topological schematic diagram of a CMOS pixel matrix according to an embodiment of the present invention;

[0040] Figure 4a Shown is the matrix control timing of the existing CMOS pixel matrix;

[0041] Figure 4b FIG. 1 shows the matrix control timing of the CMOS pixel matrix according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the technical solutions proposed in this application, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments in this specification, not all of the embodiments. Based on one or more embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0043] The pixel circuit and anti-overexposure control method proposed in the present application do not require an additional hardware storage unit to record the status of each pixel point. The detection unit is used to detect whether the charge amount on the FD has reached the threshold. If it is detected that the set threshold is reached, a response is made, and the original charge amount on the node "FD" is always maintained until the next recovery signal is triggered, thereby reducing the overexposure risk of the pixel circuit. In this way, only one more control signal needs to be added to the interface of each pixel point. Once the pixel point is detected to have too much charge, its corresponding control line (flag) will send a pulse signal, and then the charge transfer path on the pixel point will always remain in a closed state until the overall charge of the entire pixel matrix is ​​cleared, and the channel will be reopened.

[0044] The detection unit includes at least one switch, wherein the switch has a first end (drain end), a second end (source end), and a third end (gate end), wherein the first end is electrically connected to a node FD, the second end is the drain end of an electrical MOS switch (M14), and the third end is electrically connected to a control end. If it is detected that the amount of charge on the node FD reaches a set threshold, the third end electrically disconnects the connection between the first end and the second end based on a received signal until the third end receives a next recovery signal, thereby restoring the connection between the first end and the second end.

[0045] Figure 2a This is a conventional pixel circuit. The pixel circuit 10 (4T-APS) comprises four MOS switches M1-M4, a photodiode D, and a capacitor C.

[0046] The drain terminal of the MOS switch M1 is electrically connected to the drain terminal of the MOS switch M3 and the power supply terminal.

[0047] The gate terminal of the MOS switch M1 is electrically connected to the source terminal of the MOS switch M3 and one end of the capacitor C. The other end of the capacitor C is electrically connected to the line equipotential terminal.

[0048] The source terminal of the MOS switch M1 is electrically connected to the drain terminal of the MOS switch M2;

[0049] The source terminal of the MOS switch M3 is electrically connected to the drain terminal of the MOS switch M4 and one end of the capacitor C, and the gate terminal of the MOS switch M3 serves as a reset rst terminal;

[0050] The source terminal of the MOS switch M4 is electrically connected to the cathode terminal of the photodiode D, the anode terminal of the photodiode D is electrically connected to the ground, and the gate terminal of the MOS switch M4 serves as the trigger terminal TX.

[0051] The gate terminal of the MOS switch M2 serves as the trigger terminal S terminal, and the source terminal of the MOS switch M2 is electrically connected to the reading module (not shown). When the pixel circuit is running, if the reset rst signal at the gate terminal of the MOS switch M3 is high, the charge previously accumulated or coupled on the node FD (Floating Diffusion) of the pixel is completely cleared. When the signal TX at the gate terminal of the MOS switch M4 is high, the photosensitive device D is in an exposure state, and the light signal is converted by the photosensitive device D to generate charge accumulated on the node FD and stored on the capacitor C. The stronger the light intensity and the longer the exposure time, the higher the accumulated charge. When the S at the gate terminal of the MOS switch M2 is a high signal, the pixel is in a charge information reading state, the MOS switch tube M2 is turned on, and the charge accumulated on the FD is converted into current or voltage information by the MOS switch (also called MOS transistor, switch tube) M1, and output to the subsequent module (not shown) for analysis and processing after passing through the MOS switch M2.

[0052] In the above implementation, it can be seen from the formula Q=C*V that as the amount of charge Q converted by the photosensitive device D increases, the voltage on FD will increase because the capacitor C is fixed. Once the FD voltage exceeds a certain range (the range depends on the process parameters of the MOS switch M1 and the voltage value of the power supply VDD), the transistor M1 cannot linearly convert the charge on the FD node into corresponding current or voltage information, and the pixel is overexposed.

[0053] To this end, the applicant Figure 2a The implementation method shown in the figure is improved, and an overexposure prevention function is configured on this basis. Next, combined with Figure 2b The CMOS image sensor pixel circuit proposed in the embodiment of the present application is described. The CMOS image sensor pixel circuit is added with a detection unit 21 on the original basis. The detection unit 21 is used to detect whether the charge amount on FD has reached a threshold value. If it is detected that the set threshold value is reached, a response is made, and the original charge amount on the node "FD" is always maintained until the next recovery signal is triggered. Through such a design, the overexposure risk of the pixel circuit is reduced.

[0054] The detection unit 21 comprises:

[0055] MOS switch M15, MOS switch M16, MOS switch M17, MOS switch M18, capacitor C2,

[0056] The gate terminal of the MOS switch M15 is electrically connected to the source terminal of the MOS switch M16, one end of the capacitor C2, and the drain terminal of the MOS switch M17.

[0057] The drain terminal of the MOS switch M15 is electrically connected to the source terminal of the MOS switch M13 and one end of the capacitor C1.

[0058] The source terminal of the MOS switch M15 is electrically connected to the drain terminal of the MOS switch M14.

[0059] The drain terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M13 and the power supply terminal. The source terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M17 and one end of the capacitor C2. The gate terminal of the MOS switch M16 is a signal reset terminal (rst).

[0060] The source terminal of the MOS switch M17 is electrically connected to the drain terminal of the MOS switch M18, the gate terminal of the MOS switch M17 serves as a flag terminal, and the gate terminal of the MOS switch M18 serves as a trigger terminal S.

[0061] The other end of the capacitor C2 is electrically connected to the equipotential terminal. Through such a design, the pixel's anti-overexposure function and control line (flag) multiplexing are realized, and the detection unit 21 has little effect on the pixel circuit layout area and pixel matrix wiring during production. The node pdb switch tube switch is at a high level when the rst received by the gate is high and the pixel charge is cleared, so the switch tube M15 is in the on state. When the TX signal is high, the charge converted by the photosensitive element D is transferred to the node FD by the switch tube M15. When S is high, the charge on the node FD is converted into current / voltage information and read by the system. If it is found after reading that the charge on the node FD has reached the threshold (or exceeded the threshold), subsequent exposure may cause overexposure, then the flag signal is flipped from a low level to a high level. If Figure 2b As shown, the flag signal will only select to output a high level or a low level according to the reading result when the read signal S is at a high level. When the S signal is at a low level, the flag signal also becomes a low level. The node FD is electrically connected to one end of the capacitor C1, the source end of the MOS switch M13, and the drain end of the MOS switch M15. The node pdb is electrically connected to the gate end of the MOS switch M15, the source end of the MOS switch M16, the drain end of the MOS switch M17, and one end of the capacitor C2. In the embodiment of the present application, the node FD / node pdb can be a node of the process technology.

[0062] When the flag signal and the S signal are both high, the switches M17 and M18 are turned on at the same time, and the pdb node is pulled to a low level. From then on, the switch M15 will always remain in the off state until the next reset rst signal becomes high and can be turned on again. Therefore, before the next reset rst high signal comes, even if the photosensitive element is exposed multiple times, it cannot transfer charge to the node "FD". The node "FD" always maintains the original charge. Figure 2b Other devices are connected in the same Figure 2a , just the numbers are different and will not be described again.

[0063] like Figure 3a The following is a schematic diagram of the common pixel matrix layout wiring. The figure lists four rows and four columns (4X4) for a total of 16 pixel units. Each column of pixel units reuses the same exposure control line TXi (i=1,2,…,i is the number of columns), which is provided by the horizontal Tx signal driver module in the figure. Each row of pixel units reuses the same reset control line rstj and pixel charge reading control line Sj (j=1,2,…,j is the number of rows), which is provided by the vertical S and rst signal driver modules in the figure.

[0064] like Figure 3b Schematic diagram of the pixel matrix layout connection of the embodiment of the present application, compared with Figure 3a , each column of pixel units only adds a new identification signal flagi (i=1,2,…,i is the number of columns), and the rest of the structure completely reuses the original structure. With this design, pixel units in different rows / columns can reuse the same control line, so this solution simplifies the layout connection of the pixel matrix.

[0065] In this specification, each embodiment of the pixel circuit is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For related parts, refer to the partial description of the method embodiment.

[0066] Next, combine Figure 4a , Figure 4b To describe the control signal timing of the pixel matrix,

[0067] like Figure 4a The figure shows the existing matrix control signal timing. All the reset control lines are flipped at the same time, and the charge of each unit in the entire pixel matrix is ​​reset at the same time. After that, all the exposure control lines are flipped at the same time, and each unit in the pixel matrix is ​​exposed at the same time, and photoelectric conversion occurs. After that, the charge reading signal of each row is flipped accordingly, and the charge information of each unit in the matrix is ​​read row by row. The pixel units in the same row are charged and read at the same time.

[0068] like Figure 4bThe figure shows the matrix control signal timing of the embodiment of the present application, which uses the characteristic that the flag signal must be high at the same time as the read signal S to turn off the switch tube M15. Each column of pixels reuses the same flag control signal to achieve overexposure prevention control for each pixel. Figure 3b As shown, compared with the connection of the conventional pixel matrix, each column only adds one control line flagi (i=1, 2, ..., i is the number of columns). Only when the read signal of the row is selected, the column control signal flagi corresponding to each pixel unit on the row can effectively turn off the switch tube M3 of the corresponding pixel point, thereby preventing the charge of the node "FD" from continuing to accumulate and increase.

[0069] It should be noted that the implementation method proposed in this application is used in a 4T-APS pixel circuit (4T (transistor) -APS (active pixel sensor)). In other implementation methods, it can be applied to pixel circuits such as 5T-APS, 6T-APS, 7T-APS, 8T-APS, and 9T-APS. FD is also called a floating diffusion node.

[0070] In the implementation manner of the present application, the capacitance of the capacitor C2 is positively correlated to the leakage current of the pixel circuit. The smaller the leakage current, the smaller the capacitance of the capacitor C2.

[0071] The CMOS image sensor of the embodiment of the present application is electrically connected to a control module, which provides a control signal "rst" to clear the accumulated charge sensed by the pixel circuit; provides a control signal "s" to detect the accumulated charge amount of each pixel point; and provides a control signal "flag" to stop continuing to accumulate charge for each pixel point whose accumulated charge has reached an upper limit.

[0072] The present invention also provides a computer storage medium, which includes a computer program, and the computer program runs the above-mentioned automatic exposure control method to control the exposure of the image.

[0073] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer (processor) readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0074] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A CMOS image sensor pixel circuit, characterized in that: The detection unit is electrically connected to the node FD to detect whether the charge on the node FD reaches a preset threshold. If it is detected that the charge amount on the node FD reaches a set threshold, the connection with the node FD is electrically disconnected, and the node FD always maintains the original charge amount until the next recovery signal is triggered to restore the electrical connection between the detection unit and the node FD. The detection unit includes at least one switch, and the switch has a first end, a second end, and a third end. The first end is electrically connected to the node FD, the second end is electrically connected to the drain end of the MOS switch M14, and the third end is electrically connected to the control end. If it is detected that the charge amount on the node FD reaches a set threshold, the third end electrically disconnects the first end from the second end based on the received signal until it receives the next recovery signal to restore the connection between the first end and the second end.

2. The CMOS image sensor pixel circuit according to claim 1, wherein: The detection unit includes a MOS switch M15 and a capacitor C2. The gate terminal of the MOS switch M15 is electrically connected to a node pdb, and the node pdb is electrically connected to one end of the capacitor C2. The drain terminal of the MOS switch M15 is electrically connected to the source terminal of the MOS switch M13 and the node FD. The node FD is electrically connected to one end of the capacitor C1 and the gate terminal of the MOS switch M11. The source terminal of the MOS switch M15 is electrically connected to the drain terminal of the MOS switch M14. The other end of capacitor C2 is electrically connected to the equipotential terminal. The MOS switch M15 is turned on or off based on a signal received at its gate terminal.

3. The CMOS image sensor pixel circuit according to claim 2, wherein: Also includes MOS switch M16, MOS switch M17, MOS switch M18, wherein: The gate terminal of the MOS switch M15 is electrically connected to a node pdb, and the node pdb is electrically connected to a source terminal of the MOS switch M16, one end of the capacitor C2, and a drain terminal of the MOS switch M17. The drain terminal of the MOS switch M15 is electrically connected to the node FD. The drain terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M13 and the power supply terminal. The source terminal of the MOS switch M16 is electrically connected to the drain terminal of the MOS switch M17 and one end of the capacitor C2, and the gate terminal of the MOS switch M16 is electrically connected to the control module to receive a signal sent by the control module. The source terminal of the MOS switch M17 is electrically connected to the drain terminal of the MOS switch M18. The gate terminal of the MOS switch M17 is electrically connected to the control module to receive the marking signal sent by the control module. The gate terminal of the MOS switch M18 is electrically connected to the control module to receive a signal sent by the control module.

4. The CMOS image sensor pixel circuit according to claim 2, wherein: The capacitance of the capacitor C2 is positively correlated with the leakage current of the pixel circuit process of the CMOS image sensor.

5. The CMOS image sensor pixel circuit according to claim 2, wherein: When the gate terminal of the MOS switch M16 receives the rst signal at a high level, the charge of the pixel circuit is cleared and is at a high level, and the switch M15 is turned on.

6. The CMOS image sensor pixel circuit according to claim 5, characterized in that: When the TX signal received by the gate terminal of the MOS switch M14 is high, the charges converted by the photosensitive element D are transferred to the node FD by the MOS switch M15.

7. The CMOS image sensor pixel circuit according to claim 6, wherein: When the flag signal received by the gate terminal of the MOS switch M17 and the S signal received by the gate terminal of the MOS switch M18 are both high level, the MOS switches M17 and M18 are turned on at the same time, the node pdb is pulled to a low level, and the MOS switch M15 is turned off and remains in the off state until the next reset rst signal becomes high level and is turned on again.

8. The CMOS image sensor pixel circuit according to any one of claims 1 to 7, characterized in that: The pixel circuit of the CMOS image sensor is one of 4T-APS, 5T-APS, 6T-APS, 7T-APS, 8T-APS, and 9T-APS.

9. A pixel matrix, characterized in that: A CMOS image sensor pixel circuit comprising a plurality of regularly arranged pixels as claimed in any one of claims 1 to 7, Each column of pixel units is configured with a flag signal flagi, where i=1, 2, ..., i is the number of columns.

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