Semiconductor Devices

Abstract

A semiconductor device is provided. The device includes an active pattern extending along a first direction on a substrate, a field insulating film surrounding a portion of a sidewall of the active pattern, a first gate structure extending along a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending along the second direction on the active pattern and the field insulating film, and a first device isolation film between the first gate structure and the first gate structure, wherein a sidewall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle relative to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than an uppermost surface of the field insulating film or is substantially coplanar with the uppermost surface of the field insulating film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0089202, entitled “Semiconductor Device and Method of Manufacturing the Same,” filed on July 31, 2018 in the Korean Intellectual Property Office is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As a scaling technology for increasing the density of semiconductor devices, a multi-gate transistor has been proposed, in which a multi-channel active pattern (or silicon body) having a fin or nanowire shape can be formed on a substrate, and a gate can be formed on a surface of the multi-channel active pattern. Summary of the invention

[0005] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate; an active pattern extending along a first direction on the substrate; a field insulating film surrounding a portion of a side wall of the active pattern; a first gate structure extending along a second direction on the active pattern and the field insulating film, the second direction intersecting the first direction; a second gate structure spaced apart from the first gate structure and extending along the second direction on the active pattern and the field insulating film; and a first device isolation film between the first gate structure and the second gate structure, wherein the side wall of the first gate structure facing the first device isolation film includes a first inclined surface having an acute angle relative to an upper surface of the active pattern, and the lowermost surface of the first device isolation film is lower than the uppermost surface of the field insulating film or is substantially coplanar with the uppermost surface of the field insulating film.

[0006] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate; an active pattern including a separation trench on the substrate; a device isolation film filling the separation trench; a source / drain region in the active pattern; and a gate structure intersecting the active pattern on the active pattern between the device isolation film and the source / drain region, wherein a side wall of the gate structure facing the device isolation film includes a first inclined surface having an acute angle relative to an upper surface of the active pattern.

[0007] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate including a first region and a second region; a first active pattern including a first separation trench and extending along a first direction on the first region of the substrate; a second active pattern extending along the first direction on the second region of the substrate; a first gate structure extending along a second direction on the first active pattern and the second active pattern, the second direction intersecting the first direction; a second gate structure spaced apart from the first gate structure and extending along the second direction on the first active pattern and the second active pattern; and a device isolation film filling the first separation trench and extending along the second direction between the first gate structure and the second gate structure, wherein the side wall of the first gate structure facing the device isolation film includes a first inclined surface having an acute angle relative to an upper surface of the first active pattern.

[0008] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate; a first fin pattern extending along a first direction on the substrate; a second fin pattern spaced apart from the first fin pattern along the first direction and extending along the first direction on the substrate; a field insulating film separating the first fin pattern and the second fin pattern and including a separation trench therein; a first gate structure and a second gate structure extending on both sides of the separation trench and along a second direction intersecting the first direction, respectively; and a device isolation film filling the separation trench between the first gate structure and the second gate structure.

[0009] An embodiment can be implemented by providing a method for manufacturing a semiconductor device, the method comprising: forming an active pattern extending along a first direction on a substrate, forming a plurality of dummy gate electrodes spaced apart from each other and extending along a second direction intersecting the first direction on the active pattern, forming an interlayer insulating film covering the side walls of each dummy gate electrode; after forming the interlayer insulating film, forming a first gate structure and a second gate structure to replace the plurality of dummy gate electrodes, each gate structure extending along the second direction; etching the interlayer insulating film and the active pattern between the first gate structure and the second gate structure to form a separation trench; and forming a device isolation film filling the separation trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0012] Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA′.

[0013] Figure 3 Shown along Figure 1 A cross-sectional view taken along line BB′.

[0014] Figure 4 Shown along Figure 1 A cross-sectional view taken along line CC′.

[0015] Figure 5 and Figure 6 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0016] Figure 7 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0017] Figure 8 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0018] Fig. 9 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0019] Fig.10 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0020] Fig.11 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0021] Fig.12 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0022] Fig.13 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0023] Fig.14 Shown along Fig.13 A cross-sectional view taken along line DD′.

[0024] Fig.15 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0025] Fig.16 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0026] Fig.17 Shown along Fig.16 A cross-sectional view taken along line EE′.

[0027] Fig.18 Shown along Fig.16 A cross-sectional view taken along line FF′.

[0028] Fig.19 Shown along Fig.16 A cross-sectional view taken along line GG′.

[0029] Fig. 20A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0030] Fig.21 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0031] Fig. 22 Shown along Fig.21 A cross-sectional view taken along line HH′.

[0032] Fig.23 Shown along Fig.21 A cross-sectional view taken along line II′.

[0033] Fig.24 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0034] Fig.25 A schematic layout diagram of a semiconductor device according to some embodiments is shown.

[0035] Figure 26 to Figure 31 Some stages in a method for manufacturing a semiconductor device according to some embodiments are shown. DETAILED DESCRIPTION

[0036] In the following, reference will be made to Figures 1 to 25 A semiconductor device according to some embodiments is described.

[0037] In the drawings of semiconductor devices according to some embodiments, a fin transistor (FinFET) including a channel region in a fin pattern shape is exemplarily shown. The semiconductor device according to some embodiments may, for example, include a tunneling transistor (tunneling FET), a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor. In addition, the semiconductor device according to some embodiments may include a bipolar junction transistor, a lateral double diffused transistor (LDMOS), etc.

[0038] Figure 1 A schematic layout diagram of a semiconductor device according to some embodiments is shown. Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA′. Figure 3 Shown along Figure 1 A cross-sectional view taken along line BB′. Figure 4 Shown along Figure 1 For ease of explanation, Figure 1 The first interlayer insulating film 191 and the second interlayer insulating film 192 are not shown.

[0039] refer to Figures 1 to 4According to some embodiments, the semiconductor device may include: a substrate 100, first to fourth active patterns AP1, AP2, AP3 and AP4, a field insulating film 110, first to fourth gate structures GS1, GS2, GS3 and GS4, a first source / drain region 150, a second source / drain region 250, a first interlayer insulating film 191, a first device isolation film 160a and a second interlayer insulating film 192.

[0040] The substrate 100 may be bulk silicon or silicon on insulator (SOI). In one implementation, the substrate 100 may be a silicon substrate and may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0041] The substrate 100 may include a first region I and a second region II. In one implementation, the first region I and the second region II may be regions spaced apart from each other, or may be regions connected to each other. In the first region I and the second region II, semiconductor elements of the same conductivity type may be formed, and semiconductor elements of different conductivity types may be formed. Hereinafter, the first region I is described as a PMOS region, and the second region II is described as an NMOS region.

[0042] Each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may protrude from the substrate 100. Each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may extend lengthwise along the first direction X on the substrate 100. For example, each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may include a long side extending along the first direction X and a short side extending along the second direction Y. The second direction Y may intersect the first direction X, for example, be substantially perpendicular to the first direction X. In addition, each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may be defined by a fin trench FT. For example, as shown in FIG. Figure 4 As shown in FIG. 1 , each of the third active pattern AP3 and the second active pattern AP2 may be defined by a fin trench FT.

[0043] The first to fourth active patterns AP1, AP2, AP3, and AP4 may be part of the substrate 100 and may include an epitaxial layer grown from the substrate 100. Each of the first to fourth active patterns AP1, AP2, AP3, and AP4 may include silicon or germanium as an elemental semiconductor material. In one implementation, the first to fourth active patterns AP1, AP2, AP3, and AP4 may include a compound semiconductor and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0044] In the following description, the first and third active patterns AP1 and AP3 will be described as being formed on the first region I of the substrate 100 , and the second and fourth active patterns AP2 and AP4 will be described as being formed on the second region II of the substrate 100 .

[0045] The field insulating film 110 may be formed on the substrate 100. The field insulating film 110 may fill at least a portion of the fin trench FT. Thus, the field insulating film 110 may surround at least some portions of the sidewall of each of the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0046] In one implementation, upper surfaces of the first to fourth active patterns AP1, AP2, AP3, and AP4 may protrude upward from the upper surface of the field insulating film 110. Figure 4 As shown in FIG. 1 , the field insulating film 110 may surround some portions of the sidewalls of each of the third active pattern AP3 and the second active pattern AP2 .

[0047] The first to fourth gate structures GS1, GS2, GS3, and GS4 may be formed on the first to fourth active patterns AP1, AP2, AP3, and AP4 and the field insulating film 110. In addition, the first to fourth gate structures GS1, GS2, GS3, and GS4 may extend in the second direction Y. Therefore, each of the first to fourth gate structures GS1, GS2, GS3, and GS4 may intersect the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0048] Each of the first to fourth gate structures GS1, GS2, GS3 and GS4 may include: a gate insulating film 120, 220, 320 and 420, a gate electrode 130, 230, 330 and 430, a gate spacer 140, 240, 340 and 440, a gate trench 140t, 240t, 340t and 440t defined by the gate spacer 140, 240, 340 and 440, and a covering pattern 155, 255, 355 and 455.

[0049] The first to fourth gate insulating films 120, 220, 320, and 420 may be respectively interposed between the first to fourth active patterns AP1, AP2, AP3, and AP4 and the corresponding gate electrodes 130, 230, 330, and 430. In one implementation, each of the first to fourth gate insulating films 120, 220, 320, and 420 may extend along a sidewall and a lower surface of a corresponding one of the gate trenches 140t, 240t, 340t, and 440t.

[0050] The first to fourth gate insulating films 120, 220, 320, and 420 may include, for example, a high dielectric constant insulating film. The high dielectric constant insulating film may include a high dielectric material having a dielectric constant higher than that of a silicon oxide film.

[0051] The first to fourth gate electrodes 130, 230, 330 and 430 may be respectively formed on the first to fourth gate insulating films 120, 220, 320 and 420. In addition, the first to fourth gate electrodes 130, 230, 330 and 430 may respectively fill at least some portions of the gate trenches 140t, 240t, 340t and 440t.

[0052] The first to fourth gate electrodes 130, 230, 330 and 430 may include, for example, Ti, Ta, W, Al, Co or a combination thereof. In one implementation, the first to fourth gate electrodes 130, 230, 330 and 430 may be made of silicon, silicon germanium, etc. instead of metal.

[0053] First to fourth gate spacers 140 , 240 , 340 , and 440 may be formed on sidewalls of the first to fourth gate electrodes 130 , 230 , 330 , and 430 , respectively.

[0054] The first to fourth gate spacers 140, 240, 340, and 440 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0055] First to fourth capping patterns 155 , 255 , 355 , and 455 may be formed on the corresponding gate electrodes 130 , 230 , 330 , and 430 .

[0056] Each of the first to fourth capping patterns 155, 255, 355, and 455 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0057] In an implementation, the first to fourth capping patterns 155 , 255 , 355 , and 455 may also be omitted.

[0058] In one implementation, the first to fourth gate spacers 140, 240, 340, and 440 may be formed on sidewalls of the corresponding first to fourth gate electrodes 130, 230, 330, and 430 and on sidewalls of the corresponding first to fourth capping patterns 155, 255, 355, and 455. Figure 2As shown in the figure, the first to fourth gate electrodes 130, 230, 330 and 430 fill some portions of the gate trenches 140t, 240t, 340t and 440t, respectively, and the first to fourth capping patterns 155, 255, 355 and 455 may fill the remaining portions of the gate trenches 140t, 240t, 340t and 440t, respectively.

[0059] The first source / drain region 150 and the second source / drain region 250 may be formed in the first active pattern AP1. Figure 2 As shown in FIG. 1 , the first source / drain region 150 may be formed in the first active pattern AP1 between the first gate structure GS1 and the third gate structure GS3 , and the second source / drain region 250 may be formed in the first active pattern AP1 between the second gate structure GS2 and the fourth gate structure GS4 .

[0060] The first source / drain region 150 and the second source / drain region 250 may include an epitaxial layer formed on the first active pattern AP1. For example, the first source / drain region 150 may be an epitaxial pattern filling the first source / drain trench 150t formed in the first active pattern AP1, and the second source / drain region 250 may be an epitaxial pattern filling the second source / drain trench 250t formed in the first active pattern AP1. In one implementation, the first source / drain region 150 and the second source / drain region 250 may be impurity regions formed in the first active pattern AP1.

[0061] In one implementation, the first source / drain region 150 and the second source / drain region 250 may be elevated source / drain regions including upper surfaces protruding upward (eg, away from the substrate) from an upper surface of the first active pattern AP1 .

[0062] In one implementation, the first source / drain region 150 and the second source / drain region 250 may include an undercut at the lower end of the first to fourth gate structures GS1, GS2, GS3 and GS4. This may be attributed to the characteristics of the etching process used to form the first source / drain trench 150t and the second source / drain trench 250t. In one implementation, the first source / drain region 150 and the second source / drain region 250 may not include an undercut.

[0063] A first interlayer insulating film 191 may be formed on the field insulating film 110 and the first and second source / drain regions 150 and 250. In addition, the first interlayer insulating film 191 may cover sidewalls of the first to fourth gate structures GS1, GS2, GS3, and GS4.

[0064] In one implementation, the first interlayer insulating film 191 may further include an anti-etching film extending along upper surfaces of the first source / drain region 150 and the second source / drain region 250 .

[0065] In one implementation, the upper surface of the first interlayer insulating film 191 may be on substantially the same plane as the upper surfaces of the first to fourth capping patterns 155, 255, 355, and 455. In this specification, “substantially the same” means not only completely the same but also slight differences that may occur due to process margins, etc.

[0066] The first device isolation film 160a may be between the first gate structure GS1 and the second gate structure GS2. The first device isolation film 160a may fill the first separation trench 160at in the first active pattern AP1. The first separation trench 160at may be formed in the first active pattern AP1 between the first gate structure GS1 and the second gate structure GS2. In addition, the first device isolation film 160a may extend along the second direction Y. For example, the first separation trench 160at may extend along the second direction Y.

[0067] The upper surface of the first device isolation film 160a may be on substantially the same plane as the upper surface of the first interlayer insulating film 191. In one implementation, the upper surface of the first device isolation film 160a may be on substantially the same plane as the upper surfaces of the first to fourth gate structures GS1, GS2, GS3, and GS4. For example, the upper surface of the first device isolation film 160a may be on substantially the same plane as the upper surfaces of the first to fourth capping patterns 155, 255, 355, and 455.

[0068] The lowermost surface of the first device isolation film 160a may be lower than (e.g., closer to the substrate 100) or equal to (e.g., aligned with or coplanar with) the uppermost surface of the field insulation film 110. For example, the distance from the lower surface of the second interlayer insulation film 192 to the lowermost surface of the first device isolation film 160a ( Figure 2 The distance D11) may be greater than the distance from the lower surface of the second interlayer insulating film 192 to the uppermost surface of the field insulating film 110 ( Figure 4 D21).

[0069] In one implementation, the first device isolation film 160a may include an undercut formed at the lower ends of the first gate structure GS1 and the second gate structure GS2. This may be attributed to the characteristics of the etching process used to form the first separation trench 160at. In one implementation, the first device isolation film 160a may not include an undercut.

[0070] In one implementation, the first device isolation film 160a may separate the first active pattern AP1. Figure 2 As shown in FIG. 1 , the lowermost surface of the first device isolation film 160 a may be lower than or equal to (eg, may be aligned with or contact) the upper surface (or Figure 3 and Figure 4The first active pattern AP1 may include a first fin pattern F1 and a second fin pattern F2 separated by the first device isolation film 160a. The first fin pattern F1 and the second fin pattern F2 may be arranged (eg, spaced apart) along the first direction X and may extend along the first direction X, respectively.

[0071] The sidewall of the first gate structure GS1 and / or the second gate structure GS2 facing the first device isolation film 160a may include an inclined surface having an acute angle with respect to the upper surface of the first active pattern AP1. Figure 2 As shown in FIG. 1 , a sidewall of the first gate structure GS1 facing the first device isolation film 160 a may include a first inclined surface GS1 -S, and a sidewall of the second gate structure GS2 facing the first device isolation film 160 a may include a second inclined surface GS2 -S.

[0072] In one implementation, Figure 2 As shown in , both the first gate structure GS1 and the second gate structure GS2 include inclined surfaces. In one implementation, only the first gate structure GS1 may include the first inclined surface GS1-S, while the second gate structure GS2 may not include the second inclined surface GS2-S. In one implementation, only the second gate structure GS2 may include the second inclined surface GS2-S, while the first gate structure GS1 may not include the first inclined surface GS1-S. The description of the second inclined surface GS2-S is similar to the description of the first inclined surface GS1-S, and the first inclined surface GS1-S will be mainly described below.

[0073] The first inclined surface GS1-S may be formed by an etching process for forming the first separation trench 160at. For example, when the first gate structure GS1 is formed by a mask pattern ( Fig.30 When the opening O of the substrate 180 is exposed, not only the first interlayer insulating film 191 and the first active pattern AP1 may be etched, but also a portion of the first gate structure GS1 may be etched.

[0074] In one implementation, the first slanted surface GS1-S may be in direct contact with the first device isolation film 160a. Therefore, a portion of a sidewall of the first device isolation film 160a may be defined by the first slanted surface GS1-S.

[0075] In one implementation, the first gate spacer 140 may define at least a portion of the first inclined surface GS1-S. Figure 2 As shown in FIG. 1 , the first inclined surface GS1-S may be defined by the sidewalls of the first gate spacer 140 and the sidewalls of the first capping pattern 155. This may be attributed to the mask pattern ( Fig.30For example, when the first capping pattern 155 is exposed through the opening O of the mask pattern 180 , the first inclined surface GS1-S may be defined by the first gate spacer 140 and the first capping pattern 155 .

[0076] In one implementation, the first inclined surface GS1-S may be defined only by the first gate spacer 140. For example, when the first capping pattern 155 is not formed by the mask pattern ( Fig.30 When the opening O of the gate spacer 180 is exposed, the first inclined surface GS1-S may be defined only by the first gate spacer 140.

[0077] In one implementation, the first inclined surface GS1-S may be defined by the first capping pattern 155 and the first gate electrode 130. For example, by using a mask pattern ( Fig.30 The etching process of (180) may not only etch the first capping pattern 155 and the first gate spacer 140, but also etch a portion of the first gate electrode 130. In this case, the first gate electrode 130 may be in direct contact with the first device isolation film 160a.

[0078] In one implementation, a portion of the first device isolation film 160a may overlap with the field insulation film 110. Figure 3 As shown in FIG. 1 , the first device isolation film 160a may include a first portion 160a1 not overlapping the field insulating film 110 and a second portion 160a2 overlapping the field insulating film 110. The first portion 160a1 of the field insulating film 110 may be a portion formed in the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0079] In one implementation, the lower surface of the first portion 160a1 of the first device isolation film 160a may be lower than (e.g., closer to the substrate 100) the lower surface of the second portion 160a2 of the first device isolation film 160a. For example, the distance from the lower surface of the second interlayer insulating film 192 to the lower surface of the first portion 160a1 of the first device isolation film 160a is ( Figure 3 The distance D11) from the lower surface of the second interlayer insulating film 192 to the lower surface of the second portion 160a2 of the first device isolation film 160a may be greater than the distance ( Figure 3 D12).

[0080] The first device isolation film 160a may include, for example, silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, aluminum oxide, or a combination thereof. In one implementation, the first device isolation film 160a may be a single-layer film. In one implementation, the first device isolation film 160a may be a multi-layer film.

[0081] The second interlayer insulating film 192 may be formed on the first to fourth gate structures GS1, GS2, GS3, and GS4, the first interlayer insulating film 191, and the first device isolation film 160a. Therefore, the first device isolation film 160a may extend from the lower surface of the first separation trench 160at to the lower surface of the second interlayer insulating film 192. The interlayer insulating film 190 may include a first interlayer insulating film 191 and a second interlayer insulating film 192.

[0082] The first interlayer insulating film 191 and the second interlayer insulating film 192 may include, for example, a low dielectric constant insulating film. The low dielectric constant insulating film may include a low dielectric material having a dielectric constant lower than that of a silicon oxide film.

[0083] Figure 5 and Figure 6 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0084] refer to Figure 5 and Figure 6 In the semiconductor device according to some embodiments, the lowermost surface (eg, facing the substrate 100 ) of the first device isolation film 160 a may be higher than the upper surface of the substrate 100 (or the lower surface of the field insulating film 110 ).

[0085] For example, the distance from the lower surface of the second interlayer insulating film 192 to the lowermost surface of the first device isolation film 160a ( Figure 5 The distance D13) may be smaller than the distance from the lower surface of the second interlayer insulating film 192 to the upper surface of the substrate 100 (or the lower surface of the field insulating film 110).

[0086] In one implementation, Figure 6 As shown in FIG. 1 , the distance from the lower surface of the second interlayer insulating film 192 to the lowermost surface of the first device isolation film 160 a ( Figure 6 D13) may be the distance from the lower surface of the second interlayer insulating film 192 to the upper surface of the field insulating film 110 ( Figure 6 In one implementation, the lowermost surface of the first device isolation film 160a may be between the upper surface of the substrate 100 and the uppermost surface of the field insulation film 110.

[0087] Figure 7 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0088] refer to Figure 7In the semiconductor device according to some embodiments, the lowermost surface of the first device isolation film 160 a may be lower than the uppermost surface of the substrate 100 (or the lower surface of the field insulation film 110 ).

[0089] For example, the distance from the lower surface of the second interlayer insulating film 192 to the lowermost surface of the first device isolation film 160a ( Figure 7 D14) may be greater than a distance from a lower surface of the second interlayer insulating film 192 to an uppermost surface of the substrate 100 (or a lower surface of the field insulating film 110).

[0090] For example, the first device isolation film 160 a may separate the first active pattern AP1 .For example, the first active pattern AP1 may include a first fin pattern F1 and a second fin pattern F2 separated by the first device isolation film 160 a .

[0091] Figure 8 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0092] refer to Figure 8 In the semiconductor device according to some embodiments, the first inclined surface GS1-S and / or the second inclined surface GS2-S may include a plurality of acute angles, respectively.

[0093] For example, the first inclined surface GS1-S may include a first surface GS1-S1 having a first acute angle relative to the upper surface of the first active pattern AP1 and a second surface GS1-S2 having a second acute angle different from the first acute angle. For example, the second inclined surface GS2-S may include a third surface GS2-S1 having a third acute angle relative to the upper surface of the first active pattern AP1 and a fourth surface GS2-S2 having a fourth acute angle different from the third acute angle. Since the description of the second inclined surface GS2-S is similar to that of the first inclined surface GS1-S, the first inclined surface GS1-S will be mainly described below.

[0094] In one implementation, the first surface GS1 - S1 of the first inclined surface GS1 -S may be defined by the first capping pattern 155 , and the second surface GS1 - S2 of the first inclined surface GS1 -S may be defined by the first gate spacer 140 .

[0095] This can be attributed to the characteristics of the etching process used to form the first separation trench 160at. For example, when the first gate spacer 140 and the first capping pattern 155 are formed by the mask pattern ( Fig.30When the opening O of the first interlayer insulating film 191 and the first active pattern AP1 is exposed, not only the first interlayer insulating film 191 and the first active pattern AP1 can be etched, but also the first gate spacer 140 and the first capping pattern 155 can be etched. However, in the above-mentioned etching process for forming the first separation trench 160at, the corrosion resistance of the first capping pattern 155 and the corrosion resistance of the first gate spacer 140 may be different from each other. Therefore, the first acute angle of the first surface GS1-S1 and the second acute angle of the second surface GS1-S2 may be different from each other. For example, when the corrosion resistance of the first capping pattern 155 is greater than the corrosion resistance of the first gate spacer 140 in the above-mentioned etching process, the first acute angle of the first surface GS1-S1 may be smaller than the second acute angle of the second surface GS1-S2.

[0096] In one implementation, Figure 8 As shown in , the first acute angle of the first surface GS1-S1 may be smaller than the second acute angle of the second surface GS1-S2. In one implementation, when the corrosion resistance of the first capping pattern 155 is smaller than the corrosion resistance of the first gate spacer 140 in the above-mentioned etching process, the first acute angle of the first surface GS1-S1 may be larger than the second acute angle of the second surface GS1-S2.

[0097] Fig. 9 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly explained or omitted. Figures 1 to 4 and Figure 8 Duplicate content of the component being described.

[0098] refer to Fig. 9 In the semiconductor device according to some embodiments, the first surface GS1-S1 of the first inclined surface GS1-S may be defined by the first capping pattern 155, and the second surface GS1-S2 of the first inclined surface GS1-S is defined by the first gate electrode 130. Since the description of the second inclined surface GS2-S is similar to that of the first inclined surface GS1-S, the first inclined surface GS1-S may be mainly described.

[0099] In one implementation, the first acute angle of the first surface GS1-S1 may be greater than the second acute angle of the second surface GS1-S2. For example, when the corrosion resistance of the first capping pattern 155 is less than the corrosion resistance of the first gate electrode 130 in the etching process for forming the first separation trench 160at, the first acute angle of the first surface GS1-S1 may be greater than the second acute angle of the second surface GS1-S2.

[0100] In one implementation, when the corrosion resistance of the first capping pattern 155 is greater than that of the first gate electrode 130 in the above etching process, the first acute angle of the first surface GS1-S1 may be smaller than the second acute angle of the second surface GS1-S2.

[0101] Fig.10 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0102] refer to Fig.10 In the semiconductor device according to some embodiments, each of the first to fourth gate electrodes 130 , 230 , 330 , and 430 may include: a work function adjustment film 132 , 232 , 332 , and 432 , an insertion film 134 , 234 , 334 , and 434 , and a filling film 136 , 236 , 336 , and 436 .

[0103] The first to fourth work function adjusting films 132, 232, 332, and 432 may be respectively formed on the first to fourth gate insulating films 120, 220, 320, and 420. In one implementation, each of the first to fourth gate insulating films 120, 220, 320, and 420 and each of the first to fourth work function adjusting films 132, 232, 332, and 432 may extend along only a portion of a sidewall of the corresponding first to fourth gate trenches 140t, 240t, 340t, and 440t.

[0104] The first to fourth work function adjusting films 132 , 232 , 332 , and 432 may include, for example, a TiN film.

[0105] The first to fourth insertion films 134, 234, 334, 434 may be respectively formed on the first to fourth work function adjustment films 132, 232, 332, and 432. In one implementation, each of the first to fourth insertion films 134, 234, 334, and 434 may extend along other portions of the sidewalls of the corresponding first to fourth gate trenches 140t, 240t, 340t, and 440t and the contours of the corresponding first to fourth work function adjustment films 132, 232, 332, and 432.

[0106] Each of the first to fourth insertion films 134 , 234 , 334 , and 434 may include, for example, Ti, TiAl, TiAlN, TiAlC, TiAlCN, or a combination thereof.

[0107] The first to fourth filling films 136, 236, 336, and 436 may be respectively formed on the first to fourth insertion films 134, 234, 334, and 434. In one implementation, the first to fourth filling films 136, 236, 336, and 436 may fill the remaining regions of the corresponding first to fourth gate trenches 140t, 240t, 340t, and 440t.

[0108] Each of the first to fourth filling films 136 , 236 , 336 , and 436 may include, for example, W, Al, Co, Cu, Ru, Ni, Pt, Ni—Pt, TiN, or a combination thereof.

[0109] In one implementation, each of the first to fourth gate insulating films 120 , 220 , 320 , and 420 may include an interface film 122 , 222 , 322 , and 422 and a dielectric film 124 , 224 , 324 , and 424 .

[0110] Each of the first to fourth interface films 122, 222, 322, and 422 may extend along the upper surface of the first active pattern AP1. The first to fourth dielectric films 124, 224, 324, and 424 may be formed on the first to fourth interface films 122, 222, 322, and 422, respectively. In one implementation, each of the first to fourth dielectric films 124, 224, 324, and 424 may extend along only some portions of the sidewalls of the corresponding first to fourth gate trenches 140t, 240t, 340t, and 440t.

[0111] In one implementation, the uppermost surface of each of the first to fourth dielectric films 124 , 224 , 324 , and 424 and the uppermost surface of each of the first to fourth work function adjustment films 132 , 232 , 332 , and 432 may be on substantially the same plane.

[0112] Fig.11 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0113] refer to Fig.11 In the semiconductor device according to some embodiments, first to fourth capping patterns 155 , 255 , 355 , and 455 may be formed on upper surfaces of corresponding gate spacers among the first to fourth gate spacers 140 , 240 , 340 , and 440 .

[0114] For example, the first to fourth capping patterns 155, 255, 355 and 455 may extend along upper surfaces of the first to fourth gate spacers 140, 240, 340 and 440, the uppermost surfaces of the first to fourth gate insulating films 120, 220, 320 and 420, and upper surfaces of the first to fourth gates 130, 230, 330 and 430, respectively.

[0115] In one implementation, the first capping pattern 155 may define at least a portion of the first slanted surface GS1 -S. For example, as shown in the figure, the first slanted surface GS1 -S may be defined by a sidewall of the first capping pattern 155 and a sidewall of the first gate spacer 140 .

[0116] In one implementation, the first inclined surface GS1 -S may be defined only by the sidewalls of the first capping pattern 155 .

[0117] In one implementation, the first sloped surface GS1 -S may be defined by the first capping pattern 155 and the first gate electrode 130 .

[0118] Fig.12 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0119] refer to Fig.12 The semiconductor device according to some embodiments may further include a contact 195 connected to the first source / drain region 150 and the second source / drain region 250 .

[0120] The contact 195 may penetrate the interlayer insulating film 190 and may be connected to the first source / drain region 150 and the second source / drain region 250. In one implementation, the contact 195 may not contact the first to fourth gate structures GS1, GS2, GS3, and GS4. In one implementation, the contact 195 may also contact the sidewalls of the first to fourth gate structures GS1, GS2, GS3, and GS4. The contact 195 may be formed, for example, by a self-aligned contact (SAC) process.

[0121] In one implementation, the contact 195 may be made into a single structure. In one implementation, the contact 195 may include a plurality of structures arranged along the thickness direction of the substrate 100. In one implementation, a silicide film may be formed between the contact 195 and the first source / drain region 150 and the second source / drain region 250.

[0122] The contact 195 may include, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), nickel (Ni), aluminum (Al), copper (Cu), doped polysilicon, or a combination thereof.

[0123] Fig.13 A schematic layout diagram of a semiconductor device according to some embodiments is shown. Fig.14 Shown along Fig.13 For the convenience of explanation, the reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0124] refer to Fig.13 and Fig.14, the semiconductor device according to some embodiments may further include a second device isolation film 160 b .

[0125] The second device isolation film 160b may be between the second gate structure GS2 and the fourth gate structure GS4. The second device isolation film 160b may fill the second separation trench 160bt in the first active pattern AP1. The second separation trench 160bt may be formed in the first active pattern AP1 between the second gate structure GS2 and the fourth gate structure GS4. In addition, the second device isolation film 160b may extend along the second direction Y. For example, the second separation trench 160bt may extend along the second direction Y.

[0126] The upper surface of the second device isolation film 160b may be on substantially the same plane as the upper surface of the first interlayer insulating film 191. In addition, the upper surface of the second device isolation film 160b may be on substantially the same plane as the upper surfaces of the first to fourth gate structures GS1, GS2, GS3, and GS4.

[0127] Similar to the first device isolation film 160 a , the lowermost surface of the second device isolation film 160 b may be lower than or equal to the uppermost surface of the field insulation film 110 .

[0128] The sidewalls of the second gate structure GS2 and / or the fourth gate structure GS4 facing the second device isolation film 160b may include an inclined surface having an acute angle relative to the upper surface of the first active pattern AP1. For example, the sidewalls of the fourth gate structure GS4 facing the second device isolation film 160b may include a third inclined surface GS3-S.

[0129] In one implementation, the first device isolation film 160a and the second device isolation film 160b may be spaced apart from each other. For example, the first device isolation film 160a and the second device isolation film 160b may be spaced apart from each other by (eg, the second gate structure GS2 therebetween).

[0130] Fig.15 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 4 , Fig.13 and Fig.14 Duplicate content of the component being described.

[0131] refer to Fig.15 In the semiconductor device according to some embodiments, the first device isolation film 160 a and the second device isolation film 160 b may be connected to each other.

[0132] For example, the upper portion of the first device isolation film 160a and the upper portion of the second device isolation film 160b may be connected to each other on the upper surface of the second gate structure GS2. This may be attributed to the etching process used to form the first separation trench 160at and the second separation trench 160bt. For example, when the upper surface of the second gate structure GS2 is formed by the mask pattern ( Fig.30 When the opening O of the gate electrode 180 is completely exposed, not only the first interlayer insulating film 191 and the active pattern AP1 may be etched, but also the upper portion of the second gate structure GS2 may be etched.

[0133] In one implementation, the second covering pattern of the second gate structure GS2 may be completely removed. Figure 2 In one implementation, the second covering pattern of the second gate structure GS2 may be retained ( Figure 2 255 in ).

[0134] Fig.16 A schematic layout diagram of a semiconductor device according to some embodiments is shown. Fig.17 Shown along Fig.16 A cross-sectional view taken along line EE′. Fig.18 Shown along Fig.16 A cross-sectional view taken along line FF′. Fig.19 Shown along Fig.16 For the convenience of explanation, the reference may be briefly described or omitted. Figures 1 to 4 Duplicate content of the component being described.

[0135] refer to Figures 16 to 19 , a semiconductor device according to some embodiments may include third to sixth fin patterns F3 , F4 , F5 , and F6 .

[0136] The third to sixth fin patterns F3, F4, F5, and F6 may be on the second region II of the substrate 100. The third and fifth fin patterns F3 and F5 may be arranged (eg, spaced apart) along the second direction Y, and the fourth and sixth fin patterns F4 and F6 may be arranged along the second direction Y.

[0137] The third fin pattern F3 and the fourth fin pattern F4 may be arranged (eg, spaced apart) along the first direction X and may extend along the first direction X, respectively. Fig.18 As shown in , the third fin pattern F3 and the fourth fin pattern F4 may be separated from each other by the field insulating film 110. For example, Figure 1 The second active pattern AP2 may be separated by the field insulating film 110 to form a third fin pattern F3 and a fourth fin pattern F4.

[0138] The fifth fin pattern F5 and the sixth fin pattern F6 may be arranged along the first direction X and may extend along the first direction X, respectively. Similar to the third fin pattern F3 and the fourth fin pattern F4 , the fifth fin pattern F5 and the sixth fin pattern F6 may be separated by the field insulating film 110 . For example, Figure 1 The fourth active pattern AP4 may be separated by the field insulating film 110 to form a fifth fin pattern F5 and a sixth fin pattern F6.

[0139] The first device isolation film 160a may extend in the second direction Y on the first region I and the second region II. The first device isolation film 160a may be between the third fin pattern F3 and the fourth fin pattern F4 and between the fifth fin pattern F5 and the sixth fin pattern F6. Therefore, the third fin pattern F3 and the fourth fin pattern F4 may be separated from the first device isolation film 160a by the field insulating film 110. In addition, the fifth fin pattern F5 and the sixth fin pattern F6 may be separated from the first device isolation film 160a by the field insulating film 110.

[0140] The lower portion of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4 may be in the field insulating film 110. For example, Fig.18 As shown in , the first separation trench 160at between the third fin pattern F3 and the fourth fin pattern F4 may be in the field insulation film 110 between the third fin pattern F3 and the fourth fin pattern F4. The lower portion of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4 may fill the first separation trench 160at between the third fin pattern F3 and the fourth fin pattern F4. Therefore, the field insulation film 110 between the third fin pattern F3 and the fourth fin pattern F4 may surround the lower portion of the first device isolation film 160a.

[0141] In one implementation, the lower surface of the first device isolation film 160a in the first active pattern AP1 may be lower than the lower surface of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4. For example, the distance from the lower surface of the second interlayer insulating film 192 to the lower surface of the first device isolation film 160a in the first active pattern AP1 is ( Fig.17 and Fig.19 The distance D11) from the lower surface of the second interlayer insulating film 192 to the lower surface of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4 may be greater than the distance ( Fig.18 and Fig.19 D15).

[0142] In one implementation, the width of the first device isolation film 160a may be smaller than the width of the field insulation film 110 between the third fin pattern F3 and the fourth fin pattern F4. Here, the width refers to the width in the first direction X. For example, the width of the first device isolation film 160a ( Fig.18 The width W1) may be smaller than the width ( W1 ) of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4. Fig.18 W2).

[0143] In one implementation, the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 may overlap at least a portion of the first gate structure GS1 and at least a portion of the second gate structure GS2. Fig.18 As shown in , the first gate structure GS1 may extend along the upper surface of the third fin pattern F3 and the upper surface of the field insulating film 110 , and the second gate structure GS2 may extend along the upper surface of the fourth fin pattern F4 and the upper surface of the field insulating film 110 .

[0144] In one implementation, the uppermost surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 may be lower than the upper surfaces of the third fin pattern F3 and the fourth fin pattern F4. For example, the distance from the lower surface of the second interlayer insulating film 192 to the uppermost surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 is ( Fig.18 The distance D21) may be greater than the distance from the lower surface of the second interlayer insulating film 192 to the upper surfaces of the third fin pattern F3 and the fourth fin pattern F4.

[0145] In one implementation, the field insulating film 110 may include silicon oxide, and the first device isolation film 160a may include silicon nitride. In the NMOS region, the field insulating film including silicon oxide may help improve the performance of the semiconductor element by applying stress to the channel region. In the semiconductor device according to some embodiments, by forming the first device isolation film 160a on the field insulating film 110 including silicon oxide, the stress applied to the field insulating film 110 may be maintained.

[0146] Fig. 20 1 shows a cross-sectional view of a semiconductor device according to some embodiments. For ease of explanation, reference may be briefly explained or omitted. Figures 1 to 4 and Figures 16 to 19 Duplicate content of the component being described.

[0147] refer to Fig. 20In the semiconductor device according to some embodiments, the uppermost surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 may be on substantially the same plane as upper surfaces of the third fin pattern F3 and the fourth fin pattern F4.

[0148] For example, the distance from the lower surface of the second interlayer insulating film 192 to the uppermost surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 ( Fig. 20 The distance D22) may be substantially equal to the distance from the lower surface of the second interlayer insulating film 192 to the upper surfaces of the third and fourth fin patterns F3 and F4.

[0149] In one implementation, the lower surface of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4 may be lower than the uppermost surface of the field insulation film 110 between the third fin pattern F3 and the fourth fin pattern F4. For example, the distance from the lower surface of the second interlayer insulation film 192 to the lower surface of the first device isolation film 160a between the third fin pattern F3 and the fourth fin pattern F4 is ( Fig. 20 The distance D16) from the lower surface of the second interlayer insulating film 192 to the uppermost surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4 may be greater than the distance ( Fig. 20 D22).

[0150] Fig.21 A schematic layout diagram of a semiconductor device according to some embodiments is shown. Fig. 22 Shown along Fig.21 A cross-sectional view taken along line HH′. Fig.23 Shown along Fig.21 For the convenience of explanation, reference may be briefly explained or omitted. Figures 1 to 4 and Figures 16 to 19 Duplicate content of the component being described.

[0151] refer to Figure 21 to Figure 23 , in the semiconductor device according to some embodiments, the first device isolation film 160 a may be formed on the first region I of the substrate 100 , and may not be formed on the second region II of the substrate 100 .

[0152] The first device isolation film 160a may extend on the first region I of the substrate 100 in the second direction Y. Thus, the first device isolation film 160a may intersect the first and third active patterns AP1 and AP3.

[0153] The first device isolation film 160 a may not be formed between the third fin pattern F3 and the fourth fin pattern F4 . Also, the first device isolation film 160 a may not be formed between the fifth fin pattern F5 and the sixth fin pattern F6 .

[0154] The first interlayer insulating film 191 may be between the first gate structure GS1 and the second gate structure GS2 on the second region II of the substrate 100. Fig. 22 and Fig.23 As shown in FIG. 1 , the first interlayer insulating film 191 may be on the upper surface of the field insulating film 110 between the third fin pattern F3 and the fourth fin pattern F4. Therefore, the third fin pattern F3 and the fourth fin pattern F4 may be separated by the field insulating film 110 and the first interlayer insulating film 191. Similarly, the fifth fin pattern F5 and the sixth fin pattern F6 may be separated by the field insulating film 110 and the first interlayer insulating film 191.

[0155] Fig.24 Schematic layout diagrams of semiconductor devices according to some embodiments are shown. For ease of explanation, references may be briefly explained or omitted. Figures 1 to 4 and Figures 13 to 19 Duplicate content of the component being described.

[0156] refer to Fig.24 In the semiconductor device according to some embodiments, the first device isolation film 160 a and the second device isolation film 160 b may be between the third fin pattern F3 and the fourth fin pattern F4 and between the fifth fin pattern F5 and the sixth fin pattern F6 .

[0157] Therefore, the third fin pattern F3 and the fourth fin pattern F4 may be separated from each other by the field insulating film 110, the first device isolation film 160a and the second device isolation film 160b. In addition, the fifth fin pattern F5 and the sixth fin pattern F6 may be separated from each other by the field insulating film 110, the first device isolation film 160a and the second device isolation film 160b.

[0158] Fig.25 Schematic layout diagrams for illustrating semiconductor devices according to some embodiments are shown. For ease of explanation, references may be briefly described or omitted. Figures 1 to 4 and Figures 13 to 24 Duplicate content of the component being described.

[0159] refer to Fig.25 In the semiconductor device according to some embodiments, the first device isolation film 160 a and the second device isolation film 160 b may be on the first region I of the substrate 100 , and may not be on the second region II of the substrate 100 .

[0160] The first and second device isolation films 160a and 160b may extend on the first region I of the substrate 100 in the second direction Y. Thus, the first and second device isolation films 160a and 160b may intersect the first and third active patterns AP1 and AP3.

[0161] The first device isolation film 160a and the second device isolation film 160b may not be between the third fin pattern F3 and the fourth fin pattern F4. In addition, the first device isolation film 160a and the second device isolation film 160b may not be between the fifth fin pattern F5 and the sixth fin pattern F6.

[0162] On the second region II of the substrate 100, the first interlayer insulating film 191 may be between the first gate structure GS1 and the second gate structure GS2 and between the second gate structure GS2 and the fourth gate structure GS4. Therefore, the third fin pattern F3 and the fourth fin pattern F4 may be separated by the field insulating film 110 and the first interlayer insulating film 191. Similarly, the fifth fin pattern F5 and the sixth fin pattern F6 may be separated by the field insulating film 110 and the first interlayer insulating film 191.

[0163] In the following, reference will be made to Figures 1 to 4 , Figures 16 to 19 and Figure 26 to Figure 31 A method of manufacturing a semiconductor device according to some embodiments is described.

[0164] Figure 26 to Figure 31 Some stages in a method of manufacturing a semiconductor device according to some embodiments are shown. For ease of explanation, reference may be briefly described or omitted. Figures 1 to 25 Duplicate content of the component being described.

[0165] refer to Fig.26 , a first active pattern AP1 and a plurality of dummy gate structures DG may be formed on the substrate 100 .

[0166] The first active pattern AP1 may be formed to protrude from the substrate 100. For example, the first active pattern AP1 may be formed along a first direction ( Figure 1 The first active pattern AP1 may be a portion of the substrate 100 and may include an epitaxial layer grown from the substrate 100. Subsequently, a plurality of dummy gate structures DG intersecting the first active pattern AP1 may be formed on the first active pattern AP1. For example, each dummy gate structure DG may be arranged along the second direction ( Figure 1 Each dummy gate structure DG may include a dummy gate insulating film 520, a dummy gate electrode 530, a first mask pattern 550 and a preliminary gate spacer 540.

[0167] refer to Fig. 27, first to third source / drain regions 150 , 250 , and 350 may be formed in the first active pattern AP1 .

[0168] For example, each dummy gate structure DG may be used as an etching mask to etch a portion of the first active pattern AP1. Thus, first to third source / drain trenches 150t, 250t, and 350t may be formed in the first active pattern AP1. Subsequently, first to third source / drain regions 150, 250, and 350 may be formed to fill the first to third source / drain trenches 150t, 250t, and 350t, respectively. The first to third source / drain regions 150, 250, and 350 may be formed, for example, by an epitaxial growth process.

[0169] refer to Fig.28 , a first interlayer insulating film 191 may be formed on the first to third source / drain regions 150 , 250 , and 350 .

[0170] For example, in Fig. 27 An insulating film is formed on the resultant product. Subsequently, a planarization process may be performed. The planarization process may be performed, for example, until the upper surface of the dummy gate electrode 530 is exposed. Therefore, a first interlayer insulating film 191 covering the sidewalls of each dummy gate structure DG may be formed on the first to third source / drain regions 150, 250, and 350.

[0171] refer to Fig.29 , first to fourth gate structures GS1 , GS2 , GS3 , and GS4 may be formed instead of the dummy gate insulating film 520 and the dummy gate electrode 530 .

[0172] For example, you can Fig.28 The dummy gate insulating film 520 and the dummy gate electrode 530 are removed from the resultant product. Subsequently, the gate insulating films 120, 220, 320, and 420, the gate electrodes 130, 230, 330, and 430, and the capping patterns 155, 255, 355, and 455 may be filled in the region from which the dummy gate insulating film 520 and the dummy gate electrode 530 are removed. Thus, first to fourth gate structures GS1, GS2, GS3, and GS4 extending in the second direction Y may be formed on the first active pattern AP1.

[0173] refer to Fig.30 , a second mask pattern 180 exposing the first interlayer insulating film 191 between the first gate structure GS1 and the second gate structure GS2 may be formed.

[0174] The second mask pattern 180 may include an opening O that exposes the first interlayer insulating film 191 between the first gate structure GS1 and the second gate structure GS2. The opening O may be, for example, formed along the second direction ( Figure 1 The Y in the extension.

[0175] In one implementation, the width of the opening O may be wider than the distance between the first gate structure GS1 and the second gate structure GS2. For example, a portion of the first gate structure GS1 and / or a portion of the second gate structure GS2 may be exposed. Fig.30 As shown in FIG. 1 , the opening O may expose a portion of the first gate structure GS1 and a portion of the second gate structure GS2 .

[0176] refer to Fig.31 , a first separation trench 160at may be formed in the first active pattern AP1.

[0177] For example, the first interlayer insulating film 191 and the first active pattern AP1 between the first and second gate structures GS1 and GS2 may be etched using the second mask pattern 180 as an etching mask. Thus, the first separation trench 160at may be formed in the first active pattern AP1.

[0178] In one implementation, the opening O may expose a portion of the first gate structure GS1 and / or a portion of the second gate structure GS2, and may etch a portion of the first gate structure GS1 and / or a portion of the second gate structure GS2. For example, the first gate structure GS1 may include a first inclined surface GS1-S, and the second gate structure GS2 may include a second inclined surface GS2-S.

[0179] Next, refer to Figures 1 to 4 , a first device isolation film 160a for filling the first separation trench 160at may be formed.

[0180] For example, a separation film for filling the first separation trench 160at may be formed. Subsequently, a planarization process may be performed until the upper surfaces of the first to fourth gate structures GS1, GS2, GS3, and GS4 are exposed. Thus, a first device isolation film 160a may be formed between the first gate structure GS1 and the second gate structure GS2. A second interlayer insulating film 192 may be formed to cover the first interlayer insulating film 191, the first to fourth gate structures GS1, GS2, GS3, and GS4, and the first device isolation film 160a.

[0181] As a summary and review, multi-gate transistors can use three-dimensional channels and can be easily scaled down. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be improved. In addition, the SCE (short channel effect) in which the channel region potential is affected by the drain voltage can be effectively suppressed.

[0182] One or more embodiments may provide a semiconductor device including a device isolation film between gate structures and a method of manufacturing the same.

[0183] One or more embodiments may provide a semiconductor device in which integration, reliability, and performance of elements are improved.

[0184] One or more embodiments may provide a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved integration, reliability, and performance of elements.

[0185] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be clear to those of ordinary skill in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly noted. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: substrate; an active pattern extending along a first direction on the substrate; a field insulating film surrounding a portion of a side wall of the active pattern; a first gate structure extending on the active pattern and the field insulating film along a second direction, wherein the second direction intersects the first direction; a second gate structure spaced apart from the first gate structure and extending along a second direction on the active pattern and the field insulating film; as well as a first device isolation film, between the first gate structure and the second gate structure, and directly contacting the first gate structure and the second gate structure, in: A side wall of the first gate structure facing the first device isolation film includes a first inclined surface having an acute angle with respect to an upper surface of the active pattern, and A lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.

2. The semiconductor device according to claim 1, wherein: The active pattern includes a separation trench between the first gate structure and the second gate structure, and A lower portion of the first device isolation film fills the separation trench. 3 . The semiconductor device according to claim 1 , wherein the first inclined surface is in direct contact with the first device isolation film. 4 . The semiconductor device of claim 1 , wherein the first inclined surface comprises a first surface having a first acute angle with respect to an upper surface of the active pattern and a second surface having a second acute angle different from the first acute angle. 5 . The semiconductor device according to claim 1 , wherein a sidewall of the second gate structure facing the first device isolation film includes a second inclined surface having an acute angle with respect to an upper surface of the active pattern.

6. The semiconductor device according to claim 1, wherein: The active pattern includes a first fin pattern and a second fin pattern separated by the field insulating film, and The field insulating film between the first fin pattern and the second fin pattern surrounds a lower portion of the first device isolation film.

7. The semiconductor device according to claim 6, wherein: The active pattern is formed on the NMOS region, The field insulating film includes silicon oxide, and The first device isolation film includes silicon nitride.

8. The semiconductor device according to claim 1, further comprising: a third gate structure, spaced apart from the first gate structure, the second gate structure being located between the first gate structure and the third gate structure, and the third gate structure extending along a second direction on the active pattern and the field insulating film; as well as a second device isolation film, between the second gate structure and the third gate structure, The lowermost surface of the second device isolation film is lower than the uppermost surface of the field insulation film or is substantially coplanar with the uppermost surface of the field insulation film.

9. The semiconductor device according to claim 1, wherein: The first device isolation film includes a first portion that does not overlap with the field insulating film and a second portion that overlaps with the field insulating film, and A lower surface of the first portion is lower than a lower surface of the second portion.

10. A semiconductor device comprising: substrate; an active pattern on the substrate, the active pattern comprising a separation trench; A device isolation film filling the separation trench; a source / drain region in the active pattern; as well as a gate structure intersecting the active pattern on the active pattern between the device isolation film and the source / drain region, The sidewall of the gate structure is in direct contact with the device isolation film and includes a first inclined surface having an acute angle with respect to an upper surface of the active pattern.

11. The semiconductor device according to claim 10, wherein: The gate structure includes a gate insulating film on the active pattern, a gate electrode on the gate insulating film, and a gate spacer on a sidewall of the gate electrode, and The gate insulating film extends along sidewalls and a lower surface of a gate trench defined by the gate spacer. 12 . The semiconductor device according to claim 11 , wherein the gate spacer defines at least a portion of the first inclined surface. 13 . The semiconductor device according to claim 11 , wherein the gate structure further comprises a capping pattern on an upper surface of the gate electrode. 14 . The semiconductor device according to claim 10 , wherein an upper surface of the device isolation film and an upper surface of the gate structure are on substantially the same plane.

15. The semiconductor device according to claim 10, further comprising an interlayer insulating film on the source / drain region and covering the sidewall of the gate structure, wherein an upper surface of the device isolation film and an upper surface of the interlayer insulating film are on substantially the same plane.

16. A semiconductor device comprising: A substrate including a first region and a second region; a first active pattern including a first separation trench and extending along a first direction on the first region of the substrate; a second active pattern extending along a first direction on the second region of the substrate; a first gate structure extending on the first active pattern and the second active pattern along a second direction, wherein the second direction intersects the first direction; a second gate structure spaced apart from the first gate structure and extending along a second direction on the first active pattern and the second active pattern; as well as a device isolation film filling the first separation trench and extending along a second direction between the first gate structure and the second gate structure, The sidewall of the first gate structure is in direct contact with the device isolation film and includes a first inclined surface having an acute angle with respect to an upper surface of the first active pattern. 17 . The semiconductor device according to claim 16 , wherein the first region is a PMOS region, and the second region is an NMOS region. 18 . The semiconductor device according to claim 16 , wherein the device isolation film extends in a second direction on the first region and the second region.

19. The semiconductor device according to claim 16, wherein: The second active pattern includes a first fin pattern and a second fin pattern separated by a field insulating film, and The field insulating film surrounds a lower portion of the device isolation film.

20. The semiconductor device according to claim 16, further comprising an interlayer insulating film covering a side wall of the first gate structure and a side wall of the second gate structure, wherein an upper surface of the device isolation film and an upper surface of the interlayer insulating film are on substantially the same plane.

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