A high current silicon-on-insulator lateral insulated gate bipolar transistor

Abstract

The invention discloses a high-current silicon-on-insulator lateral insulated gate bipolar transistor, belonging to the technical field of semiconductor integrated circuits. The invention comprises an NMOS tube A, a self-biased PMOS tube B and an NMOS tube C. An N+ drain region of the NMOS tube A and an N+ source region of the NMOS tube C are interconnected by metal, and an N+ source region of the NMOS tube A is connected to a P+ drain region of the PMOS tube B. The two are short-circuited by metal and serve as the cathode of the device of the invention. Polycrystalline silicon connected to the cathode metal serves as the gate of the PMOS tube B. The anode of a conventional silicon lateral insulated gate bipolar transistor serves as the anode of the device of the invention. Compared with the silicon-on-insulator lateral insulated gate bipolar transistor of the prior art, the invention has a larger current density, a smaller conduction loss and a chip area under the condition of an equal conduction voltage drop, thereby solving the problems in the prior art.

Description

Technical Field

[0001] The invention relates to a high-current silicon-on-insulator lateral insulated gate bipolar transistor, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] An insulated gate bipolar transistor (IGBT) is a composite power device evolved from the combination of a MOS gate device structure and a bipolar transistor structure. It has the characteristics of a MOS tube and a bipolar transistor, and has a good compromise between on-state current and switching loss. Its lateral structure has been widely used in power integrated circuits. For example, Chinese patent application No. 201510998522.X discloses a lateral insulated gate bipolar transistor, which adds an electric field enhancement unit on the basis of the prior art LIGBT device. The enhancement unit consists of an acceleration gate, an acceleration gate heavily doped region, a high-resistance conductive region, a ground doped region, and a ground electrode. The electric field enhancement unit is used to generate an electric field pointing from the anode to the lower surface of the electric field enhancement unit. The electric field enhancement unit is isolated from the drift region by an insulating medium. Although this structure can increase the current density, it has the problems of large leakage current and the need for an additional drive circuit. For another example, in the document “A Composite Structure Named Self-adjusted Conductivity Modulation SOI-LIGBT with Low On-state Voltage”, a conductivity self-modulated LIGBT device with low on-state voltage drop is proposed, but this device requires the production of an isolation dielectric area and a complex grooving process.

[0003] In summary, how to obtain an insulated gate bipolar transistor with a higher current density, smaller conduction loss and chip area under the condition of equal conduction voltage drop has become a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the deficiencies in the prior art, the object of the present invention is to provide a high current silicon-on-insulator lateral insulated gate bipolar transistor to solve the problems in the prior art.

[0005] A high current silicon-on-insulator lateral insulated gate bipolar transistor described in the present invention comprises a P-type substrate, wherein a buried oxide, an N-type epitaxial layer and an N-type buffer layer are sequentially arranged above the P-type substrate, an anode, a cathode and a gate of the transistor are arranged above the N-type epitaxial layer, an NMOS tube A, a self-biased PMOS tube B and an NMOS tube C are arranged above the N-type epitaxial layer, a first P-type well region and a second P-type well region are arranged on one side above the N-type epitaxial layer, the first P-type well region and the second P-type well region are respectively close to the anode and the cathode of the transistor, wherein the NMOS tube A is arranged in the second P-type well region, the self-biased PMOS tube B is bridged between the first P-type well region and the second P-type well region, and the NMOS tube C is bridged between the first P-type well region and the N-type well region. The NMOS tube A is connected to the self-biased PMOS tube B between the epitaxial layers, the NMOS tube A includes the A tube N+ drain region and the A tube N+ source region, the self-biased PMOS tube B includes the B tube P+ drain region, and the NMOS tube C includes the C tube N+ source region, wherein the A tube N+ drain region and the C tube N+ source region are interconnected, and the A tube N+ source region and the B tube P+ drain region are connected and then led out as the cathode of the transistor through a cathode metal short circuit, the N-type buffer layer is arranged on one side of the N-type epitaxial layer, and the upper layer of the N-type buffer layer is provided with a P+ anode region on the side away from the cathode direction of the transistor, the C tube N+ source region, the first P-type well region, and the N-type epitaxial layer together constitute an NPN type parasitic transistor, and the first P-type well region, the N-type epitaxial layer and the P+ anode region together constitute a PNP type transistor.

[0006] The cathode region of the transistor of the present invention is different from the cathode region of the silicon lateral insulated gate bipolar transistor in the prior art, and is divided into an NMOS tube A, a self-biased PMOS tube B, and an NMOS tube C, and the tubes A, B, and C are compactly distributed. The gate of the NMOS tube A and the gate of the NMOS tube C are interconnected as the gate (Gate) of the device, the N+ drain region of the NMOS tube A and the N+ source region of the NMOS tube C are interconnected, the N+ source region of the NMOS tube A and the P+ drain region of the self-biased PMOS tube B are connected, and the two are short-circuited by cathode metal as the cathode (Cathode) of the device of the present invention, the polysilicon connected to the cathode metal is used as the gate of the self-biased PMOS tube B, and the anode of the silicon lateral insulated gate bipolar transistor in the prior art is used as the anode (Anode) of the device of the present invention.

[0007] Furthermore, an anode metal is provided above the P+ anode region, and the anode metal is led out to serve as an anode of the transistor.

[0008] Furthermore, the NMOS tube A also includes a polysilicon gate of the A tube, and the NMOS tube C also includes a polysilicon gate of the C tube. The polysilicon gate of the A tube and the polysilicon gate of the C tube are connected and then led out as the gate of the transistor.

[0009] Furthermore, the NMOS tube A also includes an A tube gate oxide layer, the lower surface of the A tube gate oxide layer is in contact with the upper surfaces of the A tube N+ drain region and the A tube N+ source region respectively, the A tube polysilicon gate is located above the A tube gate oxide layer, and the A tube metal is provided above the A tube N+ drain region, and the A tube metal, the A tube polysilicon gate and the cathode metal are not connected to each other.

[0010] Furthermore, the self-biased PMOS tube B also includes a polysilicon gate of the tube B, and the polysilicon gate of the tube B is connected to the cathode metal.

[0011] Furthermore, the self-biased PMOS tube B also includes a B tube P+ source region and a B tube gate oxide layer, the lower surface of the B tube gate oxide layer is in contact with the upper surfaces of the B tube P+ drain region and the B tube P+ source region respectively, the B tube polysilicon gate is located above the B tube gate oxide layer, the cathode metal is located above the B tube P+ drain region, and the A tube N+ source region and the B tube P+ drain region are respectively located on both sides below the cathode metal.

[0012] Furthermore, the NMOS tube C also includes a C tube gate oxide layer, and the C tube polysilicon gate is located above the C tube gate oxide layer.

[0013] Furthermore, the C tube N+ source region and the B tube P+ source region are adjacent, a C tube metal is provided above the C tube N+ source region, the C tube polysilicon gate, the C tube metal, and the B tube polysilicon gate are not connected to each other, and the A tube metal and the C tube metal are connected to each other.

[0014] Furthermore, a first P-type buried layer is provided inside the first P-type well region, and the B-tube P+ source region and the C-tube N+ source region are provided above the first P-type buried layer.

[0015] Furthermore, a second P-type buried layer is provided in the second P-type well region, and the B-tube P+ drain region, the A-tube N+ source region and the A-tube N+ drain region are arranged above the second P-type buried layer.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The high current silicon-on-insulator lateral insulated gate bipolar transistor described in the present invention has a larger current density, smaller conduction loss and chip area under the condition of equal conduction voltage drop compared with the silicon-on-insulator lateral insulated gate bipolar transistor in the prior art. When the anode voltage is 2.59V, the current density of the device of the present invention is increased by 47% compared with the device of the prior art, and when the anode voltage is 20V, the current density of the device of the present invention is increased by 103% compared with the device of the prior art. Obviously, the device of the present invention increases the current density at a lower voltage by latching, while maintaining a larger current density in the saturation region. At the same time, no complicated groove engraving process is required, which solves the problems in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A structural diagram of a silicon-on-insulator lateral insulated gate bipolar transistor in the prior art;

[0019] Figure 2 The structure of a high current silicon-on-insulator lateral insulated gate bipolar transistor in an embodiment of the present invention is shown in FIG. Figure 1 ;

[0020] Figure 3 The structure of a high current silicon-on-insulator lateral insulated gate bipolar transistor in an embodiment of the present invention is shown in FIG. Figure 2 ;

[0021] Figure 4 An equivalent simplified circuit diagram of a silicon lateral insulated gate bipolar transistor in the prior art in an embodiment of the present invention and a current flow diagram thereof in a forward conduction state;

[0022] Figure 5 An equivalent simplified circuit diagram and a current flow diagram of a high current silicon-on-insulator lateral insulated gate bipolar transistor operating in a linear region according to an embodiment of the present invention;

[0023] Figure 6 It is a cathode region current flow diagram of a high current silicon-on-insulator lateral insulated gate bipolar transistor operating in a saturation region in an embodiment of the present invention;

[0024] Figure 7 A cathode region current flow diagram of a high current silicon-on-insulator lateral insulated gate bipolar transistor when entering a latched state at a relatively low voltage in an embodiment of the present invention;

[0025] Figure 8 It is a current flow diagram of the cathode region when the high current silicon-on-insulator lateral insulated gate bipolar transistor enters a saturation state as the anode voltage continues to increase in an embodiment of the present invention;

[0026] Fig. 9 A comparison diagram of the breakdown voltages of a high current silicon-on-insulator lateral insulated gate bipolar transistor in an embodiment of the present invention and a LIGBT device in the prior art;

[0027] Fig.10 A comparison diagram of forward conduction characteristics of a high current silicon-on-insulator lateral insulated gate bipolar transistor and a LIGBT device in the prior art when the anode voltage is 2.59V in an embodiment of the present invention;

[0028] Fig.11 This is a comparison diagram of forward conduction characteristics of a high current silicon-on-insulator lateral insulated gate bipolar transistor and a LIGBT device in the prior art when the anode voltage is 20V in an embodiment of the present invention;

[0029] In the figure: 1, P-type substrate; 2, buried oxide; 3, N-type epitaxial layer; 4, N-type buffer layer; 5, P+ anode region; 6, anode metal; 7, first P-type well region; 8, first P-type buried layer; 9, C tube N+ source region; 10, C tube gate oxide layer; 11, C tube polysilicon gate; 12, C tube metal; 13, B tube P+ source region; 14, B tube polysilicon gate; 15, B tube gate oxide layer; 16, cathode metal; 17, B tube P+ drain region; 18, A tube N+ source region; 19, second P-type well region; 20, A tube N+ drain region; 21, A tube metal; 22, A tube polysilicon gate; 23, A tube gate oxide layer; 24, second P-type buried layer; 25, NMOS tube A; 26, self-biased PMOS tube B; 27, NMOS tube C. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0031] Embodiment 1:

[0032] like Figure 2 and Figure 3 As shown, the high current silicon-on-insulator lateral insulated gate bipolar transistor of the present invention comprises a P-type substrate 1, a buried oxide 2, an N-type epitaxial layer 3 and an N-type buffer layer 4 are sequentially arranged above the P-type substrate 1, an anode, a cathode and a gate of the transistor are arranged above the N-type epitaxial layer 3, an NMOS transistor A25, a self-biased PMOS transistor B26 and an NMOS transistor C27 are arranged above the N-type epitaxial layer 3, a first P-type well region 7 and a second P-type well region 19 are arranged on one side above the N-type epitaxial layer 3, the first P-type well region 7 and the second P-type well region 19 are respectively close to the anode and the cathode of the transistor, wherein the NMOS transistor A25 is arranged in the second P-type well region 19, the self-biased PMOS transistor B26 is bridged between the first P-type well region 7 and the second P-type well region 19, and the NMOS transistor C27 is bridged between the first P-type well region 7 and the N-type epitaxial layer 3. 3, NMOS transistor A25 is connected to self-biased PMOS transistor B26, NMOS transistor A25 includes A tube N+ drain region 20, A tube N+ source region 18, self-biased PMOS transistor B26 includes B tube P+ drain region 17, NMOS transistor C27 includes C tube N+ source region 9, wherein A tube N+ drain region 20 is interconnected with C tube N+ source region 9, A tube N+ source region 18 is connected with B tube P+ drain region 17 and then short-circuited through cathode metal 16 to be led out as the cathode of the transistor, N-type buffer layer 4 is arranged on one side of N-type epitaxial layer 3, and a P+ anode region 5 is arranged on the upper layer of N-type buffer layer 4 away from the cathode direction of the transistor, C tube N+ source region 9, first P-type well region 7, N-type epitaxial layer 3 together constitute an NPN type parasitic transistor, and the first P-type well region 7, N-type epitaxial layer 3 and P+ anode region 5 together constitute a PNP type transistor.

[0033] An anode metal 6 is disposed above the P+ anode region 5 , and the anode metal 6 is led out to serve as the anode of the transistor.

[0034] NMOS transistor A25 further includes an A-tube polysilicon gate 22, and NMOS transistor C27 further includes a C-tube polysilicon gate 11. The A-tube polysilicon gate 22 and the C-tube polysilicon gate 11 are connected and then led out as the gate of the transistor.

[0035] The NMOS tube A25 also includes an A-tube gate oxide layer 23, the lower surface of which is in contact with the upper surfaces of the A-tube N+ drain region 20 and the A-tube N+ source region 18, respectively. The A-tube polysilicon gate 22 is located above the A-tube gate oxide layer 23, and an A-tube metal 21 is provided above the A-tube N+ drain region 20. The A-tube metal 21, the A-tube polysilicon gate 22 and the cathode metal 16 are not connected to each other.

[0036] The self-biased PMOS transistor B 26 further includes a B-tube polysilicon gate 14 , which is connected to a cathode metal 16 .

[0037] The self-biased PMOS tube B 26 also includes a B tube P+ source region 13 and a B tube gate oxide layer 15. The lower surface of the B tube gate oxide layer 15 is in contact with the B tube P+ drain region 17 and the upper surface of the B tube P+ source region 13 respectively. The B tube polysilicon gate 14 is located above the B tube gate oxide layer 15. The cathode metal 16 is located above the B tube P+ drain region 17. The A tube N+ source region 18 and the B tube P+ drain region 17 are respectively located on both sides below the cathode metal 16.

[0038] The NMOS tube C 27 further includes a C tube gate oxide layer 10 , and a C tube polysilicon gate 11 is located above the C tube gate oxide layer 10 .

[0039] The C tube N+ source region 9 and the B tube P+ source region 13 are adjacent to each other. A C tube metal 12 is provided above the C tube N+ source region 9. The C tube polysilicon gate 11, the C tube metal 12, and the B tube polysilicon gate 14 are not connected to each other. The A tube metal 21 and the C tube metal 12 are connected to each other.

[0040] A first P-type buried layer 8 is provided inside the first P-type well region 7 , and a B-tube P+ source region 13 and a C-tube N+ source region 9 are provided above the first P-type buried layer 8 .

[0041] A second P-type buried layer 24 is provided in the second P-type well region 19 , and the B-tube P+ drain region 17 , the A-tube N+ source region 18 and the A-tube N+ drain region 20 are arranged above the second P-type buried layer 24 .

[0042] The working principle of this embodiment is as follows: Figure 1 As shown, Figure 1The structure diagram of the silicon-on-insulator lateral insulated gate bipolar transistor of the prior art, the cathode region of the device of the present invention is different from the cathode region of the silicon lateral insulated gate bipolar transistor of the prior art, and is divided into NMOS tube A25, self-biased PMOS tube B26, and NMOS tube C27. The gate of NMOS tube A25 and the gate of NMOS tube C27 are interconnected by metal as the gate (Gate) of the device of the present invention, the N+ drain region of NMOS tube A25 and the N+ source region of NMOS tube C27 are interconnected by metal, the N+ source region of NMOS tube A25 is connected to the P+ drain region of PMOS tube B26, and the two are short-circuited by cathode metal 16 as the cathode (Cathode) of the device of the present invention, the polysilicon connected to the above cathode metal 16 is used as the gate of PMOS tube B, and the anode of the silicon lateral insulated gate bipolar transistor of the prior art is used as the anode (Anode) of the device of the present invention. Compared with the silicon-on-insulator lateral insulated gate bipolar transistor in the prior art (such as the document “A Composite Structure Named Self-adjusted Conductivity Modulation SOI-LIGBT with Low On-state Voltage”), there is no need to make an isolation dielectric region, and obviously has a smaller chip area.

[0043] Working principle of the on-state linear region: A voltage greater than the threshold voltage is applied to the gate of the device, and electrons flow from the cathode of the device through the channels of NMOS tube A25 and NMOS tube C27 in sequence, and finally flow into the drift region of the device (N-type epitaxial layer 3). When the anode voltage of the device is relatively small, holes are injected from the anode of the device into the drift region (N-type epitaxial layer 3) of the device, and most of the injected holes accumulate in the first P-type well region 7, so that the potential of the first P-type well region 7 is raised, but has not yet reached the turn-on voltage of the self-biased PMOS tube B26, so the self-biased PMOS tube B26 has not yet turned on; when the potential between the first P-type well region 7 and the N+ source region (C tube N+ source region 9) of the NMOS tube C27 is greater than the built-in potential of its PN junction, the NPN parasitic triode composed of the C tube N+ source region 9, the first P-type well region 7, and the N-type epitaxial layer 3 is triggered, and a large number of electrons are injected into the N-type epitaxial layer 3 through the first P-type well region 7, so the carrier concentration in the drift region of the device is greatly increased, and the current is greatly increased. Obviously, when the current density of the device of the present invention is equal to that of the prior art device, the on-state voltage of the device of the present invention will be smaller, and the conduction loss will also be smaller.

[0044] On-state saturation region principle: When the anode voltage continues to increase in the on-state, the potential of the first P-type well region 7 also continues to increase, because the P+ drain region 17 of the B tube is connected to the polysilicon gate 14 of the B tube through the cathode metal 16. When the potential of the P-type well region 7 is higher than the absolute value of the threshold voltage of the self-biased PMOS tube B26, the self-biased PMOS tube B26 is turned on, and holes can flow into the cathode of the device through the self-biased PMOS tube B26. In addition, after the self-biased PMOS tube B26 is turned on, the potential of the first P-type well region 7 is clamped, and due to the equivalent on-resistance between the drain and source of the NMOS tube A25, the potential of the N+ source region 9 of the C tube will increase with the increase of the anode voltage. When the potential between the P-type well region 7 and the C tube N+ source region 9 is less than the built-in potential of its PN junction, the NPN parasitic transistor composed of the C tube N+ source region 9, the first P-type well region 7, and the N-type epitaxial layer 3 is turned off, the electron current of the device flows away through the channel of the NMOS tube C 27, and the hole current flows into the cathode of the device through the PMOS tube B 26, and the device enters a saturation state.

[0045] Figure 4 The equivalent simplified circuit diagram of the prior art LIGBT device and the current flow diagram in the forward conduction state are shown in FIG. Figure 5 and Figure 6 The equivalent simplified circuit diagram and current flow diagram of the device of the present invention when it works in the linear region and saturation region respectively. Figure 5 and Figure 6 It can be seen that the current flow direction of the device of the present invention is inconsistent in the linear region and the saturation region. Figure 4 and Figure 6 It can be seen that in the saturation working region, the current flow direction of the device of the present invention is substantially consistent with the current flow direction of the device of the prior art structure. Figure 5 It shows that when the device of the present invention is in the linear working area, the parasitic thyristor composed of the PNP transistor and the parasitic NPN transistor has a latching effect, thereby forming a strong conductivity modulation effect in the drift region, which greatly increases the current density of the device.

[0046] In order to verify the advantages of the device of the present invention, the present invention uses semiconductor simulation software to compare and simulate the device performance. The results are as follows: Figure 7 and 8 shown. Figure 7 FIG. 1 is a diagram showing the current flow direction in the cathode region when the device of the present invention enters a latched state at a relatively low voltage. Figure 7 It can be seen that the device has a latch effect at this time, and the self-biased PMOS tube B 26 has not yet been turned on. Figure 8 2 is a cathode current flow diagram when the device of the present invention enters a saturation state as the anode voltage continues to increase. As the NPN parasitic transistor is turned off and the self-biased PMOS tube B 26 is turned on, the device gradually exits the latched state and enters a saturation working area. Fig. 9 4 is a comparison diagram of the breakdown voltage of the device of the present invention and the prior art LIGBT device. It can be seen from the figure that the breakdown voltage of the device of the present invention is slightly higher and the leakage current is slightly lower, and the performance is better than the prior art device.

[0047] Fig.10 and Fig.11 is a comparison diagram of the forward conduction characteristics of the device of the present invention and the prior art device, Fig.10 When the anode voltage is 2.59V, the current density of the device of the present invention is increased by 47% compared with the prior art device, and the current density is 500A / cm 2 , the anode voltage is reduced by 34.43%, so it has smaller conduction loss. Fig.11 The current density of the device of the present invention increases by 103% compared with the prior art device when the anode voltage is 20 V. Obviously, the device of the present invention increases the current density at low voltage by latching, while maintaining a relatively large current density in the saturation region.

[0048] A high current silicon-on-insulator lateral insulated gate bipolar transistor using the embodiment of the present invention described above in combination with the accompanying drawings has a higher current density, smaller conduction loss and chip area under the same conduction voltage drop compared to the silicon-on-insulator lateral insulated gate bipolar transistor in the prior art, thereby solving the problems in the prior art. However, the present invention is not limited to the described implementation modes, and the changes, modifications, substitutions and deformations made to the implementation modes without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A high current silicon-on-insulator lateral insulated gate bipolar transistor, comprising a P-type substrate (1), a buried oxide (2), an N-type epitaxial layer (3) and an N-type buffer layer (4) are sequentially arranged above the P-type substrate (1), and an anode, a cathode and a gate of the transistor are arranged above the N-type epitaxial layer (3), characterized in that: An NMOS transistor A (25), a self-biased PMOS transistor B (26) and an NMOS transistor C (27) are arranged above the N-type epitaxial layer (3); a first P-type well region (7) and a second P-type well region (19) are arranged on one side above the N-type epitaxial layer (3); the first P-type well region (7) and the second P-type well region (19) are respectively close to the anode and cathode of the transistor; the NMOS transistor A (25) is arranged in the second P-type well region (19); the self-biased PMOS transistor B (26) is connected between the first P-type well region (7) and the second P-type well region (19); the NMOS transistor C (27) is connected between the first P-type well region (7) and the N-type epitaxial layer (3); the NMOS transistor A (25) is connected to the self-biased PMOS transistor B (26); the NMOS transistor A (25) comprises an A-tube N+ drain region (2 0), an A tube N+ source region (18), a self-biased PMOS tube B (26) includes a B tube P+ drain region (17), an NMOS tube C (27) includes a C tube N+ source region (9), wherein the A tube N+ drain region (20) is interconnected with the C tube N+ source region (9), the A tube N+ source region (18) is connected with the B tube P+ drain region (17) and then short-circuited through a cathode metal (16) to be led out as a cathode of the transistor, an N-type buffer layer (4) is arranged on one side of the N-type epitaxial layer (3), a P+ anode region (5) is arranged on the upper layer of the N-type buffer layer (4) away from the cathode direction of the transistor, the C tube N+ source region (9), the first P-type well region (7), and the N-type epitaxial layer (3) together constitute an NPN type parasitic triode, and the first P-type well region (7), the N-type epitaxial layer (3) and the P+ anode region (5) together constitute a PNP type triode; The NMOS tube A (25) further comprises a polysilicon gate electrode (22) of the A tube, and the NMOS tube C (27) further comprises a polysilicon gate electrode (11) of the C tube. The polysilicon gate electrode (22) of the A tube and the polysilicon gate electrode (11) of the C tube are connected to serve as the gate electrode of the transistor. The NMOS tube A (25) further comprises an A tube gate oxide layer (23), the lower surface of the A tube gate oxide layer (23) is in contact with the upper surface of the A tube N+ drain region (20) and the A tube N+ source region (18), respectively, the A tube polysilicon gate (22) is located above the A tube gate oxide layer (23), and an A tube metal (21) is provided above the A tube N+ drain region (20), and the A tube metal (21), the A tube polysilicon gate (22) and the cathode metal (16) are not connected to each other; The self-biased PMOS tube B (26) further comprises a B tube polysilicon gate (14), and the B tube polysilicon gate (14) is connected to a cathode metal (16); The self-biased PMOS tube B (26) further comprises a B tube P+ source region (13) and a B tube gate oxide layer (15), the lower surface of the B tube gate oxide layer (15) is in contact with the upper surface of the B tube P+ drain region (17) and the B tube P+ source region (13), the B tube polysilicon gate (14) is located above the B tube gate oxide layer (15), the cathode metal (16) is located above the B tube P+ drain region (17), and the A tube N+ source region (18) and the B tube P+ drain region (17) are respectively located on both sides below the cathode metal (16); A first P-type buried layer (8) is provided inside the first P-type well region (7), and a B-tube P+ source region (13) and a C-tube N+ source region (9) are arranged above the first P-type buried layer (8).

2. A high current silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, characterized in that: An anode metal (6) is provided above the P+ anode region (5), and the anode metal (6) is led out to serve as the anode of the transistor.

3. The high current silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, characterized in that: The NMOS tube C (27) further comprises a C tube gate oxide layer (10), and the C tube polysilicon gate (11) is located above the C tube gate oxide layer (10).

4. The high current silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, characterized in that: The C tube N+ source region (9) and the B tube P+ source region (13) are adjacent to each other, a C tube metal (12) is provided above the C tube N+ source region (9), the C tube polysilicon gate (11), the C tube metal (12), and the B tube polysilicon gate (14) are not connected to each other, and the A tube metal (21) and the C tube metal (12) are connected to each other.

5. The high current silicon-on-insulator lateral insulated gate bipolar transistor according to claim 1, characterized in that: A second P-type buried layer (24) is provided in the second P-type well region (19), and the B-tube P+ drain region (17), the A-tube N+ source region (18) and the A-tube N+ drain region (20) are arranged above the second P-type buried layer (24).

Images