Micro Ultra-Low Capacitance Solid Discharge Tube and Its Preparation Method

Abstract

A micro ultra-low capacitance solid discharge tube and a preparation method thereof. A boron-based region P is provided on the upper surface of the solid discharge tube. A partially overlapping phosphorus-diffused buried layer N- is arranged on one side of the boron-based region P. A first phosphorus-diffused region N+ is arranged in the boron-based region P. A plurality of short-circuit holes are arranged in the first phosphorus-diffused region N+ to form a cell-type cathode. A boron region P and a second phosphorus-diffused region N+ are arranged on the lower surface of the solid discharge tube. The aforementioned boron region P and the second phosphorus-diffused region N+ are arranged at intervals to form a unidirectional chip anode structure. Based on the original low-capacitance structure design, an N- buried layer is added to the cathode in the present invention, so that the heat sink of each cell cathode increases, thereby increasing the current-carrying capacity on the basis of the same chip area. The following uses a symmetric layout of the boron region and the second phosphorus-diffused region N+ to eliminate the reverse voltage drop of the unidirectional discharge tube. Based on this design, the original chip area can be reduced, and then the PN junction area can be reduced, and the junction capacitance can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to the design and manufacture of semiconductor chips, and particularly to a micro ultra-low capacitance solid discharge tube. Background Art

[0002] At present, the withstand voltage control of conventional low-voltage solid discharge tubes (below 64V) can achieve a consistency within 5V, which can fully meet the current circuit requirements of the client. However, as the data transmission rate of the client application circuit is getting higher and higher, and the design power consumption of the circuit board is getting lower and lower, the application of low-voltage, small-size, and high-integration solid protection devices is becoming more and more extensive. However, the junction capacitance of low-voltage solid protection devices with the same lightning strike level is generally relatively high, 25 - 30 pF. Because the higher junction capacitance will affect the data transmission quality, the junction capacitance will cause packet loss in the transmission of digital signals, thereby reducing the data transmission rate. The junction capacitance is mainly affected by the P-region diffusion concentration and the substrate resistivity. Generally, the lower the doping concentration at both ends of the semiconductor PN junction, the wider the barrier width, and the smaller the junction parasitic capacitance. Among them, conventional structure devices control the voltage by the P-region diffusion concentration and the substrate resistivity. As Figure 1 shown, the parasitic junction capacitance value is closely related to the voltage value, and the application of solid discharge tubes takes voltage as the most important characteristic parameter. Therefore, when the material resistivity and boron diffusion concentration are fixed, the capacitance in this structure is a fixed parameter. The current minimum area of this type of device is 0.9 * 0.9, and the package form is mainly SMA package. The capacitance value is usually between 25 - 30 pF (breakdown voltage 64V, withstand 1500V lightning strike). With the continuous improvement of the integration degree of the client circuit board, in order to conform to the development of the application field, signal-level protection devices integrating a micro-small area and low-capacitance structure have emerged as the times require. As Figure 2 shown, this structure uses an N-buried layer to form a region with a higher doping concentration in a high-resistivity silicon substrate, so that when the same P diffusion concentration is ensured, that is, the breakdown voltage is guaranteed, and the parasitic capacitance in the region other than the buried layer is greatly reduced. The capacitance value of this type of device under a fixed area is usually between 5 - 7 pF (breakdown voltage 24V, withstand 600V lightning strike).

[0003] With the development of 5G networks, including the trend of high integration in circuit board design, since 2018, customers have proposed products with a parasitic capacitance below 15 pF, and require that the external dimensions of the device be as small as possible (below 0.6mm * 0.6mm), which is convenient for integrated packaging limited to SOT-23 surface mount packaging. However, according to the current low-capacitance structure and area, the packaging requirements and the application requirements of customers cannot be met. Summary of the Invention

[0004] The object of the present invention is to address the problems that the current low-capacitance structure cannot achieve a parasitic capacitance below 15 pF, and the current chip area cannot meet the requirements of the tiny SOT-23 integrated package. The product required by the customer needs to integrate and package 4 chips in the SOT-23. The maximum chip mounting area of the main chip base island is 0.6 um * 0.6 um. Therefore, a micro ultra-low capacitance solid discharge tube is proposed according to this requirement.

[0005] The technical solution of the present invention is as follows:

[0006] A preparation method of a micro ultra-low capacitance solid discharge tube, the upper surface of the solid discharge tube has a boron-based region P, and the preparation method includes the following steps:

[0007] S1. Before preparing the boron-based region P, a phosphorus diffusion buried layer N- that overlaps with a unilateral part of the boron-based region P is arranged in advance, and the depth of the phosphorus diffusion buried layer N- is greater than the depth of the boron-based region P;

[0008] S2. Prepare the boron-based region P and the boron region P, and the aforementioned boron region P is arranged on the lower surface of the solid discharge tube;

[0009] S3. Arrange a first phosphorus diffusion region N+ in the boron-based region P, and arrange a plurality of short-circuit holes in the first phosphorus diffusion region N+ to form a cell-type cathode;

[0010] S4. Arrange a second phosphorus diffusion region N+ on the lower surface of the solid discharge tube, and the aforementioned second phosphorus diffusion region N+ is arranged at intervals with the aforementioned boron region P to form the solid discharge tube.

[0011] A micro ultra-low capacitance solid discharge tube, the upper surface of the solid discharge tube is provided with a boron-based region P, a phosphorus diffusion buried layer N- with partial overlap is arranged on one side of the boron-based region P, a first phosphorus diffusion region N+ is arranged in the boron-based region P, and a plurality of short-circuit holes are arranged in the first phosphorus diffusion region N+ to form a cell-type cathode; a boron region P and a second phosphorus diffusion region N+ are arranged on the lower surface of the solid discharge tube, and the aforementioned boron region P and the second phosphorus diffusion region N+ are arranged at intervals to form a unidirectional chip anode structure.

[0012] Further, the chip area of the solid discharge tube is 0.5 mm * 0.5 mm - 0.6 mm * 0.6 mm, and the junction capacitance is less than 6 pF.

[0013] Further, the chip area is 0.56 mm * 0.56 mm.

[0014] Further, the junction depths of the boron-based region P and the boron region P are both 20 - 25 μm; the junction depths of the first phosphorus diffusion region N+ and the second phosphorus diffusion region N+ are both 10 - 15 μm;.

[0015] Further, the buried layer junction depth of the phosphorus diffusion buried layer N- is 40 um - 45 um.

[0016] Further, the first phosphorus diffusion region N+ and the boron-based region P have the same shape and are concentrically arranged, and the first phosphorus diffusion region N+ is 3 / 4 - 4 / 5 of the area of the boron-based region P.

[0017] Further, the short-circuit holes are arranged in a plurality of rows at a fixed interval within the first phosphorus diffusion region N+, and a plurality of short-circuit holes are arranged at a fixed interval within each row, and the short-circuit holes in adjacent rows are arranged in a staggered manner.

[0018] Further, the phosphorus diffusion buried layer N- is arranged on the upper side, lower side, left side or right side of the boron-based region P.

[0019] Further, metal layers are provided on the outer sides of both the boron-based region P and the boron region P.

[0020] Advantages of the present invention:

[0021] While ensuring the current-carrying capacity (PN junction area) of the device, the micro ultra-low capacitance solid discharge tube of the present invention reduces the device area to 0.56 mm * 0.56 mm, and the junction capacitance is reduced to less than 6 pF, meeting the integration requirements of customers.

[0022] Based on the original low-capacitance structure design, the present invention adds an N- buried layer to the cathode, thereby increasing the current-carrying capacity on the basis of a small chip area. Based on this design, the original chip area can be greatly reduced, thereby reducing the PN junction area and the junction capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of the structure of a conventional device of the same type.

[0024] Figure 2 is a longitudinal structure schematic diagram of the micro ultra-low capacitance solid discharge tube of the present invention.

[0025] Figure 3 is the front layout of the micro ultra-low capacitance solid discharge tube of the present invention.

[0026] In the figure: 1. Boron-based region P; 2. Phosphorus diffusion buried layer N-; 3. First phosphorus diffusion region N+; 4. Short-circuit hole; 5. Boron region P; 6. Second phosphorus diffusion region N+. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The present invention will be further described below with reference to the drawings and embodiments.

[0028] A micro ultra-low capacitance solid discharge tube with a micro chip area of 0.56 mm * 0.56 mm, as Figure 2 、 3As shown in the figure, it includes a boron-based region P1 on the top and a boron region P5 on the bottom. A phosphorus diffusion region N+3 is respectively arranged within the boron-based region P1 on the top to form a cell-type cathode; the junction depths of both the boron-based region P1 and the boron region P5 are 20 - 25 μm. A boron region P5 and a second phosphorus diffusion region N+6 are arranged below, and the two regions are independently arranged, and the junction depth of the boron region is 20 - 25 μm.

[0029] In the present invention, the junction capacitance of the ultra-low capacitance is less than 6 pF.

[0030] In the present invention, metal layers are provided on the outer sides of both the upper boron-based region P1 and the lower boron region P5; the lower boron region P and the second phosphorus diffusion region N+ are independently and symmetrically distributed; the junction depth of the second phosphorus diffusion region N+ is 10 - 15 μm.

[0031] As Figure 3 shown in the figure, in the present invention, the position of the upper phosphorus diffusion buried layer N-2 can be at the symmetric position of the current position, or at the adjacent position or the symmetric position of the adjacent position.

[0032] The positions of the lower boron region P5 and the second phosphorus diffusion region N+6 can be interchanged.

[0033] The device breakdown voltage parameter range of this invention can cover the conventional voltage range, that is, the range from 6V - 400V, and the layout shapes cover different geometric shapes such as rectangles, squares, circles, and ellipses.

[0034] The following table is a parameter comparison table of one of the samples fabricated using this design. As can be seen from the following table, under the condition that the other process conditions of the conventional low-capacitance version remain unchanged, adding the "buried layer N- structure and the symmetric structure of the back boron region and phosphorus region" reduces the parasitic junction capacitance to 6 pF, and ensures that the 30A current impact of the 8 / 20μs waveform passes 100%, fully meeting the customer's requirements for miniaturization and high density in its SOT-23 package integrated with 3 chips, thus meeting its application in a high-speed data communication environment. Currently, this miniaturized ultra-low parasitic capacitance process level is relatively leading in the industry, reaching the same level abroad, filling the gap in the field of integrated packaging technology for miniaturized ultra-low capacitance solid discharge tubes at home and abroad.

[0035]

[0036] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments.

Claims

1. A preparation method of a micro ultra-low capacitance solid discharge tube, the solid discharge tube having a boron-based region P(1) on its upper surface, a partially overlapping phosphorus-diffused buried layer N-(2) being disposed on one side of the boron-based region P(1), a first phosphorus-diffused region N+(3) being arranged within the boron-based region P(1), and a plurality of short-circuit holes (4) being arranged within the first phosphorus-diffused region N+(3) to form a cell-type cathode; a boron region P(5) and a second phosphorus-diffused region N+(6) being arranged on the lower surface of the solid discharge tube, the boron region P(5) and the second phosphorus-diffused region N+(6) being spaced apart to form a unidirectional chip anode structure; The chip area of the solid discharge tube is 0.5 mm * 0.5 mm - 0.6 mm * 0.6 mm, and the junction capacitance is less than 6 pF; the buried junction depth of the phosphorus-diffused buried layer N-(2) is 40 μm - 45 μm; Its characteristics are This preparation method includes the following steps: S1. Before preparing the boron-based region P(1), a phosphorus-diffused buried layer N-(2) that partially overlaps with one side of the boron-based region P(1) is pre-arranged, and the depth of the phosphorus-diffused buried layer N-(2) is greater than the depth of the boron-based region P(1); S2. Prepare the boron-based region P(1) and the boron region P(5), and the boron region P(5) is arranged on the lower surface of the solid discharge tube; S3. Arrange a first phosphorus-diffused region N+(3) within the boron-based region P(1), and arrange a plurality of short-circuit holes (4) within the first phosphorus-diffused region N+(3) to form a cell-type cathode; S4. Arrange a second phosphorus-diffused region N+(6) on the lower surface of the solid discharge tube, and the second phosphorus-diffused region N+(6) is spaced apart from the boron region P(5) to form the solid discharge tube.

2. A micro ultra-low capacitance solid discharge tube, the solid discharge tube having a boron-based region P(1) on its upper surface, Its characteristics are A partially overlapping phosphorus-diffused buried layer N-(2) is disposed on one side of the boron-based region P(1), a first phosphorus-diffused region N+(3) is arranged within the boron-based region P(1), and a plurality of short-circuit holes (4) are arranged within the first phosphorus-diffused region N+(3) to form a cell-type cathode; a boron region P(5) and a second phosphorus-diffused region N+(6) are arranged on the lower surface of the solid discharge tube, and the boron region P(5) and the second phosphorus-diffused region N+(6) are spaced apart to form a unidirectional chip anode structure; The chip area of the solid discharge tube is 0.5 mm * 0.5 mm - 0.6 mm * 0.6 mm, and the junction capacitance is less than 6 pF; the buried junction depth of the phosphorus-diffused buried layer N-(2) is 40 μm - 45 μm.

3. The micro ultra-low capacitance solid discharge tube according to claim 2, Its characteristics are The chip area is 0.56 mm * 0.56 mm.

4. The micro ultra-low capacitance solid discharge tube according to claim 2, Its characteristics are that the junction depths of the boron-based region P(1) and the boron region P(5) are both 20 - 25 μm; the junction depths of the first phosphorus-diffused region N+(3) and the second phosphorus-diffused region N+(6) are both 10 - 15 μm.

5. The micro ultra-low capacitance solid discharge tube according to claim 2, Its characteristics are The shape of the first phosphorus diffusion region N+(3) is consistent with that of the boron-based region P(1) and they are concentrically arranged. The area of the first phosphorus diffusion region N+(3) is 3 / 4 - 4 / 5 of the area of the boron-based region P(1).

6. The micro ultra-low capacitance solid discharge tube according to claim 2, characterized in that the short-circuit holes (4) are arranged in several rows at fixed intervals within the first phosphorus diffusion region N+(3), and several are arranged at fixed intervals within each row, and the short-circuit holes (4) in adjacent rows are arranged in a staggered manner.

7. The micro ultra-low capacitance solid discharge tube according to claim 2, characterized in that the phosphorus diffusion buried layer N-(2) is arranged on the upper side, lower side, left side or right side of the boron-based region P(1).

8. The micro ultra-low capacitance solid discharge tube according to claim 2, characterized in that metal layers are provided on the outsides of both the boron-based region P(1) and the boron region P(5).

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