Semiconductor structure and semiconductor manufacturing method

Abstract

The present invention relates to a semiconductor structure and a semiconductor manufacturing method. The semiconductor structure includes: a substrate; an active region including a channel region sandwiched between two source / drain regions; an insulating region surrounding the active region from a top view; and a dielectric layer placed above the interface between the insulating region and the source / drain region and in contact with the interface. The present invention also discloses a method for manufacturing a semiconductor structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a semiconductor manufacturing method. Background Art

[0002] Shallow trench isolation (STI) is widely used in semiconductor manufacturing to provide isolation of active areas on a substrate. However, STI is susceptible to noise and leakage problems. Therefore, there is a need to alleviate the above problems. Summary of the invention

[0003] One embodiment of the present invention relates to a semiconductor structure, which includes: a substrate; an active area, which includes a channel region and two source / drain regions, and the channel region is sandwiched between the two source / drain regions; an insulating region, which surrounds the active area from a top view; and a dielectric layer, which is placed above the interface between the insulating region and the source / drain regions and covers the interface.

[0004] One embodiment of the present invention relates to a semiconductor structure, comprising: a semiconductor substrate; a gate structure, which is above the semiconductor substrate and extends along a first direction; an active area pattern, which is in the semiconductor substrate and extends along a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction; an insulating region, which surrounds the active area pattern; a first dielectric strip, which is above the semiconductor substrate, wherein the first dielectric strip at least directly covers an interface between the first edge of the active area pattern and the insulating region; and a second dielectric strip, which is above the semiconductor substrate and is separated from the first dielectric strip, wherein the second dielectric strip at least directly covers an interface between the second edge of the active area pattern and the second insulating region.

[0005] One embodiment of the present invention relates to a method for manufacturing a semiconductor structure, which includes: receiving a semiconductor substrate; forming an insulating region in the semiconductor substrate to define an active region in the semiconductor substrate; forming a gate structure across the active region defined in the semiconductor substrate; forming a source or drain region in the active region, wherein the source or drain region is adjacent to the insulating region; and forming a photoresist protective dielectric film over the source or drain region, the insulating region, and the gate structure, wherein the photoresist protective dielectric film overlaps with an interface between the source or drain region and the insulating region, and exposes a portion of the source or drain region and a portion of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 2 illustrates a cross-sectional view of a semiconductor device in process;

[0008] Figure 3A , 4A , 5A, 6A, and 7A are diagrams illustrating fragmentary layout views of semiconductor devices at various stages of fabrication according to some embodiments of the present disclosure; and

[0009] Figure 3B , 4B , 5B, 6B, and 7B are diagrams illustrating fragmentary cross-sectional views of semiconductor devices at various fabrication stages according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different components of the present disclosure. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the first component in the following description is formed above or on the second component and may include an embodiment in which the first component and the second component are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or component to another element or components, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted likewise.

[0012] Although the numerical ranges and parameters describing the wide range of the present disclosure are approximate, the numerical values ​​described in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors caused by the standard deviation found in the respective test measurements. Moreover, as used herein, the term "about" generally means within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the term "about" means within the acceptable standard error of the mean value when considered by a person of ordinary skill. Except in the operating / working examples, or unless otherwise explicitly specified, all numerical ranges, amounts, values ​​and percentages (e.g., for the amount of material, duration, temperature, operating conditions, ratios of amounts and the numerical ranges, amounts, values ​​and percentages of the analogs disclosed herein) should be understood as modified by the term "about" in all examples. Therefore, unless otherwise indicated, the numerical parameters described in the present disclosure and the accompanying claims are approximate values ​​that can be changed as needed. At least, each numerical parameter should be understood at least based on the number of reported significant figures and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints.

[0013] In today's integrated circuit industry, hundreds of thousands of semiconductor devices are built on a single chip. Each device on the chip must be electrically isolated to ensure that it operates independently without interfering with another device. The technology of isolating semiconductor devices has become an important aspect of modern metal oxide semiconductors (MOS) (particularly, MOS adopted by fully customized integrated circuit design and bipolar integrated circuit technology for separating different devices or different functional areas). With the high integration of semiconductor devices, improper electrical isolation in the device will lead to current leakage, and current leakage can consume a lot of power and damage functionality. Some examples of reduced functionality include latch-up, noise margin degradation, voltage offset and crosstalk that can temporarily or permanently damage the circuit.

[0014] Shallow trench isolation (STI) is an electrical isolation technology for semiconductor chips with high integration. STI structures can be made using a variety of methods including, for example, a buried oxide (BOX) isolation method for shallow trenches. The BOX method involves filling the trenches with chemical vapor deposition (CVD) silicon oxide (SiO2), followed by planarizing the chemical vapor deposition (CVD) silicon oxide (SiO2) by a plasma etch-back process and / or a chemical mechanical polishing (CMP) process to produce a flat surface. The shallow trenches etched for the BOX process are plasma etched anisotropically into the substrate (for example, silicon), and the depth is typically between about 0.3 microns and about 1.0 microns.

[0015] Silicide layers are typically formed on top of silicon structures (e.g., polysilicon gates, source / drain regions, and local interconnects) in semiconductor devices to reduce contact resistance when forming gate or source / drain contacts. In the process of forming the silicide layer, a dielectric layer may be used to cover some portions of the silicon structure and expose some predetermined areas. A metal layer is blanket deposited over the dielectric layer and the exposed areas. A thermal treatment is then performed to promote a chemical reaction in which the metal layer contacts the silicon structure to form a silicide layer. Since the dielectric layer shields a portion of the semiconductor device from the metal layer, no silicide layer will be formed on the portion covered by the dielectric layer during the thermal treatment. The unreacted portions of the metal layer are then stripped off, leaving the silicide layer on the desired area.

[0016] Figures 1 to 2 A cross-sectional view of a semiconductor device 10 in process is illustrated. Shallow trench isolation (STI) 101 defines a first region 102 and a second region 103 on a semiconductor substrate 104. In the first region 102, a gate oxide layer 105 separates a gate electrode 106 from the semiconductor substrate 104. A spacer liner 107 and a spacer 108 are formed on the sidewalls of the gate electrode 106. A source / drain region 109 is formed in the semiconductor substrate 104 adjacent to the spacer 108. In the second region 103, passive devices such as a resistor 110 and an insulator layer 111 are formed on the semiconductor substrate 104. A dielectric layer 112 is blanket deposited over the source / drain region 109, the spacer 108, the spacer liner 107, the gate electrode 106, the STI 101, and the resistor 110. A photoresist mask 113 is formed on the dielectric layer 112 in a manner of covering the second region 103 and exposing the first region 102 .

[0017] In the semiconductor device 10, only the gate electrode 106 and the source / drain region 109 need to form a silicide layer, so it is desirable to remove the dielectric layer 112 from the first region 102 while maintaining the dielectric layer 112 in the second region 103. Accordingly, the photoresist mask 113 is defined so as to shield the second region 103 and expose the first region 102. A wet etching step using an HF solution is performed to remove the exposed portion of the dielectric layer 112. Then, the photoresist mask 113 is stripped to leave the semiconductor structure 10, as shown in FIG. Figure 2 Displayed in.

[0018] Etching Figure 2The process of etching the dielectric layer 112 of the STI 101 has the problem of damaging the STI 101. Since the STI 101 is made of an oxide material, its etching rate will be very close to the dielectric layer 112. In a 100:1 HF solution, the etching rate of the dielectric layer 112 is about 70 angstroms per minute, and the etching rate of the STI 101 is about 50 angstroms per minute. Therefore, the use of the HF solution to etch the dielectric layer 112 may be non-selective relative to the STI 101. Pit 115 is often formed after the wet etching process. After the silicide layer is formed on the source or drain region, the silicide layer may also be formed in the pit and thus cause higher junction leakage. In addition, defects and stress at the edge of the STI 101 are important reasons that affect the flicker noise characteristics of the device.

[0019] Figure 3A , 4A , 5A, 6A, and 7A are diagrams illustrating fragmentary layout views of a semiconductor device 300 at various stages of fabrication according to some embodiments of the present disclosure. Figure 3B , 4B , 5B, 6B, and 7B are diagrams illustrating fragmentary cross-sectional views of a semiconductor device 300 at various stages of fabrication according to some embodiments of the present disclosure. Figure 3B , 4B , 5B, 6B and 7B each include respectively along Figure 3A , 4A , 5A, 6A and 7A, respectively, are two cross-sectional views of the semiconductor device 300 taken along line AA′ and line BB′. Figure 3B , 4B , 5B, 6B and 7B, the cross-sectional view 300A is obtained along the line AA'. On the other hand, the cross-sectional view 300A is obtained along the line BB' Figure 3B , 4B , 5B, 6B and 7B are cross-sectional views 300B on the right hand side.

[0020] refer to Figure 3A , the semiconductor device 300 includes a gate structure 304 and an active area pattern 302. The gate structure 304 extends continuously above the active area pattern 302. Specifically, the gate structure 304 extends above the active area pattern 302 along the axis Y. Figure 3A, the active area pattern 302 is exposed on both sides of the gate structure 304 along the axis X. Specifically, the active area pattern 302 includes two portions, which are arranged on opposite sides of the gate structure 304 and are configured to form corresponding drain or source regions of the transistor. The active area pattern 302 further includes a channel region sandwiched between the drain or source regions. Examples of transistors including at least the gate structure 304 and the active area pattern 302 include (but are not limited to) metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFET / NFET), FinFETs, planar MOS transistors with raised source / drain, etc. In at least one embodiment, the transistor is an n-channel metal oxide semiconductor (NMOS) transistor. In at least one embodiment, the transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

[0021] Exemplary materials for gate structure 304 include polysilicon. Other materials such as metals are within the scope of various embodiments. Exemplary materials for active area pattern 302 include, but are not limited to, semiconductor materials doped with various types of p-dopants and / or n-dopants. In at least one embodiment, active area pattern 302 includes the same type of dopant on both sides of gate structure 304.

[0022] about Figure 3B 300A, a gate structure 304 is formed above a top surface 307 of a semiconductor substrate 301. The semiconductor substrate 301 may be a portion of a semiconductor wafer, such as a silicon wafer. Alternatively, the semiconductor substrate 301 may include other semiconductor materials, such as germanium. The semiconductor substrate 301 may also include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide, a III-V compound semiconductor material, or the like. The semiconductor substrate 301 may be a bulk semiconductor substrate, and an epitaxial layer may or may not be formed on the bulk substrate. In addition, the semiconductor substrate 301 may be a semiconductor on insulator (SOI) substrate.

[0023] In some embodiments, the gate structure 304 may include a gate dielectric 32 and a gate electrode 34 overlying the gate dielectric 32. In some exemplary embodiments, the gate dielectric 32 may include silicon dioxide. Alternatively, the gate dielectric 32 may include a high-k material, silicon oxynitride, other suitable materials, or combinations thereof. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, hafnium oxide, or combinations thereof. The gate dielectric 32 may be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxide, and the like.

[0024] The gate electrode 34 may include polycrystalline silicon (polysilicon). Alternatively, the gate electrode 34 may include a metal or a metal silicide, such as Al, Cu, W, Ni, Mo, Co, Ti, Ta, TiN, TaN, NiSi, NiPtSi, CoSi, or a combination thereof. The formation method of the gate electrode 34 includes CVD, physical vapor deposition (PVD), ALD, and other appropriate processes. The formation of the gate dielectric 32 and the gate electrode 34 may include forming a blanket dielectric layer and a blanket gate electrode layer, and then performing patterning to form the gate dielectric 32 and the gate electrode 34.

[0025] The gate spacers 43 may be formed by depositing a dielectric layer(s) and then patterning the dielectric layer to remove horizontal portions deposited on the top surface 307, leaving vertical portions of the dielectric layer on the sidewalls of the gate structure 30 to form the gate spacers 43. The formation process of the active area pattern 302 (i.e., drain or source region) may include forming a photoresist (not shown), and then performing an implantation to form the active area pattern 302 in the semiconductor substrate 301.

[0026] With respect to the cross-sectional view 300B, an insulating region 303 is formed in the semiconductor substrate 301 to define and electrically isolate the active area pattern 302 in which the transistor is formed. In other words, the insulating region 303 surrounds the active area pattern 302 from a top view. The insulating region 303 may be a shallow trench isolation (STI) region or a local oxidation of silicon (LOCOS) region. The STI may be formed by the steps of photolithography, trench etching, and trench filling with an oxide layer. The LOCOS isolation may be formed by the steps of depositing a protective nitride layer and locally oxidizing a portion of the semiconductor substrate not covered by the protective nitride layer.

[0027] refer to Figure 4A ,exist Figure 3AA dielectric layer 306 is formed above the semiconductor device 300 to contact at least the active area pattern 302, the gate structure 304 and the isolation region 303. The dielectric layer 306 may include silicon oxide or other types of dielectric materials, including but not limited to silicon carbide, silicon nitride, silicon oxynitride (SiON), oxygen-doped silicon nitride, nitrided oxide, combinations thereof, and multilayers thereof. Figure 4B , a dielectric layer 306 is blanket deposited over the gate structure 304, the active area pattern 302, and the insulating region 303. In some embodiments, the dielectric layer 306 may be conformally deposited over the gate structure 304. In this embodiment, the deposition step may be low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma assisted chemical vapor deposition (PECVD), or atomic layer deposition (ALD). It is recommended that the temperature be less than 600 degrees Celsius, and in many instances may be between 400 degrees Celsius and 500 degrees Celsius. It is recommended that the pressure be between 0.1 Torr and 10 Torr. It is recommended that the thickness of the dielectric layer 306 be from 10 angstroms to 1000 angstroms, and in many instances may be from 200 angstroms to 600 angstroms.

[0028] refer to Figure 5A , a portion of the dielectric layer 306 is removed to expose a portion of the active area pattern 302, the gate structure 304, and the insulating region 303. The removal of the dielectric layer 306 may be performed by forming a photoresist mask on the dielectric layer 306 using conventional photolithography and then etching the dielectric layer 306 not covered by the photoresist mask, thereby exposing a predetermined area. The remaining dielectric layers 306_1 and 306_2 are left to prevent silicide formation. Specifically, the remaining dielectric layer 306_1 is left over a region around the topmost edge 302_1 of the active area pattern 302 between the active area pattern 302 and the adjacent insulating region 303. The remaining dielectric layer 306_2 is left over a region around the bottommost edge 302_2 of the active area pattern 302 between the active area pattern 302 and the adjacent insulating region 303. In some embodiments, the remaining dielectric layer 306_1 and the remaining dielectric layer 306_2 may be rectangular in shape and straddle the gate structure 304. Therefore, the dielectric layers 306_1 and 306_2 overlap a portion of the gate structure 304 .

[0029] In some embodiments, the remaining dielectric layer 306_1 overlaps a portion of the active area pattern 302 adjacent to the topmost edge 302_1 with an overlap width d1 along the axis Y. The remaining dielectric layer 306_2 overlaps a portion of the active area pattern 302 adjacent to the bottommost edge 302_2 with an overlap width d1 along the axis Y. In some embodiments, the overlap width d1 may be greater than about 0.2 μm. In some embodiments, the overlap width d1 may be in a range from about 0.2 μm to about 0.25 μm. The remaining dielectric layer 306_1 further extends upward beyond the topmost edge 302_1 of the active area pattern 302 to overlap the insulating region 303 adjacent to the topmost edge 302_1 with an overlap width d2 along the axis Y. The remaining dielectric layer 306_2 further extends downward beyond the bottommost edge 302_2 of the active area pattern 302 to overlap the insulating region 303 adjacent to the bottommost edge 302_2 with an overlap width d2 along the axis Y. In some embodiments, the overlap width d2 may be greater than about 0.2 μm. In some embodiments, the overlap width d2 may be in a range from about 0.2 μm to about 0.25 μm. The width d3 along the axis Y of the active area pattern 302 not covered by the remaining dielectric layers 306_1 and 306_2 may be greater than about 0.5 μm.

[0030] In some embodiments, the left and right ends of each of the remaining dielectric layers 306_1 and 306_2 may be aligned with the leftmost edge 302_3 and the rightmost edge 302_4 of the active area pattern 302, respectively. However, this is not a limitation of the present disclosure. In some embodiments, the left and / or right ends of each of the remaining dielectric layers 306_1 and 306_2 may extend beyond the leftmost edge 302_3 and / or the rightmost edge 302_4 of the active area pattern 302, respectively, along the axis X. In some embodiments, the left and / or right ends of each of the remaining dielectric layers 306_1 and 306_2 may not extend to the leftmost edge 302_3 and / or the rightmost edge 302_4 of the active area pattern 302, respectively, along the axis X.

[0031] refer to Figure 5B , a portion of the dielectric layer 306 is removed to form at least one opening 305 having a width d3. Thus, a portion of the active area pattern 302 is exposed through the opening 305. Figure 6B refer to Fig. 6A , forming a silicide region 308 over a portion of the active area pattern 302 and a portion of the gate structure 304. In some embodiments, the formation of the silicide region 308 may include a self-aligned silicide (SASI) process. The silicide process includes blanket depositing a metal layer (not shown) over the active area pattern 302 and a portion of the gate structure 304. Figure 5A and 5B, annealing is then performed on the semiconductor device 300 shown in FIG. 1 to cause a reaction between the metal layer and the underlying silicon. Thus, a silicide region 308 is formed. The metal layer may include nickel, cobalt, titanium, platinum, or the like. The unreacted portion of the metal layer is then removed. Due to the shielding of the remaining dielectric layers 306_1 and 306_2, the resulting silicide region 308 is formed in the opening 305 between the remaining dielectric layers 306_1 and 306_2. Thus, the silicide region 308 laterally adjoins the remaining dielectric layers 306_1 and 306_2. The silicide region 308 does not extend to the topmost edge 302_1 and the bottommost edge 302_2 between the active area pattern 302 (i.e., the drain or source region) of the transistor and the insulating region 303.

[0032] Fig. 7A and 7B The diagram illustrates the formation of an insulating dielectric layer 310 (e.g., a contact etch stop layer (CESL)) and a contact plug 314. The insulating dielectric layer 310 covers and contacts the silicide region 308 and the remaining dielectric layers 306_1 and 306_2. The insulating dielectric layer 310 may be formed of a dielectric material such as silicon oxide, silicon nitride, or a combination thereof. In addition, the material of the insulating dielectric layer 310 may be selected to be different from the material of the remaining dielectric layers 306_1 and 306_2, so that when etching the insulating dielectric layer 310 and the overlying interlayer dielectric (ILD) layer 312 for forming the contact opening, there is a high etch selectivity between the insulating dielectric layer 310 and the remaining dielectric layers 306_1 and 306_2.

[0033] After forming the insulating dielectric layer 310, an ILD layer 312 is formed. The ILD layer 312 may be formed by a suitable technique such as chemical vapor deposition (CVD). For example, high density plasma CVD may be performed to form the ILD layer 312. The ILD layer 312 may be formed on the semiconductor substrate 301 to a level above the top surface of the insulating dielectric layer 310 above the gate structure 304 such that the gate structure 304 is embedded therein. In various embodiments, the ILD layer 312 includes silicon oxide, a low-k dielectric material (a dielectric material having a dielectric constant less than about 3.9 (the dielectric constant of thermal silicon oxide)). In one embodiment, a chemical mechanical polishing (CMP) process may be further applied to the ILD layer 312 to planarize the top surface of the ILD layer 312. Processing conditions and parameters of the CMP process including slurry chemistry and polishing pressure may be tuned to partially remove and planarize the ILD layer 312.

[0034] Next, a contact opening is formed in the ILD 312 and the insulating dielectric layer 310 by a photolithography process and an etching process including one or more etching steps, so that the silicide region 308 is exposed through the contact opening. When forming the contact opening, the ILD 312 is first etched, wherein the insulating dielectric layer 310 acts as an etching stop layer. After the etching stops on the insulating dielectric layer 310, the exposed portion of the insulating dielectric layer 310 in the contact opening is etched. The etching of the insulating dielectric layer 310 stops on the silicide region 308. In the scenario where the contact opening is not aligned with the respective silicide region 308 (as illustrated), the remaining dielectric layers 306_1 and 306_2 may be exposed in the contact opening. Accordingly, when etching the insulating dielectric layer 310, the remaining dielectric layers 306_1 and 306_2 may act as an etching stop layer and may be substantially unetched, or at least a lower portion may be left after the etching of the insulating dielectric layer 310 is completed. Accordingly, the topmost edge 302_1 and the bottommost edge 302_2 between the active area pattern 302 (ie, the drain or source region) and the insulating region 303 are protected by the remaining dielectric layers 306_1 and 306_2 .

[0035] Next, a contact plug 314 is formed in the contact opening to contact the silicide region 308. In some embodiments, the contact plug 314 includes tungsten. The formation process may include filling a conductive material such as tungsten into the contact opening by using physical vapor deposition (PVD), plating, or a combination thereof, and then performing chemical mechanical polishing (CMP) to remove excess portions of the conductive material from above the ILD 312. The remaining portion of the conductive material forms the contact plug 314.

[0036] In many embodiments, an interconnect structure may be further formed on the ILD layer 312. The interconnect structure may include vertical interconnects (e.g., conventional vias or contacts) and horizontal interconnects (e.g., metal lines). The interconnect structure may implement a variety of conductive materials including copper, tungsten, and silicide. In one example, a damascene process is used to form a copper-related interconnect structure. Although the semiconductor device 300 and the formation of the semiconductor device 300 are described, other alternatives and embodiments may exist without departing from the scope of the present disclosure. In addition, it should be understood that the transistors included in the semiconductor device 300 may be of different types, including and not limited to high voltage MOSFETs, low voltage MOSFETs (e.g., logic MOSFETs), memory MOSFETs, and the like. In some embodiments, the transistor may be a p-type MOSFET. In some embodiments, the transistor may be an n-type MOSFET, wherein the conductivity type of the respective doped regions is opposite to the conductivity type of the p-type MOSFET.

[0037] Some embodiments of the present disclosure provide a semiconductor structure, which includes: a substrate; an active region including a channel region sandwiched between two source / drain regions; an insulating region surrounding the active region from a top view; and a dielectric layer disposed above and in contact with an interface between the insulating region and the source / drain regions.

[0038] Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a semiconductor substrate; a gate structure, which is above the semiconductor substrate, and the gate structure extends along a first direction; an active area pattern, which is in the semiconductor substrate, and the active area pattern extends along a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction; an insulating region, which surrounds the active area pattern; a first dielectric strip, which is above the semiconductor substrate, wherein the first dielectric strip directly covers at least an interface between the first edge of the active area pattern and the insulating region; and a second dielectric strip, which is above the semiconductor substrate, and the second dielectric strip is separated from the first dielectric strip, wherein the second dielectric strip directly covers at least an interface between the second edge of the active area pattern and the second insulating region.

[0039] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes: receiving a semiconductor substrate; forming an insulating region in the semiconductor substrate to define an active region in the semiconductor substrate; forming a gate structure across the active region defined in the semiconductor substrate; forming a source or drain region in the active region, wherein the source or drain region is adjacent to the insulating region; and forming a photoresist protective dielectric film over the source or drain region, the insulating region, and the gate structure, wherein the photoresist protective dielectric film overlaps an interface between the source or drain region and the insulating region, and exposes a portion of the source or drain region and a portion of the gate structure.

[0040] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0041] Explanation of symbols

[0042] 10 Semiconductor devices

[0043] 32 Gate dielectric

[0044] 34 Gate electrode

[0045] 43 Gate spacer

[0046] 101 Shallow Trench Isolation (STI)

[0047] 102 First Area

[0048] 103 Second Area

[0049] 104 Semiconductor Substrate

[0050] 105 Gate Oxide Layer

[0051] 106 Gate electrode

[0052] 107 Spacer Lining

[0053] 108 Spacer

[0054] 109 Source / Drain Region

[0055] 110 Resistors

[0056] 111 Insulator layer

[0057] 112 Dielectric layer

[0058] 113 Photoresist mask

[0059] 115 pit

[0060] 300 Semiconductor devices

[0061] 300A Cross-section

[0062] 300B Cross-section

[0063] 301 Semiconductor Substrate

[0064] 302 Active Area Pattern

[0065] 302_1 Top edge

[0066] 302_2 Bottom edge

[0067] 302_3 Leftmost edge

[0068] 302_4 Rightmost edge

[0069] 303 Insulation Area

[0070] 304 Gate structure

[0071] 305 Opening

[0072] 306 Dielectric layer

[0073] 306_1 Remaining dielectric layer

[0074] 306_2 Remaining dielectric layer

[0075] 307 Top surface

[0076] 308 Silicide Area

[0077] 310 Insulating dielectric layer

[0078] 312 Interlayer Dielectric (ILD) Layer

[0079] 314 Contact Plug

[0080] d1 overlap width

[0081] d2 overlap width

[0082] d3 width

Claims

1. A semiconductor structure comprising: substrate; an active region comprising a channel region and two source / drain regions, wherein the channel region is sandwiched between the two source / drain regions, wherein the two source / drain regions include a source region and a drain region; an insulating region surrounding the active region from a plan view; and a dielectric layer arranged to span the channel region from the source region to the drain region, wherein the dielectric layer is disposed above and covers a first interface between the insulating region and the source / drain region; in A second interface between the insulating region and the source region is perpendicular to the first interface, and a portion of the second interface is not covered by the dielectric layer; and A third interface between the insulating region and the drain region is perpendicular to the first interface, and a portion of the third interface is not covered by the dielectric layer, wherein from a top view, a band region in the active region is not covered by the dielectric layer, and the band region continuously extends from the second interface to the third interface along a direction. 2 . The semiconductor structure of claim 1 , further comprising at least one metal silicide member above and in contact with the active region, wherein the metal silicide member extends to the second interface and the third interface. 3 . The semiconductor structure according to claim 2 , wherein the metal silicide member does not extend to the first interface between the insulating region and the source / drain region. 4 . The semiconductor structure of claim 1 , wherein the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

5. The semiconductor structure of claim 3, wherein the metal silicide member laterally abuts the dielectric layer.

6. The semiconductor structure of claim 2, further comprising a contact etch stop layer over the dielectric layer and the metal silicide member. 7 . The semiconductor structure of claim 6 , further comprising a contact passing through the contact etch stop layer and contacting the metal silicide member. 8 . The semiconductor structure of claim 1 , wherein the dielectric layer overlaps the source / drain regions with an overlap width greater than 0.2 μm.

9. The semiconductor structure of claim 1, wherein a thickness of the dielectric layer is in a range from 200 angstroms to 600 angstroms.

10. A semiconductor structure comprising: Semiconductor substrate; A gate structure, which is above the semiconductor substrate, and the gate structure extends along a first direction; an active area pattern, wherein in the semiconductor substrate, the active area pattern extends along a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction, and the active area pattern further includes a third edge and a fourth edge along the first direction; an insulating region surrounding the active area pattern; A first dielectric strip is formed over the semiconductor substrate and wrapped around the gate structure, wherein the a first dielectric tape directly covering at least an interface between the first edge of the active area pattern and the insulating region; and a second dielectric tape over the semiconductor substrate and wrapped around the gate structure, the second dielectric tape being spaced apart from the first dielectric tape, wherein the second dielectric tape at least directly covers an interface between the second edge of the active area pattern and a second insulating region; A portion of the third edge and a portion of the fourth edge are not covered by the first dielectric strip and the second dielectric strip, and from a top view, a strip region in the active area pattern is not covered by the first dielectric strip and the second dielectric strip, and the strip region extends continuously from the third edge to the fourth edge along the second direction. 11 . The semiconductor structure according to claim 10 , further comprising a silicide layer above and in contact with the active area pattern, wherein the silicide layer extends to the third edge and the fourth edge. 12 . The semiconductor structure of claim 10 , wherein the first dielectric strip and the second dielectric strip each further overlap a portion of the gate structure.

13. The semiconductor structure of claim 10, wherein the first dielectric strip and the second dielectric strip comprise silicon oxide, silicon nitride, or silicon oxynitride.

14. The semiconductor structure of claim 11 wherein the silicide layer is between the first dielectric strip and the second dielectric strip.

15. The semiconductor structure of claim 10, wherein each of the first dielectric strip and the second dielectric strip overlaps the active area pattern with an overlap width greater than 0.2 μm.

16. The semiconductor structure of claim 10, wherein a thickness of each of the first dielectric strip and the second dielectric strip is in a range from 10 angstroms to 1000 angstroms.

17. The semiconductor structure of claim 11 further comprising a contact etch stop layer over the first dielectric strip, the second dielectric strip, and the silicide layer.

18. The semiconductor structure of claim 17, further comprising a contact passing through the contact etch stop layer and contacting the silicide layer.

19. A semiconductor structure comprising: Semiconductor substrate; A gate structure, which is above the semiconductor substrate, and the gate structure extends along a first direction; an active area pattern, wherein in the semiconductor substrate, the active area pattern extends along a second direction perpendicular to the first direction; an insulating region extending perpendicular to the second direction and adjacent to an edge of the active area pattern; a photoresist protection dielectric film wrapped around the gate structure and in contact with a portion of the active area pattern and a portion of the insulating region to cover an interface between the insulating region and an edge of the active area pattern, wherein from a top view, a strip region in the active area pattern is not covered by the photoresist protection dielectric film, and the strip region continuously extends from one end of the active area pattern to the other end of the active area pattern along the second direction; and An insulating dielectric layer covers the photoresist protection dielectric film, wherein a high etching selectivity exists between the insulating dielectric layer and the photoresist protection dielectric film. 20 . The semiconductor structure of claim 19 , further comprising a silicide layer over and in contact with the active area pattern, wherein the insulating dielectric layer covers a portion of the silicide layer.

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