Semiconductor Devices

Abstract

The present disclosure relates to a semiconductor device comprising "n" pairs of pn junction structures, wherein n is an integer ≥ 2, wherein the i-th pair comprises two pn junction structures of the i-th type, wherein i = {1, ..., n}, wherein the two pn junction structures of the i-th type are connected in anti-series, wherein the i-th type of pn junction structure is arranged to have an i-th junction gradation coefficient m i . At least a first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, where #imgabs0# and m1<0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction gradient coefficient m2, where #imgabs1# The junction gradient coefficients m1, m2 of the first pair and the second pair of the n pairs of pn junction structures are adjusted to cause the generation of a spurious third harmonic signal of the semiconductor device having a signal power level, which is at least 10db lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case, in which the first junction gradient coefficient and the second junction gradient coefficient m1, m2 are 0.25.

Description

Technical Field

[0001] An embodiment relates to a semiconductor device having at least two pairs of anti-series connected pn junction structures (also referred to herein as diode structures) having an adjusted junction ramping coefficient (also referred to as a diode power-law index) for providing at least reduced or minimized generation of stray odd harmonics (e.g., third harmonics).

[0002] Further embodiments relate to a semiconductor device having at least two anti-series connected pn junction structures with adjusted junction taper coefficients, wherein one of the two pn junction structures comprises a "composite" diode structure to adjust and obtain the desired TVS behavior (TVS = transient voltage suppressor) of the semiconductor device with respect to breakdown voltage and to provide at least reduced or minimized generation of stray odd harmonics (e.g. third harmonic). Background Art

[0003] Discrete ESD protection devices (ESD = Electrostatic Discharge) and TVS devices (TVS = Transient Voltage Suppressor) generally have non-linear electrical characteristics that lead to harmonic distortion of RF signals (RF = Radio Frequency) present on signal lines, for example on PCB traces (PCB = Printed Circuit Board) connected to the ESD protection device or TVS device. This harmonic generation creates stray and unwanted harmonic signals that may interfere with other functions or functional blocks of the electronic system if these use frequency bands that are integer multiples of the distorted RF signal.

[0004] For example, third harmonic (H3) frequencies of certain frequency bands in the range between 800 MHz and 900 MHz used in mobile telecommunication standards interfere with RF signals in the 2.4 GHz-WIFI band, ie, in the frequency range between 2.412 and 2.472 GHz.

[0005] In order to avoid such unwanted interference between the frequency bands exemplarily described above, an electronic device such as a TVS device should minimize its harmonic generation to a sufficiently low level.

[0006] In known embodiments, the generation of even harmonics is minimized, for example, by utilizing a strictly symmetrical design and highly symmetrical behavior of the electronics for the positive and negative half-waves of the RF signal. By ensuring symmetry, even harmonics can be effectively suppressed, however, the generation of odd harmonics is not affected by this approach or is sufficiently suppressed by this approach.

[0007] With respect to minimal generation of odd harmonics, such as the third harmonic (h3), in the prior art, it has long been assumed that low capacitance and flat capacitance versus voltage (CV) behavior of electronic devices results in low harmonic generation including the third harmonic.

[0008] However, the applicant's current research has shown that the above-mentioned method for suppressing the generation of odd harmonics is insufficient in view of the comparison of harmonic generation of electronic devices having different capacitance values ​​and CV characteristics.

[0009] Generally speaking, there is a need in the art for a method for implementing a semiconductor device, such as a discrete ESD protection device or a TVS device, having reduced or minimized generation of odd harmonics, such as the third harmonic.

[0010] Generally speaking, there is a need in the art for a method for implementing a semiconductor device, such as a discrete ESD protection device or a TVS device, that also has a reduced or tuned breakdown voltage. Summary of the invention

[0011] According to one embodiment, the semiconductor device includes "n" pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1,…,n}, where the two pn junction structures of the i-th type are anti-series connected, and where the i-th type of pn junction structure is arranged to have an i-th junction grading coefficient m i .

[0012] At least a first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, wherein and m1<0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m2, wherein And wherein the junction taper coefficients m1 and m2 of the first pair and the second pair of the n pairs of pn junction structures are adjusted to result in the generation of a spurious third harmonic signal of the semiconductor device having a signal power level (PH3), which signal power level (PH3) is at least 10 dB lower than the (e.g., simulated) reference signal power level (PH3) of the spurious third harmonic signal obtained for a (e.g., simulated) reference case, in which the first junction taper coefficient and the second junction taper coefficient m1 and m2 are 0.25.

[0013] In the commonly used model of pn junction structure, the ramp coefficient m of the i-th junction is i is based on the voltage-dependent capacitance characteristic C of the depletion region of the i-th type pn junction structure for a reverse bias voltage Vi applicable to the i-th type pn junction structure. i (V i ), where:

[0014]

[0015] Among them C J0i represents the i-th zero-bias junction capacitance, and V Ji represents the voltage potential of the i-th junction.

[0016] For example, for this reference case, spurious odd harmonic generation may be determined by simulation using a standard circuit simulation tool such as Keysight's Advanced Design System (ADS), for example, by harmonic balance analysis as is generally known in the art.

[0017] According to another embodiment, a semiconductor device includes "n" pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1, ..., n, where the two pn junction structures of the i-th type are anti-series connected, where the i-th type of pn junction structure is arranged to have an i-th junction grading coefficient m i .

[0018] Among them, the first to nth junction ramp coefficients m1 to m n The following ellipse equation is met within a tolerance of ±0.05:

[0019] in

[0020] At least the first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, wherein and m1<0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction gradient coefficient m2, wherein And the parameter a i It is the zero bias capacitance C based on the i-th type pn junction structure. J0i and junction voltage potential V Ji To be determined.

[0021] The tolerance range of ±0.05 indicates the range of the ramp coefficient for each node. In the present context, the ellipse intersects or at least touches the n-dimensional space (coordinate system) of the ramp coefficients around a specific point (m1 to m2). n ) in the case of a volume limited by the tolerance range, the ramp coefficient m1 to m n is considered to conform to the ellipse equation within the tolerance range. For illustrative purposes, in the two-dimensional case of two pairs of pn junction structures with ramp coefficients m1 and m2, the volume defined by the tolerance range is a circle with a diameter of 0.10 and a specific point (m1, m2) in the middle. Thus, effectively, a range of width 0.10 around the ellipse is defined, in which the ramp coefficients m1 to m2 can be setn possible combinations.

[0022] The i-th junction ramp coefficient m of the i-th type pn junction structure is i , zero bias capacitor C J0i and junction potential V Ji It can also be described by the above mentioned formula (A1).

[0023] Therefore, an embodiment relates to a semiconductor device having at least two pairs of anti-series connected pn junction structures, wherein for each of the at least two pairs, the at least two pairs of anti-series connected pn junction structures have an adjusted junction gradient coefficient to provide at least reduced or minimized generation of stray odd harmonics, such as third harmonics.

[0024] According to another embodiment, a semiconductor device includes a composite pn junction structure in a semiconductor substrate, wherein the composite pn junction structure is arranged to have a predetermined first junction grading coefficient m1, wherein m1>0.50, wherein the composite pn junction structure includes a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure is arranged to have a predetermined first partial junction grading coefficient m1. 11 , and wherein the second portion pn junction structure is arranged to have a predetermined second portion junction grading coefficient m 12 , where the predetermined first part of the ramp coefficient m 11 The second part of the predetermined ramp coefficient m 12 Different, among which m 11 ≠m 12 , and wherein the predetermined first part junction ramp coefficient and the second part junction ramp coefficient m 11 、m 12 At least one of the junction ramp coefficients is greater than 0.5, where m 11 and / or m 12 >0.5, and wherein the predetermined first junction grading coefficient m1 of the composite pn junction structure is based on the first part junction grading coefficient and the second part junction grading coefficient m 11 、m 12 The predetermined combination.

[0025] Therefore, embodiments relate to a semiconductor device having at least two pairs of anti-series connected pn junction structures having adjusted junction taper coefficients, wherein at least one pair of the at least two pairs of pn junction structures is a pair of anti-series connected composite pn junction structures (also denoted herein as "composite diode structures"), to adjust and obtain the desired TVS behavior (TVS = transient voltage suppressor) of the semiconductor device with respect to breakdown voltage, and to provide at least reduced or minimized generation of stray odd harmonics, such as third harmonics. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Embodiments of the present concept are described herein with reference to the accompanying drawings, in which:

[0027] Figure 1a to Figure 1d 1 shows an exemplary schematic circuit diagram of a semiconductor device having n pairs of anti-series connected pn junction structures according to an embodiment,

[0028] Figure 2 shows an exemplary circuit block diagram for testing a semiconductor device,

[0029] Figure 3a , Figure 3b shows a schematic power distribution of an RF signal according to an embodiment,

[0030] Figure 4a FIG. 1 shows a graphical representation (a graph of a function) of a cancellation line of a third harmonic signal of a semiconductor device according to an embodiment as a function of first junction tapering coefficient and second junction tapering coefficient m1, m2,

[0031] Figure 4b Shows Figure 4a A magnified view of

[0032] Figure 4c Another graphical representation of a functional diagram showing how the third harmonic generation PH3 of a semiconductor device can be optimally suppressed,

[0033] Figure 4d Shows Figure 4c A magnified view (view) of a graphical representation of

[0034] Figure 4e A graphical representation of the parameters a1, a2 (=radii r1, r2) of an ellipse which can optimally suppress the generation of the third harmonic PH3 of the semiconductor device 100 is shown,

[0035] Figure 4f shows that given the first junction voltage potential and the second junction voltage potential V J1 、V J2 , a graphical representation of the cancellation line of the third harmonic PH3 of the semiconductor device as a function of the first junction ramp coefficient m1 and the second junction ramp coefficient m2,

[0036] Figure 4g to Figure 4j The first bias junction capacitance and the second bias junction capacitance C with equal power levels of the fundamental frequency signal are shown in FIG. J01 =C J02 The spurious third harmonic PH3 of the simulated semiconductor device,

[0037] Figure 5aa and Figure 5ab Shows Figure 1aA schematic cross-sectional view of a semiconductor device,

[0038] Figure 5b Shows Figure 5aa and Figure 5ab A schematic simulation diagram of an exemplary doping distribution of a pn junction structure of a semiconductor device,

[0039] Figure 6a shows a schematic cross-sectional view of a semiconductor device according to an embodiment,

[0040] Figure 6b Shows Figure 6a A schematic top view of a semiconductor device,

[0041] Figure 7a , Figure 7b 1 shows an exemplary schematic circuit diagram of a semiconductor device having n pairs of anti-series connected pn junction structures according to an embodiment,

[0042] Figure 8a As shown in the Figure 5b Schematic simulation diagram of the junction gradient coefficient m1 caused by the doping concentration of different implantation doses of the doping profile,

[0043] Figure 8b As shown in the Figure 5b Schematic simulation diagram of the breakdown voltage resulting from different implantation doses of the doping profile as a function of the doping concentration,

[0044] Figure 8c The area ratio between the area of ​​the first partial pn junction structure and the area of ​​the second partial pn junction structure is shown. Figure 5b The two adjusted partial junction grading coefficients m for the two doping profiles shown 11 、m 12 The combined junction gradation coefficient of the composite first type pn junction structure is caused by

[0045] Figure 9a shows a schematic cross-sectional view of another exemplary implementation of a semiconductor device,

[0046] Figure 9b Shows Figure 9a Schematic simulation diagram of different exemplary doping distributions of the composite pn junction structure of the semiconductor device,

[0047] Fig.9c shows a plane passing through the composite first type pn junction structure Figure 9a A schematic top view of a semiconductor device, the Fig.9c The "active" region of the first partial anode region and the second partial anode region of the first type pn junction structure is shown, and

[0048] Figures 9d to 9f Schematic cross-sectional views of further exemplary implementations of semiconductor devices are shown.

[0049] Before discussing the embodiments of the present invention in more detail using the drawings, it is pointed out that in the drawings and the description, identical elements and elements having the same functions and / or the same technical or physical effects are generally provided with the same reference numerals or identified with the same names, so that the descriptions of these elements and their functions as illustrated in different embodiments are interchangeable with each other or can be applied to each other in different embodiments. DETAILED DESCRIPTION

[0050] In the following description, embodiments of the present invention are discussed in detail, but it should be appreciated that the present invention provides many applicable concepts that can be specifically implemented in various semiconductor devices. The specific embodiments discussed only illustrate the specific way of making and using the present invention, and do not limit the scope of the present invention. In the following description of the embodiments, the same or similar elements with the same function have the same reference symbols or the same names associated therewith, and the description of such elements will not be repeated for each embodiment. Moreover, the features of the different embodiments described below can be combined with each other, unless otherwise specifically mentioned.

[0051] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly" connected to another element, it is "connected" or "coupled" without the presence of intervening elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0052] As used herein, the abbreviations “CV” or “C(V)” represent capacitance versus voltage, respectively. The terms C(V) characteristic, C(V) property, and C(V) behavior may be used synonymously in this document.

[0053] Figure 1a to Figure 1d Different schematic circuit diagrams of a semiconductor device 100 are shown, having “n” pairs 102, 104 (…) of anti-series connected pn junction structures J1, J2, J3, J4 (…), which may be adapted based on the present concept as described below to include reduced, e.g. strongly reduced, or even minimized generation of stray odd harmonics, e.g., third harmonics.

[0054] More specifically, the semiconductor device 100 includes "n" pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...), where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1,...,n}, where the two pn junction structures of the i-th type are connected in anti-series. The i-th type of pn junction structure is arranged to have an i-th junction gradation coefficient m i (m1, m2, ...), the i-th zero bias junction capacitance C J0i , and the i-th junction voltage potential V Ji , and based on the reverse bias voltage V for the i-th type pn junction structure i And has the following capacitance behavior C i (V i ),in

[0055]

[0056] The C(V) characteristic described by the above equation is also valid for a smaller forward bias voltage. In other words, the expression is also valid for the applied voltage range where the reverse bias voltage is negative, i.e., the applied voltage is a forward bias voltage. In this specification, the expression "having a ramp coefficient m" is used to represent the voltage applied to the reverse bias voltage. i The term "pn junction (or diode structure)" is used to represent a structure that can be formed by a gradual change coefficient or power law index m i The above equation is used to describe the C(V) characteristics of the pn junction or diode structure.

[0057] According to an embodiment, at least a first pair 102 of the n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a first junction grading coefficient m1, wherein And the second pair 104 of the n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a second junction grading coefficient m2, wherein and wherein the pn junction structures J1, J2 of the first pair 102 are arranged to have a first junction grading coefficient m1, wherein m1<0.50, and wherein the junction grading coefficients m1, m2 of the first and second pairs 102, 104 (...) of the n pairs of pn junction structures J1, J2 and J3, J4 (...) are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device 100 having a signal power level PH3 which is at least 10 dB lower, preferably at least 15 dB lower, and more preferably at least 20 dB lower than a (e.g. simulated) reference signal power level PH3 of the spurious third harmonic signal obtained for a (e.g. simulated) reference case in which the first and second junction grading coefficients m1, m2 are 0.25, respectively. Keeping m1≤0.48 may be preferred in terms of facilitating the manufacture of the pn junction structure.

[0058] The second pair 104 of pn junction structures J3 , J4 may be arranged to have a second junction grading coefficient m2 , wherein m2 > 0.50, preferably m2 ≥ 0.52.

[0059] In the reference case, by setting the reference values ​​of the junction ramp coefficients m1, m2, (...) (i.e., all the junction ramp coefficients m1, m2, (...) which have been previously adjusted and deviated from 0.00 and 0.50) to m i =0.25 is used to simulate and calculate the reference signal power level PH3 ′ of the spurious third harmonic signal of the semiconductor device 100 .

[0060] According to the embodiments defined above, the junction gradation coefficients m1, m2 (...) of the n pairs 102, 104 (...) pn junction structures J1, J2 and J3, J4 are adjusted to provide at least a reduced signal power level PH3 of the spurious third harmonic signal when compared to a, e.g. simulated, reference signal power level PH3' of a spurious third harmonic signal of the semiconductor device 100 obtained in a reference case in which the junction gradation coefficients m1, m2 (...) are set to a reference value of 0.25. For example, with respect to Figure 2 The following evaluation will show that a simulation of the reference signal power level PH3' of the semiconductor device 100 with junction taper coefficients m1, m2 (...) set to a reference value of 0.25 using a circuit simulation tool described in more detail below is correlated with the (theoretical) local maximum of the reference signal power level PH3' of the spurious third harmonic signal of the semiconductor device 100.

[0061] According to another embodiment, the semiconductor device 100 includes "n" pairs 102, 104 (...) pn junction structures J1, J2 and J3, J4 (...), where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1,...,n}, where the two pn junction structures of the i-th type are connected in anti-series. The i-th type pn junction structure is arranged to have an i-th junction gradation coefficient m i , the i-th zero bias junction capacitance C J0i , and the i-th junction voltage potential V Ji , and based on the reverse bias voltage V for the i-th type pn junction structure i And has the following capacitance behavior C i (V i ),in

[0062] as well as

[0063] Among them, the first to nth junction ramp coefficients m1 to m nThe following ellipse equation is met within a tolerance of ±0.05:

[0064] in

[0065] At least a first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, wherein Where m1<0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction gradient coefficient m2, where And the first to nth parameters "a1 to a n "Depending on the zero bias capacitance C of the pn junction structure J0i and junction voltage potential V Ji Keeping m1≤0.45 may be preferable in terms of facilitating the manufacture of a pn junction structure.

[0066] The second pair 104 of pn junction structures J3 , J4 may be arranged to have a second junction grading coefficient m2 , wherein m2 ≥ 0.50, preferably m2 ≥ 0.52.

[0067] As indicated above, the first to nth junction grading coefficients m1 to m n The (n-dimensional) ellipse equation indicated is satisfied within a tolerance range of ±0.05. For example, a tolerance range of ±0.05 (or ±0.03) may take into account unavoidable semiconductor manufacturing tolerances of the semiconductor device 100. For example, a tolerance range of ±0.05 (or ±0.03) may also take into account (possible) differences between the trajectory of theoretical optimal suppression of spurious third harmonics and the trajectory of actual (e.g., input power-dependent) optimal suppression at different input power levels of the semiconductor device 100. This will be referred to below. Figure 4g to Figure 4j Describe in more detail.

[0068] In the following, reference is made to Figure 1a to Figure 1d Schematic circuit diagrams depicting some possible implementations of a semiconductor device 100 according to the present concepts.

[0069] like Figure 1a As shown by way of example, the semiconductor device 100 may include n=2 pairs 102, 104 of anti-series connected pn junction structures J1, J2, J3, J4, wherein the first pair of pn junction structures 102 includes a first gradual coefficient m1, a first junction voltage potential V J1 and the first zero bias capacitor C J01 The first type of pn junction structure J1, J2, wherein the second pair of pn junction structures 104 includes a second gradual coefficient m2, a second junction voltage potential V J2 and the second zero bias capacitor C J02 The second type of pn junction structure J3, J4. Figure 1a As shown, the first pair 102 of pn junction structures J1 , J2 and the second pair 104 of pn junction structures J3 , J4 are respectively connected in anti-series, wherein (at least) two pairs 102 , 104 of pn junction structures J1 to J4 are connected between a first terminal 107 and a second terminal 108 .

[0070] Figure 1b Another exemplary schematic circuit diagram of a semiconductor device 100 having two (n=2) pairs 102, 104 of junction structures J1, J2, J3, J4, wherein the first pair 102 includes a junction structure having a first ramp coefficient m1, a first junction voltage potential V J1 and the first zero bias capacitor C J01 The first type of pn junction structure J1, J2, and the second pair 104 includes a second gradual coefficient m2, a second junction voltage potential V J2 and the second zero bias capacitor C J02 The second type of pn junction structure J3, J4. Figure 1b As shown, the pn junction structures J1 and J2 of the first pair 102 are connected in anti-series and the pn junction structures J3 and J4 of the second pair 104 are connected in anti-series, wherein (at least) two pairs 102 and 104 of the pn junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108. Figure 1a When compared with the semiconductor device 100, as Figure 1b The illustrated arrangements of the pn junction structures J1 , J2 and J3 , J4 of the two pairs 102 , 104 differ only by the inverted orientation of the respective pn junction structures J1 to J4 .

[0071] Figure 1c Another schematic circuit diagram of a semiconductor device 100 having N=2 pairs 102, 104 on pn junction structures J1, J2, J3, J4 is shown, wherein Figure 1c The first pair 102 includes a first ramp coefficient m1, a first junction voltage potential V J1 and the first zero bias capacitor C J01 The first type of pn junction structure J1, J2, wherein the second pair 104 includes a second gradual coefficient m2, a second junction voltage potential V J2 and the second zero bias capacitor C J02 The second type of pn junction structure J3, J4. Figure 1c As shown, the first pair 102 of pn junction structures J1, J2 and the second pair 104 of pn junction structures J3, J4 are respectively connected in anti-series, wherein (at least) two pairs 102, 104 of pn junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108. Figure 1a When compared with the semiconductor device 100, as Figure 1cThe illustrated arrangements of the pn junction structures J1 to J4 of the two pairs 102 , 104 differ only by the order in which the respective pn junction structures J1 to J4 are arranged.

[0072] Figure 1d Another schematic circuit diagram of a semiconductor device 100 is shown having n=3 pairs 102, 104, 106 of anti-series connected pn junction structures J1, J2 and J3, J4 and J5, J6. Figure 1d As shown, for example, the first pair 102 includes a first ramp coefficient m1, a first junction voltage potential V J1 and the first zero bias capacitor C J01 The second pair 104 includes two pn junction structures J1 and J2 of the first type, and a second junction voltage potential V J2 and the second zero bias capacitor C J02 The second type of pn junction structure J3, J4, and the third pair 106 includes a third gradual coefficient m3, a third junction voltage potential V J3 and the third zero bias capacitor C J03 The third type of pn junction structure J5, J6. Figure 1d As shown, the pn junction structures J1, J2 of the first pair 102, the pn junction structures J3, J4 of the second pair 104 and the pn junction structures J5, J6 of the third pair 104 are respectively connected in anti-series, wherein the pn junction structures J1 to J6 of the three pairs 102, 104, 106 are connected between the first terminal 107 and the second terminal 108.

[0073] The above-described schematic circuit diagram of the semiconductor device 100 shows that the semiconductor device 100 may include multiple pairs 102, 104, 106 of pn junction structures J1 to J6, wherein the two associated pn junction structures of the corresponding pairs are respectively arranged in anti-series or connected between the first terminal 107 and the second terminal 108, wherein the order of the corresponding pn junction structures does not affect the final reduction of the third harmonic generation of the semiconductor device, so that n pairs of different pn junction structures can be arbitrarily arranged in an anti-series manner between the first terminal 107 and the second terminal 108.

[0074] For example, for a reference case, the spurious odd harmonic generation can be determined by simulation using a standard circuit simulation tool, such as Keysight Technologies' Advanced Design System (ADS), where, for example, harmonic balance analysis generally known in the art can be employed. The simulation results can be compared with measurements of the spurious harmonic generation of the semiconductor device under test, and thus with the harmonic generation of the reference case, to determine the power level of the measured spurious third harmonic of the device under test relative to the power level of the spurious third harmonic determined by simulation for the reference case. Model parameters for the simulation of the reference case, except for ramp coefficients (such as zero bias junction capacitance and junction potential), can be obtained from measurements of the device to be compared by methods generally known in the art.

[0075] Figure 2 The block circuit diagram shows a possible circuit setup for the measurement or simulation of harmonic generation of a semiconductor device under test. Figure 2 A transmission line comprising two sections TL1 201 and TL2 202 is depicted, wherein semiconductor devices under test 200 (shown by way of example as four diode structures J1 to J4) are connected to ground in a shunt configuration. An RF signal is delivered by an RF source PORT1 211 at a fundamental frequency f0 and is coupled into TL1 201 at the depicted left end of the transmission line TL1 201 by a circulator CIR1 203.

[0076] An RF signal is conducted to the semiconductor device under test 200 (J1 to J4), wherein harmonic signals at integer multiples of the fundamental frequency (overtones) are generated due to nonlinearity in the electrical properties of the semiconductor device under test 200. The generated harmonic signal is transmitted from the semiconductor device under test 200 to the terminal Term2 212 via TL2 202, and to the terminal Term3 213 via TL1 201, circulator CIR1 203, and transmission line TL3 204. By using a spectrum analyzer (not shown), the RF power distribution of the harmonic signal can be determined at the location of the terminal Term2 212 or at the location of the terminal Term3 213. By sweeping the power of the delivered RF signal at the fundamental frequency, the input power dependence of the harmonic generation can be determined.

[0077] The sensitivity of the determination of the generated harmonic signals may be further increased by adding, for example, additional filters or duplexers (not shown) to filter out the signal at the fundamental frequency f0.

[0078] exist Figure 3a and 3b Schematically showing typical spectra of the generated RF signal and harmonic signal. Figure 3aShown is the spectrum of the RF signal delivered by the RF source PORT1 211. The signal is delivered to consist only of the fundamental frequency f0 (first harmonic, x=1). Figure 3b The spectrum of a signal arriving at, for example, terminal Term2 212 is depicted. The signal power at the fundamental frequency is proportional to Figure 3a 214. The incident signal shown in FIG. 214 is reduced compared to: (1) due to the impedance mismatch caused by the semiconductor device under test 200 in the shunt configuration, and (2) due to the partial conversion of the electrical signal at the fundamental frequency into overtones, shown here for simplicity as second to fourth harmonics. The spectrum further shows that, for example, the signal in terminal Term2 212 also includes power contributions at integer multiples of the fundamental frequency, such as the second harmonic power Ph2 at 2 times f0 (2×f0, x=2), the third harmonic power PH3 at 3 times f0 (3×f0, x=3), etc. In general, the power contribution of the overtones decreases with the order of the harmonics.

[0079] The following assessment is based on Figure 1a to Figure 1d The described implementation and embodiment of the semiconductor device 100 with appropriately adjusted junction gradation coefficients mi (m1, m2, ...) provide a comprehensive explanation of the present concept. In particular, the following aspects proposed by the applicant regarding Figure 4a -to Figure 4j The discussion involves technical and mathematical analysis of the semiconductor device field, for example, the field of discrete ESD protection devices and TVS devices, and involves the resulting technical findings and conclusions for appropriately adjusting the junction gradation coefficient m of the n-pn junction structure of the semiconductor device 100. i .

[0080] Under the assumption that the “capacitance relative to voltage C(V) characteristic” of the pn junction structure (or simply referred to as pn junction) is the main contributor to the generation of odd harmonics of the semiconductor device 100, the generation of third harmonics can be substantially completely eliminated or at least strongly reduced by appropriately adjusting the C(V) characteristics of the individual pn junction structures, which can include at least two pairs 102, 104 (…) of anti-series connected pn junction structures J1, J2, J3, J4 (…).

[0081] More specifically, in the case of a connection or stack of, for example, four anti-series connected pn junction structures J1 to J4 (i.e., two pairs of pn junction structures), the third harmonic generation can be eliminated or at least minimized by selecting a suitable combination of C(V) behaviors of different pn junction structures J1 to J4 in the four pn junction stack, for example, by selecting a suitable combination of C(V) behaviors of different pn junction structures J1 to J4 according to the junction ramp coefficient m shown below. iThe equations and formulas for the parameters a1, a2 appropriately select the (first and second) pn junction grading coefficients m1, m2, which depend on the zero bias capacitance C of the two pairs 102, 104 of the pn junction structures. J01 , C J02 and junction voltage V J1 、V J2 .

[0082] The C(V) behavior of a pn junction, which is labeled “i” in this description to indicate the “ith” type, can generally be described by the following expression:

[0083]

[0084] In many cases, this expression provides an accurate description of the C(V) characteristics of a pn junction structure. The parameters have the following meanings: C j0 is the capacitance under 0V bias, V ji is the built-in voltage, and m i is the "junction grading coefficient". V represents the reverse bias across the i-th pn junction. As can be understood from expression (A1), the junction grading coefficient m i m is a key parameter for controlling the C(V) behavior of the pn junction structure, and thus the C(V) behavior of the semiconductor device 100 can be controlled. m can be adjusted by the doping profile of the corresponding pn junction structures J1 to J4 (...) i .

[0085] Some examples of ramping coefficients m are:

[0086] - m = 0.5 means that the behavior is (1.) an abrupt pn junction with uniform dopant (= doping concentration) in the n-region and the p-region, or (2.) a one-sided junction with a very abrupt pn junction between a highly doped region and a uniformly doped lower doped region. It may be difficult or expensive to realize such an idealized junction with conventional semiconductor technology.

[0087] - m = 0.33 indicates the behavior of a linear graded junction. In this case, the doping concentration around the junction varies linearly with depth. This pn junction type is very common in conventional semiconductor technology due to the diffusion of p-doped and n-doped regions.

[0088] - In case m>0.5, the term hyperabrupt junction is used. The hyperabrupt junction can be considered as a one-sided junction, where the lower doped region does not have a constant doping profile but a doping concentration that decreases with the distance from the metallurgical junction.

[0089] In the following, a general discussion is given of the mathematical derivation of the optimal C(V) parameter for suppressing the third harmonic generation of the semiconductor device 100. The following derivation may describe the C(V) characteristic sufficiently well for a low input power Pin of an input RF signal, for example, not exceeding 20 dBm, but may be less accurate for higher input powers.

[0090] In the following equations (1) to (38) and related Figure 4a To 4J, radius r i corresponds to the parameter a described so far of the described ellipse equation i , that is, r i =a i Typically within this document, a radius r as described and / or depicted herein i Corresponding to the parameter a as described and / or depicted herein i , that is, r i =a i .

[0091] The capacitance versus voltage behavior of 2 different pn junctions is represented by the following equations. These equations can be successfully used to describe the depletion capacitance behavior of pn junctions under reverse and small forward bias conditions over a wide range of doping profiles.

[0092]

[0093]

[0094] Where V is the applied reverse bias voltage, C J0i is the zero bias junction capacitance, V Ji is the junction voltage or junction potential (equal to or close to the built-in voltage, sometimes called the “effective built-in voltage”), and m i is the ramp coefficient (also called the “diode power-law index”).

[0095] The capacitor-voltage behavior equation can be expanded into a Taylor series:

[0096] C1(V)=K 10 +K 11 V+K 12 V 2 +... (3)

[0097] C2(V)=K 20 +K 21 V+K 22 V 2 +... (4)

[0098] By adding C I (V) The expression is integrated from 0V to a specific voltage V ij, determine the total charge Q ij In case of series connection of 2 pairs of anti-series pn junctions, the following will be applied to find the charge on each pn junction, considering that in each junction pair one junction is reverse biased and one is forward biased.

[0099]

[0100]

[0101]

[0102]

[0103] Applying the integral of the capacitance versus voltage relationship, C(V), to the series expansion yields the following expression:

[0104]

[0105]

[0106]

[0107]

[0108] In a series-connected capacitor configuration, the charge on all capacitors is equal:

[0109] Q 11 =Q 12 =Q 21 =Q 22 =Q (13)

[0110] By series inversion, the charge as a function of voltage (Equations 9-12) can be inverted to voltage as a function of charge.

[0111]

[0112]

[0113]

[0114]

[0115] The total voltage V across the two pairs of anti-series connected pn junctions is

[0116] V=V 11 +V 12 +V 21 +V 22 (18)

[0117] The total voltage V across the series-connected pn junctions as a function of charge Q is given by summing equations 14 to 17:

[0118]

[0119] By series inversion of Equation 19, the charge Q as a function of the total voltage V across the series-connected pn junctions is given by:

[0120]

[0121] The capacitance versus voltage characteristics of a series-connected junction can be calculated by differentiating the Q(V) expression (Equation 20).

[0122]

[0123]

[0124] We define the coefficients in this resulting series for the C(V) behavior as follows:

[0125] C=κ0+κ1V+κ2V 2 +... (23)

[0126] The quadratic term κ2V 2 The coefficient of determines the generation of the third harmonic. The coefficient κ2 is:

[0127]

[0128] Now, the coefficient K of the series expansion of the individual pn junctions is 10 , K 11 , K 12 , K 20 , K 21 , K 22 are replaced by the corresponding Taylor coefficients, which are generated by the Taylor expansion of the behavior of C(V) (Equations 1 and 2). After this substitution, the coefficient of the quadratic term κ2 becomes:

[0129]

[0130] In the series expansion of the C(V) behavior, the quadratic term is responsible for the generation of the third harmonic. If the quadratic term is zero, the third harmonic will be completely eliminated.

[0131] κ2=0 (26)

[0132] We can transform this expression Equation 25 for κ2=0 into the following form describing the ellipse in the m1, m2 plane:

[0133]

[0134] Among them (m 0,1 , m 0,2 ) is the center point of the ellipse, and r1 and r2 are the radii in the directions m1 and m2 respectively

[0135] Equation 25 under the condition expressed by Equation 26 is transformed into the form of Equation 27, and thus yields:

[0136]

[0137] From this, we can infer that the third harmonic generation is eliminated if the ramping coefficients m1 and m2 lie on an ellipse, as described by the following equation, centered at (1 / 4, 1 / 4) with radii r1 and r2:

[0138]

[0139]

[0140] From equations 29 and 30, we can infer the shape of an ellipse on which the combination of ramp coefficients m1 and m2 falls depends on the ratio of the zero bias capacitances and the junction potentials of the two junction pairs. The zero bias capacitance can be varied over a wide range by adjusting the doping profile of the pn junction and / or the physical design (layout) of the pn junction. The flip side is that the range of variation of the junction potential is significantly smaller, since this parameter is related to the built-in voltage of the pn junction. For a silicon pn junction, V J The usual range of variation is from about 0.6 to 0.9 V. In the case where a certain breakdown voltage is required by the pn junction, the influence of V J The possibilities are very limited and cannot be considered as a useful parameter for designing device performance.

[0141] As described below, Figure 4a to Figure 4j The device parameters (i.e., the grading coefficients m1 to m2 at the first to nth (here: second) junctions) are shown. n (Here: m1 and m2) the relationship between the zero bias junction capacitance C J01 , C J02 and the junction voltage potential V J1 、V J2 )’s impact.

[0142] Figure 4a A graphical representation (graph of a function) of a cancellation line of a third harmonic signal PH3 of a semiconductor device 100 according to an embodiment is shown as a function of first and second junction taper coefficients m1 , m2 .

[0143] Based on the above mathematical derivation of the optimal C(V) parameter, Figure 4aAn ellipse, where the combination of ramp coefficients m1 and m2 falls on the ellipse, indicates the elimination of the third harmonic signal PH3 of the semiconductor device 100. Therefore, in this context, these ellipses are also referred to as elimination lines. The shape of the ellipse depends on the zero bias capacitor C J01 , C J02 and the junction voltage potentials V of the two pairs 102, 104 of the pn junction structures J1 to J4 of the semiconductor device 100. J1 、V J2 .

[0144] More specifically, Figure 4a The combination of junction gradation coefficients m1, m2 is shown, where the third harmonic PH3 generated by the semiconductor device 100 (e.g., having two pairs of pn junction structures J1, J2 and J3, J4 102, 104) is zero or at least close to zero, where the zero bias capacitance C J01 , C J02 The ratio of α1 to α2 determines the shape of the ellipse (= eccentricity) by determining the parameters a1 and a2, as indicated in equations 29 and 30 above. As described above, the parameter a i The radius r corresponding to the above equations (1) to (31) is i , and corresponds to Figures 4a to 4j The radius r shown i , that is, r i =a i Other parameters that have an impact on the parameters a1 and a2 of the ellipse (such as the first junction voltage potential and the second junction voltage potential V J1 、V J2 ) For example, in Figure 4a The curves (function diagrams) are set to equal values ​​during the calculation.

[0145] Figure 4b Shows Figure 4a From Figure 4a and Figure 4b It can be seen that all ellipses have the following conditions: (1.) m1=m2=0; (2.) m1=m2=0.5; (3.) m1=0 and m2=0.5; and (4.) m1=0.5 and m2=0, that is, m i ∈{0.00,0.50}.

[0146] Figure 4c Another graphical representation of a functional diagram for theoretically completely suppressing the third harmonic generation PH3 of the semiconductor device 100 is shown. More specifically, Figure 4c The ramp coefficient m2 of the second pair 104 of pn junction structures J3 and J4 in which the third harmonic generation PH3 is completely suppressed is shown as the ratio C of the first zero bias capacitance to the second zero bias capacitance. R =CJ01 / C J02 The slow-changing system m1 of the first pair 102 of pn junction structures J1 and J2 is a parameter of the curve diagram (functional diagram). Figure 4c During the calculation of these curves, the first junction voltage potential and the second junction voltage potential V J1 、V J2 are set to equal values, where V R =V J01 / V J02 =1.

[0147] Figure 4d Shows Figure 4c An enlarged view (view) of a graphical representation of .

[0148] Figure 4e The parameters a1, a2 (radii r1, r2) of an ellipse in which the third harmonic PH3 of the semiconductor device 100 is at least theoretically completely suppressed are shown as a ratio C of the first zero-bias capacitance to the second zero-bias capacitance. R C J01 / C J02 During the calculation of these curves, the first junction voltage potential and the second junction voltage potential V J1 、V J2 are set to equal values, where V R =V J01 / V J02 =1.

[0149] The ratio C from the first bias capacitor to the second bias capacitor R C J01 / C J02 The relatively large dependence of the first parameter a1 (first radius R1) of the ellipse reflects the fact that Figure 4a The ellipse shown is relative to the increase ratio C of the first zero bias capacitance and the second zero bias capacitance. R C R =C J01 / C J02 The increased eccentricity.

[0150] Figure 4f shows that given the first junction voltage potential and the second junction voltage potential V J1 、V J2 The effect of unequal values ​​of V R =V J01 / V J02 ≠1, a graphical representation of the cancellation line of the third harmonic PH3 of the semiconductor device 100 as a function of the first junction ramp coefficient and the second junction ramp coefficient m1, m2. More specifically, Figure 4fshows the first junction voltage potential and the second junction voltage potential V J1 、V J2 The influence of the unequal values ​​of on the combination of ramp coefficients m1 and m2, which results in complete suppression of the generation of the third harmonic PH3 of the semiconductor device 100. Figure 4f In the case of the first zero bias capacitor and the second zero bias capacitor C J01 , C J02 are set to equal values, where C J01 =C J02 The junction voltage potential V of the second pair 104 of pn junction structures J3 and J4 is J2 is set to a fixed value V J2 =0.8.

[0151] Figure 4g to Figure 4j A graphical representation of the corresponding power level PH3 of the third harmonic of the semiconductor device 100 as a function of the first and second junction ramping coefficients m1, m2 is shown, as used for example with reference to Figure 2 and the simulation results of the method explained in FIG3 . Figure 4g to Figure 4j The theoretical cancellation line (= for low input power level P IN The trajectory of the theoretical optimal suppression of the third harmonic PH3). More specifically, Figure 4g to Figure 4j shows different input power levels P of the fundamental frequency RF signal IN ( Figure 4g P IN =-10dBm; Figure 4h P IN = 0 dBm; and Figure 4i P IN = +10dBm) has equal first zero bias junction capacitance and second zero bias junction capacitance C J01 =C J02 The simulated spurious third harmonic PH3 of the semiconductor device 100 (e.g., using the above-mentioned circuit simulation tool). The theoretically optimal trajectory (also referred to herein as the cancellation line) of PH3 suppression derived above is represented by curve "A" (the "gray" curve). At lower input power levels P IN The minimum third harmonic PH3 of the circuit simulation and theoretical derivation (curve "A") are very closely matched, where for increasing input power levels P IN , the deviation of the minimum third harmonic PH3 produced from the circuit simulation and from the theoretical optimal suppression (curve "A") becomes a little more significant, but remains flat up to 20 dBm for the input powers studied.

[0152] It should be noted that Figure 4g to Figure 4jThe irregular character of the contour lines in and even the appearance of disconnected contour areas near the elimination lines in the contour plot are due to the algorithm used to generate the contour plot from a simulation data set, in which simulation data exists only for a limited number of simulation m1, m2 combinations located on a regular rectangular grid.

[0153] from Figure 4j It can also be seen that the optimum junction ramp coefficient varies with input power. Figure 4j The results show that for different input powers P IN Simulated PH3 power levels as a function of junction ramp coefficient m2 for (-10 dBm, 0 dBm, 10 dBm and 20 dBm). The junction ramp coefficient m1 is kept fixed at m1 = 0.25, with C further set J01 =C J02 . And the power level is normalized to the local maximum at m1=m2=0.25 (reference case) to better compare the results. From this, it can be understood that the suppression of the generation of spurious third harmonics can be optimized for a desired predetermined input power level. To this end, it is also possible to purposefully deviate from curve "A", which for small input power levels P IN is analytically derived, and the pn junction structure is arranged with a corresponding junction grading coefficient designed to be relative to a predetermined input level P by using the results from the above simulation for a circuit simulation tool IN The ideal amount of reference situation suppresses the generation of spurious third harmonics.

[0154] Furthermore, depending on the desired level of suppression, it may only be necessary to reproduce the optimum junction ramping coefficient with a certain accuracy. For example, if the power level of the spurious third harmonic is to be suppressed by 10 dB relative to the reference case, a deviation of ±0.05 for the junction ramping coefficient m2 may be acceptable. To achieve a higher level of suppression, a smaller deviation of ±0.03 or even ±0.02 may be required. Similar considerations apply to the junction ramping coefficient m1 or m in general. i .

[0155] The relationship between the simulated PH3 value and the optimal value (curve "A") for unequal zero bias capacitance C J0,1 , C J0,2 is also valid, which leads to an increased eccentricity of the ellipse, as in Figure 4a As described.

[0156] In the following, the mathematical derivation of the optimal C(V) parameters for suppressing third harmonic generation is extended to three (n=3) pairs 102, 104, 106 of anti-series connected pn junction structures J1, J2 and J3, J4 and J5, J6, and further generalized to n pairs.

[0157] By using the same steps as described above, we can determine the conditions for eliminating third harmonic generation for 3 pairs of anti-series connected pn junctions. In this case, the quadratic coefficient of the series expansion of the C(V) behavior is as follows:

[0158]

[0159] This can be further simplified to:

[0160]

[0161] This is a three-dimensional ellipsoid with the following general form:

[0162]

[0163] The center point m 0，i = 1 / 4, where i∈{1,…,n} and the radius

[0164]

[0165]

[0166] Generalization for n pn pairs: m laid out on the following n-dimensional ellipsoid i All combinations of lead to the cancellation of the third harmonic, where i∈{1,…,n}

[0167]

[0168] The radius ri of the ellipsoid (where i∈{1,…,n}) is defined as

[0169]

[0170] In the following, different aspects of the inventive concept of a semiconductor device 100 as derivable from the above evaluation are described in detail, wherein the semiconductor device 100 has n (at least two) pairs 102, 104 (...) of anti-series connected pn junction structures J1, J2, J3, J4 (...) having adjusted junction gradation coefficients m1-m n , for providing at least reduced or minimal generation of spurious odd harmonics, for example for a predetermined input power level P IN The third harmonic of .

[0171] As shown from the anti-series connection of n pairs 102, 104 (...) with adjusted junction ramping coefficient m1-m n The above evaluation of the semiconductor device 100 having the pn junction structures J1, J2, J3, J4 (...) can be derived that the first to nth parameters "a1 to an Each of the n zero-bias capacitors C J0,1 To C J0,n and n junction voltage potentials V of n pairs of pn junction structures J1 To V Jn .

[0172] As can be deduced from the above evaluation for the semiconductor device 100, the first to nth parameters “a1 to a n ” meets the following equation:

[0173]

[0174] Based on the above evaluation of the semiconductor device 100 and referring to Figure 4g to Figure 4j , a simulated graphical representation of the corresponding power level PH3 of the third harmonic of the semiconductor device 100 as a function of the first and second junction grading coefficients m1, m2 and the theoretical cancellation line is shown together with the general derivation described above, which can be adjusted for the first to "nth" junction grading coefficients m1 to m n The value of , to produce a third-order intercept point IP3 of at least 50dBm, 55dBm or even 60dBm. For example, at an input power of 10dBm, a third-order intercept point IP3 of 50dBm corresponds to a PH3 power level of -70dBm. Among them, one of the junction taper coefficients, such as m2, can be adjusted to m2<0.50, preferably to m2≤0.48, the latter being advantageous from a manufacturing perspective, as described above.

[0175] According to an embodiment of the semiconductor device 100, the first to nth junction grading coefficients m1 to m n More specifically, the "n" pairs of pn junctions include at least a first pair 102 and a second pair 104, wherein the first pair 102 has a first type pn junction with a grading coefficient m1, and the second pair 104 has a second type pn junction with a grading coefficient m2.

[0176] According to an embodiment of the semiconductor device 100, for Cj01=Cj02, and Vj1=Vj2, the first type pn junction structures J1, J2 are arranged to include a first junction gradation coefficient m1=0.59±0.03, and wherein the second type pn junction structures J3, J4 are arranged to have a second junction gradation coefficient m2, wherein m2=0.33±0.10. The latter may represent an almost linearly graded junction.

[0177] Based on the above evaluation for some embodiments of the semiconductor device 100, where i∈{1,2}, the parameters a1 and a2 (=radii r1, r2) of the ellipse equation conform to the following equation:

[0178] as well as

[0179]

[0180] According to another embodiment, the pn junction structures J1, J2 and J3, J4 of the first type / pair 102 and the second type / pair 104 are arranged to have a zero bias capacitance C that meets the following condition: J0-1 , C J0-2 Ratio:

[0181]

[0182] According to another embodiment, the i-th type pn junction structure forms an i-th type diode structure having an anode region and a cathode region. In addition, the semiconductor device 100 may include a first connection terminal 107 and a second connection terminal 108, wherein the "n" pairs 102, 104 (...) pn junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108.

[0183] According to another embodiment, "n" pairs 102, 104 (...) pn junction structures J1 to J4 (...) are arranged in a stacked configuration in a semiconductor substrate. According to another embodiment, the different doped semiconductor regions of the pn junction structure extend vertically into the semiconductor substrate relative to the main surface area of ​​the semiconductor substrate, and the main part of the area of ​​the metallurgical pn junction is a planar pn junction extending parallel to the main surface area of ​​the semiconductor substrate. According to another embodiment, the two pn junction structures of the i-th pair can be arranged together in a stacked configuration in the semiconductor substrate. According to another embodiment, one pn junction structure of the two pn junction structures of the first pair can be arranged in a stacked configuration in a semiconductor substrate having one pn junction structure of the two pn junction structures of the second pair. According to another embodiment, the stacked configuration may include an npn structure having a floating base region in the semiconductor substrate.

[0184] Figure 5aa and Figure 5ab 1 shows a schematic cross-sectional view of a semiconductor device 100 according to an embodiment, the embodiment having, for example, a semiconductor device 100 according to an embodiment (see, for example, Figure 1a ) of four anti-series connected pn junction structures J1, J2, J3, and J4, wherein the first stack or pair 102 includes pn junction structures J1, J2 of the first type (i=1), and wherein the second stack or pair 104 includes pn junction structures J3, J4 of the second type (i=2).

[0185] like Figure 5aa and Figure 5abAs shown, the semiconductor device 100 comprises a semiconductor substrate 120. The semiconductor substrate 120 has a first main surface portion 120a and a second main surface portion 120b on opposite main sides of the semiconductor substrate 120.

[0186] The following exemplary description of different layers and regions of the semiconductor substrate 120 extends substantially from the second main surface portion 120b of the semiconductor substrate 120 to the first main surface portion 120. The different regions and structures in the semiconductor substrate 120 may be manufactured, for example, during a so-called front end of line (FEOL) process stage.

[0187] The semiconductor substrate 120 may include a low-ohmic n-type substrate 120-1. A p-type semiconductor layer 120-2 is arranged on the n-type substrate 120-1. The p-type semiconductor layer 120-2 (e.g., p-epitaxial layer 120-2) may be epitaxially applied on the n-type substrate 120-1. The p-type semiconductor layer 120-2 includes a buried p-type semiconductor layer 120-3 (p-buried layer 120-3). The buried p-type semiconductor layer 120-3 may be formed, for example, in the form of a blanket (maskless) implantation of a p-type dopant in the semiconductor layer 120-2.

[0188] Another p-type layer 120-4 (e.g. p-epitaxial layer 120-4) is arranged on the p-type layer 120-2 with the buried p-type layer 120-3. The p-type semiconductor layer 120-4 can be epitaxially applied on the p-type layer 120-2. Alternatively, the layer 120-4 can also be realized by an i-type (i.e., intrinsic or unintentionally doped) layer.

[0189] In the second epitaxial layer 120-4, a p-type well region 120-5 (p-well 120-5) may be arranged. The p-type well region 120-5 may be formed after LOCOS oxidation of the main surface region 120a of the p-type layer 120-4 of the semiconductor substrate 120 and by performing a blanket implantation step. Based on this method, no photolithography resist mask is required on the surface region 120a of the p-type layer 120-4, but a self-aligned implantation process may be performed due to the LOCOS oxidation on the surface 120a. The LOCOS process (LOCOS = Local Oxidation of Silicon) is a microfabrication process in which silicon dioxide is formed in selected regions on a silicon wafer (i.e., the semiconductor substrate 120) having a Si-SiO2 interface at a point or plane lower than the rest of the silicon main body surface region 120a. Of course, the p-well 102-5 may also be formed by using photolithography methods known in the art.

[0190] like Figure 5aa and Figure 5abAs shown, the pn junction structures J1, J3 and the pn junction structures J2, J4 can be arranged in separate semiconductor regions 122, 124 of the semiconductor substrate 120, wherein the separate regions 122, 124 can be realized by means of so-called deep isolation trenches 130 which laterally limit and / or laterally surround the semiconductor regions 122, 124 having the pn junction structures J1, J3 and J2, J4. The deep isolation trenches 130 can be formed in the semiconductor substrate 120, for example, by means of an RIE process step (RIE=reactive ion etching), wherein the realized trenches can be lined with an oxide material 134, for example a SiO2 liner, by means of a trench liner oxidation process and filled with the semiconductor material 132, for example, polysilicon.

[0191] The semiconductor device 100 also includes a highly doped n-type contact region 120-7 in the form of an implanted region adjacent to the surface region of the p-type well 120-5. In some embodiments, the n-type contact region 120-7 may also be simply considered a shallow n region 120-7 or an emitter region. The n-type contact region 120-7 may be formed by means of an n-contact implant process step (e.g., by means of a blanket implant), which may be self-aligned by means of the LOCOS process (described above), so that no photolithography resist mask is required.

[0192] As a further (e.g. final) process step of a front-end process for processing the semiconductor substrate 120, an oxide material 128 may be deposited on the first main surface area 120a of the semiconductor substrate 120. The semiconductor device 100 may further include a contact and metallization layer stack 140 (BEOL stack, BEOL=back-end of line) on the first main surface area 120a of the semiconductor substrate 120 for providing a contact and metallization layer stack 140 (BEOL stack, BEOL=back-end of line) for the semiconductor device(s) 100 and optionally another circuit element (in the semiconductor substrate 120). Figure 5aa and Figure 5ab The semiconductor device 100 is provided with interconnects 110 (e.g., contact plugs or vias) and interconnect layers 107, 108 (not shown). The contact structures and (structured) metallization layers of the metallization stack 140 may be formed by means of BEOL process steps. Finally, if a plurality of semiconductor devices 100 are manufactured in a semiconductor substrate 120 (such as a semiconductor wafer 120), the semiconductor devices 100 may be packaged and separated (diced). For example, a chip-scale packaging process includes, for example, forming an electrode (or pad) as a top layer of the metallization stack 140 and a dicing process.

[0193] like Figure 5aa and Figure 5abAs shown, the n-type contact region 120-7 (= cathode region) and the p-type well region 120-5 (= anode region) form first type pn junction structures J1 and J2, respectively, in different semiconductor substrate regions 122 and 124. In addition, the buried p-type layer 120-3 (= anode region) and the n-type substrate 121 (= cathode region) form second type pn junction structures J3 and J4, respectively, in separate semiconductor regions 122, 124 of the semiconductor substrate 120.

[0194] Figure 5b Shows Figure 5aa and Figure 5ab Schematic calculation diagram of an exemplary doping profile of the semiconductor device 100 , where different doping concentrations in the p-type well 120 - 5 can be achieved by different implantation doses, which are indicated by “ 36 ” to “ 42 ”. Figure 5b The curve also contains Figure 5aa and Figure 5ab 1 and 12. The metallurgical junction between the n-type region 120-7 and the p-type region 120-5 falls into the descending slope of the p-type implant profile of the region 120-5. In the case of a sufficiently steep slope of the n-type implant of the n-type region 120-7, the C(V) properties of the pn junction formed by the regions 120-5 and 120-7 may represent a hyperabrupt characteristic and may therefore have a ramping factor > 0.5.

[0195] Figure 6a The semiconductor device 100 is shown along the Figure 6b Schematic cross-sectional view of a cutting line ABCD in a schematic top view of a semiconductor device 100. According to an embodiment, the semiconductor device 100 has, for example, four anti-series connected pn junction structures J1, J2, J3, J4 (see, for example, Figure 1a ). The pn junction structures J1, J3 (vertical device 1) may include a first npn structure having a first floating base region in the semiconductor substrate 120, wherein the pn junction structures J2, J4 include a second npn structure having a second floating base region in the semiconductor substrate 120. The floating base regions are respectively formed by p-type portions (e.g., by p-type regions 120-2 to 120-5) between the n-type substrate 120 and the n-type contact region 120-7.

[0196] As about Figure 5aa-Figure 5bAs discussed, with respect to the first and second pairs 102, 104 of anti-series connected pn junction structures J1, J2 and J3, J4, the first type pn junction structures J1 and J2 may have (substantially) the same layout and doping distribution and have a gradual change coefficient m1, wherein the second type pn junction structures J3 and J4 may also have (substantially) the same layout and doping distribution and have a second junction gradual change coefficient m2.

[0197] According to an embodiment, the semiconductor device forms, for example, a discrete ESD device (ESD=Electrostatic Discharge) having a TVS functionality.

[0198] According to other embodiments, the semiconductor device 100 may have n (at least two) pairs of junction grading coefficients m1, m2, . . . m n The device 100 includes an anti-series connected pn junction structure 102, 104 (...), wherein (at least) one pair of the n pairs 102, 104 (...) of pn junction structures J1 to J4 (...) comprises a "composite" diode structure to adjust and obtain the desired behavior with respect to the breakdown voltage of the device 100, and to provide at least reduced or minimal generation of stray odd harmonics (e.g., third harmonics). For example, the device 100 can be used in a TVS (transient voltage suppressor) device.

[0199] Figure 7a A schematic diagram of a semiconductor device 100 is shown having n=2 pairs 102, 104 of anti-series connected pn junction structures, wherein (at least) one pair 102 of at least two pairs 102, 104 of pn junction structures are arranged to have a junction type described herein as a composite pn junction structure (composite diode structure) and will be referred to below Figure 7b Describe in detail.

[0200] Figure 7b Only shown Figure 7a The first pair 102 of the semiconductor device 100 shown in FIG. 1 is formed as a pair of two composite pn junction structures 102-1 and 102-2. The first composite pn junction structure 102-1 includes a first partial pn junction structure J 11 and the second part pn junction structure J 12 , and the second composite pn junction structure 102-2 includes a first partial pn junction structure J 21 and the second part pn junction structure J 22 That is to say, Figure 7a and 7b The first pair 102 is formed by a pair of anti-series connected composite pn junction structures 102-1, 102-2, each of which has a first partial pn junction structure J 11 , J 21and the second part pn junction structure J 12 , J 22 The first part of the pn junction structure J11, J21 has a first part of the junction gradual coefficient m 11 , the first part of the junction voltage potential V J11 and the first part zero bias capacitor C J011 , where the second part pn junction structure J 12 , J 22 The second part has a gradual change coefficient m 12 , the second part junction voltage potential V J12 and the second part zero bias capacitor C J012 , where for example the second part of the junction ramp coefficient m 12 , the second part junction voltage potential V J12 and the second part zero bias capacitor C J012 The first part can be combined with the ramp coefficient m 11 , the first part of the junction voltage potential V J11 and the first part zero bias capacitor C J011 Different. Based on the first part of the gradual change coefficient and the second part of the gradual change coefficient m 11 、m 12 The first effective junction grading coefficient m1 of the corresponding composite pn junction structures 102-1 and 102-2 is generated. That is, the composite pn junction structures 102-1 and 102-2 exhibit an effective junction grading coefficient m1, an effective junction potential V J1 and the effective zero bias junction capacitance C J01 The effective behavior of the composite pn junction structure as a simple pn junction structure is Figure 7b In the embodiment, the composite pn junction structure 102-1 corresponds to the pn junction structure J1 and the composite pn junction structure 102-2 corresponds to the pn junction structure J2. Accordingly, in many cases, the voltage-dependent capacitance characteristics of the composite pn junction structure can be satisfactorily described or modeled by the above expression A1, where m i as the effective (combined) junction grading coefficient and for the junction potential V Ji and zero bias junction capacitance C J0i similar.

[0201] In other words, according to the embodiment Figure 7a and Figure 7b The semiconductor device 100 shown includes a first partial pn junction structure J 11 and the second part pn junction structure J 12 The first parallel circuit 102-1 and the first partial pn junction structure J 21 and the second part pn junction structure J 22The second parallel circuit 102-2 is connected in series, wherein the first parallel circuit and the second parallel circuit 102-1 and 102-2 are connected in anti-series. Figure 7a As shown, the anti-series connected first and second parallel circuits 102 - 1 , 102 - 2 form a first pair 102 of pn junction structures J1 , J2 connected in series to a second pair 104 of pn junction structures J3 , J4 .

[0202] That is, according to an embodiment of the semiconductor device 100, at least one pair 102 of the n pairs 102, 104 (...) of pn junction structures J1 to J4 (...) may be arranged to form a Figure 7b The first partial pn junction structure J having parallel connection is shown 11 , J 21 and the second part pn junction structure J 12 , J 22 The composite pn junction structure 102, wherein the first part of the pn junction structure J 11 , J 21 The first part has a gradual change coefficient m 11 , and wherein the second part pn junction structure J 12 , J 22 The second part has a gradual change coefficient m 12 , the second part of the gradual change coefficient m 12 In some embodiments, the first part can be combined with the ramp coefficient m 11 The effective junction grading coefficient m1 of the composite pn junction structure 120 is based on the first part of the junction grading coefficient and the second part of the junction grading coefficient m 11 、m 12 combination.

[0203] In order to provide the basis Figure 7a and 7b Another explanation of the present concept in the form of the described implementation and embodiment of the semiconductor device 100, with respect to Figures 8a to 8c The following discussion relates to an exemplary technical analysis of the field of semiconductor devices, for example, the fields of discrete ESD protection devices and TVS devices, respectively, pertaining to the applicant and the technical discoveries and conclusions resulting therefrom.

[0204] like Figure 7a As shown, the semiconductor device 100 having the generated junction gradation coefficients m1, m2 of the first pair (102) and the second pair (104) of pn junction structures can be realized with great freedom. In particular, the pn junction structure with great freedom of tuning the breakdown voltage in which the gradation coefficient m≥0.5 can be realized as a composite pn junction structure and used in the semiconductor device 100 of some embodiments.

[0205] In conventional semiconductor technology, it is difficult to achieve a hyper-abrupt junction at a low breakdown voltage of less than 25V or even less than 16V or 12V and a controllable ramp coefficient m≥0.5. Some embodiments provide a semiconductor device 100 having both the desired properties, i.e., a low breakdown voltage and an adjustable ramp coefficient of at least 0.5. This is due to the fact that conventionally used processing steps in semiconductor technology, such as implantation and diffusion, produce a dopant distribution that exhibits some ramping in a narrow region around a metallurgical junction. The space charge region that determines the capacitance with respect to voltage behavior and the breakdown voltage of a pn junction extends around the metallurgical junction. In the case of low breakdown voltages, the doping concentration is high and the extension of the space charge region is small. As the breakdown voltage increases, the doping concentration on one or both sides of the metallurgical junction decreases and the width of the space charge region increases. Due to the inevitable ramping near the metallurgical junction, a low voltage breakdown junction will see more or less ramping distributions in practice, rather than the desired abrupt or hyper-abrupt doping distributions. Therefore, it is difficult to achieve a combination of low breakdown voltage and ramping coefficient m≥5 using conventional semiconductor processes used in mass production of semiconductor devices and circuits.

[0206] In summary, a higher doping level leads to a less extended space charge region (=depletion region) and thus to a (lower) breakdown voltage V bd Furthermore, the resulting more linear graded junction behavior leads to a (smaller) gradient coefficient m.

[0207] (Relatively) high ramping coefficients m≥0.5 require more (or hyper) abrupt doping profiles. In the case of lower doping levels on one side of the metallurgical junction, the depletion layer will extend further into this lower doping region. Therefore, the depletion layer is not limited to a narrow region around the metallurgical junction, as in the case of higher doping levels, where typically the doping profile is showing more or less linear ramping. Since the depletion region extends beyond this ramping region close to the metallurgical junction in the case of lower doping levels, the C(V) characteristics of the lower doped junction can be more easily adapted to the ramping coefficient m≥0.5. At the same time, the (relatively) low doping level leads to a higher breakdown voltage V bd .

[0208] Therefore, it is difficult to achieve a combination of low breakdown voltage and ramp coefficient m≥0.5 using conventional technology.

[0209] To overcome this limitation, Figure 7a and Figure 7b The illustrated embodiment introduces a concept to obtain a junction (pn junction structure) having desired properties (i.e. both a predetermined low breakdown voltage of not more than 25 V and a predetermined grading coefficient equal to or higher than 0.5) by subdividing the junction into two regions, i.e., subdividing the composite pn junction structure into a partial pn junction structure together, the two regions being:

[0210] (1) An active region with a higher well implant dose, which results in a pn junction J 11 , J 21 A portion of the device has a low predetermined breakdown voltage and a ramp coefficient m 11 <0.5, and

[0211] (2) Another active region with a lower well implant dose, which results in a pn junction J 12 , J 22 A portion of the breakdown voltage having a breakdown voltage higher than a predetermined breakdown voltage and a ramp coefficient m 12 >0.5.

[0212] The overall behavior of the composite pn junctions 102-1 and 102-2 shows the breakdown voltage determined by the higher well doping and by the first and second partial pn junction structures J, respectively. 11 , J 12 and J 21 , J 22 The parallel connection of the two branches determines the gradual change coefficient of the capacitance with respect to the voltage characteristic.

[0213] By adjusting (1) the first part pn junction structure and the second part pn junction structure J 11 , J 12 and J 21 , J 22 The slow-varying coefficient m in the two regions 11 、m 12 (by well implantation dose and energy and by further diffusion steps) and by adjusting (2) the first partial pn junction structure and the second partial pn junction structure with different well implantations J 11 , J 12 and J 21 , J 22 The effective ramp coefficient m1 of the composite junction structures 102-1 and 102-2 can be adjusted to a target value close to the value that minimizes the generation of the third harmonic (h3). In some embodiments, for the pair 102 of composite junctions 102-1 and 102-2, J 11 and J 21 The zero bias capacitance (C J0 )(and respectively J 12 and J 22 ) can be arranged to be equal from the angle of forming a symmetrical device 100 to also suppress the generation of even (eg, second) harmonics. Similar considerations apply to the partial pn junction structure J 11 and J 21 (and respectively J 12 and J 22 ) junction voltage potential (V J0) and the area ratio of the partial pn junctions in each of the composite structures 102-1 and 102-2 forming the pair of composite pn junction structures 102. In the above concept, a pair of composite pn junctions 102-1 and 102-2 is realized, in which both the breakdown voltage and the net gradation coefficient can be controlled in a much larger parameter range through technical and physical design or layout adjustment.

[0214] Figure 8a Schematic simulation diagram of the generated junction grading coefficient m1 as a function of doping concentration based on different implantation doses is shown. More specifically, for the region including regions 120-7 and 120-5 (see Figure 5aa and Figure 5ab 5 (described in more detail above), in Figure 8a The simulated capacitance-to-voltage characteristics of the pn junction between the highly n-doped shallow contact region and the p-doped well region are shown in FIG. 3 , where equal numbers (36-42) represent the corresponding doping profiles. It can be seen from the figure that m>0.5 can be obtained in the case of a low implantation dose for the p-well hyperabrupt junction.

[0215] Figure 8b Shown based on Figure 8a and Figure 5b Schematic simulation of the breakdown voltage generated as a function of doping concentration for different implant doses and doping profiles indicated by the same numbers in FIG. However, as mentioned above, the breakdown voltage of the junction with the lowest p-well dose and the highest grading coefficient tends to have a high breakdown voltage, such as Figure 8b In the case of this simulation example it can be seen that if the ramp coefficient for the minimum third harmonic generation is between 0.5 and 0.6, the junction will have a breakdown voltage of 40V or more without using a composite pn junction structure as explained above.

[0216] Figure 8c shows the partial junction ramp coefficient (J) based on two adjustments 11 or J 21 )m 11 and (J 12 or J 22 )m 12 , as the first partial pn junction structure and the second partial pn junction structure J of the composite pn junction structure 102-1 (102-2). 11 and J 12 (or J 21 and J 22 ) is a function of the area ratio between the active regions of the first and second pn junction structures. In this case, the doping profiles of the first and second pn junction structures correspond to Figure 5b 37 and 41 shown in (see also Figure 8a and Figure 8b As discussed above, the breakdown voltage of the junction with the lowest p-well dose and the highest grading coefficient tends to have a high breakdown voltage, such as Figure 8b The relative area contribution can be easily controlled by the physical design (layout) of the device.

[0217] More generally, the composite junction 102-1 described above can be described as being arranged as a type i pn junction structure 120-i. Thus, according to an embodiment, the first partial pn junction structure is arranged to have a first partial junction grading coefficient m i1 >0.5, and wherein the second part pn junction structure is arranged to have a second part junction grading coefficient m i2 <m i1 , for example m i1 Can be between 0.30 and 0.5.

[0218] According to an embodiment, the first partial pn junction structure and the second partial pn junction structure J 11 , J 21 and J 12 , J 22 The composite pn junction structure 102-1 is arranged in the semiconductor substrate, wherein the combination is proportionally dependent on the first partial pn junction structure and the second partial pn junction structure J of the composite pn junction structure 102-1 parallel to the first main surface area of ​​the semiconductor substrate. 11 and J 12 The active region of the composite pn junction structure 102-2 and the first and second partial pn junction structures J 21 and J 22 According to an embodiment, the first partial pn junction structure J of the first composite pn junction structure 102-1 is 11 and the second part pn junction structure J 12 and the first partial pn junction structure J of the second composite pn junction structure 102-2 21 and the second part pn junction structure J 22 They may be arranged together in a laterally isolated common region of the semiconductor substrate. According to an embodiment, the first partial pn junction structure and the second partial pn junction structure extend vertically into the semiconductor substrate in a depth direction relative to the first main surface region of the semiconductor substrate.

[0219] Figure 9a and Figure 9d A schematic cross-sectional view of another exemplary implementation of a semiconductor device 100 including a pair of composite pn junction structures is shown. Figure 9b It shows that Figure 5b shown in and is now used for Figure 9a Schematic simulation diagram of different exemplary doping distributions of a semiconductor device. Fig.9c shows that the composite type pn junction structure passes through the plane Figure 9a Schematic top view of a semiconductor device of FIG. 1 , for example showing the “active” regions of the first partial anode region 120 - 5 and the second partial anode region 120 - 6 of the composite pn junction structures J1 and J2 .

[0220] In the drawings and the description, identical elements and elements having the same function and / or the same technical or physical effect have the same reference numerals or are identified by the same names. Figure 9a and 9d In the following description of an embodiment of the semiconductor device 100 in FIG. Figure 5aa-Figure 5b and Figure 6a-6b When comparing the embodiments of the semiconductor device 100 in the drawings, the main focus is on the corresponding differences and adaptations between different implementations of the semiconductor device 100.

[0221] Figure 9a and 9d Different schematic cross-sectional views of a semiconductor device 100 are shown according to an embodiment having, for example, two pairs of anti-series connected pn junction structures J1, J2 (=first pair 102) and J3, J4 (=second pair 104), wherein the first pair 102 comprises composite pn junction structures 102-1, 102-2, and wherein the second pair 104 comprises pn junction structures J3, J4 (see, for example, FIG. Figure 7a ) in order to adjust and obtain, for example, a desired TVS behavior (TVS=Transient Voltage Suppressor) of the semiconductor device 100 with respect to its breakdown voltage and junction ramping factor.

[0222] The first composite pn junction structure 102-1 includes a first partial junction grading coefficient m 11 The first part of the pn junction structure J 11 and has the second part of the gradual change coefficient m 12 The second part of the pn junction structure J 12 The second composite pn junction structure 102-2 also includes a partial junction grading coefficient m 11 The third part of the pn junction structure J 21 (Similarly for the zero bias capacitor C J0 and junction potential V J0 Basically with J 11 equal structure), and has a partial junction ramp coefficient m 12 Partial pn junction structure J 22 (Similarly for the zero bias capacitor C J0 and junction potential V J0 Basically with J 12The generated junction gradation coefficient m1 of the first composite pn junction structure and the second composite pn junction structure 102-1, 102-2 is based on the first part of the junction gradation coefficient and the second part of the junction gradation coefficient m 11 、m 12 combination.

[0223] like Figure 9a As shown, the first composite pn junction structure 102-1 can be realized by using two different implant regions 120-5, 120-6 in the substrate region 122. Therefore, the n-type contact region 120-7 in the substrate region 122 is embedded in the adjacent implant regions 120-5, 120-6. The second composite pn junction structure 102-2 can be realized by using two different implant regions 120-5, 120-6 in the substrate region 124. Therefore, the other n-type contact region 120-7 in the substrate region 124 is embedded in the other adjacent implant regions 120-5, 120-6.

[0224] like Figure 9a As shown, part of the pn junction structure J 11 , J 12 The semiconductor region 122 of the semiconductor substrate 120 may be arranged as a part of the adjacent pn junction structure J 11 , J 12 ), where part of the pn junction structure J 21 , J 22 The semiconductor substrate 120 may be arranged in the further semiconductor region 124 (as an adjacent part of the pn junction structure J 21 , J 22 ). The separated regions 122, 124 can be realized by means of so-called deep isolation trenches 130, which laterally limit and / or laterally surround the semiconductor regions 122, 124. In addition, the buried p-type layer 120-3 (=anode region) and the low-ohmic n-type substrate 121 (=cathode region) form second type pn junction structures J3 and J4 in the separated semiconductor regions 122, 124 of the semiconductor substrate 120, respectively.

[0225] Figure 9b Shown for Figure 9a Schematic simulation diagram of different exemplary doping profiles of the semiconductor device 100. Different doping concentrations of the implanted regions 120-5 and 120-6 in the p-type layer 120-4 can be achieved by using different implantation doses. Figure 9b 36 to 42 in the figure. The figure also contains an indication of the approximate expansion of different layers and / or regions of the semiconductor substrate 120. Figure 9aAs shown, the first composite pn junction structure 102-1 having the first partial pn junction and the second partial pn junction (diode) structures J11 and J12 includes two p-type well regions 120-5 and 120-6. The doping concentration distribution (A) of the p-well 120-5 results in, for example, a first partial junction gradient coefficient m 11 The doping concentration distribution (B) of the P-well 120 - 6 may be lower than the doping concentration (A) of the P-well 120 - 5 , resulting in a second part junction grading coefficient m 12 , for example, where m 12 >m 11 Based on the first part of the gradual change coefficient and the second part of the gradual change coefficient m 11 、m 12 , the effective net ramp coefficient m1 of the composite junction 102-1 can be achieved.

[0226] Since the higher doping level leads to a less extended space charge region (=depletion region) and thus to a (lower) breakdown voltage V bd , the resulting more linear graded junction behavior leads to a (relatively) small gradient coefficient m. (Relatively) high grading coefficients m require more (or hyper) abrupt doping profiles. However, there are practical difficulties in creating an "ideal" abrupt profile. Therefore, in order to form a pn junction structure with a grading coefficient m ≥ 0.50, a (relatively) wide space charge region with a (relatively) low doping level may be necessary. (Relatively) low doping levels lead to (relatively) high breakdown voltage V bd .

[0227] The above evaluation regarding the schematic simulation diagrams of different exemplary doping profiles applies correspondingly to the second composite pn junction structure 102 - 2 of the first pair of pn junction structures 102 and the resulting effective net gradation coefficient m1 .

[0228] Fig.9c Shows Figure 9a Schematic top view of a possible layout of a semiconductor device 100 showing the extension of the "active" areas of the first partial anode region 120-5 (with a higher p-well doping implant) and the second partial anode region 120-6 (with a lower p-well doping implant) of the composite type pn junction structures 102-1 and 102-2. Exemplary area ratios are 40% for the first partial anode region 120-5 and 60% for the second partial anode region 120-6.

[0229] By optimizing the layout, the ratio of the area defined by the lower dopant concentration and the higher dopant concentration of the p-well regions 120-6 and 120-5 can be adjusted to achieve a target (optimal) value of the junction gradation coefficient m1>0.5, for example, m1~0.55 while maintaining a breakdown voltage not exceeding 25V.

[0230] like Figure 9dAs shown, the first pair of partial pn junction structures J 11 , J 12 can be arranged in the semiconductor region 122 of the semiconductor substrate 120, wherein the second pair of partial pn junction structures J 21 , J 22 The semiconductor regions 122 , 124 may be arranged in the further semiconductor region 124 of the semiconductor substrate 120 . The separated regions 122 , 124 may be realized by means of so-called deep isolation trenches 130 which laterally delimit and / or laterally surround the semiconductor regions 122 , 124 .

[0231] like Figure 9d As shown, a p-type well region 120-5 (p-well 120-5) is arranged in the second epitaxial p-type layer 120-4 in the semiconductor regions 122 and 124, wherein the p-type well 120-5 only partially surrounds the highly doped n-type contact region 120-7 in the p-type layer 120-4 of the semiconductor substrate 120. Therefore, in the semiconductor region 122, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a first partial pn junction structure J. 11 , wherein the p-type well region 120-5 and the highly doped n-type contact region 120-7 form a second partial pn junction structure J 12 (As the adjacent partial pn junction structure J 11 , J 12 ). Therefore, in the semiconductor region 124, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a third partial pn junction structure J 21 , wherein the p-type well region 120-5 and the highly doped n-type contact region 120-7 form a fourth partial pn junction structure J 22 (As the adjacent partial pn junction structure J 21 , J 22 ). Therefore, the first part pn junction structure and the third part pn junction structure J 12 , J 21 A p-type well region, for example, is not included.As described above, layer 120-4 may also be implemented as an i-type (ie, intrinsic or unintentionally doped) layer.

[0232] Alternatively, the doping profile in the layer 120-4 may be adjusted by gradually adjusting the doping level during the epitaxial growth of the layer 120-4 to respectively 11 and J 21 The predetermined slow-changing coefficient m is obtained from 12 In other words, by controlling the gas flow of the dopant source gas during the growth of the epitaxial layer, it is possible to create a depth dependence of the doping level in the epitaxial layer at a portion of the pn junction. 11 and J 21 Hyperabrupt junction behavior is achieved in

[0233] Furthermore, the buried p-type layer 120 - 3 (=anode region) and the n-type substrate 121 (=cathode region) form second type pn junction structures J3 and J4 in separate semiconductor regions 122 , 124 of the semiconductor substrate 120 , respectively.

[0234] A p-type well region 120 - 5 (p-well 120 - 5 ) may be disposed in the second epitaxial p-type layer 120 - 4 by forming a desired doping profile in the p-type semiconductor layer 120 - 4 , for example during epitaxial growth or by performing an implantation step.

[0235] Fig.9e A configuration of a composite pn junction structure 102-1 according to another embodiment is shown. The composite pn junction structure 102-1 includes a pn junction between an n+ region 120-7 and a p-well region 120-5 and another adjacent voltage-dependent capacitance, which in this embodiment may be formed by an inversion charge layer 120-8 at an interface 135 between an oxide layer of semiconductor material and a bulk or epitaxial layer 120-4. For example, the bulk semiconductor material or epitaxial layer 120-4 may be p-doped or intrinsic (i.e., not intentionally doped). One electrode of the voltage-dependent capacitance (corresponding to the cathode) is formed by the inversion charge layer 120-8, which is caused by the presence of fixed oxide charges 136 at or near the semiconductor / oxide interface 135. Directly adjacent to the inversion charge layer 120-8, such as by Fig.9e As indicated by the depletion region 120-9 in FIG. 1 , the volume of semiconductor material is depleted by mobile charges, and the undepleted semiconductor material below the depletion region forms another electrode (corresponding to the anode) of the voltage-dependent capacitor. Fig.9e The depletion region is indicated in FIG. 1 by means of a dashed line 137 schematically representing the boundary of the depletion layer.

[0236] In some embodiments, the doping profile of the p-well 120-5 near the edge and semiconductor / oxide interface 135 is adjusted so that an inversion charge layer 120-8 also exists in this region and an electrical connection between the n+ region 120-7 and the surrounding inversion charge layer 120-8 is established.

[0237] The characteristics of the voltage-dependent capacitance formed due to the electronic inversion charge layer 120-8 can be modeled according to the above formula (A1), which defines the ramp coefficient, zero bias capacitance and junction potential also for such voltage-dependent capacitance. In this regard, the voltage-dependent capacitance formed due to the presence of the inversion charge layer 120-8 as described above is also considered to be a partial pn junction structure J in the context of the composite pn junction structure 102-1, 102-2. 11 , J 12 / J 21, J 22 .

[0238] The effective grading coefficient of the composite pn junction structure 102-1 according to the present embodiment is a combination of the grading coefficient of the pn junction and the grading coefficient of the voltage-dependent capacitance formed due to the presence of the electron inversion charge layer 120-8. The relative contributions of the two grading coefficients can be adjusted by (1) defining the doping profiles of the various regions of the pn junction and the voltage-dependent capacitance 120-8, and (2) the relative areas of the pn junction and the voltage-dependent capacitance 120-8.

[0239] The voltage dependent capacitance 120 - 8 may be surrounded by a channel stop region 120 - 10 that prevents regions outside of the intended region where the voltage dependent capacitance 120 - 8 is formed from contributing to the voltage dependent capacitance.

[0240] The breakdown voltage V bd Determined by the pn junction structure between the n+ region and the P-well region.

[0241] Figure 9f Yet another embodiment of a composite pn junction structure is shown. Fig.9e The voltage dependent capacitance of the embodiment shown in FIG. Figure 9f The inversion layer 120-8 is further extended by the inversion layer 120-8 formed on the vertical sidewalls of the deep isolation trench structure 130. Other details are similar to those of Fig.9e The details described are not repeated here.

[0242] Aspects of the present invention may also include a method of manufacturing a semiconductor device, the semiconductor device including at least a first pair of pn junction structures of a first type and a second pair of pn junction structures of a second type. The method may include a design step of determining a first tapering coefficient for the first type of pn junction structure and a second tapering coefficient for the second type of pn junction structure, wherein the first tapering coefficient is different from the second tapering coefficient, and at least one of the first tapering coefficient and the second tapering coefficient is less than 0.50, wherein the tapering coefficient is determined to suppress spurious third harmonics generated by the semiconductor device.

[0243] Example embodiments may provide a semiconductor device including:

[0244] “n” pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1,…,n}, where the two pn junction structures of the i-th type are connected in anti-series,

[0245] The i-th type pn junction structure is arranged to have an i-th junction gradient coefficient m i .

[0246] At least a first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, wherein and m1<0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m2, wherein and

[0247] The junction taper coefficients m1 and m2 of the first pair and the second pair of n pairs of pn junction structures are adjusted to cause the generation of a spurious third harmonic signal having a signal power level (PH3) of the semiconductor device, which signal power level (PH3) is at least 10 dB lower than the reference signal power level (PH3) of the spurious third harmonic signal obtained for a reference case, wherein in the reference case, the first junction taper coefficient and the second junction taper coefficient m1 and m2 are 0.25.

[0248] According to an exemplary embodiment, the first to nth junction grading coefficients m1 to m n The following ellipse equation is met within a tolerance of ±0.05:

[0249] with

[0250] The parameter a i It is the zero bias capacitance C based on the i-th type pn junction structure. J0i and junction voltage potential V Ji To be determined.

[0251] Another exemplary embodiment may provide a semiconductor device including:

[0252] “n” pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i∈{1,…,n}, where the two pn junction structures of the i-th type are connected in anti-series,

[0253] The pn junction structure of the i-th type is arranged to have an i-th junction gradient coefficient m i

[0254] The first to nth junction ramp coefficients m1 to m n The following ellipse equation is met within a tolerance of ±0.05:

[0255] with

[0256] At least the first pair of the n pairs of pn junction structures is arranged to have a first junction gradient coefficient m1, wherein and m1<0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction gradient coefficient m2, wherein The parameter a i It is the zero bias capacitance C based on the i-th type pn junction structure. J0i and junction voltage potential V Ji To be determined.

[0257] According to an exemplary embodiment, the first pair of n pairs of pn junction structures is arranged to have the first junction grading coefficient m1, where m1≤0.48.

[0258] According to an exemplary embodiment, the second pair of the n pairs of pn junction structures is arranged to have the second junction grading coefficient m2, where m2>0.50.

[0259] According to an exemplary embodiment, the first to nth parameters "a1 to a n Each parameter in " is based on n zero-bias capacitors C J0,1 -C J0,ni And n junction voltage potentials V based on n pairs of pn junction structures J1 -V Jn To determine

[0260] According to an exemplary embodiment, the first to nth parameters "a1 to a n ” meets the following equation:

[0261]

[0262] According to an exemplary embodiment, the first to "nth" junction grading coefficients m1 to m2 are adjusted. n values ​​to produce a third-order intercept point IP3 of at least 50dBm.

[0263] According to an exemplary embodiment, the first to nth junction grading coefficients m1 to m n At least two of them are different.

[0264] According to an exemplary embodiment, for n=2 and C j01 =C j02 , the first type pn junction structure is arranged to have a first junction grading coefficient m1 between 0.56 and 0.62, and wherein the second type pn junction structure is arranged to have a second junction grading coefficient m2 between 0.23 and 0.43.

[0265] According to an exemplary embodiment, for n=2, the first type and the second type pn junction structures are arranged to have a zero bias capacitance C that satisfies the following condition: J0-1 , C J0-2 Ratio:

[0266]

[0267] According to an exemplary embodiment, the i-th type pn junction structure forms an i-th type diode structure having an anode region and a cathode region.

[0268] According to an exemplary embodiment, the semiconductor device may further include a first connection terminal and a second connection terminal, wherein “n” pairs of pn junction structures are connected between the first terminal and the second terminal.

[0269] According to an exemplary embodiment, “n” pairs of pn junction structures are arranged in a stacked configuration in a semiconductor substrate.

[0270] According to an exemplary embodiment, the differently doped semiconductor regions of the pn junction structure extend perpendicularly into the semiconductor substrate relative to a main surface area of ​​the semiconductor substrate, and wherein a major portion of the area of ​​the metallurgical pn junction is a planar pn junction extending parallel to the main surface area of ​​the semiconductor substrate.

[0271] According to an exemplary embodiment, two pn junction structures of an i-th pair of pn junction structures are arranged together in a stacked configuration in a semiconductor substrate.

[0272] According to an exemplary embodiment, one of two pn junction structures of a first pair of n pairs of pn junction structures is arranged in a stacked configuration in a semiconductor substrate having one of two pn junction structures of a second pair of n pairs of pn junction structures.

[0273] According to an exemplary embodiment, a stacked configuration includes an npn structure having a floating base region in a semiconductor substrate.

[0274] At least one pair of the n pairs of pn junction structures is arranged as a pair of two composite pn junction structures, each of the two composite pn junction structures having a first partial pn junction structure and a second partial pn junction structure,

[0275] The first part of the pn junction structure has a first part of the junction gradient coefficient m i1 , and wherein the second part of the pn junction structure has a different gradient coefficient m from the first part of the junction i1 The second part of the gradual change coefficient m i2 ,

[0276] The junction ramp coefficient m of the composite pn junction structure is i It is based on the first part of the slow-changing coefficient and the second part of the slow-changing coefficient m i1 、m i2 combination.

[0277] According to an exemplary embodiment, the first partial pn junction structure and the second partial pn junction structure are arranged in a semiconductor substrate, wherein the combination proportionally depends on an area ratio between active areas of the first partial pn junction structure and the second partial pn junction structure parallel to a first main surface area of ​​the semiconductor substrate.

[0278] According to an exemplary embodiment, first and second partial pn junction structures of the first type pn junction structure and first and second partial pn junction structures of the second type pn junction structure are arranged together in a laterally isolated common region of the semiconductor substrate.

[0279] According to an exemplary embodiment, the first partial pn junction structure is arranged to have a first partial junction grading coefficient m i1 >0.50, and wherein the second portion pn junction structure is arranged to have a second portion junction grading coefficient m between 0.30 and 0.5 i2 .

[0280] According to an exemplary embodiment, the first partial pn junction structure and the second partial pn junction structure extend vertically into the semiconductor substrate in a depth direction relative to a first main surface region of the semiconductor substrate.

[0281] Although some aspects have been described as features in the context of an apparatus, it is clear that such description may also be considered as a description of corresponding features of a method. Although some aspects have been described as features in the context of a method, it is clear that such description may also be considered as a description of corresponding features of the functionality of the apparatus.

[0282] In the foregoing detailed description, it can be seen that, for the purpose of simplifying the present disclosure, various features are combined together in the examples. This method of the present disclosure should not be interpreted as reflecting the intention that the claimed examples require more features than the features explicitly stated in each claim. Instead, as reflected in the attached claims, the subject matter of the invention may be less than all the features in a single disclosed example. Therefore, the attached claims are hereby incorporated into the detailed description, wherein each claim may be independently used as a separate example. Although each claim may be independently used as a separate example, it should be noted that, although the dependent claims may be related to a specific combination with one or more other claims in the claims, other examples may also include a combination of the dependent claims with the subject matter of each other dependent claim, or a combination of each feature with other dependent or independent claims. Such a combination is proposed herein unless it is stated that a specific combination is not intended. In addition, it is intended to also include the features of any other independent claim, even if this claim is not directly subordinate to the independent claim.

[0283] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. The present application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

[0284] Reference numerals list

[0285] 32-42 Different injection doses

[0286] 100 Semiconductor Devices

[0287] 102 The first pair of pn junction structures

[0288] 102-1,102-2 The first and second parallel circuits / composite pn junction structure

[0289] 104 The second pair of pn junction structures

[0290] 106 The third pair of pn junction structures

[0291] 107 First terminal

[0292] 108 Second terminal

[0293] 110 Interconnection

[0294] 120 Semiconductor substrate

[0295] 120a, 120b first and second main surface portions

[0296] 120-1 n-type substrate

[0297] 120-2 p-type semiconductor layer

[0298] 120-3 Buried p-type semiconductor layer

[0299] 120-4 p-type semiconductor layer

[0300] 120-5 p-type well region

[0301] 120-6 p-type well region

[0302] 120-7 n-type contact area

[0303] 120-8 Inversion charge layer

[0304] 120-9 Depletion Region

[0305] 120-10 Channel stop area

[0306] 122 Separated semiconductor regions

[0307] 124 Separated semiconductor regions

[0308] 130 Deep Isolation Trench

[0309] 132 Semiconductor filler

[0310] 134 Pad Oxide

[0311] 135 Semiconductor / Oxide Interface

[0312] 136 Fixed Oxide Charge

[0313] 137 Depletion Layer Boundary

[0314] a1, a2 Shape parameters of the ellipse (=radius r1, r2)

[0315] (A), (B) Higher and lower P-well doping concentrations

[0316] C J01 ,C J02 First and second zero bias capacitors

[0317] C J011 ,C J012 Part 1 and Part 2 Zero Bias Capacitors

[0318] J1, J2 Type I pn junction structure

[0319] J3, J4 Second type pn junction structure

[0320] J 11 , J 21 Type I partial pn junction structure

[0321] J 11 , J 21 Type I partial pn junction structure

[0322] m1,m2 First and second junction ramp coefficients

[0323] m 11 ,m 12 Partial junction ramp coefficient

[0324] S1, S2 The first and second serial circuits

[0325] V bd Breakdown voltage

[0326] V J1 , V J2 The first and second junction voltage potentials

[0327] VJ11 , V J12 The voltage potential of the first and second junctions

[0328] PH3 Signal power level of the spurious third harmonic

Claims

1. A semiconductor device (100), comprising: n pairs of pn junction structures, wherein n is an integer ≥ 2, wherein the i-th pair comprises two pn junction structures of the i-th type, wherein i∈{1,…,n}, wherein the two pn junction structures of the i-th type are connected in anti-series, The pn junction structure of the i-th type is arranged to have an i-th junction gradient coefficient m i , wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction grading coefficient m1, wherein m1≤0.48, and a second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m2, wherein m2≥0.52, and The junction taper coefficients m1 and m2 of the first pair and the second pair of the n pairs of pn junction structures are adjusted to result in the generation of a spurious third harmonic signal having a signal power level (PH3) of the semiconductor device, wherein the signal power level (PH3) is at least 10 dB lower than a reference signal power level (PH3) of the spurious third harmonic signal obtained for a reference case, wherein in the reference case, the first junction taper coefficient and the second junction taper coefficient m1 and m2 are 0.

25.

2. The semiconductor device according to claim 1, wherein the first junction grading coefficient m1 to the nth junction grading coefficient m n The following ellipse equation is met within a tolerance of ±0.05: in The parameter a i is the zero bias capacitance C based on the pn junction structure of the i-th type J0i and junction voltage potential V Ji To be determined. 3 . The semiconductor device according to claim 1 , wherein the first junction gradation coefficient m1=0.33±0.10, and wherein the second junction gradation coefficient m2=0.59±0.

03.

4. A semiconductor device comprising: n pairs of pn junction structures, wherein n is an integer ≥ 2, wherein the i-th pair comprises two pn junction structures of the i-th type, wherein i∈{1,…,n}, wherein the two pn junction structures of the i-th type are connected in anti-series, The pn junction structure of the i-th type is arranged to have an i-th junction gradient coefficient m i , The first junction ramp coefficient m1 to the nth junction ramp coefficient m n The following ellipse equation is met within a tolerance of ±0.05: in wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction grading coefficient m1, wherein m1≤0.48, and a second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m2, wherein m2≥0.52, wherein parameter a i is the zero bias capacitance C based on the pn junction structure of the i-th type J0i and junction voltage potential V Ji To be determined. 5 . The semiconductor device according to claim 4 , wherein the first junction gradation coefficient m1=0.33±0.10, and wherein the second junction gradation coefficient m2=0.59±0.

03.

6. The semiconductor device according to claim 4, wherein the first to nth parameters "a1 to a n Each parameter in the table is based on the zero bias capacitor C J0,1 -C J0,ni and n said junction voltage potentials V based on said n pairs of pn junction structures J1 -V Jn to be sure.

7. The semiconductor device according to claim 6, wherein the first to nth parameters "a1 to a n ” meets the following equation:

8. The semiconductor device according to claim 4, wherein for the first junction grading coefficient m1 to the nth junction grading coefficient m n The value of is adjusted to produce a third-order intercept point IP3 of at least 50dBm.

9. The semiconductor device according to claim 4, wherein the first junction grading coefficient m1 to the nth junction grading coefficient m n The ramp coefficients of at least two junctions are different.

10. The semiconductor device according to claim 4, wherein for n=2 and C j01 =C j02 , the first type pn junction structure is arranged to have the first junction grading coefficient m1 between 0.56 and 0.62, and wherein the second type pn junction structure is arranged to have the second junction grading coefficient m2 between 0.23 and 0.

43.

11. The semiconductor device according to claim 10, wherein for n=2, the first type pn junction structure and the second type pn junction structure are arranged to have a zero bias capacitance C satisfying the following condition: J0-1 , C J0-2 Ratio: 12 . The semiconductor device according to claim 4 , wherein the pn junction structure of the i-th type forms an i-th type diode structure having an anode region and a cathode region. 13 . The semiconductor device according to claim 4 , further comprising a first connection terminal and a second connection terminal, wherein the n pair of pn junction structures are connected between the first connection terminal and the second connection terminal. 14 . The semiconductor device according to claim 13 , wherein the n pairs of pn junction structures are arranged in a stacked configuration in a semiconductor substrate.

15. The semiconductor device of claim 14, wherein the differently doped semiconductor regions of the pn junction structure extend into the semiconductor substrate perpendicularly relative to a main surface region of the semiconductor substrate, and a planar metallurgical pn junction extends parallel to the main surface region of the semiconductor substrate. 16 . The semiconductor device according to claim 15 , wherein the i-th pair of the two pn junction structures are arranged together in a stacked configuration in the semiconductor substrate.

17. A semiconductor device according to claim 15, wherein one pn junction structure of the two pn junction structures of a first pair of pn junction structures in the n pairs of pn junction structures is arranged in a stacked configuration in the semiconductor substrate having one pn junction structure of the two pn junction structures of a second pair of pn junction structures in the n pairs of pn junction structures. 18 . The semiconductor device of claim 16 , wherein the stacked configuration comprises an npn structure having a floating base region in the semiconductor substrate.

19. The semiconductor device according to claim 10, wherein at least one pair of the n pairs of pn junction structures is arranged as a pair of two composite pn junction structures, each of the pair of two composite pn junction structures having a first partial pn junction structure and a second partial pn junction structure, The first part of the pn junction structure has a first part of the junction gradient coefficient m i1 , and wherein the second portion of the pn junction structure has a different grading coefficient m from the first portion of the junction i1 The second part of the gradual change coefficient m i2 , The junction gradient coefficient m of the composite pn junction structure i Based on the first part of the gradual change coefficient and the second part of the gradual change coefficient m i1 、m i2 combination.

20. A semiconductor device according to claim 19, wherein the first partial pn junction structure and the second partial pn junction structure are arranged in a semiconductor substrate, wherein the combination proportionally depends on the area ratio between the active areas of the first partial pn junction structure and the second partial pn junction structure parallel to the first main surface area of ​​the semiconductor substrate.

21. The semiconductor device of claim 20, wherein the first partial pn junction structure and the second partial pn junction structure of the first type pn junction structure and the first partial pn junction structure and the second partial pn junction structure of the second type pn junction structure are arranged together in a laterally isolated common area of ​​the semiconductor substrate.

22. The semiconductor device according to claim 19, wherein the first partial pn junction structure is arranged to have a first partial junction grading coefficient m i1 >0.50, and wherein the second partial pn junction structure is arranged to have a second partial junction grading coefficient m between 0.30 and 0.5 i2 . 23 . The semiconductor device according to claim 20 , wherein the first partial pn junction structure and the second partial pn junction structure extend vertically into the semiconductor substrate in a depth direction relative to a first main surface region of the semiconductor substrate.

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