Display Devices

Abstract

A display device is disclosed. The display device includes a plurality of pixels. Each of the pixels includes: a thin film transistor; a first insulating pattern located on the thin film transistor; a pixel electrode located on the first insulating pattern; and a second insulating pattern covering an edge of the pixel electrode and contacting an edge of the first insulating pattern.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0105309 filed on September 4, 2018 in the Korean Intellectual Property Office; the disclosure of which is incorporated herein in its entirety by reference.

[0002] The technical field relates to a display device and a method of manufacturing the display device. Background Art

[0003] To promote commercialization of display devices, various design and manufacturing methods have been implemented to improve the image quality and / or reliability of the display devices. Summary of the invention

[0004] Embodiments may relate to a method of manufacturing a display device with a shortened manufacturing process time. Embodiments may relate to a display device with minimized undesired deformation.

[0005] According to one or more embodiments, a display device includes a plurality of pixel areas in which a plurality of pixels are arranged, and in each pixel area includes: a thin film transistor; a first insulating pattern located on the thin film transistor; a pixel electrode located on the first insulating pattern; and a second insulating pattern covering an edge of the pixel electrode, and wherein a first gap is located between the first insulating patterns of the plurality of pixels, and a second gap is located between the second insulating patterns of the plurality of pixels.

[0006] The second insulation pattern may cover sides of the first insulation pattern.

[0007] The first insulating pattern may include a via hole partially exposing an electrode of the thin film transistor.

[0008] The second insulation pattern may also cover the via hole in the first insulation pattern.

[0009] At least one insulating layer may also be disposed between the thin film transistor and the first insulating pattern.

[0010] The multiple pixel regions include a first pixel region in which a first pixel is arranged and a second pixel region in which a second pixel is arranged, and a first gap between a first insulating pattern located in the first pixel region and a first insulating pattern located in the second pixel region may be larger than a second gap between a second insulating pattern located in the first pixel region and a second insulating pattern located in the second pixel region.

[0011] According to one or more embodiments, a display device includes: a thin film transistor; a first insulating layer located on the thin film transistor; a pixel electrode located on the first insulating layer; and a second insulating layer covering an edge of the pixel electrode, wherein the first insulating layer includes a plurality of first insulating patterns having different sizes, and the second insulating layer includes a plurality of second insulating patterns having different sizes, and wherein a first gap is located between the first insulating patterns of the first insulating layer, and a second gap is located between the second insulating patterns of the second insulating layer.

[0012] A first gap between the first insulation patterns is larger than a second gap between the second insulation patterns.

[0013] The number of the first insulation patterns of the first insulation layer is the same as the number of the second insulation patterns of the second insulation layer.

[0014] The number of the first insulation patterns of the first insulation layer is different from the number of the second insulation patterns of the second insulation layer.

[0015] Each of some of the plurality of first insulation patterns is shared by at least two pixels, and each of some of the plurality of second insulation patterns is shared by at least two pixels.

[0016] According to one or more embodiments, a method for manufacturing a display device includes: forming a thin film transistor for each of a plurality of pixels; forming a first insulating layer on the thin film transistors of the plurality of pixels; forming a pixel electrode for each of the plurality of pixels on the first insulating layer; and forming a second insulating layer covering edges of the pixel electrodes of the plurality of pixels, and wherein the first insulating layer includes a plurality of first insulating patterns having different sizes, and the second insulating layer includes a plurality of second insulating patterns having different sizes, and wherein a first gap is located between the first insulating patterns of the first insulating layer, and a second gap is located between the second insulating patterns of the second insulating layer.

[0017] The second insulation pattern may cover sides of the first insulation pattern.

[0018] The first insulating pattern may include at least one via hole partially exposing an electrode of the thin film transistor.

[0019] The second insulation pattern may overlap an edge of the at least one via hole of the first insulation pattern.

[0020] The method may further include forming at least one insulating layer between the thin film transistor and the first insulating layer.

[0021] A first gap between the first insulation patterns is larger than a second gap between the second insulation patterns.

[0022] The number of the first insulation patterns of the first insulation layer is the same as the number of the second insulation patterns of the second insulation layer.

[0023] The number of the first insulation patterns of the first insulation layer is different from the number of the second insulation patterns of the second insulation layer.

[0024] Each of some of the plurality of first insulation patterns is shared by at least two pixels, and each of some of the plurality of second insulation patterns is shared by at least two pixels.

[0025] Embodiments may be directed to a display device. The display device may include a plurality of pixels. Each of the pixels may include: a thin film transistor; a first insulating pattern located on the thin film transistor; a pixel electrode located on the first insulating pattern; and a second insulating pattern covering an edge of the pixel electrode and directly contacting an edge of the first insulating pattern. The edge of the first insulating pattern may be located between two portions of the second insulating pattern.

[0026] The second insulation pattern may cover sides of the first insulation pattern.

[0027] The first insulating pattern may include a hole partially exposing an electrode of the thin film transistor.

[0028] The second insulating pattern may overlap an edge of the hole.

[0029] Each of the pixels may further include an insulating layer between the components of the thin film transistor and the first insulating pattern.

[0030] The pixel may include a first pixel and a second pixel. A gap between a first insulating pattern of the first pixel and a first insulating pattern of the second pixel may be larger than a gap between a second insulating pattern of the first pixel and a second insulating pattern of the second pixel.

[0031] The pixel may include a first pixel and a second pixel. The first insulating pattern of the first pixel may be directly connected to the first insulating pattern of the second pixel.

[0032] The pixel may include a first pixel and a second pixel. The second insulating pattern of the first pixel may be directly connected to the second insulating pattern of the second pixel.

[0033] The pixel may include a first pixel, a second pixel, and a third pixel. The first insulating pattern of the third pixel may be directly connected to at least one of the first insulating pattern of the first pixel and the first insulating pattern of the second pixel.

[0034] The pixel may include a first pixel, a second pixel, and a third pixel. The second insulating pattern of the third pixel may be directly connected to at least one of the second insulating pattern of the first pixel and the second insulating pattern of the second pixel.

[0035] Embodiments may be directed to a method of manufacturing a display device. The method may include forming a plurality of pixels. The formation of each of the pixels may include the following steps: forming a thin film transistor; forming a first insulating pattern on the thin film transistor; forming a pixel electrode on the first insulating pattern; and forming a second insulating pattern covering an edge of the pixel electrode and directly contacting an edge of the first insulating pattern. The edge of the first insulating pattern may be located between two portions of the second insulating pattern.

[0036] The second insulation pattern may cover sides of the first insulation pattern.

[0037] The first insulating pattern may include a hole partially exposing an electrode of the thin film transistor.

[0038] The second insulation pattern may overlap edges of the holes of the first insulation pattern.

[0039] The method may further include forming an insulating layer between the components of the thin film transistor and the first insulating pattern in each of the pixels.

[0040] The pixel may include a first pixel and a second pixel. A gap between a first insulating pattern of the first pixel and a first insulating pattern of the second pixel may be larger than a gap between a second insulating pattern of the first pixel and a second insulating pattern of the second pixel.

[0041] The pixel may include a first pixel and a second pixel. The first insulating pattern of the first pixel and the first insulating pattern of the second pixel may be formed of one or more of the same materials and may be directly connected to each other.

[0042] The pixel may include a first pixel and a second pixel. The second insulating pattern of the first pixel region and the second insulating pattern of the second pixel region may be formed of one or more of the same materials and may be directly connected to each other.

[0043] The pixel may include a first pixel, a second pixel, and a third pixel. The first insulating pattern of the second pixel may be directly connected to at least one of the first insulating pattern of the first pixel and the first insulating pattern of the third pixel.

[0044] The pixel may include a first pixel, a second pixel, and a third pixel. The second insulating pattern of the second pixel may be directly connected to at least one of the second insulating pattern of the first pixel and the second insulating pattern of the third pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a diagram (eg, a perspective view) schematically showing a display device according to an embodiment.

[0046] Figure 2is a diagram (eg, a plan view) showing a display panel (provided on a substrate) according to an embodiment.

[0047] Figure 3 is a top view showing an arrangement of pixels in a portion of a display panel according to an embodiment.

[0048] Figure 4 is a plan view showing a portion of a display panel according to an embodiment.

[0049] Figure 5A According to an embodiment, Figure 4 A cross-sectional view taken along the line II' indicated in FIG.

[0050] Figure 5B According to an embodiment, Figure 4 A cross-sectional view taken along the line II' indicated in FIG.

[0051] Figure 6 is a cross-sectional view showing an organic light emitting device of a display apparatus according to an embodiment.

[0052] Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a cross-sectional view schematically illustrating a structure formed in a process of forming a pixel of a display device according to an embodiment.

[0053] Fig.12 A plan view showing a portion of a display device according to an embodiment.

[0054] Fig.13 A plan view showing a portion of a display device according to an embodiment.

[0055] Fig.14 A plan view showing a portion of a display device according to an embodiment. DETAILED DESCRIPTION

[0056] Example embodiments are described with reference to the accompanying drawings, wherein like reference numerals may refer to like elements. Actual embodiments may have different forms and should not be construed as limited to the descriptions set forth herein.

[0057] Although the terms "first", "second" etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish an element from another element. Therefore, without departing from the teaching of one or more embodiments, the first element can be named as the second element. An element is described as a "first" element without requiring or implying the existence of a second element or other elements. The terms "first", "second" etc. can also be used here to distinguish the elements of different categories or groups. For simplicity, the terms "first", "second" etc. can represent "first type (or first group)", "second type (or second group)" etc. respectively.

[0058] In the description, unless an expression used in the singular has an apparently different meaning in the context, the expression may include an expression in the plural.

[0059] Terms such as “includes,” “has,” and “comprising” may indicate the presence of features or components disclosed in the specification, and are not intended to exclude the possibility that one or more other features or components may be added.

[0060] When a first component is referred to as being “on” a second component, the first component may be directly on the second component, or one or more components may exist between the first component and the second component.

[0061] The dimensions of the components in the drawings may be exaggerated for convenience of explanation and do not limit the described embodiments. When a particular embodiment may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the order described.

[0062] The term "corresponding" may be used to define another component that is arranged in the same region as one component.

[0063] In the description with reference to the accompanying drawings, the same reference numerals may be given to the same or corresponding elements, and the description may not be repeated. The term "pattern" may refer to a "member"; the term "pixel region" may refer to a "pixel"; the term "pixel" may refer to a "pixel region".

[0064] Figure 1 is a diagram schematically showing a display device according to an embodiment. Figure 2 is a diagram showing a display panel according to an embodiment. Figure 3 is a diagram showing the Figure 2 A top view of the pixel arrangement in the display panel is shown in FIG.

[0065] Reference Figures 1 to 3, the display device 10 includes a display panel 200 and a packaging member 300 which are sequentially stacked in a third direction.

[0066] The display device 10 may be a liquid crystal display, an organic light emitting display, an electrophoretic display, an electrowetting display, etc. An organic light emitting display device is taken as an example for description.

[0067] The display panel 200 includes a substrate 100 including a display area DA and a peripheral area PA outside the display area DA.

[0068] The display panel 200 may include a plurality of pixels PX arranged on a display area DA of the substrate 100. Various wirings transferring electrical signals to the display area DA may be located in the peripheral area PA of the substrate 100.

[0069] A plurality of pixels PX may be arranged in a first direction (row direction) and a second direction (column direction) in the display panel 200. For example, a plurality of first pixels PX1, a plurality of second pixels PX2, and a plurality of third pixels PX3 may be repeatedly arranged in the first direction and the second direction on the substrate 100 according to a specific pattern.

[0070] The pixel PX may include a display device and a pixel circuit electrically connected to the display device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The display device may be an organic light emitting device.

[0071] The first pixel PX1 may be arranged in a first pixel region of the substrate 100 , the second pixel PX2 may be arranged in a second pixel region of the substrate 100 , and the third pixel PX3 may be arranged in a third pixel region of the substrate 100 .

[0072] The area of ​​the second pixel PX2 may be smaller than the areas of the first pixel PX1 and the third pixel PX3 adjacent to the second pixel PX2. The second pixel PX2 may be a blue pixel B emitting blue light. The second pixels PX2 are arranged on the first imaginary straight line IL1 spaced apart from each other. In a plan view of the display device, the second pixel PX2 may be substantially a polygon such as a quadrilateral or an octagon, a circle or an ellipse, etc., and the basic polygon may have rounded vertices.

[0073] A pair of third pixels PX3 is located at a pair of first vertices P1 facing each other diagonally in an imaginary quadrilateral IS having the second pixel PX2 as a center point / part, and a pair of first pixels PX1 is located at a pair of second vertices P2 facing each other diagonally in the imaginary quadrilateral IS. The imaginary quadrilateral IS may be a square.

[0074] The first pixel PX1 is separated from the corresponding second pixel PX2 and the corresponding third pixel PX3, and is located at the second vertex P2 adjacent to the first vertex P1 of the corresponding imaginary quadrilateral IS. The area of ​​the first pixel PX1 may be larger than the area of ​​the second pixel PX2 adjacent to the first pixel PX1. The first pixel PX1 may be a red pixel R emitting red light. In a plan view of the display device 10, the first pixel PX1 may be substantially a polygon such as a quadrilateral or an octagon, a circle, an ellipse, etc., and the basic polygon may have rounded vertices.

[0075] The third pixel PX3 is separated from the corresponding first pixel PX1 and the corresponding second pixel PX2, and is located at the first vertex P1 of the imaginary quadrilateral IS. The area of ​​the third pixel PX3 may be larger than the area of ​​the second pixel PX2 adjacent to the third pixel PX3. In addition, the area of ​​the third pixel PX3 may be different from the area of ​​the first pixel PX1; for example, the area of ​​the third pixel PX3 may be larger than the area of ​​the first pixel PX1. In an embodiment, the area of ​​the third pixel PX3 may be equal to the area of ​​the first pixel PX1. The third pixel PX3 may be a green pixel G that emits green light. In the plan view of the display device 10, the third pixel PX3 may be substantially a polygon such as a quadrilateral or an octagon, a circle or an ellipse, etc., and the basic polygon may have rounded vertices.

[0076] The first pixels PX1 and the third pixels PX3 are alternately arranged on the second imaginary straight line IL2. The two third pixels PX3 at the two first vertices P1 and the two first pixels PX1 at the two second vertices P2 surround the corresponding second pixels PX2.

[0077] The plurality of pixels PX may be repeatedly arranged in the first direction in the order of the first pixel PX1 , the second pixel PX2 , the third pixel PX3 , and the second pixel PX2 in each row.

[0078] In an organic light emitting device, the efficiency of a blue pixel B is relatively low. Therefore, in an embodiment, the efficiency of a display device may be improved by arranging two blue pixels B with respect to one red pixel R and one green pixel G.

[0079] Figure 3 The pixel PX shown in FIG. 1 may have an emission unit. The emission unit may be a display device (organic light emitting device) of the pixel PX or an emission layer of the display device. The aperture ratio of the pixel PX may depend on the area of ​​the emission unit.

[0080] The packaging member 300 may include at least one film stacked on the display panel 200. In an embodiment, the packaging member 300 may include a plurality of films to prevent moisture and / or air from penetrating into the display panel 200.

[0081] The encapsulation member 300 may cover the display panel 200. The encapsulation member 300 may include at least one inorganic layer including an inorganic material and at least one organic layer including an organic material. In some embodiments, the encapsulation member 300 may have a structure in which a first inorganic layer, an organic layer, and a second inorganic layer are sequentially stacked.

[0082] Although not shown, various functional layers such as a polarizing layer for reducing reflection of external light, a black matrix, a color filter, and / or a touch screen layer including a touch electrode may be provided at the upper region of the packaging member 300. In addition, the window may be combined to the upper region of the packaging member 300 using a pressure sensitive adhesive (PSA).

[0083] Figure 4 is a diagram showing the Figure 3 2 is a partial plan view of a portion of a display panel 200 shown in FIG. Figure 5A According to an embodiment, Figure 4 A cross-sectional view taken along line II' shown in FIG. Figure 5B According to an embodiment, Figure 4 A cross-sectional view taken along line II' shown in FIG.

[0084] In each pixel PX (or pixel region) in the display panel 200 according to the embodiment, the organic insulating layer under the pixel electrode and the organic insulating layer on the pixel electrode may be provided in the form of an island in the pixel unit.

[0085] exist Figure 4 , Figure 5A and Figure 5B , for convenience of explanation, the first pixel PX1 and the second pixel PX2 are described as examples, and at least some of the descriptions may be similarly applied to the third pixel PX3.

[0086] Reference Figure 4 , Figure 5A and Figure 5B The first pixel PX1 may include at least one first thin film transistor TFTa and a first organic light emitting device OLEDa (eg, Figure 6 The first organic light emitting device OLEDa may include a first pixel electrode 301a, a counter electrode (similar to Figure 6 305a) and an emission layer (similar to Figure 6 303a shown in FIG. 303b). The second pixel PX2 may include at least one second thin film transistor TFTb and a second organic light emitting device OLEDb (eg, Figure 6The second organic light emitting device OLEDb may include a second pixel electrode 301b, a counter electrode opposite to the second pixel electrode 301b, and an emission layer located between the second pixel electrode 301b and the counter electrode. Figure 4 , Figure 5A and Figure 5B In the figure, for convenience of explanation, a first pixel electrode 301a of a first organic light emitting device OLEDa, a first thin film transistor TFTa, a second pixel electrode 301b of a second organic light emitting device OLEDb, and a second thin film transistor TFTb are shown.

[0087] The first organic light emitting device OLEDa and the second organic light emitting device OLEDb may be arranged on at least one insulating layer IL covering the first thin film transistor TFTa and the second thin film transistor TFTb, and may correspond to the first thin film transistor TFTa and the second thin film transistor TFTb, respectively. The insulating layer IL may cover the pixel circuit and planarize the pixel circuit. In an embodiment, the uppermost layer of the insulating layer IL may be Figure 5A The second insulating layer 112 is shown in FIG. In an embodiment, the uppermost layer of the insulating layer IL may be Figure 5B The fifth insulating layer 115 is shown in FIG. The fifth insulating layer 115 may be disposed between the second insulating layer 112 and the first insulating patterns 113Pa and 113Pb.

[0088] The first thin film transistor TFTa may include a first active layer 201a disposed on the buffer layer 110, a first gate electrode 202a insulated from the first active layer 201a and overlapping a portion of the first active layer 201a, a first source electrode 203a, and a first drain electrode 204a. One of the first source electrode 203a and the first drain electrode 204a (e.g., the first drain electrode 204a) may be electrically connected to the first pixel electrode 301a. The first source electrode 203a and the first drain electrode 204a may be electrically connected to a source region and a drain region in the first active layer 201a, respectively.

[0089] The second thin film transistor TFTb may include a second active layer 201b disposed on the buffer layer 110, a second gate electrode 202b insulated from the second active layer 201b and overlapping a portion of the second active layer 201b, a second source electrode 203b, and a second drain electrode 204b. One of the second source electrode 203b and the second drain electrode 204b (e.g., the second drain electrode 204b) may be electrically connected to the second pixel electrode 301b. The second source electrode 203b and the second drain electrode 204b may be electrically connected to a source region and a drain region in the second active layer 201b, respectively.

[0090] The first insulating layer 111 may be disposed as a gate insulating layer between the first active layer 201a and the first gate electrode 202a and between the second active layer 201b and the second gate electrode 202b. The second insulating layer 112 may be disposed as an interlayer insulating layer between the first gate electrode 202a and each of the first source electrode 203a and the first drain electrode 204a and between the second gate electrode 202b and each of the second source electrode 203b and the second drain electrode 204b.

[0091] According to the thin film transistor TFT (such as Figure 7 100 is a top gate type in which the gate electrode is arranged above the active layer and the substrate 100 is at the bottom. In an embodiment, the thin film transistor TFT may be a bottom gate type in which the gate electrode is arranged below the active layer and the substrate 100 is at the top.

[0092] The buffer layer 110, the first insulating layer 111, and the second insulating layer 112 may extend not only to the display area DA but also to a portion of the non-display area (i.e., the peripheral area PA) around the display area DA. According to an embodiment, the buffer layer 110, the first insulating layer 111, and the second insulating layer 112 may be arranged on an area other than the outermost edge area of ​​the substrate 100.

[0093] The first insulating pattern 113Pa and 113Pb may be disposed on the first thin film transistor TFTa and the second thin film transistor TFTb. The first insulating pattern 113Pa may cover and / or overlap the first thin film transistor TFTa, and the first insulating pattern 113Pb may cover and / or overlap the second thin film transistor TFTb.

[0094] Reference Figure 5B When the fifth insulating layer 115 is arranged on the second insulating layer 112, the fifth insulating layer 115 may cover the first thin film transistor TFTa and the second thin film transistor TFTb, the first insulating pattern 113Pa may cover at least a portion of the first thin film transistor TFTa and / or overlap with at least a portion of the first thin film transistor TFTa, and the first insulating pattern 113Pb may cover at least a portion of the second thin film transistor TFTb and / or overlap with at least a portion of the second thin film transistor TFTb.

[0095] The first insulating patterns 113Pa and 113Pb may be arranged in the form of an island. When viewed from the top, the first insulating patterns 113Pa and 113Pb may have shapes similar to the shapes of the corresponding first pixel electrode 301a and the corresponding second pixel electrode 301b, respectively. A via hole 123a partially exposing one of the first source electrode 203a and the first drain electrode 204a in the first thin film transistor TFTa may be provided in the first insulating pattern 113Pa. A via hole 123b partially exposing one of the second source electrode 203b and the second drain electrode 204b in the second thin film transistor TFTb may be provided in the first insulating pattern 113Pb.

[0096] Each of the first insulating patterns 113Pa and 113Pb may be a single layer or multi-layer structure including an organic material. In an embodiment, each of the first insulating patterns 113Pa and 113Pb may be a laminate including at least one inorganic insulating layer and at least one organic insulating layer.

[0097] The first pixel electrode 301a of the first pixel PX1 may be arranged on the first insulating pattern 113Pa in the form of an island, and the second pixel electrode 301b of the second pixel PX2 may be arranged on the first insulating pattern 113Pb in the form of an island. The first pixel electrode 301a may be electrically connected to the first thin film transistor TFTa through the via hole 123a. The second pixel electrode 301b may be electrically connected to the second thin film transistor TFTb through the via hole 123b.

[0098] exist Figure 4 , Figure 5A and Figure 5B In the embodiment, the pixel electrode is electrically connected to the drain electrode. In the embodiment, the pixel electrode can be electrically connected to the source electrode.

[0099] The edge of the first pixel electrode 301a may be covered by the second insulating pattern 114Pa, and the edge of the second pixel electrode 301b may be covered by the second insulating pattern 114Pb. The second insulating patterns 114Pa and 114Pb may be arranged in the form of an island. When viewed from the top, the second insulating patterns 114Pa and 114Pb may have shapes similar to the shapes of the corresponding first pixel electrode 301a and the corresponding second pixel electrode 301b, respectively. The second insulating pattern 114Pa may cover the side surface of the first insulating pattern 113Pa not covered by the first pixel electrode 301a and the top surface portion of the first insulating pattern 113Pa. The second insulating pattern 114Pb may cover the side surface of the first insulating pattern 113Pb not covered by the second pixel electrode 301b and the top surface portion of the first insulating pattern 113Pb. The second insulating pattern 114Pa may cover the area of ​​the first pixel electrode 301a corresponding to the via 123a and / or overlap with the area of ​​the first pixel electrode 301a. In other words, the second insulating pattern 114Pa may overlap the edge of the via hole 123a. The second insulating pattern 114Pb may cover the region of the second pixel electrode 301b corresponding to the via hole 123b and / or overlap the region of the second pixel electrode 301b. In other words, the second insulating pattern 114Pb may overlap the edge of the via hole 123b.

[0100] Each of the second insulating patterns 114Pa and 114Pb may be a single layer or multi-layer structure including an organic material. In an embodiment, each of the second insulating patterns 114Pa and 114Pb may be a laminate including at least one inorganic insulating layer and at least one organic insulating layer.

[0101] Since the first insulating pattern 113Pa of the first pixel PX1 and the first insulating pattern 113Pb of the second pixel PX2 are respectively arranged in the form of independent islands, the first opening OP1 may be formed between the first insulating patterns 113Pa and 113Pb.

[0102] Since the second insulating pattern 114Pa of the first pixel PX1 and the second insulating pattern 114Pb of the second pixel PX2 are respectively arranged in the form of independent islands, the second opening OP2 may be formed between the second insulating patterns 114Pa and 114Pb.

[0103] Due to the first opening OP1 and the second opening OP2, a gap may be formed between the structure of the first pixel PX1 and the structure of the second pixel PX2. The first gap GAP1 formed due to the first opening OP1 may be larger than the second gap GAP2 formed due to the second opening OP2.

[0104] The first pixel electrode 301a may include a first region 311a on which an emission layer is arranged and a second region 321a around the first region 311a. The first region 311a in the first pixel electrode 301a may have a shape such as a basic polygon such as a rectangle or an octagon, a circle or an ellipse, etc. The emission layer (not shown) may be arranged on the first region 311a of the first pixel electrode 301a, and the counter electrode (not shown) may be formed on the emission layer. The form of the first pixel PX1 may be determined according to the form of the first region 311a of the first pixel electrode 301a. The second region 321a of the first pixel electrode 301a is an area covered by the second insulating pattern 114Pa, and a portion of the second region 321a may be located above / on the via 123a. The direction along which the second region 321a extends from the first region 311a may be constructed according to an embodiment.

[0105] Similarly, the second pixel electrode 301b may include a first region 311b on which the emission layer is arranged and a second region 321b around the first region 311b. The first region 311b of the second pixel electrode 301b may have a shape such as a basic polygon, a circle, and an ellipse, such as a rectangle or an octagon. The emission layer (not shown) is arranged on the first region 311b of the second pixel electrode 301b, and the counter electrode (not shown) may be formed on the emission layer. The form of the second pixel PX2 may be determined according to the form of the first region 311b of the second pixel electrode 301b. The second region 321b of the second pixel electrode 301b is an area covered by the second insulating pattern 114Pb, and a portion of the second region 321b may be located above / on the via 123b.

[0106] The direction in which the protrusions in the second regions 321a and 321b extend from the first regions 311a and 311b may be configured according to an embodiment. Figure 4 , when viewed from the top, the protrusions in the second regions 321a and 321b extend in the first direction from one side of the first region 311a and one side of the first region 311b, respectively. In an embodiment, the second regions 321a and 321b may extend in the second direction or diagonally from one side of the first region 311a and one side of the first region 311b, respectively. The structure of the second regions 321a and 321b may be configured according to pixel arrangement and via arrangement, etc. The area of ​​the second regions 321a and 321b may be different in different pixels according to pixel arrangement and via arrangement, etc.

[0107] Figure 6 is a cross-sectional view showing an organic light emitting device according to an embodiment.

[0108] Reference Figure 6, the intermediate layers 303a and 303b, each including an emission layer, may be arranged at the exposed upper surface portion of the first pixel electrode 301a exposed by the second insulating pattern 114Pa and the exposed upper surface portion of the second pixel electrode 301b exposed by the second insulating pattern 114Pb, respectively. Each of the intermediate layers 303a and 303b may include at least one functional layer. Some functional layers of the intermediate layers 303a and 303b may cover the upper surface of the first pixel electrode 301a, the upper surface of the second pixel electrode 301b, and the upper surface and / or side surface of the second insulating patterns 114Pa and 114Pb. Some functional layers of the intermediate layers 303a and 303b may cover the upper surface of the first pixel electrode 301a, the upper surface of the second pixel electrode 301b, the upper surface and / or side surface of the second insulating patterns 114Pa and 114Pb, and the upper surface portion of the second insulating layer 112 exposed via the second opening OP2. The counter electrodes 305a and 305b may be disposed at the upper portions of the intermediate layers 303a and 303b, respectively. The counter electrode 305a of the first pixel PX1 and the counter electrode 305b of the second pixel PX2 may be integrated with each other (i.e., directly connected to each other). The counter electrodes 305a and 305b may be integrally formed on the entire surface of the substrate 100, and may cover the upper and side surfaces of the first insulating patterns 114Pa and 114Pb and the upper surface portion of the second insulating layer 112 exposed via the second opening OP2.

[0109] Figures 7 to 11 It is schematically shown in the embodiment that the Figure 3 2 is a cross-sectional view of a structure formed in a process of manufacturing a pixel shown in FIG. The pixel PX may be one of a first pixel PX1, a second pixel PX2, and a third pixel PX3.

[0110] Reference Figure 7 , a buffer layer 110 is formed on the substrate 100 , and a thin film transistor TFT of the pixel PX may be formed on the buffer layer 110 .

[0111] The substrate 100 may include a glass material, a ceramic material, a metal material, a plastic material, or a flexible or bendable material. The substrate 100 may include a material having high heat resistance and durability, and may have a curved surface; the material may include one or more of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, polyetherimide, polyethersulfone, and polyimide, etc. In an embodiment, the substrate 100 may include one or more flexible materials.

[0112] The substrate 100 may have a single layer structure or a multilayer structure including one or more of the above materials, and the multilayer structure may also include an inorganic material. In some embodiments, the substrate 100 may have a structure including one organic material layer, one inorganic material layer, and another organic material layer.

[0113] The buffer layer 110 may include at least one of an inorganic layer and an organic layer. For example, the buffer layer 110 may prevent impure elements from penetrating through the substrate 100, may planarize the surface of the substrate 100, and may include a layer containing a silicon nitride (SiN x ) and / or silicon oxide (SiO x ) of an inorganic material. In an embodiment, the buffer layer 110 may not be necessary.

[0114] An active layer 201 of a thin film transistor TFT may be formed on the buffer layer 110. The active layer 201 may be formed by patterning a semiconductor layer previously formed on the buffer layer 110. For example, the semiconductor layer may include an inorganic semiconductor material such as amorphous silicon or crystalline silicon. As another example, the semiconductor layer may include an oxide semiconductor or an organic semiconductor material.

[0115] The first insulating layer 111 may be disposed on the active layer 201. The first insulating layer 111 may be an inorganic insulating layer. The first insulating layer 111 may include a single layer or a multi-layer structure having at least one insulating layer including silicon dioxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum pentoxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), one or more of barium strontium titanate (BST) and lead zirconate titanate (PZT) or made of one or more of the foregoing substances.

[0116] The gate electrode 202 may be formed on the first insulating layer 111 and may overlap the channel region of the active layer 201. The gate electrode 202 may include one or more conductive materials. The gate electrode 202 may include a single layer or multilayer structure including at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0117] A second insulating layer 112 may be disposed on the gate electrode 202 , and a source electrode 203 and a drain electrode 204 may be formed on the second insulating layer 112 .

[0118] The second insulating layer 112 may be an inorganic insulating layer. The second insulating layer 112 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 、ZrO 2 , BST and PZT. In an embodiment, the second insulating layer 112 may include an organic insulating layer. A contact hole CH exposing a portion of the source region and the drain region of the active layer 201 may be formed in the second insulating layer 112 and the first insulating layer 111.

[0119] The source electrode 203 and the drain electrode 204 may contact the source region and the drain region of the active layer 201 via the contact hole CH, respectively. The source electrode 203 and the drain electrode 204 may include one or more conductive materials. Each of the source electrode 203 and the drain electrode 204 may include a single layer or a multilayer structure including at least one of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu.

[0120] A third insulating layer 113 may be disposed on the source electrode 203 and the drain electrode 204. The third insulating layer 113 may include an organic insulating layer of a single layer or a multilayer structure. The third insulating layer 113 may include at least one of a general polymer (e.g., poly(methacrylate) (PMMA), polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend. For example, the third insulating layer 113 may include at least one of polyimide, polyamide, and acrylic resin, etc.

[0121] Reference Figure 8 By patterning the third insulating layer 113, a partially exposed source electrode 203 and drain electrode 204 (eg, Figure 8 The third insulating layer 113 may be formed into a plurality of first insulating patterns 113P separated by the first opening OP1 for different pixels. The first insulating pattern 113P may overlap the thin film transistor TFT.

[0122] In an embodiment, Figure 5B As shown in , before forming the third insulating layer 113, a fifth insulating layer 115 may be formed on (the entire surface of) the substrate 100. A first insulating pattern 113P may be arranged on the fifth insulating layer 115. A via 123 may be formed in the fifth insulating layer 115 and the third insulating layer 113, and the upper surface of the fifth insulating layer 115 may be exposed through the first opening OP1. The fifth insulating layer 115 may include an inorganic insulating layer and / or an organic insulating layer of a single-layer or multi-layer structure.

[0123] Reference Fig. 9 , a pixel electrode 301 may be formed on the first insulating pattern 113P. The pixel electrode 301 may directly contact one of the source electrode 203 and the drain electrode 204 through the via hole 123 (eg, Fig. 9 The drain electrode 204 in FIG.

[0124] Reference Fig.10 , the fourth insulating layer 114 may be formed on (the entire surface of) the substrate 100 and may cover the pixel electrode 301. The fourth insulating layer 114 may include an organic insulating layer of a single layer or multilayer structure. The fourth insulating layer 114 may include at least one of a general polymer (e.g., PMMA, PS), a polymer derivative with a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend. For example, the fourth insulating layer 114 may include at least one of polyimide, polyamide, and acrylic resin, etc. In an embodiment, the fourth insulating layer 114 may be an inorganic layer or a stacked layer including at least one inorganic insulating layer and at least one organic insulating layer.

[0125] Reference Fig.11 By patterning the fourth insulating layer 114, a third opening OP3 partially exposing the pixel electrode 301 and a second opening OP2 exposing a portion of the top surface of the second insulating layer 112 may be formed. The fourth insulating layer 114 may be patterned to form a plurality of second insulating patterns 114P for different pixels. The second insulating pattern 114P may function as a pixel defining layer.

[0126] Next, an intermediate layer including an emission layer may be disposed in the third opening OP3 , and a counter electrode at an upper surface of the intermediate layer may be disposed on the entire surface of the substrate 100 .

[0127] In an embodiment, the first insulating pattern 113P and the second insulating pattern 114P are disposed in each pixel of the display device.

[0128] Figure 12 to Figure 14 is a top view of a display device according to an embodiment.

[0129] Reference Figure 12 to Figure 14 , a first insulating pattern 113P is formed on the second insulating layer 112 in at least one pixel, one or more pixel electrodes 301 may be formed on the first insulating pattern 113P in one or more pixels, and a second insulating pattern 114P may be formed on one or more pixel electrodes 301 in the at least one pixel. For some pixels, the first insulating pattern 113P may have a single structure corresponding to at least two pixels, and the at least two pixels may share the first insulating pattern 113P, and the second insulating pattern 114P may have a single structure corresponding to the at least two pixels, and the at least two pixels may share the second insulating pattern 114P. That is, each of some of the plurality of first insulating patterns 113P may be shared by at least two pixels. The sizes of the plurality of first insulating patterns 113P may be different from each other. Moreover, each of some of the plurality of second insulating patterns 114P may be shared by at least two pixels. The sizes of the plurality of second insulating patterns 114P may be different from each other.

[0130] Fig.12 An embodiment in which the first insulating pattern 113P and the second insulating pattern 114P correspond to the same number of pixels is shown. That is, the number of the first insulating patterns 113P of the third insulating layer 113 is the same as the number of the second insulating patterns 114P of the fourth insulating layer 114. The first insulating pattern 113P and the second insulating pattern 114P may each correspond to one pixel, two pixels, or four pixels and may be arranged / included in one pixel, two pixels, or four pixels.

[0131] Fig.13 and Fig.14 Each shows an embodiment in which the first insulating pattern 113P and the second insulating pattern 114P correspond to different numbers of pixels. That is, the number of the first insulating patterns 113P of the third insulating layer 113 is different from the number of the second insulating patterns 114P of the fourth insulating layer 114. Fig.13 An embodiment is shown in which the first insulating pattern 113P corresponds to one pixel, two pixels, or four pixels and is arranged / included in the one pixel, two pixels, or four pixels and in which the second insulating pattern 114P corresponds to eight pixels and is arranged / included in the eight pixels. Fig.14 An embodiment is shown in which the first insulating pattern 113P corresponds to eight pixels and is arranged / included in the eight pixels and in which the second insulating pattern 114P corresponds to one pixel, two pixels, or four pixels and is arranged / included in one pixel, two pixels, or four pixels. Fig.14 In the embodiment shown in FIG. 1 , top surfaces of the first insulation patterns 113P may be partially exposed between the second insulation patterns 114P.

[0132] Figure 12 to Figure 14 The first insulating pattern 113P and the second insulating pattern 114P shown in the figure are examples, and the number of pixels sharing the first insulating pattern 113P and the number of pixels sharing the second insulating pattern 114P can be determined according to the manufacturing process and type of the display device. For example, in the display panel 200, the first insulating pattern 113P can be formed in one pixel, and the integrated second insulating pattern 114P can be formed in two pixels and shared by the two pixels. In an embodiment, in the display panel 200, the integrated first insulating pattern 113P can be formed in four pixels and shared by the four pixels, and the integrated second insulating pattern 114P can be formed in two pixels and shared by the two pixels.

[0133] If an organic insulating layer including an organic material on a thin film transistor is formed on the entire surface of a substrate, a curing time and the number of exhaust sources for the organic insulating layer may increase in a manufacturing process. As a result, undesirable stress caused by stacked layers after the organic insulating layer may increase, and / or a large amount of heat treatment may be required.

[0134] According to an embodiment, an organic insulating layer (e.g., an organic insulating layer having a via hole and an organic insulating layer functioning as a pixel defining layer) on a thin film transistor is provided in the form of an island. Advantageously, the manufacturing process time can be minimized due to the reduction in the curing time of the organic insulating layer, the exhaust volume can be minimized, and deformation such as warping of the display device can be prevented due to stress dispersion.

[0135] According to the embodiments, the display device may be manufactured with less manufacturing process time and may have minimized undesired deformation.

[0136] The described embodiments are intended to be illustrative rather than limiting. Features or aspects described in one embodiment may be applicable to other embodiments.

[0137] Although the embodiments have been described with reference to the accompanying drawings, various changes in form and details may be made without departing from the scope defined by the claims.

Claims

1. A display device, comprising: A plurality of pixels, wherein each of the plurality of pixels comprises: a thin film transistor; a first insulating pattern located on the thin film transistor; a pixel electrode located on the first insulating pattern; and a second insulating pattern covering an edge of the pixel electrode, Wherein, the second insulating pattern covers the side surface of the first insulating pattern, wherein each of the first insulating pattern and the second insulating pattern of each of the plurality of pixels is arranged in the form of an island and is spaced apart from the first insulating pattern of other pixels and the second insulating pattern of other pixels in a plan view and a cross-sectional view, and the second insulating pattern of each of the plurality of pixels completely surrounds the first insulating pattern of the pixel in a plan view, and The first gap is located between the first insulating patterns of the plurality of pixels, and the second gap is located between the second insulating patterns of the plurality of pixels.

2. The display device according to claim 1, in, The first insulating pattern includes a hole partially exposing an electrode of the thin film transistor.

3. The display device according to claim 2, in, The second insulating pattern overlaps an edge of the hole.

4. The display device according to claim 1, wherein: Each of the plurality of pixels further comprises: An insulating layer is located between the components of the thin film transistor and the first insulating pattern.

5. The display device according to claim 1, in, The plurality of pixels include a first pixel and a second pixel, and The first gap between the first insulating pattern of the first pixel and the first insulating pattern of the second pixel is larger than the second gap between the second insulating pattern of the first pixel and the second insulating pattern of the second pixel.

6. A display device, comprising: Thin film transistors; A first insulating layer, located on the thin film transistor; A pixel electrode, located on the first insulating layer; as well as a second insulating layer, covering the edge of the pixel electrode, wherein the first insulating layer includes a plurality of first insulating patterns having different sizes, and the second insulating layer includes a plurality of second insulating patterns having different sizes, wherein each of the plurality of second insulating patterns covers a side surface of each of the plurality of first insulating patterns, wherein each of the plurality of first insulation patterns and the plurality of second insulation patterns is arranged in the form of an island and is spaced apart from other first insulation patterns and other second insulation patterns in a plan view and a cross-sectional view, wherein the first gap is located between the first insulating patterns of the first insulating layer, and the second gap is located between the second insulating patterns of the second insulating layer, and wherein each of some of the plurality of first insulating patterns corresponds to a single pixel, each of the other of the plurality of first insulating patterns is shared by at least two pixels, and each of some of the plurality of second insulating patterns corresponds to a single pixel, each of the other of the plurality of second insulating patterns is shared by at least two pixels.

7. The display device according to claim 6, in, The first gap between the first insulation patterns is larger than the second gap between the second insulation patterns.

8. The display device according to claim 6, in, The number of the first insulating patterns of the first insulating layer is the same as the number of the second insulating patterns of the second insulating layer.

9. The display device according to claim 6, The number of the first insulating patterns of the first insulating layer is different from the number of the second insulating patterns of the second insulating layer.

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