Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. A gate structure is formed between a source region and a drain region in a substrate to form a transistor. An adjustment region is then formed at the bottom of the gate structure. The doping concentration of the channel of the transistor is increased to form a potential barrier in the channel, thereby blocking the passage of leakage current and reducing the channel leakage current. At the same time, since the potential barrier is not very high, a relatively low voltage can be applied to the gate structure to cross the potential barrier, which will basically not affect other electrical characteristics of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Dynamic random access memory (DRAM) generally uses buried-gate transistors. However, currently, in the manufacturing process of DRAM, there is no method that can effectively reduce the channel leakage current of buried-gate transistors. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for forming the same, which can conveniently and effectively reduce the channel leakage current of a transistor without affecting other electrical characteristics of the semiconductor device.

[0004] In order to achieve the above object, the present invention provides a semiconductor device, comprising:

[0005] A substrate having an active region and a drain region formed therein;

[0006] a gate structure formed in the substrate between the source region and the drain region to form a transistor; and,

[0007] An adjustment region is located in the substrate below the gate structure to increase the doping concentration of the channel of the transistor.

[0008] Optionally, the drain region and the source region extend from the surface of the substrate to a first depth position within the substrate, and the gate structure extends from the surface of the substrate to a second depth position within the substrate, and the second depth position is further sunken than the first depth position, so that the area from the source region to the drain region along the side wall and bottom wall of the gate structure constitutes the channel of the transistor, and the adjustment region is located between the second depth position and a third depth position of the substrate, and the third depth position is further sunken than the second depth position.

[0009] Optionally, a well region is also formed in the substrate, and the adjustment region is located in the well region.

[0010] Optionally, a lateral width of the adjustment region is smaller than a lateral width of the gate structure.

[0011] Optionally, the lateral width of the adjustment zone is between 3 nm and 5 nm.

[0012] Optionally, when the transistor is an N-type transistor, the adjustment region is P-type doped to increase the doping concentration of the channel of the transistor.

[0013] Optionally, the conductive ions doped in the adjustment region include boron ions.

[0014] Optionally, the concentration of the conductive ions doped in the adjustment region is between 1E12 atoms / cm 2 ~1E13atoms / cm 2 .

[0015] The present invention also provides a method for forming a semiconductor device, comprising:

[0016] Providing a substrate, wherein an active region and a drain region are formed in the substrate;

[0017] forming a gate trench in the substrate between the source region and the drain region;

[0018] forming a mask layer on the sidewalls and a portion of the bottom wall of the gate trench, and performing ion implantation on the substrate at the bottom of the gate trench using the mask layer as a mask to form an adjustment region below the gate trench; and,

[0019] The mask layer is removed and a gate structure is formed in the gate trench.

[0020] Optionally, the energy of ion implantation into the substrate at the bottom of the gate trench is between 2keV and 10keV.

[0021] Optionally, the step of forming the mask layer includes:

[0022] forming a mask material layer on the substrate, wherein the mask material layer covers the sidewalls and bottom wall of the gate trench and extends to cover the substrate; and,

[0023] Etching is performed to remove the mask material layer on the substrate and a portion of the mask material layer on the bottom wall of the gate trench, and the mask material layer on the sidewall of the gate trench and a portion of the mask material layer on the bottom wall of the sidewall of the gate trench are retained to form the mask layer.

[0024] Optionally, the thickness of the mask layer is between 5 nm and 7 nm.

[0025] Optionally, the step of forming the gate structure includes:

[0026] forming a gate oxide layer on the sidewalls and bottom wall of the gate trench;

[0027] Performing a rapid thermal annealing process on the gate oxide layer;

[0028] A gate electrode layer and an insulating layer covering the gate electrode layer are sequentially filled in the gate trench, and the gate oxide layer, the gate electrode layer and the insulating layer constitute the gate structure.

[0029] Optionally, the gate oxide layer is formed by a thermal oxidation process at a temperature of 800 degrees Celsius to 1000 degrees Celsius, and the thickness of the gate oxide layer is between 3 nm and 4 nm.

[0030] Optionally, a rapid thermal annealing process is performed on the gate oxide layer under the protection of an inert gas, and the temperature of the rapid thermal annealing process is between 500 degrees Celsius and 700 degrees Celsius.

[0031] In the semiconductor device and the method for forming the same provided by the present invention, a gate structure is formed between a source region and a drain region in a substrate to form a transistor, and then an adjustment region is formed at the bottom of the gate structure. By increasing the doping concentration of the channel of the transistor to form a potential barrier in the channel, the passage of leakage current is blocked, thereby reducing the channel leakage current. At the same time, since the potential barrier is not very high, a lower voltage can be applied to the gate structure to cross the potential barrier, which basically does not affect other electrical characteristics of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flow chart of a method for forming a semiconductor device provided by an embodiment of the present invention;

[0033] Figure 2-Figure 6 A schematic cross-sectional view of a semiconductor structure formed by a method for forming a semiconductor device provided by an embodiment of the present invention;

[0034] In the figure, the reference numerals are:

[0035] 1-substrate; 11-well region; 12-deep N-well; 111-source region; 112-drain region; 113-adjustment region; 13-trench isolation structure;

[0036] 2-gate structure; 21-gate channel; 22-gate oxide layer; 23-gate electrode layer; 24-insulating layer;

[0037] 3-mask layer; 31-mask material layer;

[0038] H- lateral width of the adjustment area;

[0039] h1 - first depth value;

[0040] h2 - second depth value;

[0041] h3 - third depth value. DETAILED DESCRIPTION

[0042] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] Figure 6 A schematic diagram of a semiconductor device provided in this embodiment, such as Figure 6 As shown, the semiconductor device includes: a substrate 1, in which an active region 111 and a drain region 112 are formed; a gate structure 2 formed in the substrate 1 between the source region 111 and the drain region 112 to form a transistor; and an adjustment region 113 located in the substrate 1 below the gate structure 2 to increase the doping concentration of the channel of the transistor.

[0044] For details, please continue to refer to Figure 6 A trench isolation structure 13 and a plurality of active areas are formed in the substrate 1, and the trench isolation structure 13 isolates adjacent active areas. This embodiment will be described in detail by taking an example where two transistors are formed in one active area, but it should be understood that the present invention is not limited to the case where there are two transistors in the active area, for example, there may also be one or more than two.

[0045] In this embodiment, each of the active areas includes two source areas 111 and a drain area 112. Two gate structures 2 are formed in the substrate 1 of the active area. The gate structures 2 are formed on the substrate 1 and are both located between the source area 111 and the drain area 112 to form two transistors. It can be understood that the two transistors in the same active area respectively use one of the adjacent source areas 111 and share the drain area 112. The drain region 112 and the source region 111 extend from the surface of the substrate 1 to the inside of the substrate 1 to a first depth position (i.e., a position extending downward from the surface of the substrate 1 to a first depth value h1), and the gate structure extends from the surface of the substrate to the inside of the substrate 1 to a second depth position (i.e., a position extending downward from the surface of the substrate 1 to a second depth value h2), and the second depth position is further sunken than the first depth position (the second depth value h2 is greater than the first depth value h1), so that the bottom of the gate structure 2 is further sunken into the source region 111 and the drain region 112 to form the channel of the transistor, i.e., the region from the source region 111 to the drain region 112 along the sidewall and bottom wall of the gate structure 2. Optionally, the adjustment region 113 is located below the gate structure 2 and in the channel of the transistor. The adjustment region 113 can form a potential barrier in the channel of the transistor to block the passage of channel leakage current by increasing the doping concentration of the channel of the transistor. At the same time, since the potential barrier is not very high, a lower voltage can be applied to the gate structure 2 to cross the potential barrier, which will basically not affect other electrical characteristics of the semiconductor device (such as threshold voltage).

[0046] Optionally, the adjustment area 113 is formed under each of the gate structures 2, and the side boundary of the adjustment area 113 does not exceed the side boundary of the gate structure 2, that is, the lateral width dimension H of the adjustment area 113 is smaller than the lateral width dimension of the gate structure 2. Optionally, in this embodiment, the lateral width dimension H of the adjustment area 113 is between 3nm and 5nm. The top surface and the bottom surface of the adjustment area 113 can be respectively located at the second depth position and the third depth position (that is, the position extending downward from the surface of the substrate 1 at the third depth value h3), and the third depth position is further sunken than the second depth position (the third depth value h3 is greater than the second depth value h2), or the top surface and the bottom surface of the adjustment area 113 can also be located between the second depth position and the third depth position, as long as the doping concentration of the channel of the transistor can be increased, the present invention will not cite examples one by one.

[0047] Furthermore, a well region 11 is formed in the substrate 1. In this embodiment, the well region 11 is a P well. The adjustment region 113 is formed in the well region 11. The ion doping concentration in the well region 11 is lower than the ion doping concentration in the source region 111 and the drain region 112. Furthermore, the doping type of the well region 11 can be determined according to the type of transistor formed. For example, when the transistor is an N-type transistor, the well region 11 can be doped with boron ions (B) accordingly. A deep well region for isolation is also formed in the substrate 1. In this embodiment, the deep well region is a deep N well 12. The deep N well 12 is formed below the well region 11 to isolate the transistor, prevent external factors from interfering with the transistor, or prevent different active regions from interfering with each other, and also prevent the transistor from interfering with other external devices.

[0048] Optionally, in this embodiment, the transistor is an N-type transistor, and the adjustment region 113 is P-type doped, that is, the conductive ions doped in the adjustment region 113 are P-type ions (such as boron ions) to increase the doping concentration of the channel of the transistor. In addition, the greater the doping concentration of the adjustment region 113, the higher the potential barrier formed in the channel of the transistor, and the less likely it is for the leakage current to cross the potential barrier, but at the same time, too high a potential barrier may affect the conduction performance of the transistor, so in this embodiment, the concentration of the doped conductive ions in the adjustment region 113 is between 1E12atoms / cm2 and 1E13atoms / cm2.

[0049] Based on this, Figure 1 As shown, the present invention also provides a method for forming a semiconductor device, comprising:

[0050] S1: providing a substrate, wherein an active region and a drain region are formed in the substrate;

[0051] S2: forming a gate trench in the substrate between the source region and the drain region;

[0052] S3: forming a mask layer on the sidewalls and a portion of the bottom wall of the gate trench, and performing ion implantation on the substrate at the bottom of the gate trench using the mask layer as a mask to form an adjustment region below the gate trench; and

[0053] S4: removing the mask layer and forming a gate structure in the gate trench.

[0054] For details, please refer to Figure 2, providing the substrate 1, wherein a plurality of active regions are formed in the substrate 1, wherein the active regions include two source regions 111 and a drain region 112, wherein the drain region 112 is located between the two source regions 111, and then etching the substrate 1 to form two gate trenches 21 in the substrate 1 between each of the source regions 111 and the drain region 112, wherein the bottom of the gate trench 21 is located at a second depth position.

[0055] Then as Figure 3 As shown, a mask material layer 31 is formed on the surface of the substrate 1, and the mask material layer 31 fills the sidewalls and bottom wall of the gate trench 21 and extends to cover the substrate 1. Optionally, the material of the mask material layer 31 in this embodiment is silicon oxide, and its thickness is between 5nm and 7nm. Figure 4 , etching is performed to remove the mask material layer 31 on the substrate 1 and part of the mask material layer 31 at the bottom of the gate trench 21, so that the bottom of the gate trench 21 exposes the substrate 1, and the mask material layer 31 retained on the side wall and bottom wall of the gate trench 21 constitutes the mask layer 3.

[0056] like Figure 5 As shown, the mask layer 3 is used as a mask to perform an ion implantation process on the substrate 1 at the bottom of the gate trench 21, so as to implant boron ions into the substrate 1 at the bottom of the gate trench 21, so as to form an adjustment region 113. Further, the ion implantation energy of the ion implantation process is between 2keV and 10keV, so as to implant the boron ions below the gate trench 21. The position of the adjustment region 113 in the substrate 1 depends on the energy of the ion implantation process. If the energy of the ion implantation process is higher, the adjustment region 113 is deeper. Conversely, if the energy of the ion implantation process is lower, the adjustment region 113 is shallower. In addition, since the mask layer 3 is formed on the sidewall of the gate trench 21, the side boundary of the adjustment region 113 will not exceed the side boundary of the gate trench 21.

[0057] See next Figure 6After forming the adjustment region 113, the mask layer 3 is removed, and then a gate structure 2 is formed in the gate trench 21. The specific process is: performing a thermal oxidation process to form a gate oxide layer 22 in the gate trench 21 at a temperature of 800 degrees Celsius to 1000 degrees Celsius, wherein the gate oxide layer 22 covers the sidewalls and bottom walls of the gate trench 21, and then performing a rapid thermal annealing process on the gate oxide layer 22 under the protection of an inert gas to improve the quality of the gate oxide layer 22. Optionally, the temperature of the rapid thermal annealing process is between 500 degrees Celsius and 700 degrees Celsius; next, forming a conductive material layer on the substrate 1, wherein the conductive material layer covers the substrate 1 and fills the gate trench 21, performing a back etching process on the conductive material layer to remove the portion of the conductive material layer covering the substrate, and retaining the conductive material layer. The portion of the conductive material layer that fills the gate trench 21 is used to form the gate electrode layer 23. In a preferred embodiment, in the back-etching process of the conductive material layer, after removing the portion of the conductive material layer that covers the substrate 1, the back-etching process can be further performed on the conductive material layer filled in the gate trench 21 to reduce the height of the conductive material layer. In this way, the top of the finally formed gate electrode layer 23 can be lower than the opening of the gate trench 21, so that a accommodating space can be formed in the gate trench 21 and located above the gate electrode layer 23; then an insulating layer 24 is filled in the accommodating space of the gate trench 21 to cover the gate electrode layer 23, that is, the insulating layer 24 can be self-aligned and filled in the accommodating space, so that the gate electrode layer 23 can be isolated and protected by the insulating layer 24.

[0058] In summary, in the semiconductor device and the method for forming the same provided in the embodiments of the present invention, a gate structure is formed between the source region and the drain region in the substrate to constitute a transistor, and then an adjustment region is formed at the bottom of the gate structure. The doping concentration of the channel of the transistor is increased to form a potential barrier in the channel, thereby blocking the passage of leakage current and reducing the channel leakage current. At the same time, since the potential barrier is not very high, a lower voltage can be applied to the gate structure to cross the potential barrier, which basically does not affect other electrical characteristics of the semiconductor device.

[0059] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate having an active region and a drain region formed therein; a gate structure formed in the substrate between the source region and the drain region to form a transistor; as well as, an adjustment region, located in the substrate below the gate structure, to increase the doping concentration of the channel of the transistor; A well region is also formed in the substrate, and the adjustment region is located in the well region; the doping concentration of the well region is lower than that of the source region and the drain region; The concentration of conductive ions doped in the adjustment region is between 1E12 atoms / cm 2 ~1E13 atoms / cm 2 ; Wherein, the lateral width dimension of the adjustment region is smaller than the lateral width dimension of the gate structure.

2. The semiconductor device according to claim 1, wherein The drain region and the source region extend from the surface of the substrate to a first depth position in the substrate, and the gate structure extends from the surface of the substrate to a second depth position in the substrate, and the second depth position is further sunken than the first depth position, so that the area from the source region to the drain region along the side wall and bottom wall of the gate structure constitutes the channel of the transistor, and the adjustment region is located between the second depth position and a third depth position of the substrate, and the third depth position is further sunken than the second depth position.

3. The semiconductor device according to claim 1, wherein The lateral width of the adjustment area is between 3nm and 5nm.

4. The semiconductor device according to claim 1, wherein When the transistor is an N-type transistor, the adjustment region is P-type doped to increase the doping concentration of the channel of the transistor.

5. The semiconductor device according to claim 4, wherein: The conductive ions doped into the adjustment region include boron ions.

6. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, wherein an active region, a drain region and a well region are formed in the substrate, and the doping concentration of the well region is lower than that of the source region and the drain region; forming a gate trench in the substrate between the source region and the drain region; A mask layer is formed on the sidewalls and a portion of the bottom wall of the gate trench, and ion implantation is performed on the substrate at the bottom of the gate trench using the mask layer as a mask to form an adjustment region in the well region below the gate trench, wherein the concentration of conductive ions doped in the adjustment region is between 1E12 atoms / cm 2 ~1E13 atoms / cm 2 ;as well as, The mask layer is removed and a gate structure is formed in the gate trench.

7. The method for forming a semiconductor device according to claim 6, wherein: The energy of ion implantation into the substrate at the bottom of the gate trench is between 2keV and 10keV.

8. The method for forming a semiconductor device according to claim 6, wherein: The step of forming the mask layer comprises: forming a mask material layer on the substrate, wherein the mask material layer covers the sidewalls and bottom wall of the gate trench and extends to cover the substrate; and, Etching is performed to remove the mask material layer on the substrate and a portion of the mask material layer on the bottom wall of the gate trench, and the mask material layer on the sidewall of the gate trench and a portion of the mask material layer on the bottom wall of the sidewall of the gate trench are retained to form the mask layer.

9. The method for forming a semiconductor device according to claim 8, wherein: The thickness of the mask layer is between 5nm and 7nm.

10. The method for forming a semiconductor device according to claim 6, wherein: The steps of forming the gate structure include: forming a gate oxide layer on the sidewalls and bottom wall of the gate trench; Performing a rapid thermal annealing process on the gate oxide layer; A gate electrode layer and an insulating layer covering the gate electrode layer are sequentially filled in the gate trench, and the gate oxide layer, the gate electrode layer and the insulating layer constitute the gate structure.

11. The method for forming a semiconductor device according to claim 10, wherein: The gate oxide layer is formed by a thermal oxidation process at a temperature of 800 degrees Celsius to 1000 degrees Celsius, and the thickness of the gate oxide layer is between 3nm and 4nm.

12. The method for forming a semiconductor device according to claim 11, wherein: A rapid thermal annealing process is performed on the gate oxide layer under the protection of an inert gas, and the temperature of the rapid thermal annealing process is between 500 degrees Celsius and 700 degrees Celsius.

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