Semiconductor structure

Abstract

The semiconductor structure includes a plurality of semiconductor fins protruding from a substrate; a plurality of dielectric fins protruding from the substrate and located between the semiconductor fins; and a gate stack located on the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer located on the first dielectric material layer, and a third dielectric material layer located on the second dielectric material layer, wherein the first dielectric material layer and the second dielectric material layer have different compositions, and the first dielectric material layer and the third dielectric material layer have the same composition.

Description

Technical Field

[0001] Embodiments of the present invention relate to fin field effect transistor devices. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. As integrated circuits have evolved, functional density (the number of interconnect devices per unit chip area) has generally increased as geometry (the smallest component or circuit that can be produced by the manufacturing process) has decreased. The shrinking process size generally increases production capacity and reduces the associated costs, but also increases the complexity of manufacturing and processing integrated circuits. To achieve these advances, the methods of manufacturing and processing integrated circuits have also required similar developments.

[0003] For example, three-dimensional transistors such as fin field effect transistors have been introduced to replace planar transistors. A typical fin field effect transistor has a fin (or fin structure) extending upward from a substrate. The channel of the field effect transistor is formed in this vertical fin, and the gate is formed on the channel region of the fin (e.g., covering the channel region). Existing manufacturing techniques for fin field effect transistors are generally applicable, but are still not fully applicable in all aspects. In order to continue to meet the increasing design requirements of fin field effect transistor devices with increasing functional density and shrinking geometric dimensions, additional advances are needed. Summary of the invention

[0004] A semiconductor structure provided by one embodiment of the present invention includes: a plurality of semiconductor fins protruding from a substrate; a plurality of dielectric fins protruding from the substrate and located between the semiconductor fins, the dielectric fins including a first dielectric material layer, a second dielectric material layer located on the first dielectric material layer, and a third dielectric material layer located on the second dielectric material layer, wherein the first dielectric material layer and the second dielectric material layer have different compositions, and the first dielectric material layer and the third dielectric material layer have the same composition; and a plurality of gate stacks located on the semiconductor fins and the dielectric fins.

[0005] A method for manufacturing a semiconductor structure provided by one embodiment of the present invention includes: forming a semiconductor fin structure on a substrate, wherein the semiconductor fin structure includes a plurality of semiconductor fins and defining grooves between the semiconductor fins; filling a first dielectric material layer and a second dielectric material layer on the first dielectric material layer into the grooves to form a dielectric fin structure having a plurality of dielectric fins, and the first dielectric material layer and the second dielectric material layer have different compositions; removing a portion of the second dielectric material layer to form a first recess; after removing a portion of the second dielectric material layer, removing a portion of the semiconductor fin to form a second recess in a portion of the semiconductor fin; filling a third dielectric material layer into the first recess and the second recess, and the third dielectric material layer and the first dielectric material layer have the same composition; and forming a gate stack on the semiconductor fin and the dielectric fin.

[0006] A semiconductor structure provided by one embodiment of the present invention includes: a first fin, located on a substrate and longitudinally along a first direction, wherein the first fin includes a semiconductor material; a second fin, located between the first fins and longitudinally along the first direction, wherein the second fin includes a first dielectric material layer; a third fin, located between the first fins and between the second fins and longitudinally along the first direction, wherein a first portion of each third fin includes a semiconductor material, and a second portion of each third fin includes a second dielectric material layer, and the second dielectric material layer has the same composition as the first dielectric material layer; and a gate stack, located on the first fin, the second fin, and the third fin, and the gate stack is longitudinally along a second direction, and the second direction is perpendicular to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a perspective view of a semiconductor structure in some embodiments of the present invention.

[0008] Figure 1B In some embodiments of the present invention, Figure 1A A top plan view of a semiconductor structure.

[0009] Figure 1C In some embodiments of the present invention, Figure 1A A cross-sectional view of the semiconductor structure along dotted line AA'.

[0010] Figure 1D In some embodiments of the present invention, Figure 1A A cross-sectional view of the semiconductor structure along dotted line BB'.

[0011] Figure 1E In some embodiments of the present invention, Figure 1A A cross-sectional view of the semiconductor structure along the dashed line CC'.

[0012] Figure 2A and2B It is a flow chart of a method for manufacturing an integrated circuit in some embodiments of the present invention.

[0013] Figure 3 is a perspective view of a semiconductor structure in some embodiments of the present invention.

[0014] Figure 4A , 5A , 6A, 7A, 8A, 9A, 11A, 12A, 13A, 14A, and 15A are perspective views of semiconductor structures at various manufacturing stages of the method in some embodiments of the present invention.

[0015] Figure 4B , 5B , 6B, 7B, 8B, 9B, 11B, 12B, 13B, 14B, and 15B are respectively some embodiments of the present invention, Figure 4A , 5A , 6A, 7A, 8A, 9A, 11A, 12A, 13A, 14A, and 15A are top views of the semiconductor structures.

[0016] Fig. 10A FIG. 1 is a top view of a semiconductor structure at an intermediate manufacturing stage of a method in some embodiments of the present invention.

[0017] Figure 4C , 5C , 6C, 7C, 8C, 9C, 10B, 11C, 12C, 13C, 14C, and 15C are respectively some embodiments of the present invention, the semiconductor structure along Figure 4A , 5A , 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are cross-sectional views taken along the dotted line AA'.

[0018] Figure 4D , 5D , 6D, 7D, 8D, 9D, 10C, 11D, 12D, 13D, 14D, and 15D are respectively some embodiments of the present invention, the semiconductor structure along Figure 4A , 5A , 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are cross-sectional views taken along the dotted line BB'.

[0019] Fig.15E In some embodiments of the present invention, Fig.15A A cross-sectional view of the structure along the dotted line CC'.

[0020] The reference numerals are described as follows:

[0021] AA', BB', CC' dotted lines

[0022] H Height

[0023] Wc, Wf, W1, W2, W3, W4, W5 Width

[0024] 100 Workpieces

[0025] 102 substrate

[0026] 104 Hard Mask Layer

[0027] 106 Semiconductor Fins

[0028] 108, 108A, 108B, 108C, 108D groove

[0029] 108E Cutting groove

[0030] 110 Hybrid Fins

[0031] 110A, 110C Semiconductor part

[0032] 110B Dielectric part

[0033] 112, 129 Dielectric layer

[0034] 118 Dielectric Fin Structure

[0035] 118B, 118C, 118D, 118E Dielectric Fins

[0036] 120, 122, 124 dielectric material layer

[0037] 125, 127 Depression

[0038] 126 gate dielectric layer

[0039] 128 Isolation Structure

[0040] 130, 130A, 130B, 130C, 130D, 130E dummy gate stack

[0041] 131 dummy gate layer

[0042] 132 Gate hard mask layer

[0043] 132A, 132B Masking material film

[0044] 136 Epitaxial Source / Drain Structure

[0045] 140 Interlayer dielectric layer

[0046] 142 Etch stop layer

[0047] 146, 146A, 146B, 146C, 146D, 146E Metal gate stack

[0048] 148 Gate cutting structure

[0049] 150 Source / Drain Contact Structure

[0050] 152 Field Effect Transistor

[0051] 154 Channel Area

[0052] 200 Methods

[0053] Steps 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232 DETAILED DESCRIPTION

[0054] The following content provides different embodiments or examples that can implement different structures of the present invention. The following specific components and arrangement embodiments are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are separated by other additional components but not in direct contact. In addition, multiple embodiments of the present invention may repeatedly use the same number for simplicity, but the components with the same number in multiple embodiments and / or settings do not necessarily have the same corresponding relationship.

[0055] In addition, the structure of the embodiments of the present invention is formed on another structure, connected to another structure, and / or coupled to another structure. The structure may directly contact another structure, or an additional structure may be formed between the structure and the other structure (i.e., the structure does not contact the other structure). In addition, spatial relative terms such as "below", "beneath", "lower", "above", "above", or similar terms can be used to simplify the relative relationship between one element and another element in the diagram. Spatial relative terms can be extended to elements used in other directions and are not limited to the illustrated direction. In addition, when a numerical value or a numerical range is described with "approximately", "approximately", or similar terms, it includes + / -10% of the numerical value unless otherwise specified. For example, the term "approximately 5nm" includes a size range between 4.5nm and 5.5nm.

[0056] Embodiments of the present invention relate to, but are not limited to, FinFET devices. For example, the FinFET device may be a complementary metal oxide semiconductor device, which includes a p-type metal oxide semiconductor FinFET device and an n-type metal oxide semiconductor FinFET device. The following content illustrates various embodiments of the present invention using the example of a FinFET. Specifically, embodiments of the present invention may also be used for FinFET logic devices and FinFET storage devices (such as static random access memory). However, it should be understood that unless specifically limited by the claims, embodiments of the present invention are not limited to a specific type of device.

[0057] Figure 1A FIG. 1 is a partial perspective view of a workpiece 100 according to various embodiments of the present invention. Figure 1B is a top plan view of the workpiece 100 . Figure 1C , 1D , and 1E are cross-sectional views of the workpiece 100 along the dashed lines AA', BB', and CC', respectively, in various embodiments of the present invention. Figures 1A to 1E Additional structures may be included in the workpiece 100 , and other embodiments of the workpiece 100 may replace or omit some of the structures described below.

[0058] Workpiece 100 includes substrate 102. Substrate 102 may include semiconductor elements (single elements) such as silicon and / or germanium; semiconductor compounds such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, and / or other suitable semiconductor materials. Substrate 102 may be a single layer of material having a uniform composition. In other embodiments, substrate 102 may include multiple layers of materials having similar or different compositions, which are suitable for forming integrated circuit devices. In one example, substrate 102 may be a silicon-on-insulator substrate having a semiconductor silicon layer formed on a silicon oxide layer.

[0059] The workpiece 100 also includes a plurality of isolation structures 128 and a plurality of active regions defined by the isolation structures 128, such as semiconductor fins 106. The isolation structures 128 may include any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low-k dielectric material, and / or other suitable insulating materials. The isolation structures 128 may be shallow trench isolation structures. Other isolation structures such as field oxide, local silicon oxide, and / or other suitable structures may also be used as the isolation structures 128. The isolation structures 128 may include a multilayer structure, such as having one or more thermal oxide liner layers. In the described embodiment, the isolation structures 128 include an oxygen-containing dielectric material such as silicon oxide.

[0060] In some embodiments, an active region such as a semiconductor fin 106 has a non-planar structure that extends upwardly above an isolation structure 128, and the isolation structure 128 includes a dielectric layer 112. The active region such as the semiconductor fin 106 is different from the dielectric fins 118B to 118E and the hybrid fin 110 described below. The plurality of semiconductor fins 106 are collectively referred to as a semiconductor fin structure. The illustrated embodiment includes this fin structure, but other embodiments may include other raised active and passive devices on the substrate 102. The semiconductor fin 106 protrudes from the substrate 102 along the Z direction and extends outward from the isolation structure 128. In addition, the longitudinal direction of the semiconductor fin 106 is along the Y direction, and the semiconductor fins 106 in the X direction are separated from each other. In the embodiment, the X direction, the Y direction, and the Z direction are perpendicular to each other.

[0061] like Figures 1A to 1E In the illustrated embodiment, the workpiece 100 includes a plurality of field effect transistors designed to perform a plurality of functions, such as core devices, memory devices, input / output devices, other suitable devices, or combinations thereof. Figure 1A As shown by the dotted circle in , the structure of various field effect transistors is included, and the formation method thereof will be described in detail as follows. In many embodiments, the field effect transistor 152 includes an epitaxial source / drain structure 136 (which may include a plurality of doped semiconductor materials), a metal gate stack 146 (such as one of the metal gate stacks 146A to 146E), and a channel region 154 (such as a portion of the semiconductor fin 106) located between the epitaxial source / drain structures 136 and under the metal gate stack 146. The workpiece 100 may include a plurality of metal gate stacks 146 longitudinally along the X direction, and the metal gate stacks 146 in the Y direction are separated from each other. Each metal gate stack 146 may include one or more gate cutting structures 148, which are configured to isolate adjacent gate structures to form individual field effect transistors. The workpiece 100 may include a source / drain contact structure 150 located on the epitaxial source / drain structure 136. An etch stop layer (such as the etch stop layer 142 ) and an interlayer dielectric layer 140 are interposed between various structures (such as the field effect transistor 152 ) of the workpiece 100 .

[0062] The workpiece 100 also includes dielectric fins 118B to 118E (or collectively referred to as dielectric fin structures 118). Similar to the semiconductor fins 106, the dielectric fin structures 118 extend outward from the isolation structure 128 along the Z direction, although the dielectric fin structures 118 are dielectric structures (such as insulating structures or non-active structures) located between the semiconductor fins 106. The dielectric fin structures 118 of embodiments of the present invention have a variety of sizes and directions. For example, the dielectric fins 118B to 118D that are longitudinally along the Y direction (such as a direction substantially parallel to the semiconductor fins 106) have different widths. As described herein, the width W1 of the dielectric fin 118B is less than the width W2 of the dielectric fin 118C, and the width W2 is less than the width W3 of the dielectric fin 118D. In some embodiments, the ratio of the width W3 to the width W2 is between about 1 and about 4. In some embodiments, the width W1 is greater than the width W2 of the semiconductor fin 106. f Similarly, the dielectric fin structure 118 may also include a dielectric fin 118E having a longitudinal direction along the X direction (substantially orthogonal to the dielectric fins 118B to 118D), and having a width substantially similar to the width of the dielectric fin 118D. In some embodiments, the width W f Width W1 may be between about 5 nm and about 15 nm, width W2 may be between about 20 nm and about 50 nm, and width W3 may be between about 50 nm and about 200 nm. Other dimensions of semiconductor fin 106 and dielectric fins 118B- 118D may also be used in embodiments of the present invention.

[0063] In many embodiments, the dielectric fins 118B to 118E have individual sizes and positions that are configured to support the entire structure of the workpiece 100. Due to various design and process parameters, the density of the semiconductor fins 106 formed on the substrate 102 may not be consistent, such as some portions of the workpiece 100 having a greater density of semiconductor fins 106 than other portions. In addition, many of the semiconductor fins 106 may be truncated during fabrication, which also changes the density of the semiconductor fins 106 in some portions of the workpiece 100. As a result, when a gate structure (such as the dummy gate stacks 130A to 130E described in detail later) is subsequently formed on the semiconductor fins 106, the portion of the workpiece 100 having a lower density of semiconductor fins 106 may provide insufficient structural support to the gate structure, causing the gate structure to collapse or bend. Furthermore, when performing a metal gate cutting process on a replacement metal gate stack (such as metal gate stacks 146A to 146E) to form gate cutting structure 148, two closely adjacent semiconductor fins 106 may be inadvertently overetched laterally and damage workpiece 100. For at least the above reasons, embodiments of the present invention provide dielectric fins 118B to 118E (such as Figures 1A to 1EThe dielectric fins 118B to 118D shown in the figure are configured to provide at least structural support for the subsequently formed gate structures (such as the dummy gate stacks 130A to 130E) in the region without the semiconductor fins 106, adjust the overall fin density, increase the gate cutting structure 148 (such as Figure 1E The gate cut structure 148 formed on the dielectric fins 118 to 118D in the embodiment of the present invention is used to reduce the process tolerance used and increase the mechanical strength of the semiconductor fin 106.

[0064] Dielectric fins 118B to 118E may include a single dielectric material layer, such as dielectric material layer 120 (such as dielectric fins 118B and 118C), or multiple dielectric material layers, such as dielectric material layers 120, 122, and / or 124 (such as dielectric fins 118D and 118E). In the embodiment, narrower dielectric fins 118B and 118C may include a single dielectric material layer, such as dielectric material layer 120. In the embodiment, wider dielectric fins 118D and 118E may include multiple dielectric material layers, wherein dielectric material layer 124 is located on dielectric material layer 122, and dielectric material layer 122 is located on dielectric material layer 120. In the embodiment, dielectric material layer 120 covers dielectric material layers 122 and 124. In other words, the sidewall of the dielectric material layer 120 directly contacts the sidewalls of the dielectric material layers 122 and 124. Figure 1C and 1D As shown, the width W4 of the dielectric material layer 122 is similar to or substantially the same as the width W5 of the dielectric material layer 124, and is smaller than the width W3. In other words, both the widths W4 and W5 span from one side wall of the dielectric material layer 120 to the other side wall of the dielectric material layer 120. In some embodiments, the ratio of the width W4 (or the width W5) to the width W3 is between about 0.6 and about 0.9. In some embodiments, the widths W4 and W5 may be between about 30 nm and about 180 nm, and the width W3 may be between about 50 nm and about 200 nm. In addition, the dielectric material layer 120 is configured to contact the lower surface of the dielectric material layer 122 and the side walls of the dielectric material layers 122 and 124.

[0065] In many embodiments, the dielectric material layer 120 and the dielectric material layer 124 have similar compositions, and both may include nitrogen-containing dielectric materials such as silicon nitride, metal-containing nitrides, other suitable materials, or combinations thereof. In some examples, the difference in nitrogen composition between the dielectric material layer 120 and the dielectric material layer 124 is no greater than about 2 atomic %. The dielectric material layer 122 has a different composition than the dielectric material layers 120 and / or 124, and may include oxygen-containing dielectric materials such as silicon oxide, silicon oxycarbide, silicon oxynitride-carbon, other suitable materials, or combinations thereof. It is noteworthy that the dielectric material layer 122 and the dielectric layer 112 (such as the isolation structure 128) have similar compositions, and both include oxygen-containing dielectric materials. In some examples, the difference in oxygen composition between the dielectric material layer 122 and the dielectric layer 112 is no greater than about 2 atomic %. In addition, the methods of forming the dielectric material layers 120, 122, and 124 may be different, as described in detail below. By using multiple dielectric materials to form the dielectric fins 118D and 118E, process compatibility can be increased. For example, after filling the dielectric material layer 120, the aspect ratio of the trench can be reduced and it is easy to fill the subsequent dielectric material layer (such as the dielectric material layer 122). In this way, the process tolerance of the method for forming the dielectric fins 118D and 118E can be increased, and the details will be further described below. In addition, the dielectric fins and the isolation structure 128 can include different dielectric materials to enhance the etching selectivity between the two and improve the process capability.

[0066] The dielectric fins 118B to 118E may be formed by any suitable method, such as atomic layer deposition, chemical vapor deposition, flowable chemical vapor deposition, spin coating, physical vapor deposition, other suitable methods, or combinations thereof. In the embodiment, the dielectric material layers 120 and 124 are formed by an atomic layer deposition process, and the dielectric material layer 122 is formed by a flowable chemical vapor deposition and / or spin coating process. The method of making the dielectric fin structure 118 is described in detail below.

[0067] The workpiece 100 may further include hybrid fins 110, each of which includes Figure 1C The semiconductor portion 110A is shown with Figure 1D The semiconductor portion 110A and the dielectric portion 110B are arranged along the Y direction (substantially parallel to the semiconductor fin 106 and the dielectric fins 118B to 118D) so that the sidewalls of the semiconductor portion 110A and the sidewalls of the dielectric portion 110B are continuous along the Y direction. In some embodiments, the sidewalls of the semiconductor portion 110A and the sidewalls of the dielectric portion 110B are coplanar along the Y direction. In many embodiments, the dielectric portion 110B is located at the metal gate stack 146 (e.g., Figure 1A146B). The semiconductor portion 110A is similar in composition to the semiconductor fin 106, while the dielectric portion 110B includes a dielectric material layer 124. In the embodiment, another semiconductor portion 110C having a height H is located below the dielectric portion 110B (along the Z direction). In other words, the lower surface of the dielectric portion 110B contacts the upper surface of the semiconductor portion 110C. In other embodiments, the lower surface of the dielectric portion 110B is lower than the lower surface of the dielectric fins 118B to 118D. In one example, the height H is greater than 0 and is approximately 20% less than the height of the hybrid fin 110. In other embodiments, the semiconductor portion 110C can be omitted from the workpiece 100 so that the lower surface of the dielectric portion 110B directly contacts the upper surface of the substrate 102. In contrast, the lower surfaces of the dielectric fins 118B to 118D can be separated from the substrate 102 by an isolation structure 128.

[0068] When forming the gate structure (dummy gate stacks 130A to 130E), misalignment between the gate structure and the semiconductor fin may cause structural defects (such as voids) in the semiconductor fin, especially in the subsequent process of forming the source / drain structure. In some embodiments of the present invention, a gate structure is formed in the area where a portion of the semiconductor fin is replaced with a dielectric material to help alleviate any structural defects that may be caused by misalignment between the gate structure and the semiconductor fin. The dielectric portion 110B of the hybrid fin 110 described above is configured to alleviate possible misalignment effects in the gate structure.

[0069] The method for forming a workpiece having a field effect transistor 152 is combined with Figures 2A to 15D Instructions are as follows. Figure 2A and 2B 2 is a flow chart of a method 200 for fabricating a workpiece 100 in various embodiments of the present invention. The following figures are perspective views, top views, cross-sectional views through source / drain regions (e.g., along dashed line AA'), or cross-sectional views through a metal gate stack (e.g., along dashed line BB') of the workpiece 100.

[0070] Various embodiments of the present invention may be used together to describe the method 200 and the structure of the workpiece 100. It is understood that additional steps may be provided before, during, and after the method 200, and other embodiments of the method 200 may replace or omit some of the steps described. In the following, the active region is also referred to as the semiconductor fin 106.

[0071] like Figure 2A and 3As shown, step 202 of method 200 provides workpiece 100, which includes substrate 102 as described in detail below. Substrate 102 can have a uniform composition or have multiple layers. The layers can have similar or different compositions, and some substrate layers in various embodiments have inconsistent compositions to induce device stress and thus adjust device performance. Examples of layered substrates include silicon-on-insulator substrates. In these examples, substrate 102 can include a buried insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0072] The substrate 102 may have one or more layers formed thereon. For example, the substrate 102 includes one or more semiconductor layers, which are epitaxially grown on a base silicon such as a silicon wafer. For example, the substrate 102 includes a first semiconductor layer formed on a base silicon, and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer includes a first semiconductor material such as silicon germanium, and the second semiconductor layer includes a second semiconductor material such as silicon, and the first semiconductor material is different from the second semiconductor material. The epitaxial growth method of the first semiconductor layer and the second semiconductor layer may be a suitable technique such as selective epitaxial growth. In some embodiments, a suitable deposition process used for epitaxial growth includes atomic layer deposition, chemical vapor deposition, physical vapor deposition, high-density plasma chemical vapor deposition, and / or other suitable deposition processes. Any of these techniques can be used to grow a semiconductor layer having any composition of a gradient composition. In some embodiments, the substrate 102 may be doped by a suitable method, such as ion implantation.

[0073] In order to facilitate the production and avoid damaging the semiconductor layer, one or more hard mask layers 104 may be formed on the substrate 102. For example, the hard mask layer 104 may include a dielectric layer such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, or a semiconductor carbide. In some examples, the hard mask layer 104 includes two or more films stacked together, such as a stacked silicon oxide film and a silicon nitride film. The hard mask layer 104 may be formed by thermal growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, and / or other suitable deposition techniques. The hard mask may include other suitable materials, such as a silicon oxide layer and a polysilicon layer on the silicon oxide layer.

[0074] like Figure 2A and Figures 4A to 4DAs shown, step 204 of method 200 patterns the substrate 102 to form one or more semiconductor fins 106 extending outward from the substrate 102. In some embodiments, step 204 includes one or more lithography and etching processes. In other embodiments, step 204 includes forming a patterned photoresist layer (not shown), and using the patterned photoresist layer as an etching mask to form a fin-like structure, which includes one or more semiconductor fins 106 separated by trenches 108. In this embodiment, the openings in the patterned photoresist layer are first transferred to the hard mask layer 104 by an etching process, and then the openings are transferred to the substrate 102 by one or more subsequent etching processes. Additional details of step 204 will be provided as follows.

[0075] A photoresist layer for forming semiconductor fins 106 may be formed on hard mask layer 104. Examples of photoresist layers include photosensitive materials that can change properties after exposure to light such as ultraviolet light, deep ultraviolet light, or extreme ultraviolet light. This property change can be used to selectively remove exposed or unexposed portions of the photoresist layer by a developing process. This process of forming a patterned photoresist layer is also called photolithography or photolithography.

[0076] In one embodiment, the photoresist layer can be patterned by a lithography process, and a portion of the photoresist material can be retained on the workpiece 100. After patterning the photoresist, an etching process is performed on the workpiece 100 to open the hard mask layer 104, and the pattern can be transferred from the photoresist layer to the hard mask layer 104. After patterning the hard mask layer 104, the remaining photoresist layer can be removed. Exemplary lithography processes include spin coating the photoresist layer, soft baking the photoresist layer, aligning the mask, exposing, post-exposure baking, developing the photoresist layer, rinsing, and drying such as hard baking. In other embodiments, the lithography process can be implemented, supported, or replaced by other methods (such as maskless photolithography, electron beam writing, or ion beam writing). The etching process of the patterned hard mask layer may include wet etching, dry etching, or a combination of the above. The first etching process performed on the hard mask layer 104 may include multiple etching steps. For example, the silicon oxide film in the hard mask layer may be etched by a dilute hydrofluoric acid solution, and the silicon nitride film in the hard mask layer may be etched by a phosphoric acid solution. The second etching process performed on the substrate 102 may include any suitable etching technique, such as dry etching, wet etching, other etching methods (such as reactive ion etching), or a combination thereof. In some examples, the second etching process may include multiple etching steps with different etching chemistries, each of which targets a specific material of the workpiece 100. In some examples, the semiconductor material of the substrate 102 may be etched by a dry etching process using a fluorine-based etchant. In some embodiments, etching includes multiple etching processes using different etching chemistries, each of which targets a specific material of the substrate 102 and does not etch the hard mask layer 104. For example, the dry etching process may use an oxygen-containing gas, a fluorine-containing gas (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), a chlorine-containing gas (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), a bromine-containing gas (such as hydrogen bromide and / or bromoform), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid, an alkali hydroxide solution, ammonia, a solution containing hydrofluoric acid, nitric acid, and / or hydrofluoric acid, or other suitable wet etchants. The retained portion of the semiconductor layer is converted into semiconductor fins 106 to define trenches 108 (such as trenches 108B to 108D) between the semiconductor fins 106.

[0077] Various other embodiments of the method of forming the semiconductor fin 106 are also applicable. For example, a double patterning or multiple patterning process can be used to pattern the semiconductor fin 106. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern pitch produced is smaller than the pattern pitch obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the semiconductor fin 106 is patterned with the retained spacers or cores.

[0078] The patterning process (eg, lithography and etching) is configured to form semiconductor fins 106 extending from the substrate 102 and having any suitable height and width. Specifically, the etching process applied to the substrate 102 may be controlled to partially etch the substrate 102, such as Figure 4A As shown. The above control can be achieved by controlling the etching time or controlling other etching parameters. Through the etching process, a semiconductor fin 106 extending from the substrate 102 can be formed. The workpiece 100 includes a fin structure of multiple semiconductor fins 106 whose length direction is the Y direction. In addition to forming the semiconductor fins 106, the patterning process also defines one or more grooves 108A, 108B, 108C, and 108D (collectively referred to as grooves 108) between the semiconductor fins 106. As described above, the semiconductor fins 106 each include one or more semiconductor materials, which may be the same as or different from the substrate 102. For example, the semiconductor fins 106 each include silicon, germanium, silicon germanium, or other suitable semiconductor materials. In other embodiments, the semiconductor fins 106 include silicon germanium with a gradient concentration, such as a germanium concentration that increases toward the upper surface of the semiconductor fin.

[0079] like Figure 2A and Figures 5A to 5D As shown, step 206 of method 200 forms a dielectric layer 112 on the substrate 102. In this embodiment, the dielectric layer 112 deposited on the substrate 102 has a compliant profile that covers the substrate 102 and is located on the sidewalls and upper surface of the semiconductor fin 106. The dielectric layer 112 may include a single dielectric material layer or multiple dielectric material layers. Suitable dielectric materials for the dielectric layer 112 include silicon oxide, silicon nitride, silicon carbide, fluorine-doped silicate glass, low dielectric constant dielectric materials, field oxides, local silicon oxides, other suitable dielectric materials, or combinations thereof. The deposition method of the dielectric material may be any suitable technique, including thermal growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, and / or spin coating technology. In the described embodiment, an atomic layer deposition process is used as a compliant deposition technique to form the dielectric layer 112. The dielectric layer 112 is at least partially composed of Figures 1A to 1DThe isolation structure 128 shown (such as a shallow trench isolation structure) is formed.

[0080] As described below, at a later stage of method 200, dielectric fins 118B-118D will be formed in at least some of the trenches (e.g., in trenches 108B, 108C, and 108D). Conversely, some trenches such as trench 108A between semiconductor fins 106 having narrower spacing (e.g., less than about 2 nm) may be filled with dielectric layer 112 so that no dielectric fins are formed in these trenches. In the described embodiment, the width of some trenches such as trench 108B is substantially the same as the width W of semiconductor fin 106. f Similarly, some trenches between semiconductor fins 106 with wider spaces, such as trenches 108C or 108D, may have a gap greater than the width W. f .

[0081] like Figure 2A and Figures 6A to 6D As shown, step 208 of method 200 forms a cutting groove 108E to the semiconductor fin 106 by one or more lithography and etching processes. The cutting groove 108E is a groove that cuts through the semiconductor fin 106, which defines the end of the semiconductor fin 106. The cutting groove 108E extends through multiple semiconductor fins 106 along the X direction. The lithography and etching process implemented in step 208 is similar to the lithography and etching process implemented in step 204. Specifically, a patterned photoresist layer (not shown) is formed by a lithography patterning process, and the patterned photoresist layer is used as an etching mask to perform an etching process on the semiconductor fin 106 and the dielectric layer 112 to form the cutting groove 108E. The width W of the cutting groove 108E is c Substantially greater than the width W of the semiconductor fin 106 f In some embodiments, the width W c may be different from the width of other trenches (such as trenches 108B to 108D) because the width W c The cut grooves 108E are defined by separate patterning processes in step 208 and are configured for different design criteria (e.g., to provide adequate spacing between adjacent fin ends and / or to mitigate inadvertent over-etching of the semiconductor fins 106 during the metal gate cutting process as described above). After forming the cut grooves 108E, the patterned photoresist layer may be removed by wet stripping or plasma ashing. In some embodiments, the cut grooves 108E may be omitted from the workpiece 100.

[0082] like Figure 2A and Figures 7A to 7DAs shown, step 210 of method 200 completely or partially fills the trench 108 between the semiconductor fins 106 with a dielectric material layer 120. In many embodiments, the dielectric material layer 120 includes a nitrogen-containing material such as silicon nitride or a metal nitride (such as aluminum nitride), other suitable dielectric materials, or a combination of the above. In the embodiment, the dielectric material layer 120 completely fills the trenches 108B and 108C to form dielectric fins 118B and 118C, respectively, and the dielectric material layer 120 partially fills the trench 108D and the cut trench 108E. As described above, the trench 108 has a variable size. The dielectric material layer 120 can be conformally deposited in the trench 108, and its deposition method can be any suitable method such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable methods, or a combination of the above. In the embodiment, the method of forming the dielectric material layer 120 is an atomic layer deposition process. The trench 108D and the cut trench 108E may further include an additional dielectric material layer, as described in detail below.

[0083] like Figure 2A and Figures 8A to 8D As shown, step 212 of method 200 completely fills the trench 108D and the cut trench 108E with the dielectric material layer 122 to form dielectric fins 118D and 118E, respectively. The dielectric material layer 122 has a different composition from the dielectric material layer 120. For example, the dielectric material layer 120 includes a nitrogen-containing dielectric material, and the dielectric material layer 122 includes an oxide-containing dielectric material such as silicon oxide, silicon oxycarbide, silicon oxycarbonitride, a metal oxide such as aluminum oxide, other dielectric materials, or a combination thereof. The deposition method of the dielectric material layer 122 may be a flowable chemical vapor deposition or a spin-on deposition rather than an atomic layer deposition, because the flowable chemical vapor deposition or the spin-on deposition can more effectively fill the oxide-containing material into the trench 108D and the cut trench 108E than the atomic layer deposition process used to deposit the dielectric material layer 120.

[0084] like Figure 2A and Figures 8A to 8D As shown, step 212 of the method is followed by a polishing process such as a chemical mechanical polishing process to planarize the upper surface of the workpiece 100 and remove any excess portions of the dielectric material layer 122. In some embodiments, the hard mask layer 104 can serve as a chemical mechanical polishing stop layer. In some embodiments, the hard mask layer 104 can be removed by the chemical mechanical polishing process or an additional etching process. In the described embodiment, the chemical mechanical polishing process stops on the hard mask layer 104, leaving a portion of the dielectric material layer 122 on the hard mask layer 104.

[0085] like Figure 2A and Figures 9A to 9DAs shown, step 214 of method 200 removes a portion of the dielectric material layer 122 to form a recess 125 in the dielectric fins 118D and 118E. In other words, the etching process of step 214 causes the dielectric fins 118D and 118E to be partially recessed. The etching process may be a dry etching process, a wet etching process, a reactive ion etching process, other etching processes, or a combination thereof. In one embodiment, the etching process is a dry etching process that uses one or more fluorine-containing or chlorine-containing gases. In the embodiment, due to the different compositions of the dielectric material layer 120 and the dielectric material layer 122, method 200 may remove a portion of the dielectric material layer 122 by a selective etching process. The etching process may be adjusted so that the removal rate of the dielectric material layer 122 is greater than the removal rate of the dielectric material layer 120. Therefore, after performing step 214 of method 200, the upper surface of the dielectric material layer 122 is lower than the upper surface of the dielectric material layer 120. In one example, the etching process in step 214 may remove approximately 30% of the dielectric material layer 122 .

[0086] like Figure 2B and Figures 10A to 10C As shown, step 216 of method 200 removes a portion of at least one semiconductor fin 106 along the Y direction to form a recess 127. In the embodiment, portions of three semiconductor fins 106 are removed by one or more lithography and etching processes similar to step 204. For example, a patterned photoresist layer (not shown) may be formed on the workpiece 100 to expose portions of the semiconductor fin 106 to a subsequent etching process, and portions of the semiconductor fin 106 may be removed along the Y direction to form the recess 127. The patterned photoresist layer may then be removed by any suitable method such as photoresist stripping or plasma ashing to expose the dielectric material layer 120 and the partially recessed dielectric material layer 122 to subsequent process steps.

[0087] exist Fig. 10A and 10C In the illustrated embodiment, the semiconductor fin 106 is partially recessed so that a portion of the semiconductor fin 106 remains on the substrate 102 to form a semiconductor portion 110C of the hybrid fin 110. In one embodiment, the upper surface of the semiconductor portion 110C is substantially flush with or lower than the lower surface of the dielectric material layer 120. In other embodiments, the semiconductor fin 106 in the recess 127 is completely removed from the workpiece 100 (e.g., the semiconductor portion 110C is omitted from the workpiece 100) to expose the substrate 102.

[0088] Although not shown, in some embodiments, the method 200 may remove portions of the dielectric material layer 120 and the dielectric layer 112 on the upper surface of the hard mask layer 104 before performing the lithography and etching processes. In this way, the method 200 may first deposit a filling material (such as a photoresist material) on the recessed dielectric material layer 122 to completely fill the recess 125, and then perform a chemical mechanical polishing process to remove the filling material, the dielectric material layer 120, and the dielectric material layer 122 from the upper surface of the semiconductor fin 106 to expose the hard mask layer 104. The remaining filling material may then be removed by any suitable method such as photoresist stripping or plasma ashing, and the method 200 then performs one or more lithography and etching steps to remove portions of the semiconductor fin 106 along the Y direction as described above.

[0089] like Figure 2B and Figures 11A to 11D As shown, step 218 of method 200 deposits another dielectric material layer 124 on the workpiece 100, which can completely fill the recesses 125 and 127 to form dielectric fins 118D and 118E. The method for forming the dielectric material layer 124 can be any suitable method, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable methods, or a combination of the above. In the embodiment, the deposition method of the dielectric material layer 124 is an atomic layer deposition process. In the embodiment, the dielectric material layer 124 (such as the dielectric portion 110B) is formed on the upper surface of the semiconductor portion 110C. In the embodiment, the dielectric material layer 120 forms a U-shaped layer in the dielectric fins 118D and 118E, and the dielectric material layers 122 and 124 fill the space in the U-shaped dielectric material layer 120. In other words, dielectric fins 118D and 118E include three dielectric material layers: dielectric material layers 120, 122, and 124, wherein the sidewall of dielectric material layer 120 contacts the sidewalls of dielectric material layers 122 and 124. In contrast, dielectric fins 118B and 118C include only a single dielectric material layer: dielectric material layer 120 due to their smaller size.

[0090] The composition of the dielectric material layer 124 is different from the composition of the dielectric material layer 122 and the dielectric layer 112, but is similar to the composition of the dielectric material layer 120, as described above. For example, both the dielectric material layers 120 and 124 may include a nitrogen-containing dielectric material such as silicon nitride, a metal-containing nitride, other suitable materials, or a combination thereof, while the dielectric material layer 122 includes an oxygen-containing dielectric material such as silicon oxide, silicon oxycarbide, silicon oxycarbonitride, other suitable materials, or a combination thereof. The different composition between the dielectric material layer 124 and the dielectric layer 112 can increase the etching selectivity between the two material layers in subsequent process steps.

[0091] like Figures 11A to 11DAs shown, method 200 then forms a dielectric layer 129 on the upper surface of the workpiece 100. In some embodiments, the dielectric layer 129 is configured to be suitable for a subsequent chemical mechanical polishing process as described below. The dielectric layer 129 may include plasma enhanced oxide, plasma enhanced silicon nitride, undoped silicate glass, plasma enhanced undoped silicate, other suitable materials, or combinations thereof, and may be formed by any suitable method such as plasma enhanced chemical vapor deposition, flowable chemical vapor deposition, other suitable methods, or combinations thereof. In many embodiments, the dielectric layer 129 includes a composition that is different from the material composition of the dielectric material layer 124 and the dielectric layer 112.

[0092] like Figure 2B and Figures 12A to 12D As shown, step 220 of method 200 performs a chemical mechanical polishing process to remove dielectric layer 129, a portion of dielectric material layer 124, a portion of dielectric layer 112, and hard mask layer 104 to expose the upper surface of semiconductor fin 106. Fig. 12C and 12D As shown, step 220 of method 200 planarizes the upper surface of semiconductor fin 106 to replace a portion of semiconductor fin 106 with a dielectric fin to form hybrid fin 110 having semiconductor portion 110A and dielectric portion 110B adjacent to each other in the Y direction. As a result, the sidewalls of semiconductor portion 110A and dielectric portion 110B are substantially continuous along the Y direction.

[0093] like Figure 2B and Figures 13A to 13D As shown, step 222 of method 200 selectively recesses the dielectric layer 112 to form an isolation structure 128. After the dielectric layer 112 is recessed, the semiconductor fin 106, the dielectric fin structure 118, and the hybrid fin 110 extend higher than the recessed dielectric layer 112. The recessed dielectric layer 112, such as the isolation structure 128, can electrically isolate the semiconductor fins 106 from each other. Any suitable etching technique such as dry etching, wet etching, reactive ion etching, and / or other etching methods can be used to recess the dielectric layer 112. In one embodiment, anisotropic dry etching is used to selectively remove the dielectric layer 112, that is, a suitable etchant gas such as one or more fluorine-containing gases or chlorine-containing gases is used to make the etching rate of the dielectric layer 112 higher than the etching rate of the semiconductor fin 106, the dielectric material layer 124, and the dielectric material layer 120. The height of the semiconductor fin 106 depends on the etching depth of the etching process used to recess the dielectric layer 112. The etching depth may depend on many factors, such as etching time, etching bias, etching power, other factors, or a combination thereof.

[0094] like Figure 2B and Figures 14A to 14DAs shown, step 224 of method 200 forms dummy gate stacks 130A to 130E (collectively referred to as dummy gate stacks 130). In this embodiment, a portion of the dummy gate stack 130 may be replaced with a metal gate stack at a later stage of fabrication. The dummy gate stack 130 is formed on a portion of the semiconductor fin 106, the dielectric fins 118B to 118D, and the hybrid fin 110. In some examples, the method of forming the dummy gate stack 130 includes depositing a gate dielectric layer 126 on the semiconductor fin 106 and the dielectric fins 118B to 118D, depositing a dummy gate layer 131 comprising polysilicon or other suitable material on a portion of the gate dielectric layer 126, and subsequently patterning the dummy gate layer 131. In some embodiments, the gate dielectric layer 126 includes a compliant silicon oxide layer, which may be formed by a suitable method such as atomic layer deposition, chemical vapor deposition, thermal oxidation, chemical oxidation, other suitable methods, or a combination thereof. In the embodiment, during the metal gate stack replacement process, the gate dielectric layer 126 can be replaced with a high-k gate dielectric layer (not shown). A gate hard mask layer 132 can be formed on the dummy gate layer and used as an etching mask when patterning the dummy gate layer. The gate hard mask layer 132 can include any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, other suitable materials, or a combination of the above. In one embodiment, the gate hard mask layer 132 includes a double mask material film 132A and 132B, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the dummy gate stacks 130A to 130E includes forming a patterned photoresist layer by one or more lithography processes, using the patterned photoresist layer as an etching mask and etching the gate hard mask layer 132, and using the patterned gate hard mask layer 132 as an etching mask and etching the dummy gate layer 131 to form the dummy gate stacks 130A to 130E. In the embodiment described, one or more dummy gate stacks 130 are formed on the dielectric portion 110B of the hybrid fin 110 , such as Fig.14D shown.

[0095] In some embodiments, one or more gate spacers (not shown) are formed on the sidewalls of the dummy gate stack 130. The gate spacer may include any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor carbide, a semiconductor oxynitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the gate spacer may include multiple layers, such as a first gate spacer (or sealing layer) on the sidewalls of the dummy gate stacks 130A to 130E, and a second gate spacer on the first gate spacer. In some embodiments, the gate spacer is formed by deposition and anisotropic etching such as dry etching. In this example, a spacer material is first formed on the workpiece 100 by a deposition process, and then the spacer material is anisotropically etched back to form a gate spacer along the sidewalls of the dummy gate stack 130.

[0096] Afterwards Figure 2B As shown, step 226 of method 200 forms an epitaxial source / drain structure 136 (see Figures 15A to 15E ) in the source / drain region, which can be defined in the semiconductor fin 106 and on both sides of the dummy gate stack 130. The method of forming the epitaxial source / drain structure 136 can be selective epitaxial growth for stress effects with improved carrier mobility and device performance. The dummy gate stack 130 and the gate spacer limit the selective epitaxial growth process so that the epitaxial source / drain structure 136 is self-alignedly formed in the source / drain region. In many embodiments, the epitaxial source / drain structure 136 is formed by one or more epitaxial growth (epitaxial process) to grow a crystalline silicon structure, a silicon germanium structure, a silicon carbide structure, and / or other suitable semiconductor structure on the semiconductor fin 106 in the source / drain region. In other embodiments, before performing epitaxial growth, an etching process is performed to recess a portion of the semiconductor fin 106 in the source / drain region. The etching process may also remove any dielectric material on the source / drain region, such as during the step of forming the gate sidewall structure. Suitable epitaxial processes include chemical vapor deposition techniques (such as vapor phase epitaxy and / or ultra-high vacuum chemical vapor deposition), molecular beam epitaxy, and / or other suitable processes. Dopant species may be introduced during the epitaxial process of the epitaxial source / drain structure 136 for in-situ doping, and the dopant species may include p-type dopants such as boron or boron difluoride, or n-type dopants such as phosphorus or arsenic. In an exemplary embodiment, the epitaxial source / drain structure 136 in the n-type field effect transistor includes phosphorus-doped silicon or phosphorus-doped silicon carbide, and the epitaxial source / drain structure 136 in the p-type field effect transistor includes boron-doped silicon germanium, boron-doped silicon germanium tin (tin may be used to adjust the lattice constant), and / or boron-doped germanium tin. In some embodiments, the epitaxial source / drain structure 136 includes more than one semiconductor material layer. One or more annealing processes may then be performed to activate the epitaxial source / drain structures 136. Suitable annealing processes include rapid thermal annealing, laser annealing, other suitable annealing techniques, or combinations thereof.

[0097] like Figure 2B As shown, step 228 of method 200 replaces the dummy gate stacks 130A to 130E with metal gate stacks 146A to 146E (collectively referred to as metal gate stacks 146, see Figures 15A to 15E), and the replacement process is a series of processes (collectively referred to as gate replacement processes). The gate replacement process of step 228 begins by depositing an interlayer dielectric layer 140 on the workpiece 100 to cover the isolation structure 128, the epitaxial source / drain structure 136, the dummy gate stacks 130A to 130E, and other structures on the substrate 102. The interlayer dielectric layer 140 can be used as an insulating layer that supports and isolates the conductive lines (such as contacts, vias, and metal lines) formed therein later. The interlayer dielectric layer 140 may include any suitable dielectric material, such as silicon oxide, a low dielectric constant dielectric material, a porous dielectric material, other suitable dielectric materials, or a combination of the foregoing. In some embodiments, before forming the interlayer dielectric layer 140, an etch stop layer 142 is deposited on the workpiece 100. The material of the etch stop layer 142 is different from the material of the interlayer dielectric layer 140 to provide etching selectivity. For example, the etch stop layer 142 may include silicon nitride deposited by chemical vapor deposition or atomic layer deposition. In some embodiments, the formation method of the interlayer dielectric layer 140 includes deposition and chemical mechanical polishing to provide a planarized upper surface. During the chemical mechanical polishing process, additional etching steps, or a combination thereof, the gate hard mask layer 132 may be removed.

[0098] The gate replacement process of step 228 may form a metal gate stack 146 to replace the dummy gate stack 130. The dummy gate stacks 130A to 130E are first removed by selective etching or a series of patterning and etching processes as described above. The etching process may be any suitable method, such as dry etching, wet etching, reactive ion etching, and / or other suitable methods, which may be used to form gate trenches (not shown). After removing the dummy gate stacks 130A to 130E, the material of the metal gate stack 146 is deposited in the gate trenches, and a chemical mechanical polishing process is performed to remove excess gate material and planarize the upper surface.

[0099] The material of the metal gate stack 146 includes a high-k gate dielectric layer and a gate (not shown). In some embodiments, the gate dielectric layer includes a high-k dielectric material, and the gate includes a metal or a metal alloy. The metal gate stack 146 is formed on the workpiece 100 to surround the channel region 154 of the semiconductor fin 106. In some examples, the high-k gate dielectric layer and the gate may each include multiple sublayers. The high-k dielectric layer may include a metal oxide or a metal nitride such as lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanate, barium titanate, barium zirconium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, barium strontium titanate, aluminum oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The high-k gate dielectric layer may be deposited by a suitable technique, such as atomic layer deposition, chemical vapor deposition, metal organic chemical vapor deposition, physical vapor deposition, thermal oxidation, and / or other suitable techniques. The high-k gate dielectric layer may additionally include an interface layer between the semiconductor fin 106 and the high-k dielectric layer. The interface layer may include silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials, and the deposition method may be a suitable method such as atomic layer deposition, chemical vapor deposition, ozone oxidation, and / or other suitable methods.

[0100] The gate material is then deposited on the high-k gate dielectric layer in the gate trench. The gate may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electroplating, other suitable processes, or a combination thereof. The gate may include a single layer or multiple layers, such as at least one work function metal layer, a substrate conductive layer, a metal layer, a barrier layer, and / or an adhesion layer. The gate may include ruthenium, copper, tungsten, cobalt, titanium, silver, aluminum, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, molybdenum, tungsten nitride, or any suitable material. In some embodiments, different metal materials may be used for n-type field effect transistors and p-type field effect transistor devices with separate work functions, respectively. In some embodiments, the n-type work function metal includes tantalum. In other embodiments, the n-type work function metal includes titanium aluminum, titanium aluminum nitride, or a combination thereof. In other embodiments, the n-type metal includes tantalum, titanium aluminum, titanium aluminum nitride, tungsten nitride, or a combination thereof. The n-type work function metal may include a stack of films based on multiple metals to optimize device performance and process compatibility. In some embodiments, the p-type work function metal includes titanium nitride or tantalum nitride. In other embodiments, the p-type metal includes titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum, or a combination thereof.

[0101] like Figure 2B and 15EAs shown, step 230 of method 200 cuts (or shortens) the metal gate stack 146. In this example, the metal gate stack 146 is patterned, etched, and filled with one or more dielectric materials to form a gate cut structure 148. In particular, as described above, the gate cut structure 148 is formed on the dielectric fins 118B to 118D, so if any lateral overetching occurs during the metal gate cutting process, the etching process will not inadvertently damage the semiconductor fins 106 adjacent to the dielectric fins 118B to 118E. The gate cut structure 148 is a dielectric structure that defines the space between the gate ends. The method of forming the gate cut structure 148 may include a lithography process, etching, and deposition, and then chemical mechanical polishing may be performed. For example, the method of forming the gate cut structure includes performing a lithography process to form a patterned photoresist having an opening, and the opening defines the area used for the gate cut structure. Then, an etching process is performed to selectively etch the gate stack through the photoresist opening to form a groove in the gate stack. Then, one or more dielectric materials are deposited to fill the trenches, and a chemical mechanical polishing process is performed to remove excess dielectric materials. The dielectric material of the gate cutting structure may include silicon oxide, silicon nitride, a low-k dielectric material, other suitable dielectric materials, or a combination thereof. In the embodiment described, the gate cutting structure 148 is formed in the metal gate stack 146. However, the embodiment of the present invention may also form the gate cutting structure 148 in the dummy gate stack 130 before performing the gate replacement process.

[0102] like Figure 2B and Figures 15A to 15DAs shown, step 232 of method 200 performs additional process steps on workpiece 100. For example, method 200 forms a source / drain contact structure 150 on the epitaxial source / drain structure 136. The source / drain contact structure 150 is a conductive structure that can be electrically connected to a field effect transistor to form a functional circuit. In this example, the source / drain contact structure 150 is designed to land on the epitaxial source / drain structure 136. The method of forming the source / drain contact structure 150 may include a lithography process, etching, and deposition, and then chemical mechanical polishing may be performed. For example, the method of forming the contact structure includes performing a lithography process to form a patterned photoresist layer having an opening, and the opening defines an area used for the contact structure. Then, an etching process is performed on the interlayer dielectric layer 140 through the photoresist opening to form a contact hole in the interlayer dielectric layer 140. One or more conductive materials are then deposited to fill the contact holes, and a chemical mechanical polishing process is performed to remove excess conductive materials. The conductive material of the contact structure may include tungsten, copper, cobalt, ruthenium, aluminum, other metals or metal alloys, or a combination of the above. The source / drain contact structure 150 may also include a barrier layer (such as titanium, titanium nitride, tantalum, tantalum nitride, or a combination of the above) to line the contact holes. For example, the source / drain contact structure 150 includes titanium or titanium nitride deposited by chemical vapor deposition, atomic layer deposition, or physical vapor deposition as a barrier layer, and a conductive material formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, other suitable techniques, or a combination of the above to fill the contact holes.

[0103] The method 200 may further include other steps during, before, and / or after the above steps. For example, the method 200 forms other structures such as interconnect structures on the workpiece 100. The interconnect structures include a variety of conductive structures to electrically connect a variety of devices (including field effect transistors) to the integrated circuit. The interconnect structures include contact structures, through-hole structures, and metal lines. The metal lines can be distributed in multiple metal layers, and the through-hole structures can vertically connect the metal lines between adjacent metal layers. For example, the through-hole structures and the metal lines can use copper technology, and the formation method thereof can be a damascene process such as a dual damascene process or a single damascene process.

[0104] Embodiments of the present invention provide semiconductor structures containing fin field effect transistors and methods for forming the same. Specifically, embodiments of the present invention provide dielectric fins having a variety of compositions and sizes dispersed between semiconductor fins (such as active fins) to meet different design requirements and address the challenges of making fin field effect transistors. Embodiments of the present invention provide multiple advantages. For example, dielectric fins formed in some embodiments are substantially parallel to semiconductor fins to provide structural support for subsequently formed gate stacks (such as metal gate stacks). In areas where semiconductor fins are sparse or disappear, subsequently formed gate stacks are prone to collapse. In static random access memory devices of fin field effect transistors made according to embodiments of the present invention, the fin density may be between about 40% and about 70%. In some embodiments, the dielectric fins are substantially perpendicular to the semiconductor fins to mitigate possible damage to the semiconductor fins during the metal gate cutting process. In some embodiments, a hybrid fin comprising a semiconductor portion and a dielectric portion is substantially parallel to a semiconductor fin proximate to and / or below a gate stack to compensate for possible misalignment of the metal gate stack (e.g., unwanted offset). Misalignment of the metal gate stack may result in structural defects such as metal gate extrusion. In other embodiments, the dielectric fin may comprise a three-layer composition formed by staggered deposition processes (e.g., a first atomic layer deposition process, followed by a flowable chemical vapor deposition process, and followed by a second atomic layer deposition process) to improve manufacturing efficiency and etch selectivity.

[0105] A semiconductor structure provided by an embodiment of the present invention includes: a plurality of semiconductor fins protruding from a substrate; a plurality of dielectric fins protruding from the substrate and located between the semiconductor fins, the dielectric fins including a first dielectric material layer, a second dielectric material layer located on the first dielectric material layer, and a third dielectric material layer located on the second dielectric material layer; and a plurality of gate stacks located on the semiconductor fins and the dielectric fins. In some embodiments, the first dielectric material layer and the second dielectric material layer have different compositions, and the first dielectric material layer and the third dielectric material layer have the same composition.

[0106] In some embodiments, the first dielectric material layer includes a nitrogen-containing material, and the second dielectric material layer includes an oxygen-containing material.

[0107] In some embodiments, the width of the second dielectric material layer and the width of the third dielectric material layer both extend across the sidewalls of the first dielectric material layer.

[0108] In some embodiments, a sidewall of the first dielectric material layer contacts sidewalls of the second dielectric material layer and the third dielectric material layer.

[0109] In some embodiments, the dielectric fin includes a first dielectric fin and a second dielectric fin, wherein the first dielectric fin includes a first dielectric material layer without a second dielectric material layer and a third dielectric material layer, and the second dielectric fin includes the first dielectric material layer, the second dielectric material layer, and the third dielectric material layer.

[0110] In this embodiment, the longitudinal direction of the semiconductor fin is the first direction, and the longitudinal direction of the first dielectric fin and the second dielectric fin is the first direction, wherein the dielectric fin further includes a third dielectric fin, and the longitudinal direction of the third dielectric fin is the second direction, and the second direction is perpendicular to the first direction.

[0111] In some embodiments, the semiconductor structure further includes a gate spacer along a sidewall of the gate stack, wherein a composition of the gate spacer is different from a composition of the first dielectric material layer and the third dielectric material layer.

[0112] In some embodiments, the semiconductor structure further includes a hybrid fin protruding from the substrate and located between the semiconductor fins and between the dielectric fins, wherein a first portion of the hybrid fin has the same composition as the third dielectric material layer of the dielectric fin, and a second portion of the hybrid fin has the same composition as the semiconductor fin. In some embodiments, the first portion is continuous with a sidewall of the second portion. In this embodiment, a lower surface of the first portion of the hybrid fin contacts the second portion of the hybrid fin.

[0113] Another embodiment of the present invention provides a method for manufacturing a semiconductor structure, including forming a semiconductor fin structure on a substrate, wherein the semiconductor fin structure includes a plurality of semiconductor fins and defines a groove between the semiconductor fins; filling a first dielectric material layer and a second dielectric material layer on the first dielectric material layer into the groove to form a dielectric fin structure having a plurality of dielectric fins, and the first dielectric material layer and the second dielectric material layer have different compositions; removing a portion of the second dielectric material layer to form a first recess; after removing a portion of the second dielectric material layer, removing a portion of the semiconductor fin to form a second recess in a portion of the semiconductor fin; filling a third dielectric material layer into the first recess and the second recess, and the third dielectric material layer and the first dielectric material layer have the same composition; and forming a gate stack on the semiconductor fin and the dielectric fin.

[0114] In some embodiments, the step of filling the trench includes: performing an atomic layer deposition process to deposit a first dielectric material layer in the trench; and depositing a second dielectric material layer on the first dielectric material layer to fill the trench, wherein the method of depositing the second dielectric material layer is a flowable chemical vapor deposition process. In this embodiment, the trench includes a first trench having a first width and a second trench having a second width, and the second width is greater than the first width, wherein the step of performing an atomic layer deposition process includes depositing the first dielectric material layer to completely fill the first trench, and the step of depositing the second dielectric material layer includes depositing the second dielectric material layer in the second trench.

[0115] In some embodiments, the step of filling the first recess and the second recess includes performing an atomic layer deposition process.

[0116] In some embodiments, removing a portion of the semiconductor fin exposes the substrate in the second recess, and filling the second recess forms a dielectric fin on the substrate.

[0117] In some embodiments, removing a portion of the semiconductor fin exposes the semiconductor fin in the second recess, and filling the second recess forms a dielectric fin on the semiconductor fin.

[0118] In some embodiments, the method further includes: performing a first chemical mechanical polishing process on the second dielectric material layer after filling the trench; and performing a second chemical mechanical polishing process on the third dielectric material layer after filling the first recess and the second recess.

[0119] A semiconductor structure provided by another embodiment of the present invention includes: a first fin, located on a substrate and longitudinally along a first direction, wherein the first fin includes a semiconductor material; a second fin, located between the first fins and longitudinally along the first direction, wherein the second fin includes a first dielectric material layer; a third fin, located between the first fins and between the second fins and longitudinally along the first direction; and a gate stack, located on the first fin, the second fin, and the third fin, the longitudinal direction of the gate stack is along a second direction, and the second direction is perpendicular to the first direction. In some embodiments, a first portion of each third fin includes a semiconductor material, and a second portion of each third fin includes a second dielectric material layer, and the second dielectric material layer has the same composition as the first dielectric material layer.

[0120] In some embodiments, the second fin further includes a third dielectric material layer on the first dielectric material layer, and a fourth dielectric material layer on the third dielectric material layer, wherein the third dielectric material layer has a different composition from the first dielectric material layer, and the fourth dielectric material layer has the same composition as the first dielectric material layer.

[0121] In some embodiments, a sidewall of the first portion of each third fin is coplanar with a sidewall of the second portion of each third fin along the first direction.

[0122] In some embodiments, a lower surface of the second portion of each third fin is lower than a lower surface of each second fin.

[0123] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: A plurality of semiconductor fins protruding from a substrate; a plurality of dielectric fins protruding from the substrate and located between the semiconductor fins, the dielectric fins comprising a first dielectric material layer, a second dielectric material layer located on the first dielectric material layer, and a third dielectric material layer located on the second dielectric material layer, wherein the first dielectric material layer and the second dielectric material layer have different compositions, and the first dielectric material layer and the third dielectric material layer have the same composition, wherein a sidewall of the first dielectric material layer contacts sidewalls of the second dielectric material layer and the third dielectric material layer; and A plurality of gate stacks are located on the semiconductor fin and the dielectric fin.

2. The semiconductor structure according to claim 1, wherein: The first dielectric material layer includes a nitrogen-containing material, and the second dielectric material layer includes an oxygen-containing material.

3. The semiconductor structure according to claim 1, wherein: The width of the second dielectric material layer and the width of the third dielectric material layer both span across the sidewalls of both sides of the first dielectric material layer.

4. The semiconductor structure according to claim 1, wherein: The dielectric fin includes a first dielectric fin and a second dielectric fin, wherein the first dielectric fin includes the first dielectric material layer without the second dielectric material layer and the third dielectric material layer, and the second dielectric fin includes the first dielectric material layer, the second dielectric material layer, and the third dielectric material layer.

5. The semiconductor structure according to claim 4, wherein: The semiconductor fin has a longitudinal direction that is a first direction, and the first dielectric fin and the second dielectric fin have a longitudinal direction that is the first direction, wherein the dielectric fin further includes a third dielectric fin, and the longitudinal direction of the third dielectric fin is a second direction that is perpendicular to the first direction. 6 . The semiconductor structure of claim 1 , further comprising a plurality of gate spacers along sidewalls of the gate stack, wherein the composition of the gate spacers is different from the composition of the first dielectric material layer and the third dielectric material layer.

7. The semiconductor structure as described in claim 1 further includes a plurality of hybrid fins protruding from the substrate and located between the semiconductor fins and the dielectric fins, wherein a first portion of the hybrid fins has the same composition as a third dielectric material layer of the dielectric fins, wherein a second portion of the hybrid fins has the same composition as the semiconductor fins, and wherein the sidewalls of the first portion of the hybrid fins are continuous with those of the second portion.

8. The semiconductor structure of claim 7, wherein: A lower surface of the first portion of the mixing fin contacts the second portion of the mixing fin.

9. A method for manufacturing a semiconductor structure, comprising: forming a semiconductor fin structure on a substrate, wherein the semiconductor fin structure includes a plurality of semiconductor fins and defines a plurality of trenches between the semiconductor fins; Filling the trench with a first dielectric material layer and a second dielectric material layer on the first dielectric material layer to form a dielectric fin structure having a plurality of dielectric fins, wherein the first dielectric material layer and the second dielectric material layer have different compositions; removing a portion of the second dielectric material layer to form a first recess; After removing a portion of the second dielectric material layer, removing a portion of the semiconductor fin to form a second recess in the portion of the semiconductor fin; Filling the first recess and the second recess with a third dielectric material layer, wherein the third dielectric material layer has the same composition as the first dielectric material layer; and A plurality of gate stacks are formed on the semiconductor fins and the dielectric fins.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The step of filling the trench comprises: performing an atomic layer deposition process to deposit the first dielectric material layer in the trench; and The second dielectric material layer is deposited on the first dielectric material layer to fill the trench, wherein the method of depositing the second dielectric material layer is a flowable chemical vapor deposition process.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The groove includes a first groove having a first width and a second groove having a second width, and the second width is greater than the first width, wherein the step of performing an atomic layer deposition process includes depositing the first dielectric material layer to completely fill the first groove, and the step of depositing the second dielectric material layer includes depositing the second dielectric material layer in the second groove.

12. The method for manufacturing a semiconductor structure according to claim 9, wherein: The step of filling the first recess and the second recess includes performing an atomic layer deposition process.

13. The method for manufacturing a semiconductor structure according to claim 9, wherein: The step of removing a portion of the semiconductor fin exposes the substrate in the second recess, and the step of filling the second recess forms a dielectric fin on the substrate.

14. The method for manufacturing a semiconductor structure according to claim 9, wherein: The step of removing a portion of the semiconductor fin exposes the semiconductor fin in the second recess, and the step of filling the second recess forms a dielectric fin on the semiconductor fin.

15. The method for manufacturing a semiconductor structure according to claim 9, further comprising: After filling the trench, performing a first chemical mechanical polishing process on the second dielectric material layer; as well as After filling the first recess and the second recess, a second chemical mechanical polishing process is performed on the third dielectric material layer.

16. A semiconductor structure comprising: A plurality of first fins are located on a substrate and are longitudinally along a first direction, wherein the first fins include a semiconductor material; a plurality of second fins, located between the first fins and longitudinally along the first direction, wherein the second fins include a first dielectric material layer; a plurality of third fins, located between the first fin and the second fin and longitudinally along the first direction; wherein a first portion of each of the third fins comprises the semiconductor material, and a second portion of each of the third fins comprises a second dielectric material layer, and the second dielectric material layer has the same composition as the first dielectric material layer; and A plurality of gate stacks are located on the first fin, the second fin, and the third fin. The longitudinal direction of the gate stacks is along a second direction, and the second direction is perpendicular to the first direction.

17. The semiconductor structure of claim 16, wherein: The second fin also includes a third dielectric material layer located on the first dielectric material layer, and a fourth dielectric material layer located on the third dielectric material layer, the third dielectric material layer and the first dielectric material layer have different compositions, and the fourth dielectric material layer and the first dielectric material layer have the same composition.

18. The semiconductor structure of claim 16, wherein: The sidewall of the first portion of each of the third fins is coplanar with the sidewall of the second portion of each of the third fins along the first direction.

19. The semiconductor structure of claim 16, wherein: A lower surface of the second portion of each of the third fins is lower than a lower surface of each of the second fins.

20. A semiconductor structure comprising: A semiconductor fin protrudes from a substrate and has a longitudinal direction along a first direction, wherein the semiconductor fin includes a semiconductor layer; a hybrid fin protruding from the substrate and parallel to the semiconductor fin, wherein the hybrid fin comprises the semiconductor layer and a first dielectric layer located on the semiconductor layer; a first dielectric fin protruding from the substrate and parallel to the semiconductor fin, wherein the first dielectric fin comprises the first dielectric layer; a second dielectric fin protruding from the substrate and parallel to the semiconductor fin, wherein the second dielectric fin comprises a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a different composition than the first dielectric layer, and wherein the first dielectric fin does not have the second dielectric layer; and A plurality of conductive gate stacks are located on the semiconductor fin, the first dielectric fin, and the second dielectric fin, and the longitudinal direction of the conductive gate stacks is along a second direction, and the first direction is perpendicular to the second direction.

21. The semiconductor structure of claim 20, wherein: The first dielectric fin is defined by a first width along the second direction, and the second dielectric fin is defined by a second width along the second direction, and the second width is smaller than the second width. 22 . The semiconductor structure of claim 20 , further comprising a third dielectric fin protruding from the substrate and parallel to the conductive gate stack, wherein the third dielectric fin comprises the second dielectric layer buried in the first dielectric layer.

23. The semiconductor structure of claim 22, wherein: A portion of the hybrid fin contacting the third dielectric fin includes the first dielectric layer, and a remaining portion of the hybrid fin does not have the first dielectric layer.

24. The semiconductor structure of claim 23, wherein: The semiconductor layer and the third dielectric fin define sidewall surfaces of the first dielectric layer in the hybrid fin.

25. The semiconductor structure of claim 20, wherein: An upper surface and sidewall surfaces of the second dielectric layer in the second dielectric fin contact the first dielectric layer.

26. The semiconductor structure of claim 20, wherein: The first dielectric layer includes a nitrogen-containing material, and the second dielectric layer includes an oxygen-containing material.

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