Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and its fabrication method. A second trench extending along a second direction is formed in a semiconductor substrate, and U-shaped fins are staggered on both sides of the second trench. Each U-shaped fin has a first trench extending along a first direction. A first source / drain region is formed at the top of the vertical fin portion of the U-shaped fin, and a second source / drain region is formed in the horizontal fin portion of the U-shaped fin. A gate surrounds the vertical fin portion, and embedded wires fill the second trench. This allows the two first source / drain regions, two gates, and one second source / drain region in the U-shaped fin to form two gate-ring transistors. This increases the gate's control over the channel, overcomes the short-channel effect, and thus facilitates smaller feature sizes and higher integration density. Furthermore, the staggered arrangement of the U-shaped fins on both sides of the second trench improves the coupling effect between adjacent second source / drain regions, enhancing device performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the semiconductor field, especially in memory, methods to increase device integration include reducing device feature size and improving cell structure. However, as feature size decreases, small-sized transistors generate severe short-channel effects; therefore, improving the memory cell structure to reduce the area occupied by the memory cell under the same feature size is another effective way to increase device integration.

[0003] Vertical surrounding gate transistors (SGTs) with buried bit lines use increased isolation rules to significantly reduce the difficulty of shallow trench isolation manufacturing. Their process includes lengthy buried bit line process steps, spin-dip dielectric (SOD) process steps, and metal and N-type doped polysilicon process steps to define the transistor gate length. The process is complicated, which leads to a significant decrease in the stability of the threshold voltage of the memory array. Furthermore, due to the limitation of vertical size, it is not possible to reduce the change of threshold voltage (Vth) with a longer channel length.

[0004] Furthermore, as semiconductor devices continue to miniaturize, the spacing between memory cells in Dynamic Random Access Memory (DRAM) becomes increasingly tighter. This often leads to very strong coupling effects between active regions, which can affect device performance and reliability, and even cause data access errors in DRAM.

[0005] Therefore, there is a need for a new semiconductor device and its fabrication method that can reduce the area occupied by the memory cell under the same feature size, simplify the process, enhance the gate's control over the channel, improve the short-channel effect, and also improve the coupling effect between adjacent active regions, thereby improving the device's electrical performance and integration density. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can reduce the area occupied by the memory cell under the same feature size conditions, simplify the process, enhance the gate's control over the channel, improve the short-channel effect and the coupling effect between adjacent active regions, and improve the electrical performance and integration density of the device.

[0007] To achieve the above objectives, the present invention provides a semiconductor device, comprising:

[0008] A semiconductor substrate having an isolation trench extending along a first direction and a second trench extending along a second direction, wherein at least one U-shaped fin is disposed on each side of the second trench arranged in the first direction, the U-shaped fins being staggered on both sides of the second trench in the first direction, each U-shaped fin having a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion, a second source / drain region being formed in the horizontal fin portion, and a first source / drain region being formed in the top end portion of each of the vertical fin portions; a first trench extending along the first direction is defined between the two vertical fin portions of the U-shaped fin, the first trench, the isolation trench, and the second trench communicating on the sidewalls of the second trench; and...

[0009] A gate surrounds the sidewall of the vertical fin portion.

[0010] Optionally, the semiconductor substrate further includes an isolation region with a conductivity type opposite to that of the second source / drain region. The isolation region extends along the second direction to the entire bottom of the U-shaped fin, and the portion of the isolation region extending at the bottom of the first trench is located below the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap with the second source / drain region in height.

[0011] Optionally, the semiconductor device further includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer being located between the gate and the U-shaped fin, and the gate isolation layer filling the first trench above the gate and the isolation trench to bury the gate therein.

[0012] Optionally, the semiconductor device further includes embedded wires buried in the second trench and extending along a second direction, wherein the embedded wires are electrically connected to a second source / drain region in a U-shaped fin on one side of the second trench.

[0013] Optionally, the semiconductor device further includes a conductive contact structure formed in the second trench and disposed between the embedded wire and the corresponding second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the embedded wire. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench.

[0014] Optionally, the semiconductor device further includes a first dielectric layer, which fills the bottom of the second trench and the bottom of the isolation trench, and the embedded wire is located on the portion of the first dielectric layer that fills the second trench.

[0015] Optionally, the semiconductor device further includes a second dielectric layer that fills the second trench, the first trench, and the isolation trench above the first dielectric layer to bury the embedded wire and isolate the gate from the second source / drain region, the embedded wire, and the adjacent U-shaped fin, respectively.

[0016] Optionally, the semiconductor device is a memory, including a plurality of U-shaped fins arranged in an array along the first direction and the second direction, wherein the gates on the vertical fin portions of the plurality of U-shaped fins aligned and arranged in a straight line along the first direction are aligned and electrically connected to each other to form a word line extending along the first direction; and the second source / drain regions of the plurality of U-shaped fins aligned and arranged in a straight line along the second direction are connected to the same buried conductor, the buried conductor forming the bit line of the memory.

[0017] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0018] A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction to form an isolation trench extending along the first direction, a second trench extending along the second direction, and U-shaped fins arranged alternately on both sides of the second trench. Each U-shaped fin has a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of each U-shaped fin. The first trench, the isolation trench, and the second trench are respectively connected on the sidewall of the second trench.

[0019] Forming an embedded conductor in the second trench; and,

[0020] A gate is formed around the vertical fin portion.

[0021] Optionally, before or after forming the embedded wire, a second source / drain region is formed in the horizontal fin portion, and a first source / drain region is simultaneously formed in the top portion of the vertical fin portion. The embedded wire is electrically connected to the second source / drain region, and the gate surrounds the sidewall of the vertical fin portion. Alternatively, after forming the gate, a second source / drain region is formed in the horizontal fin portion, and a first source / drain region is simultaneously formed in the top portion of the vertical fin portion. The embedded wire is electrically connected to the second source / drain region, and the gate surrounds the sidewall of the vertical fin portion.

[0022] Optionally, before forming the embedded wire, a trap ion implantation process is used to implant doped ions into the bottom of the U-shaped fin to form an isolation region extending along the second direction to the entire bottom of the U-shaped fin. The portion of the isolation region extending at the bottom of the first trench is located below the area of ​​the U-shaped fin used to form the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap in height with the area of ​​the U-shaped fin used for the second source / drain region.

[0023] Optionally, before forming the embedded conductor, a first dielectric layer is filled in the second trench and the isolation trench, the embedded conductor is located on the first dielectric layer in the second trench, and the embedded conductor is insulated from the semiconductor substrate through the first dielectric layer.

[0024] Optionally, the step of forming the gate includes:

[0025] A second dielectric layer is filled in the isolation trench, the second trench and the first trench, and the top surface of the second dielectric layer in the first trench is lower than the bottom surface of the first source / drain region;

[0026] A gate dielectric layer is formed on the surface of the second dielectric layer and on the sidewall of the vertical fin portion exposed by the second dielectric layer;

[0027] A gate material is filled in a first trench having the gate dielectric layer and the isolation trench, and the gate material is etched along the first direction to form a gate surrounding the vertical fin portion, the top surface of the gate being lower than the top surface of the vertical fin portion; and,

[0028] A gate isolation layer is filled in the isolation trench, the first trench, and the second trench to bury the gate and achieve isolation between the gate and the second source / drain region and the buried wire.

[0029] Optionally, the semiconductor device is a memory, including a plurality of U-shaped fins arranged along the second direction, wherein the gates on the vertical fin portions of the plurality of U-shaped fins aligned and arranged in a straight line along the first direction are aligned and electrically connected to each other to form word lines extending along the first direction; and the second source / drain regions of the plurality of U-shaped fins aligned and arranged in a straight line along the second direction are connected to the same embedded conductor, the embedded conductor forming the bit lines of the memory.

[0030] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0031] 1. A semiconductor device of the present invention has a second trench extending in a second direction, U-shaped fins being alternately arranged on both sides of the second trench, the U-shaped fins having horizontal fin portions extending in the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portions, a first trench extending in a first direction being defined between the two vertical fin portions of the U-shaped fin, a first source / drain region being formed in the vertical fin portions of the U-shaped fin, a second source / drain region being formed in the horizontal fin portions of the U-shaped fin, a gate surrounding the vertical fin portions of the U-shaped fin, and an embedded conductor. The second trench is filled with U-shaped fins, thereby forming two ring-gate transistors (also called a U-shaped transistor). Compared to planar transistors, on the one hand, the gate surrounding the channel encloses the entire channel region between the first and second source / drain regions, allowing for control of the channel from four sides, improving channel control and suppressing short-channel effects. On the other hand, with the same substrate area, the effective channel length can be increased by increasing the height of the semiconductor pillars between the first and second source / drain regions, overcoming short-channel effects and facilitating smaller feature sizes. Simultaneously, since the second source / drain region is located at the bottom of the formed transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation around the transistor, reducing the device area within the same size, and thus providing higher device integration density in a given space. Furthermore, the staggered arrangement of the U-shaped fins on both sides of the second trench increases the distance between transistors formed by adjacent U-shaped fins, improving the coupling effect between adjacent active regions and enhancing the electrical performance of the device. Furthermore, the conductive contact structure between the embedded conductor and the second source / drain region, or the hexagonal close-packed comb teeth of the embedded conductor, increases the fabrication window for the electrical connection mechanism between the embedded conductor and the second source / drain region.

[0032] 2. The method for fabricating a semiconductor device according to the present invention firstly involves etching a semiconductor substrate along a first direction and a second direction to form a second trench extending along the second direction and U-shaped fins arranged alternately on both sides of the second trench. The U-shaped fins have horizontal fin portions extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portions. A first trench extending along the first direction is defined between the two vertical fin portions of the U-shaped fin. Next, embedded conductive lines are formed in the second trench, and first source / drain regions are formed in the vertical fin portions of the U-shaped fins. In the top portion, a second source / drain region is formed in the horizontal fin portion of the U-shaped fin, and a gate is formed around the vertical fin portion of the U-shaped fin. The embedded wire is electrically connected to the second source / drain region, thereby forming two ring gate transistors based on a U-shaped fin. The process is simple. The arrangement of the first trench in the U-shaped fin and the adjacent isolation trenches and second trenches around the U-shaped fin can avoid the use of enlarged shallow trench isolation rules, greatly reducing the difficulty of shallow trench isolation manufacturing and the process defects of the isolation structure. This is conducive to further miniaturization of product size and improvement of device performance.

[0033] 3. The semiconductor device and its fabrication method of the present invention are applicable to integrated circuit memories. Since the second source / drain region is located at the bottom of the formed transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation between transistors in the array. This reduces the memory cell area within the same size, achieving a cell area of ​​4F. 2 The hexagonal close-packed memory array improves device integration and simplifies the process, significantly reducing the difficulties and process defects in shallow trench isolation manufacturing. Attached Figure Description

[0034] Figure 1A This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0035] Figure 1B yes Figure 1A The diagram shows a top view of the semiconductor device.

[0036] Figure 2A It is along Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of line AA' in the diagram.

[0037] Figure 2B It is along Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of the BB' line in the diagram.

[0038] Figure 2C It is along Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of the CC' line in the diagram.

[0039] Figure 2D It is along Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of the DD' line in the diagram.

[0040] Figure 2E It is along Figure 1A and Figure 1B A schematic diagram of the cross-sectional structure of the EE' line in the diagram.

[0041] Figure 3A This is a top view of a semiconductor device according to another embodiment of the present invention.

[0042] Figure 3B It is along Figure 3A A schematic diagram of the cross-sectional structure of the EE' line in the diagram.

[0043] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to a specific embodiment of the present invention.

[0044] Figure 5 This is a top view of the device structure during step S1 in the fabrication method of a semiconductor device according to an embodiment of the present invention.

[0045] Figures 6A to 6E These are respectively, in one embodiment of the present invention, along Figure 5 Schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0046] Figure 7 This is a top view of the device structure during step S2 in the fabrication method of a semiconductor device according to an embodiment of the present invention.

[0047] Figures 8A to 8E These are respectively, in one embodiment of the present invention, along Figure 7 Schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0048] Figure 9 This is a top view of the device structure during step S3 in the fabrication method of a semiconductor device according to an embodiment of the present invention.

[0049] Figures 10A to 10E These are respectively, in one embodiment of the present invention, along Figure 7 Schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0050] Figure 11 and Figure 13 This is a top view of the device structure during step S4 of the semiconductor device fabrication method according to an embodiment of the present invention.

[0051] Figures 12A to 12E These are respectively, in one embodiment of the present invention, along Figure 11 Schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0052] Figures 14A to 14E These are respectively, in one embodiment of the present invention, along Figure 13 Schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0053] Figures 15A to 15E These are corresponding to another embodiment of the present invention. Figure 9 A schematic diagram of the cross-sectional structure at lines AA', BB', CC', DD', and EE'.

[0054] Figures 16A to 16B These are corresponding to another embodiment of the present invention. Figure 9 A schematic diagram of the cross-sectional structure at the CC' and EE' lines.

[0055] Figure 17 This is a top view of the semiconductor device in another embodiment of the present invention.

[0056] Figures 18A to 18C These are corresponding to another embodiment of the present invention. Figure 1B Schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0057] The reference numerals in the attached figures are as follows:

[0058] 101-U-shaped fin; 1011-Vertical fin portion of the U-shaped fin (i.e., the fin on the sidewall of the first groove 100a); 1012-Horizontal fin portion of the U-shaped fin (i.e., the fin at the bottom of the first groove 100a); 100a-First groove; 100b-Second groove; 100c-Isolation groove; 100d-Wire groove; 101c-Isolation region; 101d-Second source / drain region; 101s-First source / drain region; 102-First dielectric layer; 103-Conductive contact structure; 104-Embedded wire; 104a-Comb substrate of the embedded wire; 10 4b - The comb teeth of the embedded wire; 105 - The second dielectric layer; 106 - The gate dielectric layer; 107 - The gate; 108 - The gate isolation layer; H - The initial thickness of the semiconductor substrate 100; H1 - The depth of the first trench 100a in the U-shaped fin 101; H2 - The depth of the second trench 100b (including the depth at the point where the second trench 100b communicates with the first trench 100a); H3 - The height of the horizontal fin portion 1012 of the U-shaped fin 101 (i.e., the depth difference between the depth of the first trench 100a and the depth of the second trench 100b in the U-shaped fin 101). Detailed Implementation

[0059] To make the objectives and features of the present invention more apparent and understandable, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the embodiments described. It should be noted that, in this document, "the first groove in the U-shaped fin" refers to the groove between the two vertical fin portions of the U-shaped fin; and "the isolation groove on the outer side of the U-shaped fin" refers to the groove extending along the first direction on the outer sidewall of the U-shaped fin. Furthermore, it should be readily understood that the meanings of "on..." and "on..." in this document should be interpreted in the broadest sense, meaning not only "directly on something" in the absence of intermediate features or intermediate layers, but also "on something" in the presence of intermediate features or intermediate layers.

[0060] Figure 1A This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 1B yes Figure 1A A top view of the semiconductor device shown. Figure 2A It is along Figure 1A A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 2B It is along Figure 1A A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 2C It is along Figure 1A A schematic diagram of the cross-sectional structure of the CC' line in the diagram; Figure 2D It is along Figure 1A A schematic diagram of the cross-sectional structure of the DD' line in the diagram; Figure 2E It is along Figure 1A A schematic diagram of the cross-sectional structure of the EE' line in the diagram. Figure 1A To clearly show the buried structures in the semiconductor device, such as the gate, second source / drain region, buried wires, and conductive contact structures, the semiconductor substrate and film layers such as the first dielectric layer, second dielectric layer, and gate isolation layer located below the buried wires are omitted, so that the gate, second source / drain region, buried wires, and conductive contact structures are displayed on the outside. Figures 2A to 2E The cross-sectional structure in the image shows the omitted semiconductor substrate, first dielectric layer, second dielectric layer, gate isolation layer, and other film layers.

[0061] Please refer to Figure 1A , Figure 1B as well as Figures 2A to 2E An embodiment of the present invention provides a semiconductor device including a semiconductor substrate 100 having a U-shaped fin 101, a first source / drain region 101s, a second source / drain region 101d, a buried wire 104, a conductive contact structure 103, and a gate 107.

[0062] The semiconductor substrate 100 can be made of any suitable material well known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The semiconductor substrate 100 has at least one second trench 100b extending along a second direction and an isolation trench 100c extending along a first direction. Each second trench 100b has at least one U-shaped fin 101 arranged alternately on both sides along the first direction. The second trench 100b exposes the sidewalls of all the U-shaped fins 101 extending along the second direction on both sides. The isolation trench 100c is located at the outer sidewall of each U-shaped fin 101 extending along the first direction to isolate the U-shaped fin 101 from surrounding devices. The isolation trench 100c exposes the outer sidewall of the U-shaped fin 101 extending along the first direction. Two adjacent isolation trenches 100c and two adjacent second trenches 100b define one U-shaped fin 101.

[0063] The U-shaped fin 101 has a horizontal fin portion 1012 extending along a second direction and vertical fin portions 1011 vertically disposed at both ends of the horizontal fin portion 1012. A first groove 100a extending along a first direction is defined between the two vertical fin portions 1011. A second source / drain region 101d is formed in the horizontal fin portion 1012, and a first source / drain region 101s is formed at the top of each vertical fin portion 1011. The first groove 100a in the U-shaped fin 101 on one side of the second groove 100b is aligned with an isolation groove 100c on the outer wall of the U-shaped fin 101 on the other side of the second groove 100b. The first groove 100a and the isolation groove 100c communicate with the second groove 100b on the side wall of the second groove 100b.

[0064] Furthermore, the isolation trench 100c and the second trench 100b are used for isolation between adjacent U-shaped fins, while the first trench 100a is used to isolate the gates on the two vertical fin portions 1011 of the U-shaped fin. In this embodiment, the depth of the isolation trench 100c is equal to the depth H2 of the second trench 100b, meaning the top surface of the semiconductor substrate 100 in the isolation trench 100c is flush with the top surface of the semiconductor substrate 100 in the second trench 100b. The depth H1 of the first trench 100a in the U-shaped fin 101 is less than the depths of the isolation trench 100c and the second trench 100b, and the depth H1 of the first trench 100 is equal to the height of the semiconductor substrate 100 minus the bottom surface height of the second source / drain region 101d. This depth H1 of the first trench 100 determines the size of the second source / drain region 101d and the first source / drain region 101s, as well as the contact area of ​​the embedded wire 104. The depth of the second trench 100b is H2 globally, which is essentially equal to the height of the semiconductor substrate 100. In other embodiments of the present invention, please refer to... Figures 18A to 18C The depth of the isolation trench 100c can also be equal to the depth H1 of the first trench 100a in the U-shaped fin 101, and the depth of the second trench 100b is H2 all over the world. In this case, the top surface of the semiconductor substrate 100 in the isolation trench 100c is flush with the top surface of the horizontal fin portion 1012, and the formed isolation region 101c also extends into the semiconductor substrate 100 at the bottom of the isolation trench 100c.

[0065] The U-shaped fin 101 is used to form two ring gate transistors sharing a second source / drain region. The first source / drain region 101s and the second source / drain region 101d can be formed by the same ion implantation process. The top surface of the first source / drain region 101s is the top surface of the vertical fin portion 1011, and the top surface of the second source / drain region 101d is the top surface of the horizontal fin portion 1012 of the U-shaped fin 101 (i.e., the bottom surface of the first trench 100a). Furthermore, depending on the transistor structure with different conductivity types, the first source / drain region 101s and the second source / drain region 101d are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doping ions in the first source / drain region 101s and the second source / drain region 101d are N-type doping ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doping ions in the first source / drain region 101s and the second source / drain region 101d are P-type doping ions, such as boron (B) ions and boron fluoride (BF2). + Gallium (Ga) ions, indium (In) ions. In this embodiment, the first source / drain region 101s can be a source region, and the second source / drain region 101d can be a drain region.

[0066] The embedded conductor 104 is embedded in the second trench 100b and extends along the second direction. The embedded conductor 104 may be straight, filling the bottom of the second trench 100b and extending along the second direction to the entire length of the second trench 100b. The embedded conductor 104 is insulated from the semiconductor substrate 100 through the first dielectric layer 102 and electrically connected to the second source / drain region 101d through the conductive contact structure 103. In this configuration, the top surfaces of the embedded conductor 104 and the conductive contact structure 103 can both be flush with the top surface of the second source / drain region 101d. In this case, the sidewall of the conductive contact structure 103 is relatively high, and the contact area with the second source / drain region 101d in the horizontal fin portion 1012 of the U-shaped fin 101 is relatively large. Alternatively, the top surfaces of the embedded conductor 104 and the conductive contact structure 103 can be flush with and both lower than the top surface of the second source / drain region 101d. The second dielectric layer 105 can compensate for the height difference between the top surface of the embedded conductor 104 and the top surface of the second source / drain region 101d. The first dielectric layer 102 fills the second trench 100b and has a certain thickness. When the depth of the isolation trench 100c outside the U-shaped fin 101 is equal to the depth of the second trench 100b, the first dielectric layer 102 also fills the bottom of the isolation trench 100c outside the U-shaped fin 101. The portion of the first dielectric layer 102 filling the second trench 100b can be linear (e.g., ...). Figures 15C to 15E As shown), L-shaped (as shown) Figures 10C to 10E ) or U-shaped (such as Figures 16A to 16B The structure shown has the first dielectric layer 102 extending to the boundary between the second source / drain region 101d and the second trench 100b on a portion of the bottom surface of the embedded conductor 104.

[0067] In this embodiment, please refer to Figures 2C to 2E as well as Figures 10C to 10EThe first dielectric layer 102 fills the second trench 100b in an L-shaped structure. The portion of the first dielectric layer 102 filling the second trench 100b and the U-shaped fin 101 form a straight wire trench 100d. The embedded wire 104 and the conductive contact structure 103 are arranged in the wire trench 100d, sequentially approaching the second source / drain region 101d from a distance along the first direction. The portion of the first dielectric layer 102 filling the second trench 100b extends continuously from the sidewall surface of the embedded wire 104 away from the second source / drain region 101d towards the bottom surface of the embedded wire 104, until it reaches the second source / drain region 101d. The sidewall surface of 01d is exposed by the second trench 100b; the conductive contact structure 103 is used to realize the electrical connection between the embedded wire 104 and the second source / drain region 101d. The conductive contact structure 103 is located in the second trench 100b and between the second source / drain region 101d and the embedded wire 104. One sidewall of the conductive contact structure 103 is in contact with the sidewall surface of the second source / drain region 101d, and the other sidewall of the conductive contact structure 103 is in contact with the sidewall surface of the embedded wire 104. The bottom surface of the conductive contact structure 103 is insulated from the surface of the semiconductor substrate 100 at the bottom of the second trench 100b by a first dielectric layer 102.

[0068] In other embodiments of the present invention, when the first dielectric layer 102 fills the second trench 100b in a partially linear structure, please refer to... Figures 15C to 15EAs shown, the top surface of the portion of the first dielectric layer 102 filling the second trench 100b is lower than the top surface of the second source / drain region 101d (i.e., the top surface of the horizontal fin portion 1012 of the U-shaped fin 101) and higher than the bottom surface of the second source / drain region 101d, so that the bottom of the embedded wire 104 and the conductive contact structure 103 formed are isolated from the U-shaped fin 101 below the second source / drain region 101d. The second trench 100b above the first dielectric layer 102 serves as a straight wire trench 100d. The embedded wire 104 and the... The conductive contact structure 103 is disposed in the wire trench 100d, sequentially approaching the corresponding second source / drain region 101d along the first direction from far to near. For example, the embedded wire 104 first fills the wire trench 100d. Because the linewidth of the embedded wire 104 is smaller than the opening size of the wire trench 100d, a contact trench is formed between the embedded wire 104 and the second source / drain region 101d. The conductive contact structure 103 only fills the portion of the contact trench corresponding to the second source / drain region 101d, while the remaining portion of the contact trench is filled by the subsequent second dielectric layer 105. When the first dielectric layer 102 fills the second trench 100b in a U-shaped structure, please refer to... Figures 16A to 16B As shown, the first dielectric layer 102 fills the second trench 100b to partially form a straight wire trench 100d. The embedded wire 104 fills the wire trench 100d. A contact hole is formed by etching away the first dielectric layer 102 between the embedded wire 104 and the second source / drain region 101d. The conductive contact structure 103 fills the contact trench, realizing the electrical connection between the embedded wire 104 and the second source / drain region 101d.

[0069] Furthermore, the embedded conductor 104 can be formed using processes such as vapor deposition, electroplating, chemical vapor deposition, and atomic layer deposition. It can be a single-layer structure or a stacked structure. The stacked structure, for example, includes two layers: a metal bottom layer and a polycrystalline silicon top layer. The metal bottom layer can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold, but is not limited thereto. The polycrystalline silicon top layer can be a heavily doped polycrystalline silicon layer, such as an N-type doped polycrystalline silicon layer, or a metal silicide layer formed by reacting with polycrystalline silicon. The material of the first dielectric layer 102 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive contact structure 103 can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold.

[0070] It should be noted that, in another embodiment of the present invention, the conductive contact structure 103 can be omitted, and the embedded wire 104 can be replaced from a straight type with a comb-like structure. For details, please refer to [link / reference needed]. Figure 17 The first dielectric layer 102, which fills a portion of the second trench 100b, has a linear conductor trench that is adapted to be a comb-shaped conductor trench (not shown). The comb-shaped conductor trench has a comb-shaped base opening that extends along the second direction to the entire length of the second trench 100b. The comb-shaped tooth opening extends from the comb-shaped base opening to the sidewall of the second source / drain region 101d, thereby making the embedded conductor 104 have a comb-shaped structure. The embedded conductor 104 includes a comb base 104a and comb teeth 104b. The comb base 104a is located in the second groove 100b and extends along the second direction, that is, the comb base 104a fills the comb base opening portion of the comb-shaped conductor groove 100d. The comb teeth 104b extend from the comb base 104a along the first direction to the sidewall surface of the corresponding second source / drain region 101d, that is, the comb teeth 104b fill the comb tooth opening portion of the conductor groove. Thus, the embedded conductor 104 can directly make electrical contact with the second source / drain region 101d through its comb teeth 104b, thereby saving on the manufacturing process of the conductive contact structure 103, further simplifying the process, and reducing process defects.

[0071] It should be understood that in the above embodiments, the top surface of the embedded conductor 104 is flush with the top surface of the second source / drain region 101d. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the top surface of the embedded conductor 104 may be lower than the top surface of the second source / drain region 101d. This height difference can be made up by the second dielectric layer 105 in the future.

[0072] The second dielectric layer 105 fills the isolation trench 100c, the first trench 100a, and the second trench 100b above the first dielectric layer 102. The top surface of the portion of the second dielectric layer 105 filling the isolation trench 100c, the first trench 100a, and the second trench 100b is flush with the surface, providing a flat bottom surface for the formation of the gate 107. The second dielectric layer 105 serves two purposes: firstly, to bury the buried conductor 104 within it; and secondly, to achieve isolation between the gate 107, the buried conductor 104, the second source / drain region 101d, and the semiconductor substrate 100 at the bottom of the isolation trench 100c. Furthermore, the thickness of the second dielectric layer 105 filling the first trench 100a and the isolation trench 100c determines the height of the bottom surface of the gate 107; therefore, the deposition thickness of the second dielectric layer 105 can be set according to the required bottom surface height of the gate 107.

[0073] The gate 107 surrounds the sidewall of the vertical fin portion 1011. Gates 107 are respectively surrounded on the two vertical fin portions 1011 of the U-shaped fin 101. The top surface of the gate 107 is lower than the top surface of the vertical fin portion 1011 of the U-shaped fin 101, and the gate 107 can partially overlap with the first source / drain region 101s in height. Thus, the two first source / drain regions 101s, the two surrounding gates 107, and the second source / drain region 101d on the U-shaped fin 101 form two ring-gate transistors sharing the second source / drain region 101d. A gate dielectric layer 106 is also formed between the gate 107 and the U-shaped fin 101, which serves to isolate the gate 107 from the vertical fin portions 1011 of the U-shaped fin 101. To prevent leakage between two adjacent gates 107, the semiconductor device further includes a gate isolation layer 108 that fills the first trench 100a and the second trench 100b above the second dielectric layer 105 and exposes the top surface of the first source / drain region 101s, thereby covering and burying the gates 107. Preferably, the top surface of the gate isolation layer 108 is flush with the top surface of the vertical fin portion 1011 of the U-shaped fin 101, providing a flat operating platform for subsequent processes. The gate dielectric layer 106 can be formed using processes such as thermal oxidation (dry or wet oxidation), chemical vapor deposition, or atomic layer deposition. The gate film layer corresponding to the gate 107 can be formed using physical vapor deposition or chemical vapor deposition. The gate material can be polycrystalline silicon or a metal gate material. When the gate 107 is made of polycrystalline silicon, the gate dielectric layer 106 can be made of silicon dioxide. When the gate 107 is made of a metal gate material, the gate dielectric layer 106 can be made of a high-k dielectric with a dielectric constant K greater than 7. The gate 107 can be a stacked structure, which includes a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 106. The gate isolation layer 108 can be formed by processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The materials of the gate isolation layer 108 include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0074] In the semiconductor device of the present invention, the first trench 100a in the U-shaped fin 101 can be a rounded U-shaped trench or a right-angled U-shaped trench, thereby forming a vertical conductive channel along the current conduction direction (i.e., the current flow direction from a first source / drain region 101s to a second source / drain region 101d on each side of the first trench 100a). Compared with planar transistors, the vertical channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillar (i.e., the vertical fin portion 1011) between the first source / drain region 101s and the second source / drain region 101d, overcoming the short-channel effect and facilitating the realization of smaller feature sizes. Moreover, since the gate 107 surrounds the vertical fin portion 1011, the channel between the first source / drain region 101s and the second source / drain region 101d can be controlled on all four sides, improving the channel control capability and thus effectively improving the short-channel effect of the transistor. Furthermore, since a U-shaped fin can form two transistors with a common second source / drain region, the device density can be increased in the same area.

[0075] Furthermore, when the semiconductor device of the present invention has a plurality of adjacent U-shaped fins 101, in order to achieve isolation between adjacent transistor structures, an isolation region 101c extending along the second direction to the entire semiconductor substrate 100 is also formed in the bottom of the U-shaped fins 101, and the portion of the isolation region 101c extending at the bottom of the first trench 100a is located below the second source / drain region 101d, and the portions of the isolation region 101c extending on both sides of the first trench 100a at least partially overlap with the second source / drain region 101d in height. The isolation region 101c and the second source / drain region 101d can form a PN junction, that is, the transistor manufactured based on the U-shaped fins is isolated from surrounding adjacent components (e.g., the isolation trench 100 from the bottom substrate 100 or the U-shaped fins adjacent to each other in the second direction) through PN junction isolation. The doping type of the isolation region 101c is determined by the conductivity type of the ions doped in the second source / drain region 101d to be formed. For example, in this embodiment, if the ions doped in the second source / drain region 101d are N-type, then the ions doped in the isolation region 101c are P-type. The doping depth of the isolation region 101c needs to be adjustable according to the actual situation and must meet the following condition: the portion of the isolation region 101c extending at the bottom of the first trench 100a needs to be located below the second source / drain region 101d.

[0076] Furthermore, it should be noted that the semiconductor device in this embodiment is a general-purpose device other than a memory, such as... Figure 1A , 1BAs shown in Figure 2E, the gates 107 on both sides of the second trench 100b are discrete. That is, the gates 107 surrounding the vertical fin portion 1011 on one side of each first trench 100a are interrupted at the second trench 100b and insulated from each other by the gate isolation layer 108 filled in the second trench 100b. The embedded wires 104 of the adjacent U-shaped fins 101 on the same side of the second trench 100b can be interrupted at the isolation trench 100c on the outside of each U-shaped fin 101 and insulated from each other by the second dielectric layer 105 filled in the first trench 100a. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the semiconductor device can also be an integrated circuit memory. The first direction is the word line direction / row direction of the integrated circuit memory, and the second direction is the bit line direction / column direction of the integrated circuit memory. In this case, the gates 107 on both sides of the second trench 100b need to be connected as one unit, which serves as a word line of the integrated circuit memory. Specifically, please refer to Figure 3A and Figure 3B The semiconductor device may include a plurality of U-shaped fins 101 arranged in an array along the first direction and the second direction. The gates 107 on the vertical fin portions 1011 of the plurality of U-shaped fins 101 aligned along the first direction are aligned and electrically connected to each other to form a word line extending along the first direction. That is, the gates 107 surrounding the vertical fin portions 1011 that are located on both sides of the second trench 100b and aligned extend continuously along the first direction and are uninterrupted when passing through the second trench 100b. The second source / drain regions 101d of the plurality of U-shaped fins 101 aligned along the second direction are connected to the same buried conductor 104, which constitutes the bit line of the memory. Alternatively, it can be said that the embedded wires 104 of all the U-shaped fins 101 on the same side of the second trench 100b are connected as a whole, serving as a bit line of the memory. The embedded wires 104 in each second trench 100b extend along the second direction and are uninterrupted as they pass through a first trench 100a outside each U-shaped fin 101.

[0077] It should be understood that in the above embodiments, the first direction and the second direction are perpendicular, and the projection of the U-shaped fin 101 onto the surface of the semiconductor substrate 100 is rectangular. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the first direction and the second direction may also form an angle of 5 degrees to 85 degrees. In this case, the projection of the U-shaped fin 101 onto the surface of the semiconductor substrate 100 is a parallelogram that is not rectangular, thereby further improving the integration density.

[0078] In summary, the semiconductor device of the present invention has a second trench extending along a second direction, with U-shaped fins alternately arranged on both sides of the second trench. Each U-shaped fin has a horizontal fin portion extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion. A first trench extending along a first direction is defined between the two vertical fin portions of the U-shaped fin. A first source / drain region is formed in the vertical fin portion of the U-shaped fin, and a second source / drain region is formed in the horizontal fin portion of the U-shaped fin. A gate surrounds the U-shaped fin. On the vertical fin portion, embedded wires fill the second trench, thereby forming two ring-gate transistors (also called a U-shaped transistor) based on a U-shaped fin. Compared to planar transistors, on the one hand, the gate surrounding the channel can control the channel from four sides, improving the control over the channel and suppressing the short-channel effect; on the other hand, under the premise of occupying the same substrate area, the effective channel length can be increased by increasing the height of the semiconductor pillar between the first source / drain region and the second source / drain region, overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. At the same time, since the second source / drain region is located at the bottom of the formed transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation around the transistor, reducing the device area under the same size, and thus providing higher device integration in a given space. Furthermore, since the U-shaped fins on both sides of the second trench are staggered, the distance between adjacent active regions is increased, which can improve the coupling effect between adjacent active regions and improve the electrical performance of the device. Furthermore, the conductive contact structure between the embedded conductor and the second source / drain region, or the hexagonal close-packed comb teeth of the embedded conductor, increases the fabrication window for the electrical connection mechanism between the embedded conductor and the second source / drain region.

[0079] The following will take the manufacturing of integrated circuit memories such as dynamic random access memory as an example, and combine it with... Figure 4 , Figure 5 , Figures 6A to 6E , Figure 7 , Figures 8A to 8E , Figure 9 as well as Figures 10A to 10E This section details the method for fabricating the semiconductor device of the present invention. The first direction refers to the word line direction / row direction, and the second direction refers to the bit line direction / column direction.

[0080] Please refer to Figure 4 An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0081] S1, a semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form an isolation trench extending along the first direction, a second trench extending along the second direction, and U-shaped fins staggered on both sides of the second trench. Each U-shaped fin has a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of each U-shaped fin. The first trench and the isolation trench (which communicate with the second trench on the sidewall of the second trench respectively) are connected.

[0082] S2, forming a first source / drain region and a second source / drain region, the first source / drain region being formed in the top end of the vertical fin portion, and the second source / drain region being formed in the horizontal fin portion;

[0083] S3, forming an embedded conductor in the second trench, the embedded conductor extending along a second direction and electrically connected to the portion of the horizontal fin portion used to form the second source / drain region; and

[0084] S4, forming a gate surrounding the sidewall of the vertical fin portion.

[0085] Figure 5 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S1. Figure 6A In order to perform step S1 along Figure 5 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 6B In order to perform step S1 along Figure 5 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 6C In order to perform step S1 along Figure 5 A schematic diagram of the cross-sectional structure of the CC' line in the diagram; Figure 6D In order to perform step S1 along Figure 5 A schematic diagram of the cross-sectional structure of the DD' line in the diagram; Figure 6E In order to perform step S1 along Figure 5 A schematic diagram of the cross-sectional structure of the EE' line. Please refer to... Figure 5 , Figures 6A-6EIn step S1, firstly, a flat semiconductor substrate 100 is provided. The semiconductor substrate 100 provides an operating platform for subsequent processes and can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Its initial thickness is H, which is the height difference between the upper and lower surfaces of the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. Then, the semiconductor substrate 100 is etched along a first direction and a second direction, respectively, to form multiple isolation trenches 100c and multiple second trenches 100b extending along the second direction in the semiconductor substrate 100. Two adjacent second trenches 100b and two adjacent isolation trenches 100c define a U-shaped fin 101. Multiple U-shaped fins 101 are formed on both sides of each second groove 100b arranged along the first direction, and the U-shaped fins 101 on both sides of each second groove 100b are arranged in an alternating manner. Each second groove 100b exposes the sidewalls of the U-shaped fins 101 on both sides extending along the second direction, and each isolation groove 100c exposes the outer sidewalls of the U-shaped fins 101 on both sides extending along the first direction. Each of the U-shaped fins 101 has a first groove 100a extending along a first direction. The first groove 100a on one side of each second groove 100b is aligned with an isolation groove 100c on the outer wall of the U-shaped fin 101 on the other side of the second groove 100b. The ends of the first groove 100a and the isolation groove 100c extending along the first direction extend into the second groove 100b, communicating with the second groove 100b at its side wall. Furthermore, in this embodiment, the depth H1 of the first trench 100a in the U-shaped fin 101 is less than the depth H2 of the second trench 100b, and the depth of the isolation trench 100c is equal to the depth of the second trench 100b. Therefore, the semiconductor substrate 100 can be etched along the second direction to form a plurality of linear second trenches 100b extending along the second direction and arranged side by side. A complete fin is defined between adjacent second trenches 100b. Then, the complete fin is etched along the first direction, and the etching depth is equal to the depth of the second trench 100b, to form the initial fin for forming the U-shaped fin 101 and the isolation trench 100c extending along the first direction outside the initial fin. After that, the initial fin is etched to form the U-shaped fin 101 with the first trench 100a. The specific process is as follows:

[0086] Step 1: A first hard mask pattern (not shown) is formed on the semiconductor substrate 100 to define multiple parallel second trenches 100b, such that the first hard mask pattern can cover and protect the semiconductor substrate 100 region corresponding to the U-shaped fin 101 while exposing the semiconductor substrate 100 region corresponding to the second trenches 100b. The first hard mask pattern can be a stacked structure having an oxide layer (not shown) and a nitride layer (not shown). More specifically, the oxide layer and the nitride layer can be sequentially formed on the semiconductor substrate 100 using a deposition process or the like. Further, a photoresist (not shown) can be coated onto the surface of the nitride layer, and an exposure and development process can be performed to form a photoresist pattern (not shown). The photoresist pattern can expose the area on the semiconductor substrate 100 where the second trench 100b is to be formed, and the exposed portions can have a side-by-side linear arrangement, for example, the exposed portions can be parallel to each other. Then, the nitride layer and the oxide layer can be sequentially etched using an etching process that utilizes the photoresist pattern as an etching mask to form a first hard mask pattern. Afterwards, the photoresist pattern is removed.

[0087] Step 2: The semiconductor substrate 100 is etched by using the first hard mask pattern as an etching mask to form multiple second trenches 100b with a depth of H2. The semiconductor substrate 100 between two adjacent second trenches 100b forms a complete fin, that is, the second trench 100b exposes the sidewalls of the complete fin extending along the second direction.

[0088] Step 3: A sacrificial layer can be formed on the entire structure to fill the second trench 100b. The material of the sacrificial layer is different from that of the semiconductor substrate 100 to facilitate subsequent removal, such as silicon oxide, silicon nitride, or silicon oxynitride. Subsequently, a chemical mechanical planarization process can be used to remove the first hard mask pattern and the sacrificial layer above it to provide a flat process surface for subsequent processes.

[0089] Step 4: A second hard mask pattern (not shown) can be formed on the remaining sacrificial layer and semiconductor substrate 100. The second hard mask pattern defines multiple linear isolation trenches 100c extending side-by-side along the first direction, such that the second hard mask pattern can expose the semiconductor substrate 100 corresponding to the isolation trenches 100c while covering and protecting other areas. For example, the exposed portions can be parallel to each other. The formation process of the second hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be repeated here. The isolation trenches 100c defined by the second hard mask pattern on both sides of the same second trench 100b are staggered.

[0090] Step 5: The semiconductor substrate 100 is etched using an etching process that utilizes the second hard mask pattern as an etching mask to an etching depth of H2, forming isolation trenches 100c and initial fins for fabricating U-shaped fins. The isolation trenches 100c on both sides of the second trench 100b are staggered, meaning that within the area defined by three adjacent second trenches 100b, there are no isolation trenches 100c arranged on the same straight line along the first direction. Essentially, this step involves cutting the complete fins between two adjacent second trenches 100b using isolation trenches 100c of depth H2 to form staggered initial fins for fabricating U-shaped fins.

[0091] Step 6: The isolation trench 100c can be filled with a sacrificial layer. Then, a chemical mechanical planarization process can be used to remove the second hard mask pattern and the sacrificial layer above it to provide a flat process surface for subsequent processes.

[0092] Step 7: A third hard mask pattern (not shown) can be formed on the sacrificial layer and the semiconductor substrate 100. The third hard mask pattern is used to define multiple linear first trenches 100a that extend side by side along the first direction, such that the third hard mask pattern can expose the semiconductor substrate 100 corresponding to the first trenches 100a while covering and protecting other areas. For example, the exposed portions can be parallel to each other. The formation process of the third hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be repeated here. The position of the first trenches 100a defined by the third hard mask pattern is exactly complementary to the position of the isolation trenches 100c defined by the second hard mask pattern. The isolation trenches 100c on one side of the first trenches 100b are aligned with the corresponding first trenches 100a on the other side and arranged on the same straight line extending along the first direction.

[0093] Step 8: The semiconductor substrate 100 is etched using an etching process that utilizes the third hard mask pattern as an etching mask, with an etching depth of H1, to form a plurality of U-shaped fins 101 staggered on both sides of the second trench 100b. Each U-shaped fin 101 has a first trench 100a extending along a first direction. At this time, the first trench 100a in the U-shaped fin 101 on one side of each second trench 100b is aligned with the isolation trench 100c on the outer wall of the U-shaped fin 101 on the other side of the second trench 100b and arranged on the same straight line extending along the first direction. Each of the U-shaped fins 101 has a horizontal fin portion 1012 extending along the second direction and a vertical fin portion 1011 vertically disposed at both ends of the horizontal fin portion 1012. The groove defined between the two vertical fin portions 1011 is the first groove 100a extending along the first direction in the U-shaped fin 101. The horizontal fin portion 1012 is used to subsequently form the second source / drain region 101d with a height of H3. The vertical fin portion 1011 is used to subsequently form the first source / drain region 101s and the gate 107.

[0094] Step 9: The third hard mask pattern and the remaining sacrificial layer can be removed to expose the surface of the semiconductor substrate 100. The process for removing the sacrificial layer can be a wet etching process, and the process for removing the third hard mask pattern can be a chemical mechanical planarization process or a wet etching process.

[0095] It should be noted that in the above steps, the second groove 100b is formed first, then the isolation groove (i.e., the isolation groove 100c) with the same depth as the second groove 100b is formed, and then the first groove 100a is formed. However, the technical solution of the present invention is not limited to this. The formation order of the first groove 100a, the isolation groove 100c and the second groove 100b can also be adjusted adaptively. For example, the portion of the first groove 100a located in the U-shaped fin 101 can be formed first, and then the isolation groove 100c and the second groove 100b can be formed simultaneously. At this time, the mask used to form the second groove 100b has the pattern of the second groove 100b and the isolation groove 100c. The specific process is similar to that described above and will not be repeated here.

[0096] Furthermore, it should be noted that, Figure 5 The first trench 100a extending in the direction of extension (i.e., the first direction) and the second trench 100b extending in the direction of extension (i.e., the second direction) shown are perpendicular. The resulting U-shaped fins 101 have their bottom surfaces arranged in a rectangular, island-like pattern on the semiconductor substrate 100. This reduces the need for rotation of the semiconductor substrate 100 in subsequent processes, which is beneficial for minimizing wafer rotation and alignment operations and reducing the difficulty of device fabrication. In other embodiments of the present invention… Figure 5The first and second directions involved can also be non-perpendicular, but rather at an angle of 5 to 85 degrees. The bottom surface of the U-shaped fin 101 formed by this is a parallelogram and is distributed in an island-like manner. This allows for more effective use of the active area, resulting in a smaller transistor unit area, which is beneficial for manufacturing memories with higher storage density.

[0097] It should be understood that in this embodiment, the depth of the isolation trench 100c is the same as the depth of the second trench 100b. Therefore, two etching processes with different depths are required along the first direction to form the isolation trench 100c and the first trench 100a, respectively. However, the technical solution of the present invention is not limited to this. For other embodiments of the present invention, please refer to... Figures 14A to 14D The depth of the isolation trench 100c can also be the same as the depth of the first trench 100a. This allows for a single etching depth along the first direction to simultaneously isolate both trench 100c and the first trench 100a. In this case, the mask used to form the first trench 100a contains patterns of both the isolation trench 100c and the first trench 100a, thus eliminating the need for a mask and simplifying the process. The specific method is similar to the above and will not be repeated here. In this case, on one side of the second trench 100b, the area defined by every three adjacent trenches of depth H1 is the U-shaped fin 101. The middle trench of the three adjacent trenches is the first trench 100a, and the other two are the isolation trenches 100c. On the other side of the second trench 100b, the middle trench of these three adjacent trenches is the isolation trench 100c, and the other two are the first trenches 100a, resulting in an alternating arrangement of the U-shaped fins 101 on both sides of the second trench 100b. Subsequently, when forming the first source / drain region 100s and the second source / drain region 100d, the first groove 100a between the vertical fin portions 1011 is partially or completely blocked by staggered blocking on both sides of the second groove 100b, thereby ultimately presenting U-shaped fins 101 staggered on both sides of the second groove 100b.

[0098] Figure 7 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S2. Figure 8A In order to perform step S2 along Figure 7 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 8B In order to perform step S2 along Figure 7 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 8C In order to perform step S2 along Figure 7 A schematic diagram of the cross-sectional structure of the CC' line in the diagram; Figure 8D In order to perform step S2 along Figure 7 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 8E In order to perform step S2 along Figure 7 A schematic diagram of the cross-sectional structure of the CC' line. Please refer to... Figure 7 , Figures 8A-8E In step S2, firstly, electrical isolation between the two ring-gate transistors fabricated based on the U-shaped fin 101 and surrounding components can be achieved using PN junction isolation technology. Specifically, a trap ion implantation process can be used to implant ions of the opposite type to the second source / drain region 101d to be formed on both sides of the second trench 100b into the bottom of the semiconductor substrate 100, forming an isolation region 101c. The isolation region 101c and the subsequent second source / drain region 101d can form a PN junction, that is, isolation between the semiconductor device and adjacent peripheral components is achieved through PN junction isolation. The doping type of the isolation region 101c is determined by the conductivity type of the ions doped in the second source / drain region 101d of the transistor to be formed. For example, in this embodiment, if the ions doped in the formed second source / drain region 101d are N-type, then the ions doped in the isolation region 101c are P-type. The doping depth of the isolation region 101c needs to be adjustable according to the actual situation, and must meet the following condition: the portion of the isolation region 101c extending from the bottom of the first trench 100a in the U-shaped fin 101 needs to be located below the subsequently formed second source / drain region 101d. Then, the same ion implantation process can be used to perform source / drain ion doping on the vertical fin portions 1011 on both sides of the first trench 100a and the horizontal fin portion 1012 at the bottom of the first trench 100a to form the first source / drain region 101s located at the top of the vertical fin portion 1011 of the U-shaped fin 101 and the second source / drain region 101d located in the horizontal fin portion 1012 of the U-shaped fin 101. Furthermore, depending on the transistor structure of different conductivity types, the first source / drain region 101s and the second source / drain region 101d are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doping ions in the first source / drain region 101s and the second source / drain region 101d are N-type doping ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doping ions in the first source / drain region 101s and the second source / drain region 101d are P-type doping ions, such as boron (B) ions and boron fluoride (BF2). +The ions are gallium (Ga) ions and indium (In) ions. In this embodiment, the first source / drain region 101s and the second source / drain region 101d are formed using the same process, eliminating the need for step-by-step ion implantation. On the one hand, forming the first source / drain region 107b and the second source / drain region 107a in one ion implantation process is simple, simplifying the process flow and saving production costs. On the other hand, the ion implantation process is not limited by the trench depth, significantly reducing the difficulty of ion implantation manufacturing. At the same time, changing the trench depth does not require changing the ion implantation process, which is beneficial for adapting to changes in product size.

[0099] Figure 9 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S3. Figure 10A and Figure 15A In order to perform step S3 along Figure 9 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 10B and 15B In order to perform step S3 along Figure 9 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 10C , Figure 15C and Figure 16A In order to perform step S3 along Figure 9 A schematic diagram of the cross-sectional structure of the CC' line in the diagram; Figure 10D , Figure 15D In order to perform step S3 along Figure 9 A schematic diagram of the cross-sectional structure of the DD' line in the diagram; Figure 10E , Figure 15E and Figure 16B In order to perform step S3 along Figure 9 A schematic diagram of the cross-sectional structure of the EE' line. Please refer to... Figure 9 , Figures 10A-10E , Figures 15A to 15E , Figures 16A to 16B In step S3, a straight embedded wire 104 (i.e., the bit line of the memory) is formed in the second trench 100b. The specific process is as follows:

[0100] Step one involves forming a first dielectric layer 102 on the entire semiconductor substrate 100 structure, including the U-shaped fin 101, the first trench 100a, and the second trench 100b, using processes such as thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition. The first dielectric layer 102 fills the bottom of the second trench 100b with a thickness not exceeding H3, so that the top surface of the subsequently formed buried wire 104 is flush with or lower than the top surface of the second source / drain region 101d. The material of the first dielectric layer 102 only needs to have a high etching selectivity relative to the semiconductor substrate 100, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0101] Step two, an anisotropic dry etching process can be used to etch (i.e., back etching) the first dielectric layer 102 to expose the first trench 100a in the U-shaped fin 101, while ensuring that the top surface of the portion of the first dielectric layer 102 filling the isolation trench 100c outside the U-shaped fin 101 is equal to the top surface of the horizontal fin portion 1012 (e.g., ...). Figure 10B (as shown) or equal to the top surface of the first dielectric layer 102 at the bottom of the subsequently formed embedded conductor 104 (as shown) Figures 15A to 15E As shown), a straight conductive trench 100d is formed in the first dielectric layer 102 on the second trench 100b, and the conductive trench 100d extends along the second direction to the entire length of the second trench 100b. The conductive trench 100d exposes the sidewalls within the height of the second source / drain region 101d extending along the second direction of the U-shaped fin 101. The bottom of the conductive trench 100d does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 100a. The sidewalls of the conductive trench 100d expose a portion of the height of the horizontal fin 1012 of the U-shaped fin, so that the subsequently formed embedded conductor 104 is electrically connected to the subsequent formation of the second source / drain region 101d in the horizontal fin 1012. At this time, the remaining first dielectric layer 102 in the second trench 100b has an L-shaped structure (e.g., ...). Figure 10C ~ Figure 10E (As shown) a structure or a linear structure that only partially overlaps in height with the second source / drain region 101d (such as...) Figures 15A to 15E (As shown). When the structure of the remaining first dielectric layer 102 in the second trench 100b is an L-shaped structure, please refer to... Figures 10C to 10E The sidewall and bottom surface of the subsequently formed embedded conductor 104 are surrounded and covered by the remaining first dielectric layer 102 in the second trench 100b; when the remaining first dielectric layer 102 in the second trench 100b is linear, please refer to... Figures 15A to 15EAs shown, the remaining first dielectric layer 102 in the second trench 100b is completely located below the subsequently formed embedded conductor 104. Only the bottom surface of the embedded conductor 104 contacts the remaining first dielectric layer 102 in the second trench 100b, and the area from the top surface of the first dielectric layer 102 in the second trench 100b to the height of the horizontal fin portion 1012 is a straight conductor trench 100d.

[0102] Step 3: The conductive contact material required for fabricating the conductive contact structure 103, such as tungsten, can be filled into the conductor trench 100d using processes such as electroplating, physical vapor deposition, or chemical vapor deposition. Then, the filled conductive contact material is etched back, retaining only the portion that contacts the area of ​​the corresponding horizontal fin 1012 used to form the second source / drain region 101d, and reducing the linewidth of the retained conductive contact material to form a conductive contact structure 103 with a linewidth smaller than that of the second trench 100b. At this time, there is a gap between the side of the conductive contact structure 103 away from the horizontal fin 1012 and the side of the second trench 100b away from the horizontal fin 1012 for forming the embedded conductor 104.

[0103] Step 4: Conductive material for forming the embedded wire 104 can be filled into the wire trench 100d with the conductive contact structure 103 by processes such as electroplating, physical vapor deposition, and chemical vapor deposition. The conductive material is then etched back to remove the portion of the conductive material filled in the first trench 100a, so that the top surface of the conductive material in the second trench 100b is flush with or lower than the top surface of the second source / drain region 101d, thereby forming the embedded wire 104. The embedded wire 104 is electrically connected to the second source / drain region 101d through the conductive contact structure 103. Furthermore, the conductive material used to form the embedded wire 104 can be a single material to form a single-layer film structure, or it can be a combination of materials to form a multilayer structure. The multilayer structure may include a metal substrate and a polycrystalline silicon top layer. The metal substrate may contain, but is not limited to, tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, or gold. The polycrystalline silicon top layer may be an undoped polycrystalline silicon layer or a heavily doped polycrystalline silicon layer, such as an N-type doped polycrystalline silicon layer. Furthermore, since the manufactured semiconductor device is a memory, the semiconductor substrate 100 has multiple second trenches 100b and multiple U-shaped fins 101. The embedded wires 104 corresponding to the U-shaped fins 101 exposed on the same side of each second trench 100b are connected as one unit. That is, the embedded wires 104 of the same row of U-shaped fins 101 arranged along the second direction are uninterrupted when passing through the isolation trench 100c region outside each U-shaped fin 101, thereby forming a bit line of the memory.

[0104] It should be understood that the technical solution for forming the embedded conductor 104 in this invention is not limited to this. As long as the embedded conductor 104 can be electrically connected to the corresponding second source / drain region 101d and is insulated from the vertical fin portions 1011 on both sides of the first trench 100a, it is acceptable. Therefore, the embedded conductor 104 can be formed first, followed by the conductive contact structure 103, and the portion of the first dielectric layer 102 filled in the second trench 100b can also have a U-shaped structure. Please refer to [reference needed] for details. Figure 9 , Figures 16A to 16B In another embodiment of the present invention, the technical solution of step S3, which forms a straight embedded wire 104 (i.e., a bit line of the memory), may further include the following process:

[0105] Step one: A first dielectric layer 102 can be formed on the entire semiconductor substrate 100 structure having U-shaped fins 101, first trench 100a and second trench 100b using thermal oxidation (wet oxidation or dry oxidation) process, in-situ vapor generation process (ISSG) process, chemical vapor deposition (CVD) process or atomic layer deposition process. The thickness of the first dielectric layer 102 at the bottom of the second trench 100b is not greater than H3, so that the top surface of the subsequently formed buried wire 104 can be flush with the top surface of the second source / drain region 101d.

[0106] Step two: An anisotropic dry etching process can be used to etch back the first dielectric layer 102 to expose the first trench 100a in the U-shaped fin 101. This allows the remaining first dielectric layer 102 to fill only the portion of the first trench 100a located outside the U-shaped fin 101 and the second trench 100b, simultaneously forming straight conductive trenches in the portion of the first dielectric layer 102 filled in the second trench 100b. At this point, the remaining first dielectric layer 102 in the second trench 100b has a U-shaped structure. The conductive trench extends along the second direction to the entire length of the second trench 100b, and neither side of the conductive trench exposes the sidewalls of the semiconductor substrate 100 within the height of the second source / drain region 101d extending along the second direction. The bottom of the conductive trench does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 100a. At this time, the top surface of the first dielectric layer 102, which is filled in the second trench 100b and located on both sides of the conductive trench, can be flush with the top surface of the horizontal fin portion 1012 due to the back etching.

[0107] Step 3: Conductive material can be filled into the conductor trench 100d by processes such as electroplating, physical vapor deposition, and chemical vapor deposition to form an embedded conductor 104.

[0108] Step 4: Use a dry etching process to etch away the first dielectric layer 102 between the embedded wire 104 and the corresponding second source / drain region 101d to form a contact hole (or conductive contact groove, not shown, i.e., the portion of the wire trench occupied by the subsequently formed conductive contact structure 103). The bottom of the contact hole exposes the top surface of the first dielectric layer 102. The length of the contact hole extending along the second direction is not greater than the length of the first trench 100a extending along the second direction (i.e., the linewidth of the first trench 100a). The first dielectric layer 102 can directly isolate the embedded wire 104 and the subsequently formed conductive contact structure 103 from the vertical fin portion 1011 of the U-shaped fin 101, respectively, to prevent the embedded wire 104 and the conductive contact structure 103 from being electrically connected to the vertical fin portion 1011 of the U-shaped fin 101.

[0109] Step 5: The conductive contact structure 103 can be filled into the contact hole by processes such as electroplating, physical vapor deposition, and chemical vapor deposition. The conductive contact structure 103 fills the contact hole and its top surface is flush with the top surface of the embedded wire 104.

[0110] This method of forming the embedded wire 104 can avoid etching of excess embedded wires 104 and excess conductive contact structures 103 on the sidewall of the vertical fin portion 1011 of the U-shaped fin 101 extending along the second direction, and the process is relatively simple.

[0111] In the above solutions, the embedded conductor 104 is formed first, followed by the conductive contact structure 103. However, the technical solution of the present invention is not limited to this. Alternatively, the conductive contact structure 103 can be formed first, followed by the embedded conductor 104. For example, the first dielectric layer 102 can be etched first to form a conductive contact groove for filling the conductive contact structure 103. After filling the conductive contact groove, the first dielectric layer 102 can be etched again to form a conductor trench 100d for filling the embedded conductor 104. Then, the embedded conductor 104 is filled into the conductor trench 100d. Alternatively, the first... The first dielectric layer 102 is etched to form a conductive trench 100d for filling the conductive contact structure 103 and the embedded wire 104. The conductive contact structure 103 material is first deposited in the conductive trench 100d and then etched to form the conductive contact structure 103. Then, the embedded wire 104 material is deposited and etched to form the embedded wire 104. This increases the process window for forming the conductive contact structure 103 and reduces the process difficulty of forming the conductive contact structure 103, which is beneficial to improving the electrical connection performance between the embedded wire 104 and the subsequently formed second source / drain region 101d. Furthermore, it should be noted that in other embodiments of the present invention, when the deposition thickness of the first dielectric layer 102 is greater than that of the bottom surface of the second source / drain region 101d (e.g., ...), the process window for forming the conductive contact structure 103 is increased, and the process difficulty of forming the conductive contact structure 103 is reduced, the process window for forming the conductive contact structure 103 is increased, and the process window for forming the conductive contact structure 103 is reduced ...4 is reduced, and the process window for forming the conductive contact structure 104 is reduced, and the process window for forming the conductive contact structure 104 is reduced, and the process window for forming the conductive contact structure 104 is reduced, and the process window for forming the conductive contact structure 104 is reduced, and the process window for forming the conductive contact structure Figures 15A to 15E As shown, an additional sacrificial layer can be deposited to protect other areas, and the sacrificial layer can be further etched to open the conductive contact groove corresponding to the conductive contact structure 103. After filling the conductive contact structure 103 in the conductive contact groove, the sacrificial layer is further etched to open the wire trench corresponding to the embedded wire 104, and the embedded wire 104 is filled in the wire trench. Then the sacrificial layer is removed.

[0112] Please refer to Figure 9 , Figure 17 and Figures 10A-10E In another embodiment of the present invention, in step S3, comb-shaped embedded wires 104 (i.e., bit lines of the memory) can also be formed, and the specific process is as follows:

[0113] Step one: A first dielectric layer 102 can be formed on the entire semiconductor substrate 100 structure having U-shaped fins 101, first trench 100a and second trench 100b using thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD) or atomic layer deposition processes. The thickness of the first dielectric layer 102 at the bottom of the second trench 100b is not greater than H3 and not less than the height of the bottom surface of the second source / drain region 101d, so that the subsequently formed buried wire 104 partially or completely overlaps with the second source / drain region 101d in height.

[0114] Step two: An anisotropic dry etching process can be used to etch the first dielectric layer 102 to expose the first trench 100a in the U-shaped fin 101, so that the remaining first dielectric layer 102 only fills the isolation trench 101c and the second trench 100b, and simultaneously forms comb-shaped wire trenches (not in... Figure 13 (As shown in the diagram) In the first dielectric layer 102 on the second trench 100b, the bottom of the wire trench does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 100a. The wire trench has a comb base opening portion extending along the second direction to the entire length of the second trench 100b and a comb tooth opening portion extending from the comb base opening portion along the first direction to the sidewall of the second source / drain region 101d. At this time, the top surface of the first dielectric layer 102 in the second trench 100b can be flush with the bottom surface of the first trench 100a due to etching.

[0115] Step three: Conductive material can be filled into the conductor trench using processes such as electroplating, physical vapor deposition, or chemical vapor deposition to form a comb-shaped embedded conductor 104. The first dielectric layer 102 can directly isolate the embedded conductor 104 from the vertical fin portion 1011 of the U-shaped fin 101, preventing electrical connection between the embedded conductor 104 and the vertical fin portion 1011 of the U-shaped fin 101. Please refer to... Figure 17The comb-shaped embedded conductor 104 includes a comb base 104a and comb teeth 104b. The comb base 104a is located in the second groove 100b and extends along the second direction, that is, the comb base 104a fills the comb base opening portion of the comb-shaped conductor groove and is insulated from the vertical fin portion 1011 of the U-shaped fin 101 by the first dielectric layer 102. The comb teeth 104b extend from the comb base 104a along the first direction to the sidewall surface of the second source / drain region 101d, that is, the comb teeth 104b fill the comb tooth opening portion of the conductor groove. Thus, the embedded conductor 104 can directly make electrical contact with the subsequently formed second source / drain region 101d through its comb teeth 104b, thereby saving the manufacturing process of the conductive contact structure 103, further simplifying the process and reducing process defects. Furthermore, since the comb-shaped embedded wire 105 is in direct electrical contact with the subsequently formed second source / drain region 107a, the material of the embedded wire 105 is preferably a material that can reduce the contact resistance with the subsequently formed second source / drain region 107a, such as doped polysilicon, metal silicide, etc.

[0116] Furthermore, since the U-shaped fins 101 on both sides of the second groove 100b are arranged in an alternating manner, the comb teeth 104b of the formed conductive contact structure 103 or embedded wire 104 are hexagonally close-packed, which increases the manufacturing window of the comb teeth 104b of the conductive contact structure 103 or embedded wire 104.

[0117] Figure 11 and Figure 13 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S4. Figure 11 The second dielectric layer is omitted. Figure 12A In order to perform step S4 along Figure 11 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 12B In order to perform step S4 along Figure 11 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 12C In order to perform step S4 along Figure 11 A schematic diagram of the cross-sectional structure of the CC' line in the diagram; Figure 12D In order to perform step S4 along Figure 11 A schematic diagram of the cross-sectional structure of the DD' line in the diagram; Figure 12E In order to perform step S4 along Figure 11 A schematic diagram of the cross-sectional structure of the EE' line in the diagram; Figure 14A In order to perform step S4 along Figure 13 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 14B In order to perform step S4 along Figure 13A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 14C In order to perform step S4 along Figure 13 Schematic diagram of the cross-sectional structure of the CC' line in the diagram Figure 14D In order to perform step S4 along Figure 13 A schematic diagram of the cross-sectional structure of the DD' line in the diagram; Figure 14E In order to perform step S4 along Figure 13 A schematic diagram of the cross-sectional structure of line EE' in the diagram; please refer to... Figure 11 Figures 12A-12E , Figure 13 , Figures 14A to 14E In step S4, a gate 107 is formed surrounding the vertical fin portion 1011, and the specific process is as follows:

[0118] Step one involves using processes such as thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition to form a second dielectric layer 105 over the entire structure containing the embedded conductor 104. The second dielectric layer 105 can conceal the embedded conductor 104 and ensure that the bottom of the subsequently formed gate 107 reaches the required height. The material of the second dielectric layer 105 only needs to have a high etch selectivity relative to the semiconductor substrate 100, the embedded conductor 104, and the conductive contact structure 103. Examples include silicon oxide, silicon nitride, amorphous carbon, organic dielectric materials (ODL), and low-k dielectrics (dielectric constant K less than 4).

[0119] Step two involves using thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition to cover the inner surfaces of the first trench 100a and the second trench 100b, which have a second dielectric layer 105, with a gate dielectric layer 106 having a thickness of, for example, 3 nm to 30 nm. When the subsequently formed gate 107 is a polysilicon gate, the material of the gate dielectric layer 106 is preferably silicon dioxide; when the subsequently formed gate 107 is a metal gate, the material of the gate dielectric layer 106 is preferably a high-k dielectric (K greater than 7).

[0120] Step 3: Deposit a material layer for fabricating the gate 107 on the surface of the gate dielectric layer 106 using processes such as evaporation, electroplating, chemical vapor deposition, and atomic layer deposition. The deposition thickness must be at least the thickness required for the gate 107 to be formed. The material layer for fabricating the gate 107 can be a single-layer structure or a stacked structure. The material of the material layer for fabricating the gate 107 can be a material used for fabricating polysilicon gates, such as undoped polysilicon or doped polysilicon, or it can be a material used for fabricating metal gates, such as a metal barrier layer (TiN, etc.) and a work function layer (TiAl, Ti) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 106. The material layer for fabricating the gate 107 is formed by etching back through a process such as N (e.g., tungsten W) and a metal electrode layer (e.g., tungsten W). Then, the excess material layer for fabricating the gate 107 in the first trench 100a and the isolation trench 100c can be removed by a back etching process. The back etching process can be a dry etching process, thereby forming the gate 107 on the two vertical fin portions 1011 of the U-shaped fin 101 respectively. The gate 107 on the two vertical fin portions 1011 of the U-shaped fin 101 is spaced apart at the first trench 100a in the U-shaped fin 101. The top surface of the gate 107 is lower than the top surface of the first source / drain region 101s and can be lower than or flush with the bottom surface of the first source / drain region 101s. Furthermore, since the manufactured semiconductor device is a memory, the semiconductor substrate 100 has multiple second trenches 100b and multiple first trenches 100a, as well as multiple U-shaped fins 101. The gates 107 on the vertical fin portions 1011 arranged in the same straight line along the first direction are uninterrupted at the second trenches 100b, that is, the gates 107 on the vertical fin portions 1011 on the same straight line on one side of each first trench 100a are uninterrupted at the second trenches 100b, thereby forming the word lines of the memory.

[0121] Step four involves depositing a gate isolation layer 108 on the exposed surfaces of the gate dielectric layer 106 and gate 107 using processes such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the gate isolation layer 108 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Subsequently, excess gate isolation layer 108 and gate dielectric layer 106 above the first source / drain region 101s can be removed using a chemical mechanical planarization process to bury the gate 107 (i.e., the word line of the memory) in the first trench 100a.

[0122] It should be understood that in the above embodiments, the first source / drain region 101s and the second source / drain region 101d are formed before the embedded bit line 104 is formed, but the technical solution of the present invention is not limited to this. In one embodiment of the present invention, after the gate 107 is formed, the first source / drain region 101s can be formed in the top part of the vertical fin portion 1011 using the gate 107 as a mask, and the second source / drain region 101d can be formed in the horizontal fin portion 1012 at the same time, thereby making the embedded wire 104 electrically connected to the second source / drain region 101d. The specific formation process of the embedded bit line 104 and the first source / drain region 101s and the second source / drain region 101d in these embodiments is similar to that in the above embodiments, and will not be repeated here. In another embodiment of the present invention, a second source / drain region 101d can be formed in the horizontal fin portion 1012 before forming the embedded wire 106, and a first source / drain region 101s can be formed in the top part of the vertical fin portion 1011 after forming the gate 107 or the gate isolation layer 108. This method performs the second source / drain region 101d and the first source / drain region 101s in two ion implantation processes. Although the process is relatively more complex, it still has certain advantages. For example, this scheme can ensure the performance of the first source / drain region 101s and avoid the influence of the process after the second source / drain region 101d. On the other hand, it is particularly suitable for schemes where the gate 107 is a polysilicon gate structure and the gate 107 needs to be doped. This allows the first source / drain region 101d and the gate 107 to be doped in the same process, which helps to simplify the process and improve device performance.

[0123] It should be further understood that the above embodiments are all illustrated using memory manufacturing as an example. A U-shaped fin forms two memory transistors, and the gate 107 can extend uninterruptedly along the first direction to the entire length of the semiconductor substrate 100 used to manufacture the memory array, serving as a word line for controlling the memory array, such as... Figure 3A and Figure 17 As shown, a single gate 107 can control all transistors in the same row arranged along the first direction, i.e., all transistors located on the same side of each first trench 100a. However, the technical solution of the present invention is not limited to this. When the semiconductor device is a transistor device other than a memory, each gate 107 of each U-shaped fin 101 is discontinuous with the gates 107 of the surrounding U-shaped fins, i.e., the gate 107 is disconnected at the second trench 100b as it extends along the first direction, and is insulated by a gate isolation layer 108 filled in the second trench 100b, thereby achieving individual control of each transistor, such as... Figure 1B As shown.

[0124] In summary, the semiconductor device fabrication method of the present invention firstly etches an isolation trench 100c extending along the first direction, a second trench extending along the second direction, and U-shaped fins staggered on both sides of the second trench, respectively, along a first direction and a second direction. The U-shaped fins have horizontal fin portions extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portions. A first trench extending along the first direction is defined between the two vertical fin portions of the U-shaped fins. Next, embedded conductive lines are formed in the... In the second trench, a first source / drain region is formed in the top portion of the vertical fin of the U-shaped fin, a second source / drain region is formed in the horizontal fin of the U-shaped fin, and a gate is formed surrounding the sidewall of the vertical fin of the U-shaped fin. The embedded wire is electrically connected to the second source / drain region, thereby forming two gate-ring transistors based on a single U-shaped fin. This process is simple, reduces the device area within the same size, and thus provides higher device integration within a given space, which is beneficial for further miniaturization of product size and improvement of device performance.

[0125] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having an isolation trench extending along a first direction and a second trench extending along a second direction, wherein at least one U-shaped fin is disposed on each side of the second trench arranged in the first direction, the U-shaped fins being staggered on both sides of the second trench in the first direction, each U-shaped fin having a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion, a second source / drain region being formed in the horizontal fin portion, and a first source / drain region being formed in the top end portion of each of the vertical fin portions; a first trench extending along the first direction is defined between the two vertical fin portions of the U-shaped fin, the first trench, the isolation trench, and the second trench communicating on the sidewalls of the second trench; and... A gate surrounds the sidewall of the vertical fin portion.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor substrate also has an isolation region with a conductivity type opposite to that of the second source / drain region. The isolation region extends along the second direction to the entire bottom of the U-shaped fin, and the portion of the isolation region extending at the bottom of the first trench is located below the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap with the second source / drain region in height.

3. The semiconductor device as described in claim 1, characterized in that, It also includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer being located between the gate and the U-shaped fin, and the gate isolation layer filling the first trench above the gate and the isolation trench to bury the gate therein.

4. The semiconductor device as claimed in claim 1, characterized in that, It also includes embedded wires, which are buried in the second trench and extend along the second direction, and the embedded wires are electrically connected to the second source / drain region in the U-shaped fin on one side of the second trench.

5. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device further includes a conductive contact structure formed in the second trench and disposed between the embedded wire and the corresponding second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the embedded wire. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench.

6. The semiconductor device as claimed in claim 4 or 5, characterized in that, It also includes a first dielectric layer, which fills the bottom of the second trench and the bottom of the isolation trench, with the embedded wire located on the portion of the first dielectric layer that fills the second trench.

7. The semiconductor device as claimed in claim 6, characterized in that, It also includes a second dielectric layer that fills the second trench, the first trench, and the isolation trench above the first dielectric layer to bury the embedded conductor and to isolate the gate from the second source / drain region, the embedded conductor, and the adjacent U-shaped fin, respectively.

8. The semiconductor device as claimed in claim 4, characterized in that, The semiconductor device is a memory, comprising a plurality of U-shaped fins arranged in an array along the first direction and the second direction, wherein the gates on the vertical fin portions of the plurality of U-shaped fins aligned and arranged in a straight line along the first direction are aligned and electrically connected to each other to form a word line extending along the first direction; and the second source / drain regions of the plurality of U-shaped fins aligned and arranged in a straight line along the second direction are connected to the same embedded conductor, the embedded conductor forming the bit line of the memory.

9. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction to form an isolation trench extending along the first direction, a second trench extending along the second direction, and U-shaped fins arranged alternately on both sides of the second trench. Each U-shaped fin has a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of each U-shaped fin. The first trench, the isolation trench, and the second trench are respectively connected on the sidewall of the second trench. Forming an embedded conductor in the second trench; and, A gate is formed around the vertical fin portion.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, Before or after forming the embedded conductor, a second source / drain region is formed in the horizontal fin portion, and a first source / drain region is simultaneously formed in the top portion of the vertical fin portion. The embedded conductor is electrically connected to the second source / drain region, and the gate surrounds the sidewall of the vertical fin portion. Alternatively, after forming the gate, a second source / drain region is formed in the horizontal fin portion, and a first source / drain region is simultaneously formed in the top portion of the vertical fin portion. The embedded conductor is electrically connected to the second source / drain region, and the gate surrounds the sidewall of the vertical fin portion.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, Before forming the embedded wire, doped ions are implanted into the bottom of the U-shaped fin using a trap ion implantation process to form an isolation region extending along the second direction to the entire bottom of the U-shaped fin. The portion of the isolation region extending at the bottom of the first trench is located below the area of ​​the U-shaped fin used to form the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap in height with the area of ​​the U-shaped fin used for the second source / drain region.

12. The method for fabricating a semiconductor device as described in claim 9, characterized in that, Before forming the embedded conductor, a first dielectric layer is filled in the second trench and the isolation trench. The embedded conductor is located on the first dielectric layer in the second trench, and the embedded conductor is insulated from the semiconductor substrate through the first dielectric layer.

13. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The step of forming the gate includes: A second dielectric layer is filled in the isolation trench, the second trench and the first trench, and the top surface of the second dielectric layer in the first trench is lower than the bottom surface of the first source / drain region; A gate dielectric layer is formed on the surface of the second dielectric layer and on the sidewall of the vertical fin portion exposed by the second dielectric layer; A gate material is filled in a first trench having the gate dielectric layer and the isolation trench, and the gate material is etched along the first direction to form a gate surrounding the vertical fin portion, the top surface of the gate being lower than the top surface of the vertical fin portion; and, A gate isolation layer is filled in the isolation trench, the first trench, and the second trench to bury the gate and achieve isolation between the gate and the second source / drain region and the buried wire.

14. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The semiconductor device is a memory, including a plurality of U-shaped fins arranged along the second direction, wherein the gates on the vertical fin portions of the plurality of U-shaped fins aligned and arranged in a straight line along the first direction are aligned and electrically connected to each other to form word lines extending along the first direction; and the second source / drain regions of the plurality of U-shaped fins aligned and arranged in a straight line along the second direction are connected to the same embedded conductor, the embedded conductor forming the bit lines of the memory.

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