Dual vertical channel transistors, integrated circuit memory, and methods of making the same

Abstract

The application provides a double vertical channel transistor, an integrated circuit memory and a preparation method thereof, which has a first groove extending in a first direction in a vertical fin, a first source / drain region is formed in the fin at the top of both sides of the first groove, a second source / drain region is formed in the fin at the bottom of the first groove, a first gate structure is filled in the first groove and extends in the first direction, a buried wire is filled in a second groove at the sidewall of the vertical fin extending in a second direction, so that the first source / drain regions on both sides of the first groove and the second source / drain region on the bottom of the first groove form a double vertical L-shaped channel, which is beneficial to increase the effective channel length and overcome the short channel effect; and since the second source / drain region and the buried wire electrically connected thereto are located at the bottom of the transistor, it is not necessary to be directly led out from the upper surface, so that the isolation of the periphery of the transistor is easier to form, which is beneficial to reduce the device area, simplify the process and improve the performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a dual vertical channel transistor, an integrated circuit memory, and a method for fabricating the same. Background Technology

[0002] Vertical surrounding gate transistors (SGTs) with buried bit lines use increased isolation rules to reduce the difficulty of shallow trench isolation manufacturing. Their process includes lengthy buried bit line process steps, spin-dip dielectric (SOD) process steps, and metal and N-type doped polysilicon process steps to define the transistor gate length. The process is complicated, which leads to a significant decrease in the stability of the threshold voltage of the memory array. Furthermore, due to the limitation of vertical size, it is not possible to reduce the change of threshold voltage (Vth) with a longer channel length.

[0003] Therefore, there is a need for a new dual vertical channel transistor, integrated circuit memory, and its fabrication method that can simplify the process and improve the electrical performance and storage density of the device. Summary of the Invention

[0004] The purpose of this invention is to provide a dual vertical channel transistor, an integrated circuit memory, and a method for fabricating the same, which can simplify the process and improve the electrical performance and storage density of the device.

[0005] To achieve the above objectives, the present invention provides a dual vertical channel transistor, comprising:

[0006] A semiconductor substrate having vertical fins extending along a second direction, the vertical fins having first trenches extending along a first direction, second source / drain regions formed in the fins at the bottom of the first trench, and first source / drain regions formed in the fins at the top of the sidewalls of the first trench; and

[0007] A first gate structure is filled in the first trench and extends along the first direction. The first gate structure is located above the second source / drain region. The sidewalls of the first gate structure and the sidewalls of the first source / drain region exposed by the first trench at least partially overlap in height.

[0008] Optionally, the semiconductor substrate further has an isolation trench extending along the first direction and exposing the sidewalls of the vertical fins along the first direction for device isolation between the dual vertical channel transistor and adjacent elements. The inner surface of the isolation trench is filled with a second gate structure for applying a substrate voltage to the dual vertical channel transistor.

[0009] Optionally, an isolation zone is further provided at the bottom of the vertical fin, the isolation zone extends along the second direction, and the portion extending at the bottom of the first trench is located below the second source / drain area, and the portions of the isolation zone extending on both sides of the first trench at least partially overlap with the second source / drain area in height.

[0010] Optionally, the first gate structure includes a gate dielectric layer, a gate electrode layer, and a gate isolation layer. The gate dielectric layer covers the sidewalls and bottom surface of the first trench. The gate electrode layer fills the first trench having the gate dielectric layer and its top surface is lower than the top surface of the first source / drain region. The gate isolation layer fills the first trench above the gate electrode layer.

[0011] Optionally, the semiconductor substrate further has a second trench extending along the second direction and exposing the sidewalls of the vertical fins. The first trench extends to the second trench at its end along the first direction, such that the first trench and the second trench are connected on the sidewalls of the second trench. The bottom surface of the first trench is higher than the bottom surface of the second trench, such that the sidewalls of the fins at the bottom of the first trench, including the second source / drain region, are exposed in the second trench. An embedded conductor is disposed in the second trench, and the end of the first trench extends to the sidewalls of the embedded conductor at its end along the first direction, such that the embedded conductor is electrically connected to the second source / drain region.

[0012] Optionally, the dual vertical channel transistor further includes a first dielectric layer located in the second trench, the embedded conductor located on the first dielectric layer, and a portion of the first dielectric layer extending on the bottom surface of the embedded conductor to the boundary with the second source / drain region, such that the bottom surface of the embedded conductor is not lower than the bottom surface of the second source / drain region.

[0013] Optionally, the dual vertical channel transistor further includes a second dielectric layer that covers the second trench above the embedded conductor and exposes a portion of the first gate structure extending from the first trench into the second trench.

[0014] Optionally, the dual vertical channel transistor further includes a conductive contact structure formed in the second trench and disposed between the embedded conductor and the second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the embedded conductor. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench.

[0015] This invention also provides a method for fabricating a dual vertical channel transistor, comprising the following steps:

[0016] A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction to form a vertical fin extending along the second direction and a second trench, the second trench exposing the sidewalls of the vertical fins extending along the second direction, the vertical fins having a first trench extending along the first direction, the first trench extending along the end of the first direction to the second trench such that the first trench and the second trench communicate on the sidewalls of the second trench, and the bottom surface of the first trench is higher than the bottom surface of the second trench;

[0017] An embedded wire is formed in the second trench, the embedded wire extends along the second direction and is electrically connected to the fins at the bottom of the first trench;

[0018] The first source / drain region and the second source / drain region are formed in one step using the same ion implantation process. The first source / drain region is formed in the fin at the top of the sidewall of the first trench, and the second source / drain region is formed in the fin at the bottom of the first trench; and,

[0019] The first gate structure is filled in the first trench above the second source / drain region.

[0020] Optionally, before forming the first source / drain region and the second source / drain region, trap ion implantation process is used to implant ions with the opposite shape to the second source / drain region into the bottom of the vertical fin to form an isolation region. The isolation region extends along the second direction, and the portion extending at the bottom of the first trench is located below the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap with the second source / drain region in height.

[0021] Optionally, before forming the embedded wire, a first dielectric layer is filled in the second trench, the embedded wire is located on the first dielectric layer, and the embedded wire is insulated from the semiconductor substrate through the first dielectric layer.

[0022] Optionally, the step of forming the first gate structure includes: depositing a second dielectric layer on the surface of a semiconductor substrate having the first source / drain region and the second source / drain region, the second dielectric layer filling the second trench above the buried wire; etching the second dielectric layer to expose the sidewalls and bottom surface of the first trench above the second source / drain region, and forming a gate dielectric layer on the sidewalls and bottom surface of the first trench; filling a gate electrode layer in the first trench having the gate dielectric layer, the sidewalls of the gate electrode layer and the sidewalls of the first source / drain region at least partially spatially overlapping in height; and filling a gate isolation layer in the first trench above the gate electrode layer, the gate isolation layer filling the first trench above the gate electrode layer.

[0023] Optionally, while etching the semiconductor substrate along the first direction to form the first trench, an isolation trench is also formed in the semiconductor substrate. The isolation trench extends along the first direction and exposes the sidewalls of the vertical fins along the first direction to achieve device isolation between the dual vertical channel transistor and adjacent elements. While filling the first gate structure in the first trench above the second source / drain region, a second gate structure is also filled in the isolation trench.

[0024] The present invention also provides an integrated circuit memory, comprising: a plurality of dual vertical channel transistors as described herein, all of the dual vertical channel transistors being arranged in an array along a first direction and a second direction in cell rows and cell columns; a second trench extending along the second direction is provided between two adjacent cell columns, the second trench exposing the sidewalls of the vertical fins of all the dual vertical channel transistors on the two adjacent cell columns extending along the second direction, the second trench being filled with a bit line of the integrated circuit memory, the bit line being electrically connected to the second source / drain regions of all the dual vertical channel transistors on the cell column on one side of the second trench; all the dual vertical channel transistors on each cell row... A first trench of a straight-channel transistor extends from the end of a second trench along a first direction and communicates with the second trench on the sidewall of the second trench, such that the first gate structures of all the dual vertical-channel transistors on each cell row are connected as a single word line of the integrated circuit memory; an isolation trench extending along the first direction is also provided between two adjacent cell rows, the isolation trench exposing the outer sidewall of the vertical fins of all the dual vertical-channel transistors on the adjacent two cell rows along the first direction, for isolation between the dual vertical-channel transistors on the adjacent two cell rows, the isolation trench and the first trench are formed in the same process, and the isolation trench is filled with the second gate structure of the dual vertical-channel transistor on the corresponding side, the second gate structures of the dual vertical-channel transistors on the same side in the isolation trench are connected as a single virtual word line of the integrated circuit memory, the virtual word line and the word line are formed in the same process.

[0025] This invention also provides a method for fabricating an integrated circuit memory, comprising: fabricating a plurality of dual vertical channel transistors using the method for fabricating dual vertical channel transistors described in this invention; all the dual vertical channel transistors being arranged in an array along a first direction and a second direction in cell rows and cell columns; and simultaneously forming the first trench and an isolation trench in the semiconductor substrate to achieve isolation between the dual vertical channel transistors on two adjacent cell rows; simultaneously filling the first trench above the second source / drain region with a first gate structure and filling the isolation trench with a second gate structure; wherein a second trench extending along the second direction is provided between two adjacent cell columns. The second trench exposes the sidewalls of the vertical fins of all the dual vertical channel transistors on two adjacent cell rows extending along the second direction. A bit line of the integrated circuit memory is filled in the second trench, and the bit line is electrically connected to the second source / drain regions of all the dual vertical channel transistors on one side of the second trench. The first trenches of all the dual vertical channel transistors on each cell row extend along the end of the first direction to the second trench and communicate with the second trench on its sidewall, such that the first gate structures of all the dual vertical channel transistors on each cell row are connected as a single word line of the integrated circuit memory. The isolation trench exposes the outer sidewalls of the vertical fins of all the dual vertical channel transistors on two adjacent cell rows along the first direction. The second gate structures of the dual vertical channel transistors on the same side of the isolation trench are connected as a single virtual word line of the integrated circuit memory.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] 1. The dual vertical-channel transistor of the present invention has vertical fins extending in a second direction, wherein the vertical fins have a first trench extending in a first direction, and a first source / drain region is formed in the fins at the top of both sides of the first trench, a second source / drain region is formed in the fins at the bottom of the first trench, a first gate structure is filled in the first trench and extends in the first direction, and a buried wire is filled in a second trench at the sidewall of the vertical fin extending in the second direction, thereby forming a gap between the first source / drain region on both sides of the first trench and the second source / drain region at the bottom of the first trench. By forming an L-shaped channel, a dual vertical L-shaped channel is formed. Compared with planar transistors, dual vertical L-shaped channels can increase the effective channel length by increasing the height of the semiconductor pillars between the first and second source / drain regions while occupying the same substrate area. This overcomes the short-channel effect and facilitates the achievement of smaller feature sizes. Moreover, since the second source / drain region of the dual vertical L-shaped channel is located at the bottom of the transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation around the transistor. This reduces the device area within the same size and thus provides higher device integration in a given space. Furthermore, an isolation trench is provided on the outer sidewall of the vertical fin along the first direction, and a second gate structure (i.e., a virtual gate structure) is formed in the isolation trench, thereby forming a dual-gate dual-vertical-channel transistor. On the one hand, the virtual gate structure can be connected to the substrate voltage, so that the transistor has the function of substrate voltage, thereby optimizing the transistor's electrical performance. On the other hand, the arrangement of the isolation trench, the second trench, and the first trench can avoid the use of enlarged shallow trench isolation rules, greatly reducing the difficulty of shallow trench isolation manufacturing, and at the same time, it is conducive to further miniaturization of product size, thereby improving the performance of integrated circuit devices.

[0028] 2. The fabrication method of the dual vertical channel transistor of the present invention firstly involves etching a semiconductor substrate along a first direction and a second direction to form a vertical fin having a first trench extending along the second direction and a second trench extending along the second direction and exposing the sidewalls of the vertical fin, wherein the depth of the first trench is less than that of the second trench; nextly, embedded wires are formed in the second trench, the embedded wires extending along the second direction and electrically connected to the fins at the bottom of the first trench; then, a first source / drain region in the fins located at the top of the sidewalls of the first trench, a second source / drain region in the fins located at the bottom of the sidewalls of the first trench, and a first gate structure filling the first trench are formed, thereby forming a dual vertical L-channel transistor, which has a simple process. Furthermore, the fabrication method of the dual vertical-channel transistor of the present invention can form the first source / drain region and the second source / drain region in a single ion implantation process, eliminating the need for separate formation of the first and second source / drain regions. This simplifies the process, reduces production costs, and simplifies the ion implantation process by forming the first and second source / drain regions in one step. Additionally, the ion implantation process is not limited by trench depth, significantly reducing the difficulty of ion implantation manufacturing. Moreover, changing the trench depth does not require altering the ion implantation process, facilitating adaptation to changes in product size. Furthermore, the fabrication method of the dual vertical-channel transistor of the present invention forms an isolation trench located outside the vertical fins and parallel to the first trench simultaneously with the formation of the first trench. While the first gate structure is filled in the first trench, a second gate structure is filled in the isolation trench simultaneously to achieve isolation between the dual vertical L-channel transistor and adjacent devices. This avoids the use of enlarged shallow trench isolation rules, significantly reducing the manufacturing difficulties of shallow trench isolation and the process defects of the isolation structure, which is beneficial for further miniaturization of product size and improvement of device performance.

[0029] 3. The integrated circuit memory of the present invention includes a plurality of dual vertical channel transistors of the present invention arranged in an array. Since the second source / drain regions of each dual vertical channel transistor are located at the bottom of the transistor, they do not need to be directly led out from the surface of the transistor, making it easier to form isolation between transistors in the array. This reduces the memory cell area within the same size, achieving a cell area of ​​4F. 2 The hexagonal close-packed memory array improves device integration. Furthermore, the virtual word lines in the isolation trenches can be connected to the substrate voltage, which optimizes the electrical properties of the transistors on the corresponding cell rows in the array, thereby giving the integrated circuit memory better electrical performance.

[0030] 4. The integrated circuit memory fabrication method of the present invention simplifies the process by using the dual vertical channel transistor fabrication method of the present invention to fabricate multiple dual vertical channel transistors arranged in an array. It can avoid using enlarged shallow trench isolation rules to achieve isolation between adjacent memory cells and between the memory array and the peripheral circuit, and greatly reduces the difficulty and process defects of shallow trench isolation manufacturing. Attached Figure Description

[0031] Figure 1 This is a three-dimensional structural schematic diagram of a dual vertical channel transistor according to an embodiment of the present invention.

[0032] Figure 2A It is along Figure 1 A schematic diagram of the cross-sectional structure of the XX' line in the diagram.

[0033] Figure 2B It is along Figure 1 A schematic diagram of the cross-sectional structure of the MM' line.

[0034] Figure 2C It is along Figure 1 A schematic diagram of the cross-sectional structure of the YY' line in the diagram.

[0035] Figure 2D It is along Figure 1 A schematic diagram of the cross-sectional structure of the NN' line in the diagram.

[0036] Figure 3 This is a three-dimensional structural schematic diagram of a dual vertical channel transistor according to another embodiment of the present invention.

[0037] Figure 4 This is a flowchart of a method for fabricating a dual vertical channel transistor according to a specific embodiment of the present invention.

[0038] Figures 5A to 5F yes Figure 4 The diagram shows a top view of the device structure in the fabrication method of the dual vertical channel transistor.

[0039] Figures 6A to 6F Corresponding to Figures 5A to 5F A schematic diagram of the cross-sectional structure at line XX' in the diagram.

[0040] Figures 7A to 7E Corresponding to Figures 5A to 5F A schematic diagram of the cross-sectional structure at the MM' line.

[0041] Figures 8A to 8G Corresponding to Figures 5A to 5F A schematic diagram of the cross-sectional structure at the YY' line.

[0042] Figures 9A to 9G Corresponding to Figures 5A to 5F A schematic diagram of the cross-sectional structure at the NN' line.

[0043] The reference numerals in the attached figures are as follows:

[0044] 100 - Semiconductor substrate; 1001 - Vertical fin; 101 - Fin on the sidewall of the first trench (101a); 102 - Fin at the bottom of the first trench (101a); 101a - First trench; 101b - Second trench; 101c - Conductor trench; 101d - Contact trench; 101e - Isolation trench; 103 - Isolation region; 103b - The portion of the isolation region located at the bottom of the first trench; 103a - The portion of the isolation region other than 103b; 104 - First dielectric layer; 105 - Embedded wire; 105a - Comb substrate of embedded wire; 105b - Comb teeth of embedded wire; 106 - Conductive contact structure; 107a - Second source / drain region; 107b - First source / drain region; 108 - Second dielectric layer; 109 - Gate dielectric layer; 110 - Gate electrode layer; 111 - Gate isolation layer; 112 - First gate structure, word line; 113 - Second gate structure, virtual word line; H - Initial thickness of semiconductor substrate 100; H1 - Depth of first trench 101a in vertical fin 1001; H1+H2 - Depth of second trench 101b (including the depth at the intersection of second trench 101b and first trench 101a); H2 - Height of fin at the bottom of first trench 101a (i.e., the depth difference between the depth of first trench 101a and the depth of second trench 101b in vertical fin 1001). Detailed Implementation

[0045] To make the objectives and features of the present invention more apparent and understandable, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the embodiments described. It should be noted that, in this document, "semiconductor substrates on both sides of the first trench" refers to the semiconductor substrates on both sides of the region where the first trench does not intersect with the second trench (i.e., the region of the first trench excluding the intersection with the second trench); in this document, "semiconductor substrate at the bottom of the first trench" refers to the semiconductor substrate at the bottom of the region where the first trench does not intersect with the second trench. Furthermore, it should be readily understood that the meanings of "on" and "on" in this document should be interpreted in the broadest sense, such that "on" and "on" mean not only "directly on something" in the absence of intermediate features or intermediate layers, but also "on something" in the presence of intermediate features or intermediate layers.

[0046] Figure 1 This is a three-dimensional structural schematic diagram of a dual vertical channel transistor according to an embodiment of the present invention; Figure 2A To 2D are respectively along Figure 1 A schematic diagram of the cross-sectional structure of the XX', MM', YY', and NN' lines. Figure 1 To clearly show the buried structures such as the gate electrode layer, second source / drain region, buried wires, and conductive contact structures in the first gate structure of the dual vertical channel transistor, the film structures such as the gate dielectric layer, second dielectric layer, and gate isolation layer in the first gate structure are omitted, so that the gate electrode layer, second source / drain region, buried wires, and conductive contact structures in the first gate structure are displayed externally. Figures 2A to 2D The cross-sectional structure in the image shows the omitted gate dielectric layer, second dielectric layer, gate isolation layer, and other film layers.

[0047] Please refer to Figure 1 as well as Figures 2A to 2D An embodiment of the present invention provides a dual vertical channel transistor, including a semiconductor substrate 100 having vertical fins 1001, a first source / drain region 107b, a second source / drain region 107a, a buried wire 105, a conductive contact structure 106, and a first gate structure 112.

[0048] The semiconductor substrate 100 can be made of any suitable material well known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The vertical fin 1001 is U-shaped and has a first trench 101a extending along a first direction. The semiconductor substrate further has a second trench 101b extending along the second direction and exposing the sidewalls of the vertical fin 1001 extending along the second direction. The first trench 101a extends from its end along the first direction to the second trench 101b, such that the first trench 101a and the second trench 101b are connected on the sidewalls of the second trench 101b. The bottom surface of the first trench 101a is higher than the bottom surface of the second trench 101b, such that the sidewalls of the fin 102 at the bottom of the first trench 101a, including the second source / drain region 107a, are exposed in the second trench 101b. The embedded conductor 105 is embedded in the second trench 101b and extends along the second direction. That is, the first trench 101a and the second trench 101b are connected at their intersection, and the second trench 101b has the same depth in all regions, including the intersection. Figure 6A H1 and Figure 9AThe sum of H2 in the first trench 101a is less than the depth H1+H2 at the intersection, meaning the depth of the first trench 101a is less than the depth of the second trench 101b.

[0049] When the dual vertical channel transistor is the dual vertical channel transistor of the integrated circuit memory, the first direction is the word line direction / row direction of the integrated circuit memory, and the second direction is the bit line direction / column direction of the integrated circuit memory, that is, the first direction and the second direction are perpendicular.

[0050] The vertical fin 1001 has two fins 101 opposite to the first groove 101a along the first direction, and the vertical fin 1001 as a whole forms a U-shaped fin with the first groove 101 opposite to the second groove 101b in the second direction. The first source / drain region 107b is formed in the fins 101 at the top of both sides of the first groove 101a, and the top surface of the first source / drain region 107b is the top surface of the fins 101 at the top of both sides of the first groove 101a; the second source / drain region 107a is formed in the fins 102 at the bottom of the first groove 101a, that is, the top surface of the second source / drain region 107a is the bottom surface of the first groove 100a of the vertical fin 1001. The first source / drain region 107b and the second source / drain region 107a can be formed in one step by the same ion implantation process. Furthermore, depending on the transistor structure with different conductivity types, the first source / drain region 107b and the second source / drain region 107a are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the dopant ions in the first source / drain region 107b and the second source / drain region 107a are N-type dopant ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. When the transistor structure is a P-type transistor, the dopant ions in the first source / drain region 107b and the second source / drain region 107a are P-type dopant ions, such as boron (B) ions and boron fluoride (BF2). + Gallium (Ga) ions, indium (In) ions. In this embodiment, the first source / drain region 107b can be a source region, and the second source / drain region 107a can be a drain region.

[0051] The embedded conductor 105 can be straight, filling the bottom of the second trench 101b and extending along the second direction to the entire length of the second trench 101b. The embedded conductor 105 is insulated from the semiconductor substrate 100 by the first dielectric layer 104 and electrically connected to the second source / drain region 107a by the conductive contact structure 106. The top surfaces of the embedded conductor 105, the second source / drain region 107a, the conductive contact structure 106, and the portion of the first dielectric layer 104 surrounding the sidewall of the embedded conductor 105 are flush. The first dielectric layer 104 fills the bottom of the second trench 101b and has a certain thickness. The first dielectric layer 104 can be L-shaped or U-shaped to surround the buried wire 105. The portion of the first dielectric layer 104 on the bottom surface of the buried wire 105 extends to the boundary between the second source / drain region 107a and the second trench 101b, such that the bottom surface of the buried wire 105 is not lower than the bottom surface of the second source / drain region 107a, thereby avoiding electrical connection with the semiconductor substrate 100 below the second source / drain region 107a. Specifically, a straight wire trench 101c is formed between the first dielectric layer 104 and the vertical fin 1001. The embedded wire 105 and the conductive contact structure 106 are arranged in the wire trench 101c in sequence from far to near the second source / drain region 107a along the first direction. That is, after the embedded wire 105 fills the wire trench 101c, a contact trench 101d is generated between the embedded wire 105 and the second source / drain region 107a because the line width of the embedded wire 105 is smaller than the opening size of the wire trench 101c. The conductive contact structure 106 only fills the part of the contact trench 101d corresponding to the second source / drain region 107a, while the other part of the contact trench 101d is filled by the subsequent second dielectric layer 108. Alternatively, it can be understood that the L-shaped first dielectric layer 104 extends continuously from the sidewall surface of the embedded conductor 105 away from the second source / drain region 107a towards the bottom surface of the embedded conductor 105, until the sidewall surface of the second source / drain region 107a is exposed by the second trench 101b. The conductive contact structure 106 is used to realize the electrical connection between the embedded conductor 105 and the second source / drain region 107a. The conductive contact structure 106 is located in the second trench 101b and between the second source / drain region 107a and the embedded conductor 105. One sidewall of the conductive contact structure 106 is in contact with the sidewall surface of the second source / drain region 107a, and the other sidewall of the conductive contact structure 106 is in contact with the sidewall surface of the embedded conductor 105. The bottom surface of the conductive contact structure 106 is insulated from the surface of the semiconductor substrate 100 at the bottom of the second trench 101b by the first dielectric layer 104.Furthermore, the embedded conductor 105 can be formed using processes such as vapor deposition, electroplating, chemical vapor deposition, and atomic layer deposition. It can be a single-layer structure or a stacked structure. The stacked structure, for example, includes two layers: a metal bottom layer and a polycrystalline silicon top layer. The metal bottom layer can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold, but is not limited thereto. The polycrystalline silicon top layer can be a heavily doped polycrystalline silicon layer, such as an N-type doped polycrystalline silicon layer, or a metal silicide layer formed by reacting with polycrystalline silicon. The material of the first dielectric layer 104 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive contact structure 106 can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold.

[0052] In other embodiments of the present invention, the first dielectric layer 104 filled in the second trench 101b may also be a linear structure (not shown), with its top surface located below the embedded conductor 105. The second trench 101 between the top surface of the first dielectric layer 104 and the top surface of the second source / drain region 107a is a linear conductor trench for filling the embedded conductor 105 and the conductive contact structure 106. The embedded conductor 105 and the conductive contact structure 106 are arranged in the conductor trench from far to near along the first direction, and the remaining space of the conductor trench is filled by the subsequent second dielectric layer 108.

[0053] It should be noted that, in another embodiment of the present invention, the conductive contact structure 106 can be omitted, and the embedded wire 105 can be replaced by a comb-shaped structure instead of a straight one. For details, please refer to [link / reference needed]. Figure 3The straight-line conductor trench 101c in the first dielectric layer 104 is adapted to be a comb-shaped conductor trench 101c. The comb-shaped conductor trench 101c has an opening portion of the comb base extending along the second direction to the entire length of the second trench 101b. The opening portion of the comb teeth of the conductor trench 101c extends from the opening portion of the comb base to the sidewall of the second source / drain region 107a, thereby making the embedded conductor 105 have a comb-shaped structure, i.e., the embedded conductor... The conductor 105 includes a comb base 105a and comb teeth 105b. The comb base 105a is located in the second groove 101b and extends along the second direction, that is, the comb base 105a fills the comb base opening portion of the comb-shaped conductor groove 101c. The comb teeth 105b extend from the comb base 105a along the first direction to the sidewall surface of the second source / drain region 107a, that is, the comb teeth 105b fill the comb tooth opening portion of the conductor groove 101c. Thus, the embedded conductor 105 can directly make electrical contact with the second source / drain region 107a through its comb teeth 105b, thereby saving on the manufacturing process of the conductive contact structure 106, further simplifying the process, and reducing process defects.

[0054] The first gate structure includes a gate dielectric layer 109, a gate electrode layer 110, and a gate isolation layer 111. The gate dielectric layer 109 covers the inner surface of the first trench 101a to provide insulation between the gate electrode layer 110 and the vertical fin 1001, including the first source / drain region 107b and the second source / drain region 107a. The gate electrode layer 110 fills the first trench 101a and extends along the first direction to the entire length of the first trench 101a. At this time, the surface of the gate electrode layer 110 facing the first trench 101a is covered by the gate dielectric layer 109, that is, the gate dielectric layer 109 surrounds the bottom surface of the gate electrode layer 110 and the sidewall surface facing the vertical fin 1001. The gate electrode layer 110 can extend from the first trench 101a of the vertical fin 1001 along the first direction into the second trench 101b to form a gate line (i.e., a word line of the integrated memory). In this embodiment, the top surface of the gate electrode layer 110 is lower than the top surface of the fin 101 on the sidewall of the first trench 101a (i.e., the top surface of the first source / drain region 107b). In particular, the sidewall of the gate electrode layer 110 only partially overlaps with the first source / drain region 107b in height. To avoid leakage between the first source / drain region 107b and the gate electrode layer 110, a gate isolation layer 111 is stacked above the gate electrode layer 110. The gate isolation layer 111 fills the first trench 101a above the gate electrode layer 110 and the isolation trench 101e on the outer sidewall of the vertical fin 1001 extending in the first direction. The gate dielectric layer 109 can be formed using processes such as thermal oxidation (dry or wet oxidation), chemical vapor deposition, or atomic layer deposition. The gate electrode layer 110 can be formed using physical vapor deposition or chemical vapor deposition. The gate electrode layer 110 can be polysilicon or a metal gate material. When the gate electrode layer 110 is made of polysilicon, the gate dielectric layer 109 can be made of silicon dioxide. When the gate electrode layer 110 is made of a metal gate material, the gate dielectric layer 109 can be made of a high-k dielectric with a dielectric constant K greater than 7. When the gate electrode layer 110 is made of a metal gate material, the gate electrode layer 110 includes a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 109. The gate isolation layer 111 can be formed by processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0055] The first trench 101a can be either a rounded U-shaped trench or a right-angled U-shaped trench, thereby forming an L-shaped vertical conductive channel along the current conduction direction (i.e., the current flow direction from a first source / drain region 107b on each side of the gate electrode layer 110 to the second source / drain region 107a at the bottom of the gate electrode layer 110). Compared to planar transistors, the vertical L-shaped channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillars (i.e., fins) between the first source / drain region 107b and the second source / drain region 107a, overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. Thus, as device size shrinks, even if the absolute distance between the first source / drain region 107b on one side of the gate electrode layer 110 and the second source / drain region 107a at the bottom of the gate electrode layer 110 decreases, the L-shaped vertical conductive channel effectively improves the short-channel effect of the transistor. Furthermore, since two L-shaped vertical conductive channels are formed simultaneously on both sides of the gate electrode layer 110, it is equivalent to forming two common-drain and common-gate transistors, thereby increasing the device density in the same area.

[0056] Furthermore, the top surface of the work function layer in the gate electrode layer 110 is lower than the top surface of the first source / drain region 107b, thereby increasing the distance between the work function layer and the first source / drain region 107b, which helps to prevent gate-induce drain leakage (GIDL) from occurring between the work function layer and the first source / drain region 107b.

[0057] Furthermore, an isolation region 103 can be formed in the semiconductor substrate 300. The isolation region 103 is located in the semiconductor substrate 100 on the sidewall of the second trench 101b, and the portion 103b of the isolation region 103 at the bottom of the first trench 101a is located below the second source / drain region 107a. The portion of the isolation region 103 at the bottom of the isolation trench 101e is flush with the portion below the second source / drain region 107a. The isolation region 103 and the second source / drain region 107a can form a PN junction, that is, isolation between the dual vertical channel transistor and adjacent peripheral components is achieved through PN junction isolation. The doping type of the isolation region 103 is determined by the conductivity type of the ions doped in the second source / drain region 107a of the transistor to be formed. For example, in this embodiment, if the ions doped in the formed second source / drain region 107a are N-type, then the ions doped in the isolation region 103 are P-type. The doping depth of the isolation region 103 needs to be adjustable according to the actual situation, and must meet the following condition: the portion 103b of the isolation region 103 extending at the bottom of the first trench 101a needs to be located below the second source / drain region 107a. Furthermore, the portion of the isolation region other than 103b is designated as 103a.

[0058] The dual vertical channel transistor further includes a second dielectric layer 108 covering the inner surface of the second trench 101b above the embedded conductor 105, and exposing the inner surface of the first trench 101a (including the area intersecting with the second trench 101b) above the second source / drain region 107a and the inner surface of the isolation trench 101e (including the area intersecting with the second trench 101b) above the second source / drain region 107a. A gate dielectric layer 109 covers the inner surfaces of the first trench 101a and the isolation trench 101e above the second source / drain region 107a. The top surface of the second dielectric layer 108 is also flush with the top surface of the first source / drain region 107b to facilitate the formation of subsequent structures (interconnect structures, etc.).

[0059] Furthermore, it should be noted that in other embodiments of the present invention, an isolation trench 100e extending in the first direction can also be formed on the outer sidewall of the vertical fin 1001 extending in the first direction. The isolation trench 100e is filled with a second gate structure 113 to form a virtual gate structure for a dual vertical channel transistor. The first gate structure 112 and the second gate structure 113 transform the dual vertical channel transistor into a dual-gate dual vertical channel transistor. By connecting the substrate voltage through the second gate structure 113 in the isolation trench 100e, the electrical performance of the transistor can be improved. Specifically, please refer to... Figure 3Another embodiment of the present invention can also provide a dual-gate dual-vertical-channel transistor, including a semiconductor substrate 100 with vertical fins 1001, a first source / drain region 107b, a second source / drain region 107a, a buried wire 105, a conductive contact structure 106, a first gate structure 112, and a second gate structure 113. The dual-gate dual-vertical-channel transistor may further omit the conductive contact structure 106 and may further include, for example... Figure 2A The isolation region 103 and the second dielectric layer 108 are shown. The first gate structure 112 and the second gate structure 113 are formed using the same process, and also include a gate dielectric layer 109, a gate electrode layer 110 and a gate isolation layer 111.

[0060] In this embodiment, the vertical fin 1001 of the dual-gate dual-vertical-channel transistor is U-shaped and has a first trench 101a extending along a first direction. An isolation trench 101e extending along the first direction is located on the outer sidewall of the vertical fin 1001 extending along the first direction, exposing the sidewall of the vertical fin 1001 along the first direction. The first trench 101a and the isolation trench 101e are parallel to each other and formed using the same process, having the same depth and width. The semiconductor substrate further has a second trench 101b, which extends along the second direction and exposes the sidewalls of the vertical fin 1001. The first trench 101a extends from its end along the first direction to the second trench 101b, such that the first trench 101a and the second trench 101b are connected on the sidewalls of the second trench 101b. The bottom surface of the first trench 101a is higher than the bottom surface of the second trench 101b, so that the sidewalls of the fin 102 at the bottom of the first trench 101a, including the second source / drain region 107a, are exposed in the second trench 101b. The embedded conductor 105 is embedded in the second trench 101b and extends along the second direction. That is, the first trench 101a and the isolation trench 101e are connected to the second trench 101b at their intersections, and the second trench 101b has the same depth in all regions, including the intersections. Figure 6A H1 and Figure 9AThe sum of H2 in the first trench 101a is less than the depth H1+H2 at the intersection, meaning the depth of the first trench 101a is less than the depth of the second trench 101b. The isolation trench 101e extending in the first direction and the second trench 101b extending in the second direction define the position of the vertical fin 1001 in the semiconductor substrate 100. The first trench 101a makes the vertical fin 1001 U-shaped, meaning the vertical fin 1001 has two fins 101 relative to the first trench 101a in the first direction, while the vertical fin 1001 as a whole forms a U-shaped fin with the first trench 101 relative to the second trench 101b in the second direction. While forming the first gate structure 112 filling the first trench 101a, a second gate structure 113 is also filled in the isolation trench 101e as a virtual gate structure. Other structures of the transistor in this embodiment are similar to... Figure 1 The transistors shown have the same structure, so they will not be described again here.

[0061] In this embodiment, the second gate structure 113 of the dual-gate dual-vertical-channel transistor serves as a virtual gate structure, allowing the dual-gate dual-vertical-channel transistor to connect to a substrate voltage (connected to a negative potential) to improve the transistor's electrical performance. Furthermore, the dual-gate dual-vertical-channel transistor of this embodiment can achieve device isolation from adjacent components through the isolation trench 101e, avoiding the use of enlarged shallow trench isolation rules. This significantly reduces the manufacturing difficulties of shallow trench isolation and the process defects of the isolation structure, facilitating further miniaturization of product dimensions and improvement of device performance.

[0062] In summary, the dual vertical channel transistor of the present invention has dual vertical L-shaped channels. Compared with planar transistors, the dual vertical L-shaped channels, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillars between the first source / drain region and the second source / drain region, thus overcoming the short channel effect and facilitating the achievement of smaller feature sizes. Moreover, since the second source / drain region of the dual vertical L-shaped channel is located at the bottom of the transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation around the transistor. This reduces the device area within the same size, thereby providing higher device integration within a given space. Furthermore, an isolation trench is provided on the outer sidewall of the vertical fin along the first direction, and a second gate structure (i.e., a virtual gate structure) is formed in the isolation trench, thereby forming a dual-gate dual-vertical-channel transistor. On the one hand, the virtual gate structure can be connected to the substrate voltage, so that the transistor has the function of substrate voltage, thereby optimizing the transistor's electrical performance. On the other hand, the arrangement of the isolation trench, the second trench, and the first trench can avoid the use of enlarged shallow trench isolation rules, greatly reducing the difficulty of shallow trench isolation manufacturing, and at the same time, it is conducive to further miniaturization of product size, thereby improving the performance of integrated circuit devices.

[0063] The dual vertical-channel transistor of the present invention is applicable to integrated circuit memories such as dynamic random access memories (DRAMs) with higher storage density. The following will use the process of forming multiple dual vertical-channel transistors (with conductive contact structures 106) of the present invention in a DRAM as an example, combined with… Figure 4 , Figures 5A to 5F , Figure 6A to Figure 6F , Figures 7A to 7E , Figures 8A to 8G as well as Figures 9A to 9G This section details the fabrication method of the dual vertical channel transistor of the present invention. The first direction is the word line direction / row direction, and the second direction is the bit line direction / column direction.

[0064] Please refer to Figure 4 An embodiment of the present invention provides a method for fabricating a dual vertical channel transistor, comprising the following steps:

[0065] S1, a semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form a vertical fin extending along the second direction and a second trench, the second trench exposing the sidewalls of the vertical fins extending along the second direction, the vertical fins having a first trench extending along the first direction, the first trench extending along the end of the first direction to the second trench, such that the first trench and the second trench are connected on the sidewalls of the second trench, and the bottom surface of the first trench is higher than the bottom surface of the second trench;

[0066] S2, forming an embedded wire in the second trench, the embedded wire extending along the second direction and electrically connected to the fins at the bottom of the first trench;

[0067] S3, using the same ion implantation process, a first source / drain region and a second source / drain region are formed in one step. The first source / drain region is formed in the fin at the top of the sidewall of the first trench, and the second source / drain region is formed in the fin at the bottom of the first trench; and,

[0068] S4, fill the first gate structure in the first trench above the second source / drain region.

[0069] Figure 5A This is a top view schematic diagram of the fabrication method of a dual vertical channel transistor according to an embodiment of the present invention during step S1. Figure 6A and Figure 6B In order to perform step S1 along Figure 5A A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figure 7A In order to perform step S1 along Figure 5A A schematic diagram of the cross-sectional structure of the MM' line in the diagram; Figure 8A and Figure 8B In order to perform step S1 along Figure 5A A schematic diagram of the cross-sectional structure of the YY' line in the diagram; Figure 9A and Figure 9B In order to perform step S1 along Figure 5A A schematic diagram of the cross-sectional structure of the NN' line in the diagram.

[0070] Please refer to Figure 5A , Figure 6A , Figure 7A , Figure 8A as well as Figure 9AIn step S1, firstly, a semiconductor substrate 100 with a flat surface is provided. The semiconductor substrate 100 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer after epitaxial growth process. Its initial thickness is H, which is the height difference between the upper and lower surfaces of the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. Then, the semiconductor substrate 100 is etched along a first direction and a second direction that are perpendicular to each other to form a vertical fin 1001 extending along the second direction and a second trench 101b in the semiconductor substrate 100. The vertical fin 1001 has a first trench 101a extending along the first direction, and the outer sidewall of the vertical fin 1001 extending along the first direction has an isolation trench 101e extending along the first direction (i.e., the isolation trench 101e and the first trench 101a are parallel). In this embodiment, the isolation trench 101e is equivalent to a first trench 101a, which can be called a virtual first trench 101a. Since the depth of the first trench 101a is less than that of the second trench 101b, the semiconductor substrate 100 can be etched along the second direction to form multiple vertical fins 1001 extending along the second direction and arranged side-by-side. Then, the vertical fins 1001 are etched along the first direction to form multiple linear first trenches 101a extending along the first direction and arranged side-by-side. The middle trench of every three adjacent first trenches 101a is used as the isolation trench 101e. The specific process is as follows:

[0071] Step 1: Form a first hard mask pattern (not shown) on the semiconductor substrate 100 to define multiple parallel second trenches 101b, such that the first hard mask pattern can cover and protect the semiconductor substrate 100 regions corresponding to the isolation trenches 101e and the first trenches 101a on both sides, while covering the semiconductor substrate 100 regions corresponding to the exposed second trenches 101b. The first hard mask pattern can be a stacked structure having an oxide layer (not shown) and a nitride layer (not shown). More specifically, the oxide layer and the nitride layer can be sequentially formed on the semiconductor substrate 100 using a deposition process or the like. Further, a photoresist (not shown) can be coated onto the surface of the nitride layer, and an exposure and development process can be performed to form a photoresist pattern (not shown). The photoresist pattern can expose the area on the semiconductor substrate 100 where the second trench 101b is to be formed, and the exposed portions can have a side-by-side linear arrangement, for example, the exposed portions can be parallel to each other. Then, the nitride layer and the oxide layer can be sequentially etched using an etching process that utilizes the photoresist pattern as an etching mask to form a first hard mask pattern. Afterwards, the photoresist pattern is removed.

[0072] Step 2: The semiconductor substrate 100 is etched using an etching process that utilizes the first hard mask pattern as an etching mask to form multiple second trenches 101b with a depth of H1+H2. The semiconductor substrate 100 between two adjacent second trenches 101b forms a complete fin extending along the second direction (equivalent to multiple vertical fins 1001 connected as one unit). That is, the second trench exposes the sidewalls of the complete fin extending along the second direction.

[0073] Step 3: A sacrificial layer can be formed on the entire structure to fill the second trench 101b. The material of the sacrificial layer is different from that of the semiconductor substrate 100 to facilitate subsequent removal. For example, it can be silicon oxide, silicon nitride, or silicon oxynitride. Subsequently, a chemical mechanical planarization process can be used to remove the first hard mask pattern and the sacrificial layer above it to provide a flat process surface for subsequent processes.

[0074] Step 4: A second hard mask pattern (not shown) can be formed on the remaining sacrificial layer and semiconductor substrate 100. The second hard mask pattern is used to define multiple linear first trenches 101a that extend side by side along the first direction, so that the second hard mask pattern can expose the semiconductor substrate 100 and sacrificial layer regions corresponding to the first trenches 101a and isolation trenches 101e while covering and protecting other regions. For example, the exposed portions can be parallel to each other. The formation process of the second hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be described again here.

[0075] Step 5: Etch the semiconductor substrate 100 and the exposed sacrificial layer using an etching process that utilizes the second hard mask pattern as an etching mask. The etching depth is H1 to form multiple first trenches 101a with a depth of H1. That is, the first trenches 101a extend from the end along the first direction to the second trenches 101b, so that the first trenches 101a and the second trenches 101b are connected on the sidewall of the second trenches 101b, and the bottom surface of the first trenches 101a is higher than the bottom surface of the second trenches 101b. The middle first trench 101a among every three adjacent first trenches 101a is designated as an isolation trench 101e. The vertical fin 1001 surrounded by the isolation trench 101e and the second trench 101b then forms the active region of the dual vertical channel transistor to be formed. Each vertical fin 1001 corresponding to the dual vertical channel transistor becomes a U-shaped structure with a first trench 101a. The height of the fin 1001 at the bottom of the first trench 101a relative to the bottom surface of the second trench 101b is H2. This step is equivalent to simultaneously cutting each complete fin extending along the second direction, thereby forming each U-shaped vertical fin 1001 with a first trench 101a.

[0076] Step 6: The second hard mask pattern and the remaining sacrificial layer can be removed to expose the surface of the semiconductor substrate 100. The process for removing the sacrificial layer can be a wet etching process, and the process for removing the second hard mask pattern can be a chemical mechanical planarization process or a wet etching process.

[0077] It should be noted that in the above steps, the second trench 101b is formed first, followed by the first trench 101a and the isolation trench 101e. However, the technical solution of the present invention is not limited to this. The first trench 101a and the isolation trench 101e can also be formed first, followed by the second trench 101b. The specific method is similar to the above and will not be repeated here.

[0078] Please refer to Figure 5A , Figure 6B , Figure 7B , Figure 8B as well as Figure 9BIn step S1, a trap ion implantation process can be used to implant ions of the opposite type to those of the subsequent second source / drain region 107a into the bottom of the vertical fin 1001 to form an isolation region 103. The isolation region 103 and the subsequent second source / drain region 107a can form a PN junction, thus achieving isolation between the dual vertical channel transistor and adjacent peripheral components through PN junction isolation. The doping type of the isolation region 103 is determined by the conductivity type of the ions doped in the second source / drain region 107a of the transistor to be formed. For example, in this embodiment, if the ions doped in the formed second source / drain region 107a are N-type, then the ions doped in the isolation region 103 are P-type. The doping depth of the isolation region 103 needs to be adjusted according to the actual situation and must meet the following condition: the portion 103b of the isolation region 103 extending from the bottom of the first trench 101a needs to be located below the subsequently formed second source / drain region 107a. Furthermore, the portion of the isolation region other than 103b is labeled 103a.

[0079] Figure 5B This is a top view schematic diagram of the fabrication method of a dual vertical channel transistor in one embodiment of the present invention during step S2. Figure 6B , Figure 7B , Figure 8C , Figure 9C During the execution of step S2, along Figure 5B The diagram shows the cross-sectional structure of the XX', MM', YY', and NN' lines. Please refer to the diagram. Figure 5B , Figure 6B , Figure 7B , Figure 8C as well as Figure 9C In step S2, the specific process of forming the embedded wire 105 in the second trench 101b is as follows:

[0080] Step one involves using thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition to form a first dielectric layer 104 on the entire semiconductor substrate 100 structure having U-shaped vertical fins 1001, isolation trenches 101e, and second trenches 101b. The thickness of the first dielectric layer 104 at the bottom of the second trench 101b is less than H2 and not less than the bottom surface height of the subsequently formed second source / drain region 107a, so that the bottom surface of the subsequently formed buried conductor 105 is not lower than the bottom surface of the second source / drain region 107a and is isolated from the semiconductor substrate 100 below the second source / drain region 107a. The top surface of the subsequently formed buried conductor 105 is not higher than the top surface of the second source / drain region 107a, for example, flush with the top surface of the second source / drain region 107a, to provide a globally flat trench bottom surface for the subsequent formation of the first gate structure 112 and the second gate structure 113. The material of the first dielectric layer 104 only needs to have a high etching selectivity relative to the semiconductor substrate 100, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0081] Step two: An anisotropic dry etching process can be used to etch the first dielectric layer 104 to expose the inner surfaces (including sidewalls and bottom surfaces) of the first trench 101a of the vertical fin 1001 and the isolation trench 101e on the outer side of the vertical fin 1001 (i.e., the areas where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101b). This allows the remaining first dielectric layer 104 to fill only the second trench 101b, while simultaneously forming a straight conductor trench 101c in the first dielectric layer 104 on the second trench 101b. At this time, the structure of the remaining first dielectric layer 104 is L-shaped or straight. When the structure of the remaining first dielectric layer 104 is L-shaped, one sidewall of the subsequently formed embedded conductor 105... The bottom surface is surrounded and covered by the remaining first dielectric layer 104. When the remaining first dielectric layer 104 is linear, the remaining first dielectric layer 104 is completely located below the subsequently formed embedded conductor 105. Only the bottom surface of the embedded conductor 105 contacts the remaining first dielectric layer 104. The conductor trench 101c extends along the second direction to the entire length of the second trench 101b, and the conductor trench 101c exposes the sidewalls within the height of the second source / drain region 107a extending along the second direction of the vertical fin 1001. The bottom of the conductor trench 101c does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 101b. The sidewalls of the conductor trench 101c expose the sidewalls of the fin 102 at the bottom of the first trench 101a, so that the subsequently formed embedded conductor 105 is electrically connected to the second source / drain region 107a formed in the fin 102 at the bottom of the first trench 101a.

[0082] Step 3: Conductive material can be filled into the conductor trench 101c through processes such as electroplating, physical vapor deposition, and chemical vapor deposition to form an embedded conductor 105. The conductive material can be a single material to form a single-layer film structure embedded conductor 105, or multiple conductive materials can be used to form a multilayer structure embedded conductor 105. The multilayer structure can include a metal bottom layer and a polycrystalline silicon top layer. The metal bottom layer can include tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, or gold, but is not limited to these. The polycrystalline silicon top layer can be an undoped polycrystalline silicon layer or a heavily doped polycrystalline silicon layer, such as an N-type doped polycrystalline silicon layer.

[0083] Step 4: Using a dry etching process, at least one side of the embedded wire 105 near the vertical fin 1001 is etched to reduce the linewidth of the embedded wire 105, so as to form a conductive contact groove 101d in the wire trench 101c. The conductive contact groove 101d extends to the entire length of the second trench 101b, and the bottom of the conductive contact groove 101d exposes the top surface of the remaining first dielectric layer 104.

[0084] Step 5: The conductive contact structure 106 can be filled into the conductive contact trench 101d by processes such as electroplating, physical vapor deposition, and chemical vapor deposition. The conductive contact structure 106 fills the conductive contact trench 101d, and the conductive contact structure 106 is further etched to remove the conductive contact structure 106 on the sidewall of the vertical fin 1001 other than the fin 102 area at the bottom of the first trench 101a. This isolates the embedded wire 105 from the vertical fin 1001 portion other than the subsequently formed second source / drain area 107a. The conductive contact trench 101d area that is re-exposed in this step will be filled by the second dielectric layer 108 in the future.

[0085] It should be understood that the technical solution for forming the embedded conductor 105 in this invention is not limited to this. As long as the embedded conductor 105 can be electrically connected to the fin 102 at the bottom of the first trench 101a (i.e., the portion used to subsequently form the second source / drain region 107a), and is insulated from the fins 101 on both sides of the first trench 101a and the fins 102 below the second source / drain region 107a, it is acceptable. Therefore, please continue to refer to... Figure 5B , Figure 6B , Figure 7B , Figure 8C as well as Figure 9C In another embodiment of the present invention, the technical solution of step S2 for forming the embedded conductor 105 may further include the following process:

[0086] Step one involves forming a first dielectric layer 104 on the entire semiconductor substrate 100 structure, including the U-shaped vertical fins 1001, isolation trenches 101e, and second trenches 101b, using processes such as thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition. The thickness of the first dielectric layer 104 at the bottom of the second trench 101b is less than H2 and not less than the bottom surface height of the subsequently formed second source / drain region 107a. This ensures that the bottom surface of the subsequently formed buried conductor 105 is not lower than the bottom surface of the second source / drain region 107a, isolating it from the semiconductor substrate 100 below the second source / drain region 107a. Furthermore, the top surface of the subsequently formed buried conductor 105 is not higher than the top surface of the second source / drain region 107a, for example, flush with the top surface of the second source / drain region 107a, providing a globally flat trench bottom surface for the subsequent formation of the first gate structure 112 and the second gate structure 113.

[0087] Step two: An anisotropic dry etching process can be used to etch the first dielectric layer 104 to expose the inner surfaces (including sidewalls and bottom surfaces) of the first trench 101a of the vertical fin 1001 and the isolation trench 101e on the outer side of the vertical fin 1001 (i.e., the areas where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101b). This allows the remaining first dielectric layer 104 to fill only the second trench 101b, while simultaneously forming a straight conductive trench 101c in the first dielectric layer 104. At this point, the remaining first dielectric layer 104 has a U-shaped structure, and the conductive trench 101c extends along the second direction to the entire length of the second trench 101b. Furthermore, neither side of the conductive trench 101c exposes the second source / source extending along the second direction.

[0088] In the sidewall of the semiconductor substrate 100 within the height of the drain region 107a, the bottom of the wire trench 101c does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 101b. At this time, the top surface of the first dielectric layer 104 in the second trench 101b, including the intersection with the first trench 101a and the isolation trench 101e, can be flush with the top surface of the bottom of the first trench 101a due to etching.

[0089] Step 3: Conductive material can be filled into the conductor trench 101c by processes such as electroplating, physical vapor deposition, and chemical vapor deposition to form an embedded conductor 105.

[0090] Step 4: Use a dry etching process to etch away the first dielectric layer 104 between the embedded wire 105 and the fin 102 at the bottom of the first trench 101a to form a conductive contact trench 101d. The bottom of the conductive contact trench 101d exposes the top surface of the remaining first dielectric layer 104. The length of the conductive contact trench 101d along the second direction is only the length of the fin 102 at the bottom of the first trench 101a (i.e., the linewidth of the first trench 101a). The first dielectric layer 104 can directly isolate the embedded wire 105 and the subsequently formed conductive contact structure 106 from the fins 101 on both sides of the first trench 101a, respectively, to prevent the embedded wire 105 and the conductive contact structure 106 from being electrically connected to the fins 101 on both sides of the first trench 101a.

[0091] Step 5: The conductive contact structure 106 can be filled into the conductive contact groove 101d by processes such as electroplating, physical vapor deposition, and chemical vapor deposition, so that the conductive contact structure 106 fills the conductive contact groove 101d.

[0092] This method of forming the embedded wire 105 can avoid the etching of excess embedded wires 105 and excess conductive contact structures 106 on the sidewalls of the fins 101 on both sides of the first trench 101a, and the process is relatively simple.

[0093] In other embodiments of the present invention, when etching the first dielectric layer 104 in step two, the second dielectric layer 104 in the second trench 101b can be further made into a linear structure, with its top surface located below the subsequently formed embedded conductor 105. The second trench 101 between the top surface of the first dielectric layer 104 and the top surface of the second source / drain region 107a to be formed is a linear conductor trench used to fill the embedded conductor 105 and the conductive contact structure 106. The embedded conductor 105 and the conductive contact structure 106 are arranged in the conductor trench along the first direction from far to near the second source / drain region 107a, and the remaining space of the conductor trench is filled by the subsequent second dielectric layer 108. This method of forming the embedded conductor 105 can reduce the etching difficulty of the first dielectric layer 104.

[0094] In the above solutions, the embedded conductor 105 is formed first, followed by the conductive contact structure 106. However, the technical solution of the present invention is not limited to this. Alternatively, the conductive contact structure 106 can be formed first, followed by the embedded conductor 105. For example, the first dielectric layer 104 can be etched first to form a conductive contact groove for filling the conductive contact structure 106. After filling the conductive contact groove, the first dielectric layer 104 can be etched again to form a conductor trench 101c for filling the embedded conductor 105. Then, the embedded conductor 105 is filled into the conductor trench 101c. Alternatively, the first dielectric layer 104 can be etched first to form the conductive contact structure 106. The conductive trench 101c of the embedded conductor 105 is formed by first depositing conductive contact structure 106 material and etching it in the conductive trench 101c, and then depositing embedded conductor 105 material and etching it in the same way. This increases the process window for forming the conductive contact structure 106 and reduces the process difficulty of forming the conductive contact structure 106, which is beneficial to improving the electrical connection performance between the embedded conductor 105 and the subsequently formed second source / drain region 107a. Furthermore, it should be noted that in other embodiments of the present invention, when the deposition thickness of the first dielectric layer 105 is at the bottom surface of the second source / drain region 107a, an additional sacrificial layer can be deposited to protect other areas, and the sacrificial layer can be further etched to open the conductive contact groove corresponding to the conductive contact structure 106. After filling the conductive contact structure 106 into the conductive contact groove, the sacrificial layer is etched again to open the conductive trench corresponding to the embedded conductor 105, and the embedded conductor 105 is filled into the conductive trench. Then, the sacrificial layer is removed.

[0095] Please continue to refer to this. Figure 3 , Figure 5B , Figure 6B , Figure 7B , Figure 8C as well as Figure 9C In another embodiment of the present invention, the technical solution of step S2 for forming the embedded conductor 105 may further include the following process:

[0096] Step one involves forming a first dielectric layer 104 on the entire semiconductor substrate 100 structure, including the U-shaped vertical fins 1001, isolation trenches 101e, and second trenches 101b, using processes such as thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition. The thickness of the first dielectric layer 104 at the bottom of the second trench 101b is less than H2 and not less than the bottom surface height of the subsequently formed second source / drain region 107a. This ensures that the bottom surface of the subsequently formed buried conductor 105 is not lower than the bottom surface of the second source / drain region 107a, isolating it from the semiconductor substrate 100 below the second source / drain region 107a. Furthermore, the top surface of the subsequently formed buried conductor 105 is not higher than the top surface of the second source / drain region 107a, for example, flush with the top surface of the second source / drain region 107a, providing a globally flat trench bottom surface for the subsequent formation of the first gate structure 112 and the second gate structure 113.

[0097] Step two: An anisotropic dry etching process can be used to etch the first dielectric layer 104 to expose the inner surfaces (including sidewalls and bottom surfaces) of the first trench 101a of the vertical fin 1001 and the isolation trench 101e on the outer side of the vertical fin 1001 (i.e., the areas where the first trench 101a and the isolation trench 101e do not intersect with the second trench 101b). This ensures that the remaining first dielectric layer 104 only fills the second trench 101b, and simultaneously forms comb-shaped conductive trenches 101c on the second trench 101b. In the first dielectric layer 104, the bottom of the conductive trench 101c does not expose the surface of the semiconductor substrate 100 at the bottom of the second trench 101b. The conductive trench 101c has a comb-based opening portion extending along the second direction to the entire length of the second trench 101b and a comb-tooth opening portion extending from the comb-based opening portion along the first direction to the sidewall of the second source / drain region 107a. At this time, the top surface of the first dielectric layer 104 in the second trench 101b can be flush with the bottom surface of the first trench 101a due to etching.

[0098] Step three: Conductive material can be filled into the conductor trench 101c using processes such as electroplating, physical vapor deposition, or chemical vapor deposition to form a comb-shaped embedded conductor 105. The first dielectric layer 104 can directly isolate the embedded conductor 105 from the fins 101 on both sides of the first trench 101a, preventing the embedded conductor 105 from being electrically connected to the fins 101 on both sides of the first trench 101a. Please refer to... Figure 3The comb-shaped embedded conductor 105 includes a comb base 105a and comb teeth 105b. The comb base 105a is located in the second groove 101b and extends along the second direction, that is, the comb base 105a fills the comb base opening portion of the comb-shaped conductor groove 101c and is insulated from the fins 101 on both sides of the first groove 101a by the first dielectric layer 104. The comb teeth 105b extend along the first direction from the comb base 105a to the sidewall surface of the fin 102 (i.e., the subsequent second source / drain region 107a) at the bottom of the first groove 101a, that is, the comb teeth 105b fill the comb tooth opening portion of the conductor groove 101c. Thus, the embedded conductor 105 can directly make electrical contact with the subsequently formed second source / drain region 107a through its comb teeth 105b, thereby saving the manufacturing process of the conductive contact structure 106, further simplifying the process and reducing process defects.

[0099] Figure 5C This is a top view schematic diagram of the fabrication method of a dual vertical channel transistor in one embodiment of the present invention during step S3. Figure 6C , Figure 7B , Figure 8D , Figure 9D During the execution of step S3, along Figure 5C A schematic diagram of the cross-sectional structure of the XX' line, MM' line, YY' line and NN' line.

[0100] Please refer to Figure 5C , Figure 6C , Figure 7B , Figure 8D as well as Figure 9D In step S3, the same source / drain ion implantation process can be used to dop the fins 101 at the top of both sides of the first trench 101a and the fins 102 at the bottom of the first trench 101a with source / drain ions, so as to simultaneously form the first source / drain region 107b in the fins 101 at the top of both sides of the first trench 101a and the second source / drain region 107a in the fins 102 at the bottom of the first trench 101a in one step. Furthermore, depending on the transistor structure of different conductivity types, the first source / drain region 107b and the second source / drain region 107a are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doping ions in the first source / drain region 107b and the second source / drain region 107a are N-type doping ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. When the transistor structure is a P-type transistor, the doping ions in the first source / drain region 107b and the second source / drain region 107a are P-type doping ions, such as boron (B) ions and boron fluoride (BF2). +The ions are gallium (Ga) ions and indium (In) ions. In this embodiment, it is not necessary to form the first source / drain region 107b and the second source / drain region 107a through step-by-step ion implantation. The ion implantation is formed using the same process. The first source / drain region 107b and the second source / drain region 107a formed in one step are simple in terms of ion implantation process, simplify the process flow and save production costs. On the other hand, the ion implantation process is not limited by the trench depth, which greatly reduces the difficulty of ion implantation process manufacturing. At the same time, while changing the trench depth, it is not necessary to change the ion implantation process, which is conducive to adapting to changes in product size.

[0101] Figures 5D to 5F This is a top view schematic diagram of the fabrication method of a dual vertical channel transistor in one embodiment of the present invention during step S4. Figures 6D to 6F In order to perform step S4 along Figures 5D to 5F A schematic diagram of the cross-sectional structure of the XX' line in the diagram; Figures 7C to 7E In order to perform step S4 along Figure 5D A schematic diagram of the cross-sectional structure of the MM' line in 5F; Figures 8E to 8G In order to perform step S4 along Figure 5D A schematic diagram of the cross-sectional structure of line YY' in 5F; Figures 9E to 9G This is a schematic diagram of the cross-sectional structure along line NN' in Figures 5D to 5F during the execution of step S4.

[0102] Please refer to Figure 5D , Figure 6D , Figure 7C , Figure 8E as well as Figure 9E , Figure 6D , Figure 7C , Figure 8E Figures 9 and 9E are respectively along Figure 5DThe diagram shows the cross-sectional structure of the XX', MM', YY', and NN' lines. In step S4, firstly, a second dielectric layer 108 is formed on the entire structure having the first source / drain region 107b and the second source / drain region 107a using thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD), or atomic layer deposition processes. The second dielectric layer 108 can fill the second trench 101b. The material of the second dielectric layer 108 only needs to have a high etching selectivity relative to the semiconductor substrate 100, the buried wire 105, and the conductive contact structure 106, such as silicon oxide, silicon nitride, amorphous carbon, organic dielectric (ODL), and low-k dielectrics (dielectric constant K less than 4). Furthermore, chemical mechanical planarization (CMP) can be used to planarize the top surface of the second dielectric layer 108 to provide a flat process surface for subsequent processes. Optionally, planarization of the top surface of the second dielectric layer 108 can be stopped on the top surface of the first source / drain region 107b.

[0103] Please refer to Figure 5E , Figure 6E , Figure 7D , Figure 8F as well as Figure 9F , Figure 6E , Figure 7D , Figure 8F Figures 9F and 9F are respectively along Figure 5EA schematic diagram of the cross-sectional structure of the XX' line, MM' line, YY' line, and NN' line in the diagram. In step S4, the second dielectric layer 108 in the first trench 101a (including the area intersecting with the second trench 101b) and the isolation trench 101e (including the area intersecting with the second trench 101b) above the second source / drain region 107a can be removed by photolithography and further combined with plasma etching to expose the top surface of the second source / drain region 107a, that is, to re-expose the sidewalls and bottom surface of the first trench 101a, which forms the gate trench (also known as the word line trench). At this time, the area above the second source / drain region 107a is... The second dielectric layer 108 on the top surface of the drain region 107a, including all areas of the first trench 101a (i.e., the intersection with the second trench 101b) and all areas of the isolation trench 101e (including the intersection with the second trench 101b), is removed. This re-exposed first trench 101a, traversing multiple side-by-side vertical fins 1001, is used for the subsequent formation of the first gate structure 112 (i.e., the word line of the integrated circuit memory). The re-exposed isolation trench 100 located outside the multiple side-by-side vertical fins 1001 is used for the subsequent formation of the second gate structure 113 (i.e., the virtual gate structure of a dual vertical channel transistor). This refers to the virtual word line of the integrated circuit memory. Then, a gate dielectric layer 109 can be covered on the inner surface of the exposed first trench 101a and the inner surface of the isolation trench 101e using thermal oxidation (wet oxidation or dry oxidation), in-situ vapor generation (ISSG), chemical vapor deposition (CVD) or atomic layer deposition processes. The inner surface of the first trench 101a includes the inner sidewall of the fin 101 with the first source / drain region 107b, the top surface of the second source / drain region 107a, and the sidewall and bottom surface at the connection between the first trench 101a and the second trench 101b. The inner surface of the isolation trench 101e includes the outer sidewall of the fin 101 with the first source / drain region 107b, the top surface of the semiconductor substrate 100, and the sidewall and bottom surface at the connection between the isolation trench 101e and the second trench 101b. When the subsequently formed first gate structure 112 and second gate structure 113 are polysilicon gate structures, the material of the gate dielectric layer 109 is preferably silicon dioxide; when the subsequently formed gate electrode layer 110 is a metal gate, the material of the gate dielectric layer 109 is preferably a high-K dielectric (K greater than 7).

[0104] Please refer to Figure 5F , Figure 6F , Figure 7E , Figure 8G as well as Figure 9G , Figure 5F This is a top view diagram omitting the second dielectric layer 108 and the gate isolation layer 111, etc. Figure 6F , Figure 7E , Figure 8G Figures 9 and 9G are respectively along Figure 5F A schematic diagram of the cross-sectional structure of the XX' line, MM' line, YY' line, and NN' line. In step S4, the gate electrode layer 110 (i.e., word line) is filled in the first trench 101a having the gate dielectric layer 109, and the gate electrode layer 110 is simultaneously filled in the isolation trench 110e having the gate dielectric layer 109. The specific process includes:

[0105] First, a gate electrode layer 110 is deposited on the surface of the gate dielectric layer 109 using processes such as evaporation, electroplating, chemical vapor deposition, and atomic layer deposition. The deposition thickness on the bottom surfaces of the first trench 101a and the isolation trench 110e must at least reach the required thickness of the gate electrode layer 110 (i.e., word line). The gate electrode layer 110 can be a single-layer structure or a multilayer structure. The material of the gate electrode layer 110 can be a material used to fabricate polysilicon gates, such as undoped polysilicon, doped polysilicon, or a material used to fabricate gold. The gate material includes, for example, a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 109. Subsequently, the gate electrode layer 110 in areas other than the first trench 101a and the isolation trench 110e can be removed by etching back or chemical mechanical planarization processes, so that the gate electrode layer 110 only fills the first trench 101a and the isolation trench 110e, and in the first trench 101a... The top surface of the remaining gate electrode layer 110 in the isolation trench 110 is lower than the top surface of the first source / drain region 107b, and even lower than the bottom surface of the first source / drain region 107b. Next, a gate isolation layer 111 can be deposited on the exposed gate dielectric layer 109 and gate electrode layer 110 using processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The material of the gate isolation layer 111 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Subsequently, the excess gate isolation layer 111 and gate dielectric layer 109 above the first source / drain region 107b can be removed using a chemical mechanical planarization process to bury the gate electrode layer 110 in the first trench 101a and the isolation trench 101e, respectively. This forms a buried first gate structure 112 (i.e., a buried word line) in the first trench 101a and a buried second gate structure 113 (i.e., a buried virtual word line or virtual gate structure) in the isolation trench 101e.

[0106] In summary, the fabrication method of the dual vertical channel transistor of the present invention forms a dual vertical L-shaped channel. Compared with planar transistors, the dual vertical L-shaped channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillars between the first and second source / drain regions, overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. Furthermore, since the second source / drain region of the dual vertical L-shaped channel is located at the bottom of the transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation around the transistor. This reduces the device area within the same size, thereby providing higher device integration density within a given space. In addition, the fabrication method of the dual vertical channel transistor of the present invention can form the first and second source / drain regions in the same ion implantation process. On the one hand, this simplifies the process flow and saves production costs; on the other hand, the ion implantation process is not limited by the trench depth, significantly reducing the difficulty of ion implantation manufacturing. Simultaneously, changing the trench depth does not require changing the ion implantation process, which is beneficial for adapting to changes in product size. Furthermore, an isolation trench is provided on the outer sidewall of the vertical fin along the first direction. This isolation trench is formed using the same process as the first trench. While the first gate structure is filled in the first trench, a second gate structure (i.e., a virtual gate structure) is also filled in the isolation trench, thereby forming a dual-gate dual-vertical-channel transistor. The virtual gate structure can be connected to the substrate voltage, enabling the transistor to function with the substrate voltage, thus optimizing the transistor's electrical performance. On the other hand, the isolation trench, the second trench, and the first trench avoid the need for enlarged shallow trench isolation rules, significantly reducing the manufacturing difficulties of shallow trench isolation, and facilitating further miniaturization of the product size, thereby improving the performance of integrated circuit devices. The fabrication method of the dual-vertical-channel transistor of this invention is applicable to the manufacture of memory arrays for integrated circuit memories such as dynamic random access memory.

[0107] Therefore, please continue to refer to Figure 3 , Figure 5F , Figure 6F , Figure 7E , Figure 8G as well as Figure 9GAn embodiment of the present invention provides an integrated circuit memory, including a plurality of dual vertical channel transistors as described in the present invention. These dual vertical channel transistors are arranged in an array along a first direction and a second direction in cell rows and cell columns. That is, each dual vertical channel transistor can form a memory cell and a memory array by connecting a corresponding memory capacitor. The first trench 101a of all dual vertical channel transistors on each cell row is integrally formed (i.e., connected as one unit along the row direction), so that the first gate structure 112 of all dual vertical channel transistors on the cell row is integrally formed as a word line (WL) of the integrated circuit memory. The isolation trench 101e of all dual vertical channel transistors on each cell row is integrally formed (i.e., connected as one unit along the row direction), so that the second gate structure 113 of all dual vertical channel transistors on the cell row is integrally formed as a virtual word line (DUMMY WL) of the integrated circuit memory. The buried wire 105 of all dual vertical channel transistors on each cell column is integrally formed as a bit line (BL) of the integrated circuit memory. The isolation trench 101e is located outside the outer sidewall of the vertical fins 1001 of all dual vertical channel transistors on the cell row along the first direction, and exposes the outer sidewall of the vertical fins 1001 of all dual vertical channel transistors on the cell row along the first direction, for the purpose of achieving isolation between dual vertical channel transistors on two adjacent cell rows. The isolation trench 101e and the first trench 101a are formed in the same process, and the virtual word lines embedded in the isolation trench 101e and the word lines embedded in the first trench 101a are formed in the same process.

[0108] The semiconductor substrate 100 also has a second trench 101b extending along the second direction, the second trench 101b exposing the sidewalls of the vertical fins 1001 of all the dual vertical channel transistors on the cell column extending along the second direction, the bit line being formed in the second trench 101b, the first trench 101a and the isolation trench 101e extending to the end of the first direction to the second trench 101b such that the first trench 101a and the isolation trench 101e are respectively connected to the second trench 101b on the sidewall of the second trench 101b, and the first trench 101a and the isolation trench 101e have the same depth and the bottom surfaces of the first trench 101a and the isolation trench 101e are both higher than the bottom surface of the second trench 101b, so that the second source / drain region 107a is exposed in the second trench 101b and electrically connected to the bit line, the bottom surfaces of the first gate structure 112 and the second gate structure 113 are at the same height.

[0109] In other words, in the integrated circuit memory of the present invention, a second trench 101b extending along the second direction is provided between two adjacent cell columns. The second trench 101b exposes the sidewalls of the vertical fins 1001 of all the dual vertical channel transistors on the two adjacent cell columns extending along the second direction. A bit line of the integrated circuit memory is filled in the second trench 101b. The bit line is electrically connected to the second source / drain regions 107a of all the dual vertical channel transistors on the cell column on one side of the second trench 101b. An isolation trench 101e extending along the first direction is provided between two adjacent cell rows. The isolation trench 101e exposes the outer sidewalls of the vertical fins 1001 of all the dual vertical channel transistors on the two adjacent cell rows along the first direction, for the purpose of achieving isolation between the dual vertical channel transistors on the two adjacent cell rows.

[0110] Please continue to refer to this. Figure 4 The present invention also provides a method for fabricating an integrated circuit memory. Multiple dual vertical channel transistors are fabricated using the dual vertical channel transistor fabrication method described in this invention. All the dual vertical channel transistors are arranged in an array along a first direction and a second direction in cell rows and cell columns. The first trench 101a of all the dual vertical channel transistors on each cell row is integrally formed, such that the first gate structure 112 of all the dual vertical channel transistors on the cell row is integrally formed to serve as a word line of the integrated circuit memory. The embedded conductors 105 of all the dual vertical channel transistors on each cell column are integrally formed to serve as a bit line of the integrated circuit memory. A second trench 101b extending along the second direction is provided between two adjacent cell columns. The second trench 101b exposes the sidewalls of the vertical fins 1001 of all the dual vertical channel transistors on the two adjacent cell columns extending along the second direction. A bit line of the integrated circuit memory is filled in the second trench 101b. The bit line is electrically connected to the second source / drain region 107a of all the dual vertical channel transistors on the cell column on one side of the second trench 101b.

[0111] The method for fabricating an integrated circuit memory of the present invention, while forming the first trench 101a, also forms an isolation trench 101e in the semiconductor substrate 100 between the dual vertical channel transistors located on two adjacent cell rows. The isolation trench 101e extends along the first direction and exposes the outer sidewalls of the vertical fins 1001 of all the dual vertical channel transistors on the two adjacent cell rows along the first direction, for the purpose of achieving isolation between the dual vertical channel transistors on the two adjacent cell rows. While filling the first gate structure 112 in the first trench 101a above the second source / drain region 107a, a second gate structure 113 is also filled in the isolation trench 101e. That is, the second gate structures 113 of the dual vertical channel transistors on the same side of the isolation trench 101e are connected as one unit to form the virtual word line of the integrated circuit memory.

[0112] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A dual vertical channel transistor, characterized by, include: A semiconductor substrate having vertical fins extending along a second direction, the vertical fins having a first trench extending along a first direction, a second source / drain region being formed in the fins at the bottom of the first trench, and a first source / drain region being formed in the fins at the top of the sidewalls of the first trench. as well as A first gate structure is filled in the first trench and extends along the first direction. The first gate structure is located above the second source / drain region. The sidewalls of the first gate structure and the sidewalls of the first source / drain region exposed by the first trench at least partially overlap in height. The semiconductor substrate also has an isolation trench that extends along the first direction and exposes the sidewalls of the vertical fins along the first direction for device isolation between the dual vertical channel transistor and adjacent elements. The dual vertical channel transistor is a dual vertical channel transistor of an integrated circuit memory. The first direction is the word line direction / row direction of the integrated circuit memory, and the second direction is the bit line direction / column direction of the integrated circuit memory.

2. The dual vertical channel transistor as described in claim 1, characterized in that, The inner surface of the isolation trench is filled with a second gate structure, which is used to apply substrate voltage to the dual vertical channel transistor.

3. The dual vertical channel transistor as described in claim 1, characterized in that, An isolation zone is also provided at the bottom of the vertical fin. The isolation zone extends along the second direction, and the portion extending at the bottom of the first trench is located below the second source / drain area. The portions of the isolation zone extending on both sides of the first trench at least partially overlap with the second source / drain area in height.

4. The dual vertical channel transistor as described in claim 1, characterized in that, The first gate structure includes a gate dielectric layer, a gate electrode layer, and a gate isolation layer. The gate dielectric layer covers the sidewalls and bottom surface of the first trench. The gate electrode layer fills the first trench having the gate dielectric layer and its top surface is lower than the top surface of the first source / drain region. The gate isolation layer fills the first trench above the gate electrode layer.

5. The dual vertical channel transistor as claimed in claim 1, characterized in that, The semiconductor substrate further has a second trench extending along the second direction and exposing the sidewalls of the vertical fins. The first trench extends to the second trench at its end along the first direction, such that the first trench and the second trench are connected on the sidewalls of the second trench. The bottom surface of the first trench is higher than the bottom surface of the second trench, such that the sidewalls of the fins at the bottom of the first trench, including the second source / drain region, are exposed in the second trench. An embedded conductor is disposed in the second trench, and the end of the first trench extends to the sidewalls of the embedded conductor at its end along the first direction, such that the embedded conductor is electrically connected to the second source / drain region.

6. The dual vertical channel transistor as described in claim 5, characterized in that, It also includes a first dielectric layer located in the second trench, the embedded conductor located on the first dielectric layer, and a portion of the first dielectric layer on the bottom surface of the embedded conductor extending to the boundary with the second source / drain region such that the bottom surface of the embedded conductor is not lower than the bottom surface of the second source / drain region.

7. The dual vertical channel transistor as claimed in claim 6, characterized in that, It also includes a second dielectric layer that covers the second trench above the embedded conductor and exposes a portion of the first gate structure extending from the first trench into the second trench.

8. The dual vertical channel transistor as claimed in claim 5, characterized in that, It also includes a conductive contact structure formed in the second trench and disposed between the embedded wire and the second source / drain region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the embedded wire. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench.

9. A method for fabricating a dual vertical channel transistor, characterized in that, Includes the following steps: A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form a vertical fin extending along the second direction and a second trench, the second trench exposing the sidewalls of the vertical fins extending along the second direction, the vertical fins having a first trench extending along the first direction, the first trench extending along the end of the first direction to the second trench such that the first trench and the second trench communicate on the sidewalls of the second trench, and the bottom surface of the first trench is higher than the bottom surface of the second trench; An embedded wire is formed in the second trench, the embedded wire extending along the second direction and electrically connected to the fins at the bottom of the first trench; The first source / drain region and the second source / drain region are formed in one step using the same ion implantation process. The first source / drain region is formed in the fin at the top of the sidewall of the first trench, and the second source / drain region is formed in the fin at the bottom of the first trench; and, The first gate structure is filled in the first trench above the second source / drain region. The dual vertical channel transistor is a dual vertical channel transistor of an integrated circuit memory. The first direction is the word line direction / row direction of the integrated circuit memory, and the second direction is the bit line direction / column direction of the integrated circuit memory.

10. The method for fabricating a dual vertical channel transistor as described in claim 9, characterized in that, Before forming the first source / drain region and the second source / drain region, trap ion implantation process is used to implant ions with the opposite shape to the second source / drain region into the bottom of the vertical fin to form an isolation region. The isolation region extends along the second direction, and the portion extending at the bottom of the first trench is located below the second source / drain region. The portions of the isolation region extending on both sides of the first trench at least partially overlap with the second source / drain region in height.

11. The method for fabricating a dual vertical channel transistor as described in claim 9, characterized in that, Before forming the embedded conductor, a first dielectric layer is filled in the second trench, the embedded conductor is located on the first dielectric layer, and the embedded conductor is insulated from the semiconductor substrate through the first dielectric layer.

12. The method for fabricating a dual vertical channel transistor as described in claim 9, characterized in that, The steps for forming the first gate structure include: A second dielectric layer is deposited on the surface of a semiconductor substrate having the first source / drain region and the second source / drain region, the second dielectric layer filling the second trench above the buried wire; The second dielectric layer is etched to expose the sidewalls and bottom surface of the first trench above the second source / drain region, and a gate dielectric layer is formed on the sidewalls and bottom surface of the first trench. A gate electrode layer is filled in the first trench having the gate dielectric layer, wherein the sidewalls of the gate electrode layer and the sidewalls of the first source / drain region at least partially overlap in height; and; A gate isolation layer is filled in a first trench above the gate electrode layer, and the gate isolation layer completely fills the first trench above the gate electrode layer.

13. The method for fabricating a dual vertical channel transistor as described in claim 9, characterized in that, While etching the semiconductor substrate along the first direction to form the first trench, an isolation trench is also formed in the semiconductor substrate. The isolation trench extends along the first direction and exposes the sidewalls of the vertical fins along the first direction to achieve device isolation between the dual vertical channel transistor and adjacent components. While filling the first gate structure in the first trench above the second source / drain region, a second gate structure is also filled in the isolation trench.

14. An integrated circuit memory, characterized in that, include: A plurality of dual vertical channel transistors as described in any one of claims 1 to 8, wherein all the dual vertical channel transistors are arranged in an array of cell rows and cell columns along a first direction and a second direction; a second trench extending along the second direction is provided between two adjacent cell columns, the second trench exposing the sidewalls of the vertical fins of all the dual vertical channel transistors on the two adjacent cell columns extending along the second direction, the second trench being filled with a bit line of the integrated circuit memory, the bit line being electrically connected to the second source / drain regions of all the dual vertical channel transistors on the cell column on one side of the second trench; the first trench of all the dual vertical channel transistors on each cell row extends along the end of the first direction to the second trench and communicates with the second trench on the sidewall of the second trench, such that the first gate structure of all the dual vertical channel transistors on each cell row is integrated as a word line of the integrated circuit memory; An isolation trench extending along the first direction is also provided between two adjacent cell rows. The isolation trench exposes the outer sidewall of the vertical fins of all the dual vertical channel transistors on the two adjacent cell rows along the first direction, for isolation between the dual vertical channel transistors on the two adjacent cell rows. The isolation trench is formed in the same process as the first trench, and the isolation trench is filled with the second gate structure of the dual vertical channel transistor on the corresponding side. The second gate structures of the dual vertical channel transistors on the same side in the isolation trench are connected as a whole, serving as a virtual word line of the integrated circuit memory. The virtual word line is formed in the same process as the word line. The first direction is the word line direction, and the second direction is the bit line direction.

15. A method for fabricating an integrated circuit memory, characterized in that, include: A plurality of dual vertical channel transistors are fabricated using the fabrication method of any one of claims 9 to 13. All the dual vertical channel transistors are arranged in an array along a first direction and a second direction in cell rows and cell columns. Simultaneously with forming the first trench, an isolation trench extending along the first direction is formed in the semiconductor substrate to achieve isolation between the dual vertical channel transistors on adjacent cell rows. A first gate structure is filled in the first trench above the second source / drain region, and a second gate structure is also filled in the isolation trench. A second trench extending along the second direction is provided between adjacent cell columns. The second trench exposes the sidewalls of the vertical fins of all the dual vertical channel transistors on two adjacent cell columns, extending along the second direction. The second trench is filled with a bit line of the integrated circuit memory, and the bit line is electrically connected to the second source / drain regions of all the dual vertical channel transistors on the cell column on one side of the second trench. The first trenches of all the dual vertical channel transistors on each cell row extend along the end of the first direction to the second trench and communicate with the second trench on the sidewall of the second trench, so that the first gate structures of all the dual vertical channel transistors on each cell row are connected as a single word line of the integrated circuit memory. The isolation trench exposes the outer sidewall of the vertical fins of all the dual vertical channel transistors on two adjacent cell rows along the first direction. The second gate structures of the dual vertical channel transistors on the same side of the isolation trench are connected as a single unit, serving as a virtual word line of the integrated circuit memory. The first direction is the word line direction, and the second direction is the bit line direction.

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