Magnetoresistive random access memory device and manufacturing method thereof

Abstract

A magnetoresistive random access memory (MRAM) device and a method for manufacturing the same are provided. According to an embodiment, the MRAM device may include: a first interlayer insulating layer on a substrate including a cell region and a peripheral region, a lower electrode contact of the first interlayer insulating layer extending through the cell region, a first structure on each lower electrode contact, and a covering layer covering surfaces of the first interlayer insulating layer and the first structure in the cell region and the peripheral region, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode stacked in sequence, wherein an upper surface of the covering layer on the first interlayer insulating layer in the peripheral region is higher than an upper surface of the covering layer on the first interlayer insulating layer between the first structures in the cell region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0113258, entitled “Magnetoresistive Random Access Memory Device”, filed on September 20, 2018 in the Korean Intellectual Property Office (KIPO), is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to semiconductor devices and more particularly to magnetoresistive random access memory (MRAM) devices. Background Art

[0004] When manufacturing an MRAM device, a magnetic tunnel junction (MTJ) layer may be etched to form an MTJ structure in a cell region. However, due to the etching process, a difference between the cell region and the peripheral region may occur. Summary of the invention

[0005] According to an example embodiment, an MRAM device is provided. The MRAM device may include a first interlayer insulating layer, a lower electrode contact, a first structure, and a covering layer. The first interlayer insulating layer may be formed on a substrate including a cell region and a peripheral region. The lower electrode contact may extend through the first interlayer insulating layer of the cell region. The first structure may be on each lower electrode contact. The first structure may include a lower electrode, a magnetic tunnel junction structure, and an upper electrode stacked in sequence. The covering layer may cover the surfaces of the first interlayer insulating layer and the first structure in the cell region and the peripheral region. The upper surface of the covering layer on the first interlayer insulating layer in the peripheral region may be higher than the upper surface of the covering layer on the first interlayer insulating layer between the first structures in the cell region.

[0006] According to an example embodiment, an MRAM device is provided. The MRAM device may include a first interlayer insulating layer, a lower electrode contact, and a first structure. The first interlayer insulating layer may be formed on a substrate including a cell region and a peripheral region. The lower electrode contact may extend through the first interlayer insulating layer of the cell region. The first structure may be on each lower electrode contact. The first structure may include a lower electrode, a magnetic tunnel junction structure, and an upper electrode stacked in sequence. The upper surface of the first interlayer insulating layer in the peripheral region may be higher than the upper surface of the first interlayer insulating layer between the first structures in the cell region.

[0007] According to an example embodiment, an MRAM device is provided. The MRAM device may include a first interlayer insulating layer, a lower electrode contact, a first structure, and a covering layer. The first interlayer insulating layer may be formed on a substrate including a cell region and a peripheral region. The lower electrode contact may extend through the first interlayer insulating layer of the cell region. The first structure may be on each lower electrode contact. The first structure includes a lower electrode, a magnetic tunnel junction structure, and an upper electrode stacked in sequence. The covering layer may cover the surfaces of the first interlayer insulating layer and the first structure in the cell region and the peripheral region. The covering layer may have a uniform thickness. The upper surface of the first interlayer insulating layer between the first structures in the cell region may be lower than the upper surface of the first interlayer insulating layer in the peripheral region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a cross-sectional view of an MRAM device according to example embodiments;

[0010] Figures 2 to 13 shows a cross-sectional view of some stages in a method of manufacturing an MRAM device according to an example embodiment;

[0011] Figures 14 to 24 shows a cross-sectional view of some stages in a method of manufacturing an MRAM device according to an example embodiment;

[0012] Fig.25 shows a cross-sectional view of some stages in a method of manufacturing an MRAM device according to an example embodiment;

[0013] Fig.26 shows a cross-sectional view of some stages in a method of manufacturing an MRAM device according to an example embodiment;

[0014] Fig. 27 shows a cross-sectional view of an MRAM device according to example embodiments; and

[0015] Figures 28 to 30 Cross-sectional views illustrating some stages in a method of manufacturing an MRAM device according to example embodiments are shown. DETAILED DESCRIPTION

[0016] Figure 1 is a cross-sectional view illustrating an MRAM device according to example embodiments.

[0017] Reference Figure 1, an MRAM device may be formed on a substrate 100 including a cell region C and a peripheral region P. A first interlayer insulating layer 102, a lower electrode contact 110, a lower electrode 112a, an MTJ structure 136, an intermediate electrode 116a, and an upper electrode 118a may be formed on the substrate 100 of the cell region C. A first interlayer insulating layer 102 may be formed on the substrate 100 of the peripheral region P. In addition, a first capping layer 140 may be formed on a surface of a first structure 138 and a surface of the first interlayer insulating layer 102, wherein the first structure 138 includes a lower electrode 112a, an MTJ structure 136, an intermediate electrode 116a, and an upper electrode 118a. The MRAM device may further include a second interlayer insulating layer 142, a bit line 146, a third interlayer insulating layer 144, and a through-hole contact 148.

[0018] The substrate 100 may include a semiconductor material such as silicon, germanium, silicon germanium, or a III-V semiconductor compound such as GaP, GaAs, GaSb, etc. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Various types of circuit patterns (e.g., transistors, lower wiring, etc.) and a lower interlayer insulating layer covering the circuit patterns may be further formed on the substrate 100.

[0019] The first interlayer insulating layer 102 may be on the substrate 100. The first interlayer insulating layer 102 may include silicon oxide or a low-k dielectric material having a dielectric constant smaller than that of silicon oxide (ie, less than about 3.9).

[0020] The lower electrode contact 110 may fill the first opening extending through the first interlayer insulating layer 102 in the cell region C, for example, along the Z direction. In example embodiments, the lower electrode contact 110 may include a first barrier pattern 106 and a first conductive pattern 108. The first barrier pattern 106 may include a metal nitride such as tungsten nitride, tantalum nitride, titanium nitride, etc., or a metal such as tantalum, titanium, etc. The first conductive pattern 108 may include a metal having a low resistance, such as tungsten, copper, aluminum, etc. The lower electrode contact 110 may contact the substrate 100 or a lower wiring on the substrate 100.

[0021] The first structure 138 may include a lower electrode 112a, an MTJ structure 136, an intermediate electrode 116a, and an upper electrode 118a stacked sequentially. The first structure 138 may be columnar. The first structure 138 may contact the upper surface of the lower electrode contact portion 110. Therefore, the first structure 138 may be formed on the cell region C. The first structure 138 may not be formed on the peripheral region P. In some embodiments, the first structure 138 may not include an intermediate electrode.

[0022] In example embodiments, the sidewalls of the first structures 138 may be inclined such that the width of the first structures 138 may gradually increase in a downward direction, for example, the width of the first structures 138 in the X direction may gradually increase as the distance from the substrate 100 in the Z direction decreases. Alternatively, the sidewalls of the first structures 138 may have a vertical slope.

[0023] In example embodiments, the first structures 138 may completely cover the upper surface of the lower electrode contact 110, and the first structures 138 may cover the first interlayer insulating layer 102 (e.g., the first portion 102a of the upper surface of the first interlayer insulating layer 102) adjacent to the lower electrode contact 110. In example embodiments, the upper surface of the first interlayer insulating layer 102 between the first structures 138 (e.g., the second portion 102b of the upper surface of the first interlayer insulating layer 102) may be lower than the upper surface of the lower electrode contact 110.

[0024] The upper surface 102p of the first interlayer insulating layer 102 in the peripheral region P may be higher than the second portion 102b of the upper surface of the first interlayer insulating layer 102 between the first structures 138. The upper surface 102p of the first interlayer insulating layer 102 in the peripheral region P may be substantially flat. In example embodiments, the upper surface 102p of the first interlayer insulating layer 102 in the peripheral region P may be substantially coplanar with the upper surface of the lower electrode contact 110 or lower than the upper surface of the lower electrode contact 110.

[0025] That is, the height of the upper surface 102p of the first interlayer insulating layer 102 in the peripheral region P may be higher than the height of the second portion 102b of the upper surface of the first interlayer insulating layer 102 between the first structures 138 in the cell region C. Therefore, the step difference between the cell region C where the first structure 138 is formed and the peripheral region P where the first structure 138 is not formed may be reduced.

[0026] The lower electrode 112a may be on the lower electrode contact 110. The lower electrode 112a may include a metal nitride such as tantalum nitride, titanium nitride, or the like, or a metal such as tantalum, titanium, or the like.

[0027] The MTJ structure 136 may be on the lower electrode 112a. The MTJ structure 136 may include a first magnetic pattern 136a, a tunnel barrier pattern 136b, and a second magnetic pattern 136c that are sequentially stacked.

[0028] In example embodiments, the first magnetic pattern 136a may be used as a fixed layer having a fixed magnetization direction. In example embodiments, the first magnetic pattern 136a may include a fixed pattern, a lower ferromagnetic pattern, an antiferromagnetic coupling spacing pattern, and an upper ferromagnetic pattern. In this case, the fixed pattern may include, for example, FeMn, IrMn, PtMn, MnO, MnS, MnTe, MnF2 , FeF 2 、FeCl 2 ,FeO,CoCl 2 、CoO、NiCl 2 , NiO and / or Cr, etc. The lower ferromagnetic pattern and the upper ferromagnetic pattern may include a ferromagnetic material, such as Fe, Ni and / or Co. The antiferromagnetic coupling spacer pattern may, for example, include Ru, Ir and / or Rh.

[0029] In example embodiments, the second magnetic pattern 136c may be used as a free layer having a variable magnetization direction. In this case, the second magnetic pattern 136c may include a ferromagnetic material, such as Fe, Ni, Co, Cr, Pt, etc. The second magnetic pattern 136c may also include, for example, boron, silicon, etc. The second magnetic pattern 136c may include at least one of the ferromagnetic materials. For example, the second magnetic pattern 136c may include, for example, CoFe, NiFe, FeCr, CoFeNi, PtCr, CoCrPt, CoFeB, NiFeSiB, CoFeSiB, etc.

[0030] The tunnel barrier pattern 136b may be disposed between the first magnetic pattern 136a and the second magnetic pattern 136c. Therefore, the first magnetic pattern 136a and the second magnetic pattern 136c may not directly contact each other. In example embodiments, the tunnel barrier pattern 136b may include a metal oxide having an insulating material, such as aluminum oxide or magnesium oxide.

[0031] In example embodiments, the intermediate electrode 116a may include a metal nitride such as tantalum nitride, titanium nitride, etc. or a metal such as tantalum, titanium, etc. The upper electrode 118a may include a metal such as tungsten, copper, platinum, nickel, silver, gold, etc. For example, the upper electrode 118a may include tungsten.

[0032] The first capping layer 140 may be conformally formed on the surfaces of the first structure 138 and the first interlayer insulating layer 102. Figure 1 As shown, the first capping layer 140 may include a horizontal portion on the first interlayer insulating layer 102, for example, along the X direction, and a vertical portion extending from the horizontal portion along the sidewall of the first structure 138, for example, along the Z direction. The first capping layer 140 may have a substantially uniform thickness. The first capping layer 140 may contact the sidewall of the first structure 138, so that the first capping layer 140 may protect the first structure 138. The first capping layer 140 may include, for example, silicon nitride or silicon oxynitride.

[0033] An upper surface 140p of the first capping layer 140 formed on the first interlayer insulating layer 102 in the peripheral region P may be higher than an upper surface 140c of the first capping layer 140 formed on the first interlayer insulating layer 102 in the cell region C. That is, an upper surface 140p of the first capping layer 140 in the peripheral region P may be higher (e.g., along the Z direction relative to the substrate 100) than a lowest portion of the first capping layer 140 in the cell region C (i.e., a horizontal portion on the first interlayer insulating layer 102).

[0034] A second interlayer insulating layer 142 may be formed on the first capping layer 140 to fill the gaps between the first structures 138. The second interlayer insulating layer 142 may include oxide, for example, silicon oxide.

[0035] Since the upper surface 102p of the first interlayer insulating layer 102 in the peripheral region P is relatively high (i.e., along the Z direction relative to the substrate 100), the step difference between the cell region C where the first structure 138 is formed and the peripheral region P where the first structure 138 is not formed may be reduced. Therefore, the step difference between the upper surfaces of the second interlayer insulating layer 142 in the cell region C and in the peripheral region P may be reduced. In example embodiments, the upper surfaces of the second interlayer insulating layer 142 in the cell region C and in the peripheral region P may be coplanar with each other.

[0036] The bit line 146 may contact the upper surface of the upper electrode 118a through the second interlayer insulating layer 142. In example embodiments, the bit line 146 may extend in one direction to have a line shape. The bit line 146 may include a second barrier pattern 146a and a second metal pattern 146b.

[0037] The second barrier pattern 146a may include, for example, metal nitride such as tungsten nitride, tantalum nitride, titanium nitride, etc. and / or metal such as tantalum, titanium, etc. The second metal pattern 146b may include, for example, tungsten, copper, aluminum, etc.

[0038] A third interlayer insulating layer 144 may be formed on the second interlayer insulating layer 142. A via contact 148 may extend through the third interlayer insulating layer 144, the second interlayer insulating layer 142, the first capping layer 140, and the first interlayer insulating layer 102, contacting the substrate 100 or a lower wiring on the substrate 100. In example embodiments, an upper wiring may be further formed on the via contact 148.

[0039] In example embodiments, the second interlayer insulating layer 142 and the third interlayer insulating layer 144 may include substantially the same material and thus may be merged into one interlayer insulating layer.

[0040] The step difference between the second insulating layer 142 in the cell region C and the peripheral region P and the step difference between the third insulating layer 144 in the cell region C and the peripheral region P can be reduced, respectively. Therefore, variations and failures of the photolithography process for forming the via contact 148 and the upper wiring can be reduced. Therefore, failures of the via contact 148 and the upper wiring can be reduced.

[0041] Figures 2 to 13 are cross-sectional views illustrating some stages in a method of manufacturing an MRAM device according to example embodiments.

[0042] Reference Figure 2 , a first interlayer insulating layer 102 may be formed on the substrate 100 including the cell region C and the peripheral region P. A lower electrode contact 110 may be formed through the first interlayer insulating layer 102 in the cell region C. In example embodiments, a circuit pattern including, for example, a transistor and a lower wiring, etc. may be further formed between the substrate 100 and the first interlayer insulating layer 102. In addition, a lower interlayer insulating layer may be further formed to cover the circuit pattern.

[0043] In example embodiments, the lower electrode contact 110 may be formed only on the cell region C. For example, the lower electrode contact 110 may be electrically connected to the substrate 100 or a lower wiring formed on the substrate 100 .

[0044] For example, an etching mask may be formed on the first interlayer insulating layer 102. The first interlayer insulating layer 102 may be anisotropically etched using the etching mask to form a first opening exposing the upper surface of the substrate 100. The anisotropic etching process may include a chemical etching process such as a reactive ion etching (RIE) process.

[0045] A first barrier layer may be formed on an inner surface of the first opening and on an upper surface of the first interlayer insulating layer 102. A first conductive layer may be formed on the first barrier layer to fill the first opening. The first barrier layer and the first conductive layer may be planarized until the upper surface of the first interlayer insulating layer 102 is exposed to form a lower electrode contact portion 110 filling the first opening. The lower electrode contact portion 110 may include a first barrier pattern 106 and a first conductive pattern 108.

[0046] Reference Figure 3 A lower electrode layer 112, an MTJ layer 114, and an intermediate electrode layer 116 may be sequentially formed on the first interlayer insulating layer 102 and the lower electrode contact 110. An upper electrode layer 118, a first adhesion layer 120, a mold layer 122, and a second adhesion layer 124 may be sequentially formed on the intermediate electrode layer 116.

[0047] The lower electrode layer 112 may be formed of a metal such as tantalum, titanium, etc. and / or a metal nitride such as tantalum nitride, titanium nitride, etc.

[0048] The MTJ layer 114 may include a first magnetic layer 114 a , a tunnel barrier layer 114 b , and a second magnetic layer 114 c that are sequentially stacked.

[0049] The intermediate electrode layer 116 may be formed of a metal such as tantalum, titanium, etc. and / or a metal nitride such as tantalum nitride, titanium nitride, etc. In some example embodiments, the intermediate electrode layer 116 may not be formed.

[0050] The upper electrode layer 118 may be formed of a metal such as tungsten, copper, platinum, nickel, silver, gold, etc. For example, the upper electrode layer 118 may be formed of tungsten.

[0051] The first adhesion layer 120 may be formed such that the mold layer 122 may be combined therewith. In example embodiments, the first adhesion layer 120 may include nitride, such as silicon nitride, silicon oxynitride, or the like.

[0052] The mold layer 122 may be used as a mold for forming an etching mask pattern in a subsequent damascene process. In example embodiments, the mold layer 122 may include a material that can be removed by an ashing process. For example, the mold layer 122 may include carbon, such as a spin-on hard mask (SOH).

[0053] The second adhesion layer 124 may be formed so that the photoresist film may be bonded thereto. The second adhesion layer 124 may be used as an etching mask pattern for etching the mold layer. In example embodiments, the second adhesion layer 124 may include nitride, such as silicon nitride, silicon oxynitride, or the like.

[0054] Reference Figure 4 , a photoresist pattern 126 may be formed on the second adhesion layer 124 by performing a photolithography process.

[0055] The photoresist pattern 126 may be formed only on the second adhesion layer 124 of the cell region C. The photoresist pattern 126 may include an opening having an exposed portion facing (e.g., overlapping) the lower electrode contact 110. On the other hand, the photoresist pattern 126 may not be formed on the second adhesion layer 124 of the peripheral region P, so that the second adhesion layer 124 may be exposed in the peripheral region P.

[0056] Reference Figure 5 The second adhesive layer 124 may be etched using the photoresist pattern 126 as an etching mask to form a second adhesive pattern 124a. The mold layer 122 may be etched using the second adhesive pattern 124a as an etching mask to form a mold pattern 122a. During the etching process, the photoresist pattern 126 may be removed.

[0057] Since the photoresist pattern 126 is not formed in the peripheral region P, the second adhesive layer 124 and the mold layer 122 in the peripheral region P may be removed by an etching process.

[0058] A stack structure including the mold pattern 122a and the second adhesive pattern 124a may be formed in the cell region C. The stack structure may include a second opening 128 facing (eg, overlapping) an upper surface of the lower electrode contact part 110 in a vertical direction.

[0059] Reference Figure 6 , a first hard mask layer 130 may be formed on the second adhesion pattern 124a of the cell region C to fill the second opening 128 and cover the first adhesion layer 120 of the peripheral region P. A second hard mask layer 132 may be formed on the first hard mask layer 130. Therefore, a hard mask structure including the first hard mask layer 130 and the second hard mask layer 132 may be formed in the cell region C and the peripheral region P.

[0060] The first hard mask layer 130 may be used as an etching mask for forming an upper electrode in a subsequent process. The first hard mask layer 130 may be formed to fully fill the second opening 128 by a deposition process having excellent step coverage characteristics. In example embodiments, the first hard mask layer 130 may be formed by an atomic layer deposition (ALD) process. In example embodiments, the first hard mask layer 130 may include silicon oxide.

[0061] Since the mold pattern 122 a is not formed in the peripheral region P, an upper surface of the first hard mask layer 130 in the peripheral region P may be lower than an upper surface of the first hard mask layer 130 in the cell region C (eg, in a vertical direction with respect to the substrate 100 ).

[0062] The second hard mask layer 132 may be formed to reduce or remove the step difference of the upper surface of the mask structure in the cell region C and in the peripheral region P. Therefore, the thickness of the second hard mask layer 132 in the cell region C may be less than the thickness of the second hard mask layer 132 in the peripheral region P (e.g., in the vertical direction). The second hard mask layer 132 may include an insulating material having fluidity so that the second hard mask layer 132 may be formed to be relatively thick at a low step portion. In example embodiments, the second hard mask layer 132 may be formed by a chemical vapor deposition (CVD) process or a spin-on glass (SOG) process. In example embodiments, the second hard mask layer 132 may include silicon oxide.

[0063] In example embodiments, an upper surface of the second hard mask layer 132 in the peripheral region P may be higher than an upper surface of the second adhesion pattern 124a in the cell region C. Therefore, a step difference of upper surfaces of the second hard mask layer 132 in the cell region C and in the peripheral region P may be reduced. For example, upper surfaces of the second hard mask layer 132 in the cell region C and in the peripheral region P may be coplanar with each other. Alternatively, upper surfaces of the second hard mask layer 132 in the cell region C and in the peripheral region P may have a slight step.

[0064] Reference Figure 7 , the second hard mask layer 132 and the first hard mask layer 130 may be planarized until the upper surface of the mold pattern 122a in the cell region C is exposed. Therefore, the first hard mask 130a may be formed in the cell region C to fill the second opening 128, and the first hard mask 130a and the second hard mask 132a may be formed on the first adhesion layer 120 in the peripheral region P. In example embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

[0065] In example embodiments, the first hard mask 130a in the cell region C may have a columnar shape, which may face (eg, overlap) the lower electrode contact 110 in a vertical direction. The first hard mask 130a and the second hard mask 132a in the peripheral region P may cover the entire upper surface of the first adhesion layer 120 in the peripheral region P.

[0066] In some example embodiments, during the planarization process, all of the second hard mask 132 a in the peripheral region P may be removed. In this case, the first hard mask 130 a may be formed on the first adhesion layer 120 in the peripheral region P.

[0067] Reference Figure 8 , the mold pattern 122a may be removed. Thus, a columnar first hard mask 130a may be formed on the first adhesion layer 120 in the cell region C. The first hard mask 130a may be formed by a damascene process. In example embodiments, when the mold pattern 122a includes SOH, the mold pattern 122a may be removed by an ashing process.

[0068] Reference Fig. 9 , the first adhesion layer 120 and the upper electrode layer 118 in the cell region may be anisotropically etched using the first hard mask 130a and the second hard mask 132a as etching masks. The anisotropic etching process may include an RIE process.

[0069] In the etching process, the first adhesion layer 120 and the upper electrode layer 118 between the first hard mask 130a may be etched to form a cell mask structure 131 including the upper electrode 118a and the first adhesion pattern 120a stacked on the intermediate electrode layer 116. During the etching process, the first hard mask 130a in the cell region may be completely or partially removed. In addition, the first hard mask 130a and the second hard mask 132a in the peripheral region P may be completely or partially removed by the etching process.

[0070] In example embodiments, the second hard mask 132a in the peripheral region P may be completely removed, and the first hard mask 130a in the cell region C and the peripheral region P may be partially removed by the etching process. Therefore, the first hard mask 130a may remain with a certain thickness in the cell region C and the peripheral region P. In some example embodiments, the first hard mask 130a in the cell region C and the first and second hard masks 130a and 132a in the peripheral region P may be completely removed by the etching process.

[0071] Reference Fig.10 , the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 in the cell region C may be sequentially etched using the cell mask structure 131 as an etching mask. Subsequently, the upper portion of the first interlayer insulating layer 102 may be etched. In addition, in the etching process, the first hard mask 130a, the first adhesion layer 120, the upper electrode layer 118, the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 in the peripheral region P may be etched together.

[0072] The first structure 138 including the stacked lower electrode 112a, the MTJ structure 136, the intermediate electrode 116a, and the upper electrode 118a may be formed in the cell region C by an etching process. The upper portion of the upper electrode 118a may be partially removed by the etching process. In addition, the upper surface of the first interlayer insulating layer 102 in the peripheral region P may be exposed.

[0073] The etching process may include a physical etching process such as an ion beam etching (IBE) process, etc. For example, the etching process may include argon ion sputtering etching. In example embodiments, in the etching process, an incident angle of an ion beam used as an etching source may be variable.

[0074] Specifically, the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 between the cell mask structures 131 in the cell region C may be patterned by a first etching process. In the first etching process, the ion beam may be incident at a high angle of 70 degrees or more relative to the upper surface of the substrate 100. During the first etching process, the sputtered metal material may be deposited again on the sidewalls of the patterned structure. Therefore, after the first etching process, a second etching process may be further performed to remove the redeposited metal material. In the second etching process, the ion beam may be incident at a low angle of 70 degrees or less relative to the upper surface of the substrate 100. During the first and second etching processes, the layers formed in the peripheral region P may be etched together.

[0075] Therefore, in the first and second etching processes, the ion beam may be incident on the upper surface of the exposed layer at an angle relative to the upper surface of the substrate 100. Since the unit mask structure 131 is formed only in the unit region C, the unit mask structure 131 may interfere with the movement of the ion beam used as an etching source. That is, in the etching process, a shadow effect may be generated. Therefore, the ion beam applied to the exposed layer between the unit mask structures 131 may be reduced. Therefore, the etching rate of the exposed layer between the unit mask structures 131 in the unit region C may be reduced.

[0076] On the other hand, the first hard mask 130a having a flat upper surface in the peripheral region P may be exposed. Therefore, the ion beam may be provided to the entire surface of the first hard mask 130a and subsequently to the entire surface of the layer formed under the first hard mask 130a without a shadow effect. Therefore, the etching rate of the layer formed in the peripheral region P may be higher than the etching rate of the layer formed in the cell region C. That is, during etching of the upper portion of the intermediate electrode layer 116, the MTJ layer 114, the lower electrode layer 112, and the first interlayer insulating layer 102 formed between the cell mask structure 131 in the cell region C, the first hard mask 130a, the first adhesion layer 120, the upper electrode layer 118, the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 formed in the peripheral region P may be etched together. After the etching process, the upper surface of the first interlayer insulating layer 102 exposed in the peripheral region P may be substantially flat.

[0077] The first structure 138 may have a columnar shape contacting the lower electrode contact 110. The MTJ structure 136 may include a first magnetic pattern 136a, a tunnel barrier pattern 136b, and a second magnetic pattern 136c sequentially stacked. Since the upper portion of the first interlayer insulating layer 102 in the cell region C is etched, the upper surface of the first interlayer insulating layer 102 exposed between the first structures 138 may be lower than the upper surface of the lower electrode contact 110.

[0078] Since the layer etched in the peripheral region P has a larger stacking number and a larger thickness than the layer etched in the cell region C, the upper portion of the first interlayer insulating layer 102 may be almost not etched in the etching process. In example embodiments, in the etching process, the etching thickness (e.g., the removed thickness) of the first interlayer insulating layer 102 in the peripheral region P is less than the etching thickness of the first interlayer insulating layer 102 in the cell region C. The upper surface of the first interlayer insulating layer 102 in the peripheral region P may be higher (e.g., relative to the bottom of the substrate 100) than the upper surface of the first interlayer insulating layer 102 formed (e.g., and exposed) between the first structures 138 in the cell region C. The upper surface of the first interlayer insulating layer 102 in the peripheral region P may be coplanar with the upper surface of the lower electrode contact 110 or lower than the upper surface of the lower electrode contact 110.

[0079] Reference Fig.11 , a first capping layer 140 may be formed to cover surfaces of the first structures 138 and the first interlayer insulating layer 102. The first capping layer 140 may be conformally formed on surfaces of the first structures 138 and the first interlayer insulating layer 102. Therefore, the first capping layer 140 may have a substantially uniform thickness.

[0080] The first capping layer 140 in the cell region C may directly contact the sidewalls of the first structure 138 so that the first capping layer 140 may protect the sidewalls of the MTJ structure 136 included in the first structure 138. The first capping layer 140 in the peripheral region P may have a flat upper surface and a flat lower surface.

[0081] The first capping layer 140 may include, for example, silicon nitride. The first capping layer 140 may be formed by an ALD process or a CVD process.

[0082] An upper surface of the first capping layer 140 on the first interlayer insulating layer 102 in the peripheral region P may be higher than an upper surface of the first capping layer 140 on the first interlayer insulating layer 102 in the cell region C. That is, an upper surface of the first capping layer 140 in the peripheral region P may be higher than a lowermost portion of the first capping layer 140 in the cell region C.

[0083] Reference Fig.12 , a second interlayer insulating layer 142 may be formed on the first capping layer 140. The second interlayer insulating layer 142 may be formed to fill a gap between the first structures 138. The second interlayer insulating layer 142 may include silicon oxide.

[0084] The step difference between the cell region C where the first structure 138 is formed and the peripheral region P where the first structure 138 is not formed is reduced. Therefore, the step difference between the upper surfaces of the second interlayer insulating layer 142 in the cell region C and in the peripheral region P may be reduced.

[0085] Reference Fig.13 The second interlayer insulating layer 142 and the first capping layer 140 in the cell region C may be etched to form a groove exposing the upper surface of the upper electrode 118a. A bit line 146 may be formed in the groove. The bit line 146 may include a second barrier pattern 146a and a second metal pattern 146b.

[0086] A third interlayer insulating layer 144 may be formed on the second interlayer insulating layer 142. Then, the third interlayer insulating layer 144, the second interlayer insulating layer 142, the first capping layer 140, and the first interlayer insulating layer 102 in the peripheral region P may be etched to form a via hole exposing the substrate 100 or a lower wiring on the substrate 100. A via contact 148 may be formed in the via hole.

[0087] To form the via contact 148, a barrier layer may be formed on the surface of the via and the third interlayer insulating layer 144, and a metal layer may be formed on the barrier layer to fill the inner space of the via. Then, the barrier layer and the metal layer may be planarized until the upper surface of the third interlayer insulating layer 144 may be exposed to form the via contact 148 filling the via. Therefore, the via contact 148 may include a third barrier pattern 148a and a third metal pattern 148b.

[0088] The step difference between the second interlayer insulating layer 142 in the cell region C and the peripheral region P and the step difference between the third interlayer insulating layer 144 in the cell region C and the peripheral region P can be reduced. Therefore, the variation and failure of the photolithography process for forming the through hole can be reduced. Therefore, the failure of the through hole contact 148 can be reduced. An upper wiring can be further formed on the through hole contact 148.

[0089] As described above, an MRAM device having a low step difference between a cell region and a peripheral region can be manufactured.

[0090] Figures 14 to 24 are cross-sectional views illustrating some stages of a method of manufacturing an MRAM device according to example embodiments.

[0091] First, you can execute and reference Figure 2 The illustrated processes are substantially the same or similar processes to form a first interlayer insulating layer 102 and a lower electrode contact 110 passing through the first interlayer insulating layer 102 on the substrate 100 including the cell region C and the peripheral region P.

[0092] Reference Fig.14 , a preliminary electrode layer 160 may be formed on the first interlayer insulating layer 102 and the lower electrode contact part 110. The preliminary electrode layer 160 may be formed to reduce a step difference between the cell region C and the peripheral region P in a subsequent process.

[0093] Specifically, in a subsequent ion beam etching process, the preliminary electrode layer 160 may compensate for a layer formed in the peripheral region P that may be etched faster than a layer formed in the cell region C. The thickness of the preliminary electrode layer 160 may be controlled according to the difference between the etching rates of the layers formed in the peripheral region P and the cell region C. In addition, the height of the upper surface of the first interlayer insulating layer 102 in the peripheral region P may be controlled in a subsequent process by adjusting the thickness of the preliminary electrode layer 160. The preliminary electrode layer 160 may include a metal such as titanium, tantalum, etc. or a metal nitride such as titanium nitride, tantalum nitride, etc.

[0094] Reference Fig.15 , a lower cover layer 162 may be formed on the preliminary electrode layer 160. A first mask structure 169 may be formed in the peripheral region P to cover the lower cover layer 162. The first mask structure 169 may not be formed on the lower cover layer 162 in the cell region C so that the lower cover layer 162 may be exposed in the cell region C. In example embodiments, the first mask structure 169 may include a lower adhesion pattern 164, a lower mask 166, and a first photoresist pattern 168 that are stacked.

[0095] In example embodiments, the lower capping layer 162 may include nitride such as silicon nitride, silicon oxynitride, or the like.

[0096] In order to form the first mask structure 169, a lower adhesion layer and a lower mask layer may be formed on the lower cover layer 162. A first photoresist pattern 168 may be formed on the lower mask layer to cover the entire peripheral region P. In addition, the lower mask layer may include carbon, such as a spin-on hard mask (SOH). Then, the lower mask layer and the lower adhesion layer in the cell region C may be sequentially etched using the first photoresist pattern 168 as an etching mask to form the first mask structure 169.

[0097] Reference Fig.16 , the lower capping layer 162 and the preliminary electrode layer 160 in the cell region C may be removed using the first mask structure 169 as an etching mask. During the etching process, the first mask structure 169 and the lower capping layer 162 in the peripheral region P may be mostly removed.

[0098] Therefore, the upper surfaces of the first interlayer insulating layer 102 and the lower electrode contact portion 110 may be exposed in the cell region C. In addition, the preliminary electrode layer 160 may be exposed in the peripheral region P. Since the preliminary electrode layer 160 remains only on the peripheral region P, the upper surface of the preliminary electrode layer 160 exposed in the peripheral region P may be higher than the upper surface of the first interlayer insulating layer 102 exposed in the cell region C.

[0099] Reference Fig.17, a lower electrode layer 112, an MTJ layer 114, and an intermediate electrode layer 116 may be sequentially formed on the first interlayer insulating layer 102, the lower electrode contact portion 110, and the preliminary electrode layer 160. An upper electrode layer 118, a first adhesion layer 120, a mold layer 122, and a second adhesion layer 124 may be sequentially formed on the intermediate electrode layer 116. This process may be similar to that of reference Figure 3 The processes shown are substantially the same or similar. After performing the processes, the upper surface of the second adhesion layer 124 in the peripheral region P may be higher than the upper surface of the second adhesion layer 124 in the cell region C.

[0100] Reference Fig.18 , a second photoresist pattern 170 may be formed on the second adhesion layer 124 through a photolithography process.

[0101] The second photoresist pattern 170 in the cell region C may include an opening having an exposed portion facing (eg, overlapping) the lower electrode contact 110 . The second photoresist pattern 170 in the peripheral region P may be formed to completely cover the upper surface of the second adhesion layer 124 .

[0102] Reference Fig.19 The second adhesive layer 124 may be etched using the second photoresist pattern 170 as an etch mask to form a second adhesive pattern 124a. The mold layer 122 may be etched using the second adhesive pattern 124a as an etch mask to form a mold pattern 122a.

[0103] A stack structure including the mold pattern 122 a and the second adhesive pattern 124 a may be formed on the cell region C and the peripheral region P through an etching process.

[0104] The second opening 128 may be included in the stacked structure in the cell region C, and the second opening 128 may face (e.g., overlap) the upper surface of the lower electrode contact portion 110 in the vertical direction. In addition, the second adhesion layer 124 in the peripheral region P may be masked by the second photoresist pattern 170 so that the second adhesion layer 124 and the mold layer 122 may not be etched by the etching process. Therefore, the stacked structure in the peripheral region P may cover the entire upper surface of the first adhesion layer 120. During the etching process, most of the second photoresist pattern 170 may be removed.

[0105] Reference Fig. 20 , a first hard mask layer 130 may be formed on the second adhesion pattern 124a to completely fill the second opening 128. In example embodiments, the first hard mask layer 130 may be formed by an ALD process. In example embodiments, the first hard mask layer 130 may include silicon oxide.

[0106] In this case, an upper surface of the first hard mask layer 130 in the peripheral region P may be higher than an upper surface of the first hard mask layer 130 in the cell region C.

[0107] Reference Fig.21 , the first hard mask layer 130 is planarized until the upper surface of the mold pattern 122a is exposed. Therefore, the first hard mask 130a may be formed in the cell region C to fill the second opening 128. In addition, the upper surface of the mold pattern 122a may be exposed in the cell region C and the peripheral region P. The upper surfaces of the mold pattern 122a in the cell region C and in the peripheral region P may be coplanar with each other. Therefore, the thickness of the mold pattern 122a in the peripheral region P may be less than the thickness of the mold pattern 122a in the cell region C.

[0108] Reference Fig. 22 , the mold pattern 122a may be removed. Therefore, a columnar first hard mask 130a may be formed on the first adhesion layer 120 in the cell region C. Since the mold pattern 122a in the peripheral region P is completely removed, the first adhesion layer 120 may be exposed in the peripheral region P.

[0109] Reference Fig.23 , the first adhesion layer 120 and the upper electrode layer 118 may be anisotropically etched using the first hard mask 130a as an etching mask. The anisotropic etching process may include an RIE process. The first adhesion layer 120 and the upper electrode layer 118 between the first hard mask 130a in the cell region C may be etched to form a cell mask structure 131 including an upper electrode 118a stacked on the intermediate electrode layer 116 and a first adhesion pattern 120a. Since the first hard mask 130a is not formed in the peripheral region P, the first adhesion layer 120 and the upper electrode layer 118 may be completely removed in the peripheral region P.

[0110] Reference Fig.24 , the cell mask structure 131 may be used as an etching mask to sequentially etch the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 in the cell region C. Subsequently, the upper portion of the first interlayer insulating layer 102 may be etched. In the etching process, the first adhesion layer 120, the upper electrode layer 118, the intermediate electrode layer 116, the MTJ layer 114, and the lower electrode layer 112 and the preliminary electrode layer 160 in the peripheral region P may be etched.

[0111] The first structure 138 including the stacked lower electrode 112a, the MTJ structure 136, the intermediate electrode 116a, and the upper electrode 118a may be formed in the cell region C through an etching process. In addition, the upper surface of the first interlayer insulating layer 102 in the peripheral region P may be exposed.

[0112] The etching process may include an IBE process. The etching process may be similar to the reference Fig.10 When the ion beam etching process is performed, the etching rate of the exposed layer between the cell mask structures 131 in the cell region C may be lower than the etching rate of the exposed layer in the peripheral region P due to the shadow effect.

[0113] That is, during etching of the intermediate electrode layer 116, the MTJ layer 114, the lower electrode layer 112, and the first interlayer insulating layer 102 between the cell mask structures 131 in the cell region C, the first adhesion layer 120, the upper electrode layer 118, the intermediate electrode layer 116, the MTJ layer 114, the lower electrode layer 112, and the preliminary electrode layer 160 in the peripheral region P may be etched. In addition, after the etching process, the upper surface of the first interlayer insulating layer 102 in the peripheral region P may be flat.

[0114] The first structures 138 may have a column shape, and the first structures 138 may contact the lower electrode contact 110 . An upper surface of the first interlayer insulating layer 102 between the first structures 138 may be lower than an upper surface of the lower electrode contact 110 .

[0115] Since the preliminary electrode layer 160 in the peripheral region P is etched more, the upper portion of the first interlayer insulating layer 102 in the peripheral region P may be hardly etched in the etching process. That is, the deposition thickness of the preliminary electrode layer 160 may be controlled in the previous process so that the upper portion of the first interlayer insulating layer 102 in the peripheral region P may not be substantially etched.

[0116] In the etching process, the etching thickness of the first interlayer insulating layer 102 in the peripheral region P may be less than the etching thickness of the first interlayer insulating layer 102 in the cell region C. Therefore, the upper surface of the first interlayer insulating layer 102 in the peripheral region P may be higher than the upper surface of the first interlayer insulating layer 102 between the first structures 138 in the cell region C.

[0117] When the above process is performed, a Fig.10 Thereafter, the same Figures 11 to 13 The process shown is basically the same or similar to the process to form Figure 1 The MRAM device shown in FIG.

[0118] Fig.25 is a cross-sectional view showing a method of manufacturing an MRAM device according to an example embodiment. The method can be compared with reference Figures 2 to 13 The method of manufacturing the MRAM device shown is substantially the same, except that the first hard mask is formed by an embossing process.

[0119] Reference Fig.25, a first interlayer insulating layer 102 may be formed on the substrate 100 , and a lower electrode contact 110 may be formed through the first interlayer insulating layer 102 .

[0120] A lower electrode layer 112, an MTJ layer 114, an intermediate electrode layer 116, an upper electrode layer 118, and a first adhesion layer 120 may be sequentially formed on the first interlayer insulating layer 102 and the lower electrode contact 110. Then, a first hard mask layer may be formed on the first adhesion layer 120, and the first hard mask layer may be patterned by photolithography to form a first hard mask 180.

[0121] The first hard mask 180 in the cell region C may have a columnar shape facing (eg, overlapping) the lower electrode contact 110 in a vertical direction. In addition, the first hard mask 180 in the peripheral region P may cover the entire upper surface of the first adhesion layer 120 in the peripheral region P. Thereafter, the same as the reference may be performed. Figures 9 to 13 The process shown is basically the same or similar to the process to form Figure 1 The MRAM device shown in FIG.

[0122] Fig.26 is a cross-sectional view showing a method of manufacturing an MRAM device according to an example embodiment. The method can be compared with reference Figures 14 to 24 The method of manufacturing the MRAM device shown is substantially the same, except that the first hard mask is formed by an imprint process.

[0123] Reference Fig.26 , a first interlayer insulating layer 102 may be formed on the substrate 100 , and a lower electrode contact 110 may be formed through the first interlayer insulating layer 102 .

[0124] Then, you can execute with reference Figures 14 to 16 The illustrated process is substantially the same or similar process to form a preliminary electrode layer 160 on the first interlayer insulating layer 102 in the peripheral region P.

[0125] A lower electrode layer 112, an MTJ layer 114, an intermediate electrode layer 116, an upper electrode layer 118, and a first adhesion layer 120 may be formed on the first interlayer insulating layer 102, the lower electrode contact 110, and the preliminary electrode layer 160. A first hard mask layer may be formed on the first adhesion layer 120, and the first hard mask layer may be patterned by a photolithography process to form a first hard mask 182.

[0126] The first hard mask 182 may be formed only in the cell region C and may not be formed in the peripheral region P. The first hard mask 182 in the cell region C may have a columnar shape that may face the lower electrode contact portion 110 in a vertical direction. In addition, the upper surface of the first adhesion layer 120 may be exposed in the peripheral region P. Thereafter, the same as the reference may be performed. Fig.23 and Fig.24 The process shown is basically the same or similar to the reference Figures 11 to 13 The process shown is basically the same or similar to the process to form Figure 1 The MRAM device shown in FIG.

[0127] In the following, reference will be made to Fig. 27 An MRAM device including transistors and underlying wiring on a substrate is described. Fig. 27 is a cross-sectional view illustrating an MRAM device according to example embodiments.

[0128] Reference Fig. 27 , the substrate 200 may include a cell region C and a peripheral region P. An isolation layer 202 may be formed at the substrate 200 , and thus an active region and a field region may be defined in the substrate 200 .

[0129] A cell transistor 218 may be formed on the substrate 200 of the cell region C. In example embodiments, the cell transistor 218 may be a buried gate transistor in which a gate 216 may be formed in a trench of the substrate 200. The gate 216 may extend in a first direction to have a linear shape. A first impurity region 212 and a second impurity region 214 may be formed at positions adjacent to sidewalls of the gate 216, respectively. In some example embodiments, the cell transistor 218 may be a planar transistor or a fin transistor.

[0130] The peripheral circuit transistor 220 may be formed on the substrate 200 in the peripheral region P. In example embodiments, the peripheral circuit transistor 220 may be a planar type transistor.

[0131] A first lower interlayer insulating layer 230a and a second lower interlayer insulating layer 230b may be formed on the substrate 200 to cover the cell transistor 218 and the peripheral circuit transistor 220. The source line 232 may extend through the first lower interlayer insulating layer 230a and may contact the first impurity region 212. Each contact plug 234 may extend through the first lower interlayer insulating layer 230a and the second lower interlayer insulating layer 230b in the cell region C and the peripheral region P and may be electrically connected to the second impurity region 214 or the peripheral circuit transistor 220.

[0132] A wiring structure 236 may be formed on each contact plug 234. Furthermore, a third lower interlayer insulating layer 238 may be formed between the wiring structures 236.

[0133] The wiring structure 236 may include a contact portion or a wire extending through the third lower interlayer insulating layer 238. The wiring structure 236 may include a barrier layer 236a and a metal pattern 236b formed on the barrier layer 236a, and the barrier layer 236a includes, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The barrier layer 236a may surround the sidewall and bottom of the metal pattern 236b. The metal pattern 236b may include, for example, tungsten, copper, aluminum, etc. The upper surfaces of the third lower interlayer insulating layer 238 and the wiring structure 236 may be coplanar with each other.

[0134] An etch stop layer 240 may be formed on the third lower interlayer insulating layer 238 and the wiring structure 236. The etch stop layer 240 may include nitride such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or the like.

[0135] The first interlayer insulating layer 102, the lower electrode contact 110, the lower electrode 112a, the MTJ structure 136, the intermediate electrode 116a, the upper electrode 118a, and the capping layer 140 may be formed on the etch stop layer 240. In addition, the second interlayer insulating layer 142, the bit line 146, the third interlayer insulating layer 144, the via contact 148, etc. may be formed.

[0136] In example embodiments, the structure formed on the etch stop layer 240 may be similar to the reference Figure 1 The structures shown are substantially the same. The lower electrode contact 110 in the cell region C may pass through the etch stop layer to contact the wiring structure 236. In addition, the via contact 148 in the peripheral region P may pass through the etch stop layer 240 to contact the wiring structure 236.

[0137] Figures 28 to 30 are cross-sectional views illustrating some stages in a method of manufacturing an MRAM device according to example embodiments.

[0138] Reference Fig.28 , an isolation layer 202 may be formed on the substrate 200 including the cell region C and the peripheral region P, so that the substrate 200 is divided into an active region and a field region. The isolation layer 202 may be formed by a shallow trench isolation (STI) process.

[0139] The cell transistor 218 may be formed on the substrate 200 of the cell region C. In addition, the peripheral circuit transistor 220 may be formed on the substrate 200 of the peripheral region P.

[0140] In example embodiments, a trench may be formed at the substrate 200 of the cell region C, and a gate 216 may be formed in the trench. A first impurity region 212 and a second impurity region 214 may be formed at the substrate on the side of the gate 216. Thus, a cell transistor 218 may be formed on the substrate 200 of the cell region C. In this case, each cell transistor 218 may be a buried gate type transistor.

[0141] In example embodiments, the peripheral circuit transistor 220 may be a planar transistor.

[0142] Reference Fig.29 , a first lower interlayer insulating layer 230a may be formed on the substrate 200. A source line 232 may be formed on the first impurity region 212 through the first lower interlayer insulating layer 230a.

[0143] A second lower interlayer insulating layer 230b may be formed on the first lower interlayer insulating layer 230a and the source line 232. Contact plugs 234 may be electrically connected to the second impurity region 214 and the peripheral circuit transistor 220 through the first and second lower interlayer insulating layers 230a and 230b in the cell region C and the peripheral region P.

[0144] Reference Fig.30 A third lower interlayer insulating layer 238 may be formed on the second lower interlayer insulating layer 230b. A wiring structure 236 may be formed on the contact plug 234 through the third lower interlayer insulating layer 238. An etch stop layer 240 may be formed on the third lower interlayer insulating layer 238 and the wiring structure 236.

[0145] The wiring structure 236 may include a barrier layer 236a and a metal pattern 236b. In example embodiments, the wiring structure 236 may be formed by a dual damascene process or a single damascene process.

[0146] In example embodiments, the etch stop layer 240 may be formed of silicon nitride or silicon oxynitride through a CVD process or an ALD process.

[0147] Refer again Fig. 27 , may be formed on the etch stop layer 240 and the wiring structure 236 Figure 1 In this case, the lower electrode contact 110 in the cell region C can pass through the etching stop layer 240 to contact the wiring structure 236. The through-hole contact 148 in the peripheral region P can pass through the etching stop layer 240 to contact the wiring structure 236. Therefore, it is possible to manufacture Fig. 27 The MRAM device shown in FIG.

[0148] In an example embodiment, by executing and referring to Figures 2 to 13The process shown is substantially the same or similar to the process shown in the figure to form an etch stop layer 240 and a wiring structure 236. Fig. 27 The structure shown in .

[0149] In some example embodiments, the Figures 14 to 24 The process shown is basically the same or similar to the reference Fig.25 The process shown is substantially the same or similar to the process shown in the reference Fig.26 The process shown is substantially the same or similar to the process shown in the figure to form an etch stop layer 240 and a wiring structure 236. Fig. 27 The structure shown in .

[0150] The MRAM device according to example embodiments may be used as a memory included in electronic products such as mobile devices, memory cards, and computers, etc.

[0151] As a summary and review, during the etching of the MTJ in the cell region of the MRAM device, a difference in etching rate between the cell region and the peripheral region of the MRAM device may occur, so that a step difference between the cell region and the peripheral region may be generated significantly. In contrast, in the MRAM according to the embodiment, the upper surface of the first interlayer insulating layer in the peripheral region may be higher than the upper surface of the first interlayer insulating layer in the cell region. Therefore, the step difference between the cell region and the peripheral region can be reduced. Since reliability defects and wiring defects caused by the step difference are reduced, the characteristics of the MRAM can be improved.

[0152] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as known to those of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A magnetoresistive random access memory device, comprising: a first interlayer insulating layer on the substrate including the cell region and the peripheral region; a lower electrode contact portion of the first interlayer insulating layer extending through the cell region; a first structure on each of the lower electrode contacts, the first structure comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode stacked in sequence; a covering layer covering the first interlayer insulating layer and the surface of the first structure in the cell region and the peripheral region; a second interlayer insulating layer on the cover layer in the cell region and the peripheral region to fill gaps between the first structures; a third interlayer insulating layer on the second interlayer insulating layer; as well as a through-hole contact extending through the third interlayer insulating layer, the second interlayer insulating layer, the cover layer, and the first interlayer insulating layer in the peripheral region, The upper surface of the cover layer on the first interlayer insulating layer in the peripheral region is higher than the upper surface of the cover layer on the first interlayer insulating layer between the first structures in the cell region. 2 . The magnetoresistive random access memory device according to claim 1 , wherein an upper surface of the first interlayer insulating layer in the peripheral region is higher than an upper surface of the first interlayer insulating layer between the first structures in the cell region. 3 . The magnetoresistive random access memory device according to claim 1 , wherein an upper surface of the first interlayer insulating layer between the first structures in the cell region is lower than an upper surface of the lower electrode contact portion. 4 . The magnetoresistive random access memory device according to claim 1 , wherein an upper surface of the first interlayer insulating layer in the peripheral region is coplanar with an upper surface of the lower electrode contact portion or is lower than an upper surface of the lower electrode contact portion. 5 . The magnetoresistive random access memory device of claim 1 , wherein an upper surface of the first interlayer insulating layer in the peripheral region is substantially flat. 6 . The magnetoresistive random access memory device of claim 1 , wherein the capping layer is conformal on surfaces of the first interlayer insulating layer and the first structure in the cell region and the peripheral region such that the capping layer has a uniform thickness. 7 . The magnetoresistive random access memory device according to claim 1 , wherein the capping layer comprises silicon nitride or silicon oxynitride.

8. The magnetoresistive random access memory device according to claim 1, further comprising: a bit line in the second interlayer insulating layer, the bit line contacting the upper electrode of the first structure, Wherein, the upper surface of the bit line is lower than the upper surface of the through hole contact portion.

9. The magnetoresistive random access memory device according to claim 1, further comprising: A lower wiring and a lower interlayer insulating layer are provided on the substrate, and the through-hole contact is electrically connected to the lower wiring.

10. A magnetoresistive random access memory device, comprising: a first interlayer insulating layer on the substrate including the cell region and the peripheral region; a lower electrode contact portion of the first interlayer insulating layer extending through the cell region; a first structure on each of the lower electrode contacts, the first structure comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode stacked in sequence; a second interlayer insulating layer on the first interlayer insulating layer to fill gaps between the first structures; a third interlayer insulating layer on the second interlayer insulating layer; as well as A via contact extends through the third interlayer insulating layer, the second interlayer insulating layer, and the first interlayer insulating layer in the peripheral region, wherein an upper surface of the first interlayer insulating layer in the peripheral region is higher than an upper surface of the first interlayer insulating layer between the first structures in the cell region. 11 . The magnetoresistive random access memory device according to claim 10 , further comprising a capping layer covering the first interlayer insulating layer and surfaces of the first structure in the cell region and the peripheral region, the second interlayer insulating layer being on the capping layer. 12 . The magnetoresistive random access memory device according to claim 11 , wherein an upper surface of the first interlayer insulating layer between the first structures in the cell region is lower than an upper surface of the lower electrode contact. 13 . The magnetoresistive random access memory device of claim 10 , further comprising a bit line in the second interlayer insulating layer, the bit line contacting the upper electrode of the first structure.

14. A magnetoresistive random access memory device, comprising: a first interlayer insulating layer on the substrate including the cell region and the peripheral region; a lower electrode contact portion of the first interlayer insulating layer extending through the cell region; a first structure on each of the lower electrode contacts, the first structure comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode stacked in sequence; a covering layer covering the first interlayer insulating layer and the surface of the first structure in the cell region and the peripheral region, the covering layer having a uniform thickness; a second interlayer insulating layer on the cover layer in the cell region and the peripheral region to fill gaps between the first structures; a third interlayer insulating layer on the second interlayer insulating layer; as well as A through-hole contact extends through the third interlayer insulating layer, the second interlayer insulating layer, the cover layer, and the first interlayer insulating layer in the peripheral region, wherein an upper surface of the first interlayer insulating layer between the first structures in the cell region is lower than an upper surface of the first interlayer insulating layer in the peripheral region. 15 . The magnetoresistive random access memory device according to claim 14 , wherein an upper surface of the capping layer on the first interlayer insulating layer in the peripheral region is higher than an upper surface of the capping layer on the first interlayer insulating layer between the first structures in the cell region. 16 . The magnetoresistive random access memory device of claim 14 , wherein an upper surface of the first interlayer insulating layer between the first structures in the cell region is lower than an upper surface of the lower electrode contact. 17 . The magnetoresistive random access memory device of claim 14 , wherein an upper surface of the first interlayer insulating layer in the peripheral region is coplanar with or lower than an upper surface of the lower electrode contact portion. 18 . The magnetoresistive random access memory device of claim 14 , wherein an upper surface of the first interlayer insulating layer in the peripheral region is substantially flat.

19. The magnetoresistive random access memory device according to claim 14, further comprising: a bit line in the second interlayer insulating layer, the bit line contacting the upper electrode of the first structure, Wherein, the upper surface of the bit line is lower than the upper surface of the through hole contact portion.

20. A method for manufacturing a magnetoresistive random access memory device, the method comprising: forming a first interlayer insulating layer on the substrate including the cell region and the peripheral region; forming a lower electrode contact portion of the first interlayer insulating layer extending through the cell region; forming a first structure on each of the lower electrode contacts, the first structure comprising a lower electrode, a magnetic tunnel junction structure and an upper electrode stacked in sequence; forming a cover layer covering surfaces of the first interlayer insulating layer and the first structure in the cell region and the peripheral region; forming a second interlayer insulating layer on the cover layer in the cell region and the peripheral region to fill gaps between the first structures; forming a third interlayer insulating layer on the second interlayer insulating layer; as well as A through-hole contact extending through the third interlayer insulating layer, the second interlayer insulating layer and the first interlayer insulating layer is formed in the peripheral region, wherein an upper surface of the covering layer on the first interlayer insulating layer in the peripheral region is higher than an upper surface of the covering layer on the first interlayer insulating layer between the first structures in the cell region.

21. The method of claim 20, wherein forming the first structure comprises: forming a lower electrode layer, a magnetic tunnel junction layer and an upper electrode layer on the first interlayer insulating layer and the lower electrode contact portion; forming a hard mask on the upper electrode layer, wherein the hard mask has a columnar shape in the cell region, and the hard mask covers an upper surface of the upper electrode layer in the peripheral region; as well as using the hard mask as an etching mask, etching the upper electrode layer, the magnetic tunnel junction layer, and the lower electrode layer in the cell region and the peripheral region and an upper portion of the first interlayer insulating layer in the cell region, After etching, an upper surface of the first interlayer insulating layer in the peripheral region is higher than an upper surface of the first interlayer insulating layer between the first structures in the cell region.

22. The method of claim 20, wherein forming the first structure comprises: forming a preliminary electrode layer covering the first interlayer insulating layer in the peripheral region to expose an upper surface of the first interlayer insulating layer in the cell region; forming a lower electrode layer, a magnetic tunnel junction layer and an upper electrode layer on the first interlayer insulating layer, the lower electrode contact portion and the preliminary electrode layer; forming a hard mask on the upper electrode layer, wherein the hard mask has a columnar shape in the cell region, and an upper surface of the upper electrode layer in the peripheral region is exposed by the hard mask; as well as using the hard mask as an etching mask, etching the upper electrode layer, the magnetic tunnel junction layer and the lower electrode layer in the cell region and the peripheral region, the upper portion of the first interlayer insulating layer in the cell region, and the preliminary electrode layer in the peripheral region, After etching, an upper surface of the first interlayer insulating layer in the peripheral region is higher than an upper surface of the first interlayer insulating layer between the first structures in the cell region. 23 . The method of claim 20 , wherein the capping layer is conformally formed on a surface of the first interlayer insulating layer and a surface of the first structure in the cell region and the peripheral region.

24. The method of claim 20, further comprising: forming a bit line in the second interlayer insulating layer, the bit line contacting the upper electrode of the first structure, Wherein, the upper surface of the bit line is lower than the upper surface of the through hole contact portion.

Images