Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the display device are provided, the display device comprising: a base substrate; a first thin film transistor disposed on the base substrate; a via insulating layer disposed on the first thin film transistor; and a light emitting structure disposed on the via insulating layer. The first thin film transistor comprises: a first gate electrode; an oxide semiconductor overlapping the first gate electrode and comprising tin (Sn); an etching stopper disposed on the oxide semiconductor and comprising an oxide semiconductor material that does not contain tin (Sn); a first source electrode in contact with the oxide semiconductor; and a first drain electrode in contact with the oxide semiconductor and spaced apart from the first source electrode.

Description

Technical Field

[0001] Exemplary embodiments of the invention relate generally to a display device and a method of manufacturing the same, and more particularly, to a display device capable of improving display quality and a method of manufacturing the same. Background Art

[0002] Recently, display devices with light weight and small size have been manufactured. Cathode ray tube (CRT) display devices have been used due to good performance and competitive price. However, CRT display devices have various disadvantages such as high power consumption and relatively large size, resulting in lack of portability. Therefore, display devices such as plasma display devices, liquid crystal display devices and organic light emitting display devices have received great attention due to small size, light weight and low power consumption.

[0003] A display device includes a plurality of pixels including thin film transistors. Dispersion may refer to the lack of uniformity in the quality of an element. Dispersion of thin film transistors affects display quality, and therefore efforts have been made to reduce dispersion.

[0004] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] Exemplary embodiments of the inventive concept provide a display device capable of improving display quality.

[0006] Exemplary embodiments of the inventive concept also provide a method of manufacturing a display device.

[0007] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0008] An exemplary embodiment of the inventive concept provides a display device, the display device comprising: a base substrate; a first thin film transistor disposed on the base substrate; a via insulating layer disposed on the first thin film transistor; and a light emitting structure disposed on the via insulating layer. The first thin film transistor comprises: a first gate electrode; an oxide semiconductor overlapping the first gate electrode and including tin (Sn); an etching stopper disposed on the oxide semiconductor and including an oxide semiconductor material that does not contain tin (Sn); a first source electrode in contact with the oxide semiconductor; and a first drain electrode in contact with the oxide semiconductor and spaced apart from the first source electrode.

[0009] The first gate electrode may be disposed between the base substrate and the oxide semiconductor.

[0010] The etch stopper may cover only a portion of an upper surface of the oxide semiconductor.The first source electrode and the first drain electrode may be in contact with the upper surface of the oxide semiconductor.

[0011] A contact hole may be formed through the etch stopper to expose an upper surface of the oxide semiconductor. The first source electrode and the first drain electrode may contact the oxide semiconductor through the contact hole.

[0012] The oxide semiconductor may include a x ), indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc tin oxide (IZTO), aluminum zinc tin oxide (TAZO), indium gallium tin oxide (IGTO), and indium gallium zinc tin oxide (IGZTO). The etch stopper may include at least one selected from the group consisting of zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr x O y ), at least one selected from the group consisting of indium gallium zinc oxide (IGZO) and indium gallium hafnium oxide (IGHO).

[0013] The display device may further include: an interlayer insulating layer disposed between the first gate electrode and the oxide semiconductor; and a second thin film transistor disposed on the base substrate. The second thin film transistor may include: an active pattern disposed on the base substrate; a second gate electrode disposed on the active pattern; and a second source electrode and a second drain electrode disposed on the interlayer insulating layer and electrically connected to the active pattern.

[0014] The light emitting structure may include: a first electrode electrically connected to the second thin film transistor; a light emitting layer disposed on the first electrode; and a second electrode disposed on the light emitting layer.

[0015] The display device may include a plurality of pixels to display an image, and each of the plurality of pixels may include a first thin film transistor, a second thin film transistor, and a light emitting structure.

[0016] The display device may further include a storage electrode overlapping the second gate electrode.

[0017] Another exemplary embodiment of the inventive concept provides a display device, comprising: a base substrate; a gate electrode disposed on the base substrate; an oxide semiconductor overlapping the gate electrode and including tin (Sn); an etch stopper disposed on the oxide semiconductor and including an oxide semiconductor material that does not contain tin (Sn); a source electrode in contact with the oxide semiconductor; and a drain electrode in contact with the oxide semiconductor and spaced apart from the source electrode.

[0018] Another exemplary embodiment of the inventive concept provides a method for manufacturing a display device, the method comprising: forming a first gate electrode on a base substrate; forming an interlayer insulating layer on the first gate electrode; sequentially forming an oxide semiconductor layer and an etch stop layer on the interlayer insulating layer; forming a photoresist pattern having a first thickness and a second thickness on the etch stop layer; forming an oxide semiconductor and an etch stop pattern by etching the etch stop layer and the oxide semiconductor layer using the photoresist pattern as an etch barrier; forming a first photoresist pattern by partially removing the photoresist pattern so that a portion of an upper surface of the etch stop pattern is exposed; forming an etch stop by etching the etch stop pattern using the first photoresist pattern as an etch barrier; forming a conductive layer on the etch stop, the oxide semiconductor and the interlayer insulating layer; and forming a first source electrode and a first drain electrode by etching the conductive layer.

[0019] The oxide semiconductor may include an oxide semiconductor material including tin (Sn). The etch stopper may include an oxide semiconductor material not including tin (Sn).

[0020] The oxide semiconductor may include a x ), indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc tin oxide (IZTO), aluminum zinc tin oxide (TAZO), indium gallium tin oxide (IGTO), and indium gallium zinc tin oxide (IGZTO). The etch stopper may include at least one selected from the group consisting of zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr x O y ), at least one selected from the group consisting of indium gallium zinc oxide (IGZO) and indium gallium hafnium oxide (IGHO).

[0021] The etch stopper layer and the oxide semiconductor layer may be wet-etched by a hydrofluoric acid or oxalic acid series etching solution.

[0022] The etch stopper pattern may be wet-etched by an etching solution of a phosphoric acid-nitric acid-acetic acid series.

[0023] The conductive layer may be dry-etched by a fluorine-based gas.

[0024] The method may further include forming an active pattern on the base substrate and forming a second gate electrode on the active pattern. A second source electrode and a second drain electrode electrically connected to the active pattern may also be formed by etching the conductive layer.

[0025] The method may further include forming a storage electrode overlapping the second gate electrode on the second gate electrode before forming the interlayer insulating layer. The storage electrode and the first gate electrode may be formed of the same layer.

[0026] The active pattern may include polysilicon.

[0027] The etch stopper may cover only a portion of an upper surface of the oxide semiconductor.The first source electrode and the first drain electrode may be in contact with the upper surface of the oxide semiconductor.

[0028] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0030] Figure 1 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0031] Figure 2 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0032] Figure 3 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0033] Figure 4 It is shown that the Figure 3 FIG. 1 is a diagram of an example of a pixel in a display device.

[0034] Figure 5 It is shown Figure 3 and Figure 4 A cross-sectional view of a display device.

[0035] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I It is used to explain the manufacturing Figure 1 A cross-sectional view of a method of displaying a device.

[0036] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 7H It is used to explain the manufacturing Figure 2 A cross-sectional view of a method of displaying a device.

[0037] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E It is used to explain the manufacturing Figure 5 A cross-sectional view of a method of displaying a device.

[0038] Fig. 9 is a block diagram illustrating an electronic device according to an example embodiment.

[0039] Fig. 10A It shows that Fig. 9 The electronic device is implemented as an example of a television.

[0040] Fig. 10B It shows that Fig. 9 The electronic device is implemented as an example of a smart phone.

[0041] Fig.11 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments of the invention. "Embodiment" as used herein is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0043] Unless otherwise specified, the exemplary embodiments shown will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0044] The use of cross hatching and / or shading is usually provided in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or demand for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0045] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bonded to" another element or layer, the element or layer may be directly on, directly connected to or directly bonded to the other element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bonded to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as an x-axis, a y-axis and a z-axis), and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be named as the second element without departing from the disclosed teachings.

[0047] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features would subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" may include both above and below orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0048] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limiting. As used here, unless the context clearly indicates otherwise, the singular "one (kind / person)" and "the (described)" are also intended to include plural forms. In addition, when the term "include" and its variants and / or "comprising" and its variants are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. It is also noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and are used to explain the measured values, calculated values ​​and / or the inherent deviations of the provided values ​​that those of ordinary skill in the art will recognize.

[0049] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views of schematic diagrams as idealized exemplary embodiments and / or intermediate structures. In this way, variations in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specifically shown shapes of the regions, but rather include deviations in shapes caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, so they are not necessarily intended to be limiting.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which this disclosure is a part. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0051] Figure 1 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0052] Reference Figure 1 The display device may include a base substrate 100, a gate electrode GE, an interlayer insulating layer 140, an oxide semiconductor OS, an etching stopper ES, a drain electrode DE, a source electrode SE, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0053] A base substrate 100 including a transparent or opaque insulating material can be provided. For example, the base substrate 100 can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a quartz substrate doped with fluoride, a soda-lime glass substrate, an alkali-free glass substrate, etc. Alternatively, the base substrate 100 can include a flexible transparent material, such as a flexible transparent resin substrate (e.g., a polyimide substrate). In this case, the polyimide substrate can include a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate can have a configuration in which the first polyimide layer, the barrier film layer, and the second polyimide layer are stacked on a rigid glass substrate.

[0054] The gate electrode GE may be disposed on the base substrate 100. The gate electrode GE may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0055] The interlayer insulating layer 140 may be disposed on the gate electrode GE. The interlayer insulating layer 140 may fully cover the gate electrode GE on the base substrate 100, and may have a substantially flat upper surface without a step around the gate electrode GE. Alternatively, the interlayer insulating layer 140 may cover the gate electrode GE on the base substrate 100, and may be disposed with a substantially uniform thickness along the contour of the gate electrode GE.

[0056] The interlayer insulating layer 140 may include a silicon compound, a metal oxide, etc. For example, the interlayer insulating layer 140 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiOx C y ), Silicon Carbide Nitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), titanium oxide (TiO x ) etc. The interlayer insulating layer 140 may be formed of a plurality of layers.

[0057] The oxide semiconductor OS may be disposed on the interlayer insulating layer 140. The oxide semiconductor OS may overlap the gate electrode GE. The oxide semiconductor OS may be an oxide semiconductor including tin (Sn). The oxide semiconductor OS may also include indium (In), zinc (Zn), gallium (Ga), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), and may be a two-component compound (AB x ), ternary compounds (AB x C y ), four-component compound (AB x C y D z ) etc.

[0058] For example, the oxide semiconductor OS may be made of tin oxide (SnO x At least one selected from the group consisting of indium tin oxide (ITO), zinc tin oxide (ZTO), indium zinc tin oxide (IZTO), tin aluminum zinc oxide (TAZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. Since the oxide semiconductor OS includes tin, a semiconductor having a higher mobility than that of an oxide semiconductor not including tin can be realized.

[0059] The etch stopper ES may be disposed on the oxide semiconductor OS. The etch stopper ES may have a size smaller than that of the oxide semiconductor OS. That is, the etch stopper ES may cover only a portion of the upper surface of the oxide semiconductor OS so that an edge portion of the upper surface of the oxide semiconductor OS is exposed. The etch stopper ES may include an oxide semiconductor material that does not include tin. The etch stopper ES may be an oxide semiconductor layer that includes a two-component compound (AB) that may include indium, zinc, gallium, titanium, aluminum, hafnium, zirconium, and magnesium. x ), ternary compounds (AB x C y ), four-component compound (AB x C y Dz )wait.

[0060] For example, the etch stopper ES may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide (IGZO), indium gallium hafnium oxide (IGHO), etc.

[0061] The drain electrode DE may be disposed on the interlayer insulating layer 140 on which the oxide semiconductor OS and the etch stopper ES are disposed. The drain electrode DE may be in contact with and connected to the etch stopper ES and the oxide semiconductor OS. That is, the drain electrode DE may directly contact the upper edge of the oxide semiconductor OS exposed by the etch stopper ES.

[0062] The source electrode SE may be spaced apart from the drain electrode DE on the interlayer insulating layer 140 on which the oxide semiconductor OS and the etching stopper ES are disposed. The source electrode SE may contact and be connected to the etching stopper ES and the oxide semiconductor OS. That is, the source electrode SE may directly contact the upper edge of the oxide semiconductor OS exposed by the etching stopper ES.

[0063] The drain electrode DE and the source electrode SE may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The drain electrode DE and the source electrode SE may be formed of a plurality of layers. For example, the drain electrode DE and the source electrode SE may include a titanium (Ti) layer and a molybdenum (Mo) layer (Ti / Mo structure) on the titanium layer. Alternatively, the drain electrode DE and the source electrode SE may include a titanium (Ti) layer, an aluminum (Al) layer on the titanium layer, and a titanium (Ti) layer (Ti / Al / Ti structure) on the aluminum layer.

[0064] The gate electrode GE, the oxide semiconductor OS, the etch stopper ES, and the source and drain electrodes SE and DE may be included in the thin film transistor TFT. The thin film transistor TFT may have a bottom gate structure.

[0065] The thin film transistor TFT has a bottom gate structure, has a channel length smaller than that of the top gate structure, and does not require the formation of a separate contact hole. When the source electrode SE and the drain electrode DE are patterned, since the etching stopper ES protects the oxide semiconductor OS, the thickness and size of the oxide semiconductor OS are constant, thereby reducing the dispersion of the plurality of thin film transistors included in the display device. In addition, since the source electrode SE and the drain electrode DE can be patterned by a dry etching process, the size of the thin film transistor TFT can be further reduced. Therefore, this is advantageous for realizing a high-resolution display device.

[0066] The via insulating layer 150 may be disposed on the thin film transistor TFT. The via insulating layer 150 may have a single-layer structure or a multi-layer structure including at least two insulating films. The via insulating layer 150 may be formed using an organic material. For example, the via insulating layer 150 may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, etc. In some exemplary embodiments, the via insulating layer 150 may include an inorganic material such as a silicon compound, a metal oxide, etc.

[0067] The light emitting structure 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0068] The first electrode 181 may be disposed on the via insulating layer 150. The first electrode 181 may include a reflective material or a transmissive material according to the emission type of the display device. In an exemplary embodiment, the first electrode 181 may have a single-layer structure or a multi-layer structure, and the single-layer structure or the multi-layer structure may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0069] The pixel defining layer PDL may be disposed on the via insulating layer 150 on which the first electrode 181 is disposed. The pixel defining layer PDL may be formed using an organic material. For example, the pixel defining layer PDL may include a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, and the like. In some exemplary embodiments, an opening exposing the first electrode 181 may be formed by etching the pixel defining layer PDL. The emission region and the non-emission region of the display device may be defined by the opening of the pixel defining layer PDL. For example, the portion where the opening of the pixel defining layer PDL is located may correspond to the emission region, and the non-emission region may correspond to the portion adjacent to the opening of the pixel defining layer PDL.

[0070] The light emitting layer 182 may be disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In some exemplary embodiments, the light emitting layer 182 may include an organic light emitting layer (EL), a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), an electron injection layer (EIL), etc. In some exemplary embodiments, in addition to the organic light emitting layer, the hole injection layer, the hole transport layer, the electron transport layer, and the electron injection layer may be formed in common to correspond to a plurality of pixels. In some exemplary embodiments, a plurality of organic light emitting layers may be formed using light emitting materials for generating light of different colors such as red light, green light, and blue light according to the color pixels of the display device. In some exemplary embodiments, the organic light emitting layer of the light emitting layer 182 may include a plurality of stacked light emitting materials for generating red light, green light, and blue light, thereby emitting white light. Here, the elements of the light emitting layer 182 are formed in common to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.

[0071] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to the emission type of the display device. In an exemplary embodiment, the second electrode 183 may also have a single-layer structure or a multi-layer structure, and the single-layer structure or the multi-layer structure may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0072] The thin film encapsulation layer TFE may be disposed on the second electrode 183. The thin film encapsulation layer TFE may prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer TFE may include at least one organic layer and at least one inorganic layer. At least one organic layer and at least one inorganic layer may be alternately stacked with each other. For example, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer located between the two inorganic layers, but is not limited thereto. In some exemplary embodiments, a sealing substrate for shielding external air and moisture from penetrating into the display device may be provided instead of the thin film encapsulation layer TFE.

[0073] On the other hand, in the present exemplary embodiment, the thin film transistor TFT has a bottom gate structure, but may also have a top gate structure. Fig.11 The display device may include an oxide semiconductor OS disposed on a base substrate 100, an etch stopper ES disposed on the oxide semiconductor OS, a gate insulating layer 120 disposed on the etch stopper ES, a gate electrode GE overlapped with the oxide semiconductor OS on the gate insulating layer 120, an interlayer insulating layer 140 disposed on the gate electrode GE, and a source electrode SE and a drain electrode DE disposed on the interlayer insulating layer 140.

[0074] The source electrode SE and the drain electrode DE may be connected to the oxide semiconductor OS through a contact hole formed through the interlayer insulating layer 140 and the gate insulating layer 120. Here, the contact hole may expose a portion of the etch stopper ES so that the source electrode SE and the drain electrode DE contact the etch stopper ES. Although not shown, according to another exemplary embodiment, the source electrode SE and the drain electrode DE may be arranged not to contact the etch stopper ES.

[0075] In addition, the display device may further include a via insulating layer 150 , a light emitting structure 180 , a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0076] Since each structure of the display device Figure 1 Each configuration of the display device is substantially the same, and thus a detailed description will be omitted.

[0077] Figure 2 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0078] Reference Figure 2 , except for the etching stopper ES, the display device and Figure 1 Therefore, repeated explanations will be omitted.

[0079] The display device may include a base substrate 100 , a gate electrode GE, an interlayer insulating layer 140 , an oxide semiconductor OS, an etch stopper ES, a drain electrode DE, a source electrode SE, a via insulating layer 150 , a light emitting structure 180 , a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0080] The first contact hole CNT1 and the second contact hole CNT2 may be formed through the etching stopper ES. The first contact hole CNT1 and the second contact hole CNT2 may expose the upper surface of the oxide semiconductor OS. The source electrode SE may contact the upper surface of the oxide semiconductor OS through the first contact hole CNT1. The drain electrode DE may contact the upper surface of the oxide semiconductor OS through the second contact hole CNT2.

[0081] Figure 3 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0082] Reference Figure 3 , the display device may include a display panel 10 , a scan driver 20 , a data driver 30 , an emission control driver 40 , and a controller 50 .

[0083] The display panel 10 may include a plurality of pixels PX to display an image. For example, since the pixels PX are arranged at positions corresponding to intersections of the scan lines SL1 to SLn and the data lines DL1 to DLm, the display panel 10 may include n×m pixels PX, where n and m are integers greater than 1. Each of the pixels PX may include a driving transistor and a plurality of switching transistors. Figure 4 The structure of the pixel PX is described in detail.

[0084] The scan driver 20 may provide the first scan signal to the pixel PX step by step through the scan lines SL1 to SLn based on the first control signal CTL1. The scan driver 20 may provide the second scan signal to the pixel PX step by step through the inverted scan lines / SL1 to / SLn based on the first control signal CTL1. For example, the second scan signal may correspond to a signal inverted from the first scan signal.

[0085] The data driver 30 may provide data signals to the pixels PX through the data lines DL1 to DLm based on the second control signal CTL2 .

[0086] The emission control driver 40 may provide an emission control signal to the pixel PX through the emission control lines EM1 to EMn based on the third control signal CTL3 .

[0087] The controller 50 may control the scan driver 20, the data driver 30, and the emission control driver 40. The controller 50 may generate control signals CTL1, CTL2, and CTL3 to control the scan driver 20, the data driver 30, and the emission control driver 40. The first control signal CTL1 for controlling the scan driver 20 may include a vertical start signal, a scan clock signal, etc. The second control signal CTL2 for controlling the data driver 30 may include digital image data, a horizontal start signal, etc. The third control signal CTL3 for controlling the emission control driver 40 may include an emission control start signal, an emission control clock signal, etc.

[0088] In addition, the display device (eg, an organic light emitting display device) may further include a power supply (not shown) that provides the first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage VINT to the display panel 10 .

[0089] Figure 4 It is shown that the Figure 3 FIG. 1 is a diagram of an example of a pixel PX in a display device of FIG.

[0090] Reference Figure 4, the pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST and an organic light emitting diode OLED. The pixel PX may be located at the i-th pixel row and the j-th pixel column, where i is an integer between 1 and n, and j is an integer between 1 and m.

[0091] The first transistor T1 may be a driving transistor that provides a driving current corresponding to a data signal to the organic light emitting diode OLED. The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3.

[0092] The second transistor T2 may provide a data signal to the first transistor T1 in response to the first scan signal GS1. In an exemplary embodiment, the second transistor T2 may include a gate electrode receiving the first scan signal GS1 from the i-th scan line SLi, a first electrode receiving the data signal from the j-th data line DLj, and a second electrode connected to the first electrode of the first transistor T1 (i.e., the second node N2).

[0093] The third transistor T3 may connect the second electrode of the first transistor T1 to the gate electrode of the first transistor T1 in response to the second scan signal GS2. In an exemplary embodiment, the third transistor T3 may include a gate electrode receiving the second scan signal GS2 from the i-th inversion scan line / SLi, a first electrode connected to the second electrode of the first transistor T1 (i.e., the third node N3), and a second electrode connected to the gate electrode of the first transistor T1 (i.e., the first node N1).

[0094] The fourth transistor T4 may apply the initialization voltage VINT to the gate electrode of the first transistor T1 in response to the third scan signal GS3. In an exemplary embodiment, the fourth transistor T4 may include a gate electrode receiving the third scan signal GS3 from the i-1th inverting scan line / SL(i-1), a first electrode receiving the initialization voltage VINT, and a second electrode connected to the gate electrode of the first transistor T1 (i.e., the first node N1).

[0095] The fifth transistor T5 may apply the first power voltage ELVDD to the first electrode of the first transistor T1 in response to the emission control signal. In an exemplary embodiment, the fifth transistor T5 may include a gate electrode receiving the emission control signal from the i-th emission control line EMi, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the first electrode of the first transistor T1 (i.e., the second node N2).

[0096] The sixth transistor T6 may connect the second electrode of the first transistor T1 to the first electrode of the organic light emitting diode OLED in response to the emission control signal. In an exemplary embodiment, the sixth transistor T6 may include a gate electrode receiving the emission control signal from the i-th emission control line EMi, a first electrode connected to the second electrode of the first transistor T1 (i.e., the third node N3), and a second electrode connected to the first electrode of the organic light emitting diode OLED (i.e., the fourth node N4).

[0097] The seventh transistor T7 may apply the initialization voltage VINT to the first electrode of the organic light emitting diode OLED in response to the fourth scan signal GS4. In an exemplary embodiment, the seventh transistor T7 may include a gate electrode receiving the fourth scan signal GS4 from the i-1th inversion scan line / SL(i-1), a first electrode receiving the initialization voltage VINT, and a second electrode connected to the first electrode of the organic light emitting diode OLED (i.e., the fourth node N4).

[0098] Here, each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be a polycrystalline Si thin film transistor as a P-type transistor (refer to Figure 5 TFT2 in FIG. 1 ). Each of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be an oxide thin film transistor as an N-type transistor (see FIG. 1 ). Figure 5 TFT1 in).

[0099] The storage capacitor CST may include a first electrode receiving the first power voltage ELVDD and a second electrode connected to the gate electrode of the first transistor T1 (ie, the first node N1 ).

[0100] Figure 5 It is shown Figure 3 and Figure 4 A cross-sectional view of a display device.

[0101] Reference Figure 5 The display device may include a base substrate 100, a buffer layer 110, an active pattern ACT, a first gate insulating layer 120, a first gate pattern, a second gate insulating layer 130, a second gate pattern, an interlayer insulating layer 140, an oxide semiconductor OS, an etching stopper ES, a source-drain pattern, a via insulating layer 150, a light emitting structure 180, a pixel defining layer PDL, and a thin film encapsulation layer TFE.

[0102] The base substrate 100 including a transparent or opaque insulating material may be provided. The base substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate.

[0103] The buffer layer 110 may be disposed on the base substrate 100. The buffer layer 110 may be disposed on the entire base substrate 100. The buffer layer 110 may prevent metal atoms and / or impurities from diffusing from the base substrate 100 into the active pattern ACT. In addition, the buffer layer 110 may control a heat transfer rate in a crystallization process for forming the active pattern ACT, thereby obtaining a substantially uniform active pattern ACT. In addition, when the surface of the base substrate 100 is uneven, the buffer layer 110 may improve the flatness of the surface of the base substrate 100.

[0104] The active pattern ACT may be disposed on the buffer layer 110. The active pattern ACT may include polycrystalline silicon. The active pattern ACT may include a drain region and a source region doped with impurities and a channel region between the drain region and the source region. Polycrystalline silicon may be formed by first depositing amorphous silicon and then crystallizing it. Here, amorphous silicon may be crystallized by rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), continuous lateral solidification (SLS), etc. Impurities may be doped in a portion of the active pattern ACT to form a source region and a drain region.

[0105] The first gate insulating layer 120 may cover the active pattern ACT on the buffer layer 110 and may be disposed with a substantially uniform thickness along a contour of the active pattern ACT. Alternatively, the first gate insulating layer 120 may fully cover the active pattern ACT on the buffer layer 110 and may have a substantially flat upper surface without a step around the active pattern ACT.

[0106] The first gate pattern may be disposed on the first gate insulating layer 120. The first gate pattern may include a second gate electrode GE2. The first gate pattern may also include a signal line such as a gate line for driving a display device. The first gate pattern may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0107] The second gate insulating layer 130 may be disposed on the first gate insulating layer 120 on which the first gate pattern is disposed. The second gate insulating layer 130 may cover the first gate pattern on the first gate insulating layer 120, and may be disposed with a substantially uniform thickness along the contour of the first gate pattern. Alternatively, the second gate insulating layer 130 may fully cover the first gate pattern on the first gate insulating layer 120, and may have a substantially flat upper surface without a step around the first gate pattern. The second gate insulating layer 130 may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0108] The second gate pattern may be disposed on the second gate insulating layer 130. The second gate pattern may include a first gate electrode GE1, a storage electrode CE, and a signal line. The storage electrode CE may form a storage capacitor by overlapping the second gate electrode GE2. The second gate pattern may be formed using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.

[0109] The interlayer insulating layer 140 may be disposed on the second gate insulating layer 130 on which the second gate pattern is disposed. The interlayer insulating layer 140 may sufficiently cover the second gate pattern on the second gate insulating layer 130, and may have a substantially flat upper surface without a step around the second gate pattern. The interlayer insulating layer 140 may include an inorganic insulating material such as a silicon compound or a metal oxide.

[0110] The oxide semiconductor OS may be disposed on the interlayer insulating layer 140. The oxide semiconductor OS may overlap the first gate electrode GE1. The oxide semiconductor OS may include an oxide semiconductor material including tin (Sn).

[0111] The etch stopper ES may be disposed on the oxide semiconductor OS. The etch stopper ES may include an oxide semiconductor material that does not contain tin (Sn). The etch stopper ES may cover only a portion of the upper surface of the oxide semiconductor OS so that an edge portion of the upper surface of the oxide semiconductor OS is exposed. Figure 2 In an exemplary embodiment of the present invention, the contact hole may be formed through the etch stopper ES.

[0112] The source-drain pattern may be disposed on the interlayer insulating layer 140 on which the oxide semiconductor OS and the etch stopper ES are disposed. The source-drain pattern may include a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2.

[0113] The first drain electrode DE1 may be connected to the etch stopper ES and the oxide semiconductor OS by contacting the etch stopper ES and the oxide semiconductor OS. The first source electrode SE1 may be spaced apart from the first drain electrode DE1 on the interlayer insulating layer 140 on which the etch stopper ES and the oxide semiconductor OS are disposed. The first source electrode SE1 may be connected to the etch stopper ES and the oxide semiconductor OS by contacting the etch stopper ES and the oxide semiconductor OS.

[0114] The second source electrode SE2 may be electrically connected to the active pattern ACT through a contact hole formed through the interlayer insulating layer 140, the second gate insulating layer 130, and the first gate insulating layer 120. The second drain electrode DE2 may be electrically connected to the active pattern ACT through a contact hole formed through the interlayer insulating layer 140, the second gate insulating layer 130, and the first gate insulating layer 120.

[0115] The source-drain pattern may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. The source-drain pattern may be formed of multiple layers. For example, the source-drain pattern may include a titanium (Ti) layer and a molybdenum (Mo) layer on the titanium layer (Ti / Mo structure). Alternatively, the source-drain pattern may include a titanium (Ti) layer, an aluminum (Al) layer on the titanium layer, and a titanium (Ti) layer on the aluminum layer (Ti / Al / Ti structure).

[0116] Therefore, the first thin film transistor TFT1 including the first gate electrode GE1, the first source electrode SE1, the first drain electrode DE1 and the oxide semiconductor OS may have a bottom gate structure. The second thin film transistor TFT2 including the second gate electrode GE2, the second source electrode SE2, the second drain electrode DE2 and the active pattern ACT may have a top gate structure.

[0117] The via insulating layer 150 may be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2. The via insulating layer 150 may have a single layer structure, or may have a multi-layer structure including at least two insulating layers.

[0118] The light emitting structure 180 may include a first electrode 181, a light emitting layer 182, and a second electrode 183. The pixel defining layer PDL may be disposed on the via insulating layer 150 on which the first electrode 181 is disposed. The light emitting layer 182 may be disposed on the first electrode 181 exposed through an opening of the pixel defining layer PDL. The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. A thin film encapsulation layer TFE may be disposed on the second electrode 183.

[0119] The light emitting structure 180, the pixel defining layer PDL and the thin film encapsulation layer TFE may be Figure 1 The light emitting structure 180, the pixel defining layer PDL, and the thin film encapsulation layer TFE of the display device are substantially the same. Therefore, a detailed description will be omitted.

[0120] Here, the first thin film transistor TFT1 may be Figure 4 The second thin film transistor TFT2 may be any one of the third transistor T3, the fourth transistor T4 and the seventh transistor T7. Figure 4Any one of the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6.

[0121] FIG. 6A to FIG. 6I It is used to explain the manufacturing Figure 1 A cross-sectional view of a method of displaying a device.

[0122] Reference Fig. 6A , the gate electrode GE may be formed on the base substrate 100. The interlayer insulating layer 140 may be formed on the base substrate 100 on which the gate electrode GE is formed.

[0123] Reference Figure 6B , an oxide semiconductor layer OSL may be formed on the interlayer insulating layer 140. An etch stopper layer ESL may be formed on the oxide semiconductor layer OSL.

[0124] Reference Figure 6C , a photoresist pattern PR having a first thickness t1 and a second thickness t2 may be formed on the etch stopper layer ESL. The first thickness t1 may be less than the second thickness t2. A portion of the photoresist pattern PR having the first thickness t1 may correspond to a portion of an oxide semiconductor (to be described later) exposed by the etch stopper. A portion of the photoresist pattern PR having the second thickness t2 may correspond to the etch stopper. The photoresist pattern PR may be formed using a halftone mask or the like.

[0125] Reference Fig.6D , the etch stopper layer ESL and the oxide semiconductor layer OSL may be etched using the photoresist pattern PR as an etch barrier. Thus, the oxide semiconductor OS and the etch stopper pattern ESP may be formed.

[0126] For example, the etching stopper layer ESL and the oxide semiconductor layer OSL may be wet-etched by a hydrofluoric acid or oxalic acid series etching solution. The etching stopper layer ESL includes an oxide semiconductor material that does not include tin (Sn), and the oxide semiconductor layer OSL includes an oxide semiconductor material that includes tin (Sn), so that both the etching stopper layer ESL and the oxide semiconductor layer OSL may be wet-etched using the above-mentioned hydrofluoric acid or oxalic acid series etching solution.

[0127] Reference Fig. 6E , a portion of the upper surface of the etch stopper pattern ESP may be exposed by partially removing the photoresist pattern PR.

[0128] For example, the photoresist pattern PR may be thinned as a whole by an ashing process, thereby removing a portion having a first thickness t1 and leaving only a central portion PR' (or referred to as a first photoresist pattern) having a second thickness t2. The portion of the upper surface of the etch stopper pattern ESP may be exposed.

[0129] Reference Fig. 6F , the etch stopper pattern ESP may be etched using the central portion PR′ as an etch barrier to form an etch stopper ES.

[0130] For example, the etching stopper pattern ESP may be wet-etched by an etching solution of a phosphoric acid-nitric acid-acetic acid series. At this time, since the etching stopper pattern ESP includes an oxide semiconductor material that does not contain tin, the etching stopper pattern ESP is etched by the etching solution of the phosphoric acid-nitric acid-acetic acid series. However, since the oxide semiconductor OS includes an oxide semiconductor material that contains tin, the etching selectivity for the etching solution of the phosphoric acid-nitric acid-acetic acid series is low, and the oxide semiconductor OS remains unremoved. Therefore, a portion of the upper surface of the oxide semiconductor OS may be exposed. Thereafter, the central portion PR' may be removed.

[0131] Meanwhile, the method of manufacturing the display device may further include an annealing process for heating the oxide semiconductor OS and a plasma process for improving conductivity of the oxide semiconductor OS.

[0132] Reference Figure 6G , a conductive layer CL may be formed on the interlayer insulating layer 140 on which the etch stopper ES and the oxide semiconductor OS are formed. The conductive layer CL may include a plurality of metal layers.

[0133] Reference Figure 6H , the source electrode SE and the drain electrode DE can be formed by etching the conductive layer CL. For example, the source electrode SE and the drain electrode DE can be formed by patterning the conductive layer CL using a photolithography process and / or an etching process using an additional etching mask. Here, since the oxide semiconductor OS is covered by the etching stopper ES and the etching stopper ES includes an oxide semiconductor material that does not contain tin, the oxide semiconductor OS can be protected in the process of etching the conductive layer CL.

[0134] For example, the conductive layer CL may be dry-etched by a fluorine-based gas. Thus, a thin film transistor TFT may be formed. The oxide semiconductor OS including an oxide semiconductor material containing tin may be damaged by the fluorine-based gas. However, since the oxide semiconductor OS is protected by the etching stopper ES, the properties of the oxide semiconductor OS are not changed, and thus the dispersion of the thin film transistor in the final product can be reduced.

[0135] Since the source electrode SE and the drain electrode DE are patterned by dry etching, a finer pattern can be formed, and the size of the thin film transistor TFT can be further reduced.

[0136] Reference Fig.6I , a via insulating layer 150, a first electrode 181, a pixel defining layer PDL, a light emitting layer 182, a second electrode 183, and a thin film encapsulation layer TFE may be formed on the thin film transistor TFT. Thus, a display device may be manufactured. The via insulating layer 150, the first electrode 181, the pixel defining layer PDL, the light emitting layer 182, the second electrode 183, and the thin film encapsulation layer TFE may be formed by various known methods, and a detailed description thereof will be omitted.

[0137] 7A to 7H It is used to explain the manufacturing Figure 2 The method of manufacturing a display device is similar to the method of manufacturing a display device except that the first contact hole and the second contact hole of the etching stopper are etched. FIG. 6A to FIG. 6I Therefore, repeated description will be simplified or omitted.

[0138] Reference Fig. 7A , a gate electrode GE may be formed on the base substrate 100. An interlayer insulating layer 140 may be formed on the base substrate 100 having the gate electrode GE formed thereon. An oxide semiconductor layer OSL may be formed on the interlayer insulating layer 140. An etch stopper layer ESL may be formed on the oxide semiconductor layer OSL.

[0139] Reference Figure 7B , a photoresist pattern PR having a first thickness t1 and a second thickness t2 may be formed on the etch stopper layer ESL. The first thickness t1 may be less than the second thickness t2. A portion of the photoresist pattern PR having the first thickness t1 may correspond to a portion of an oxide semiconductor to be described later that is exposed by the etch stopper. A portion of the photoresist pattern PR having the second thickness t2 may correspond to the etch stopper. The photoresist pattern PR may be formed using a half-tone mask or the like.

[0140] Reference Figure 7C , the etch stopper layer ESL and the oxide semiconductor layer OSL may be etched using the photoresist pattern PR as an etch barrier. Thus, the oxide semiconductor OS and the etch stopper pattern ESP may be formed.

[0141] Reference Fig.7D , a portion of the upper surface of the etch stopper pattern ESP may be exposed by partially removing the photoresist pattern PR, thereby remaining the first photoresist pattern PR′.

[0142] Reference Fig. 7E, the first contact hole CNT1 and the second contact hole CNT2 may be formed by etching the etch stopper pattern ESP through the etch stopper ES using the first photoresist pattern PR′ as an etch barrier.

[0143] Reference Figure 7F , a conductive layer CL may be formed on the interlayer insulating layer 140 on which the etch stopper ES and the oxide semiconductor OS are formed.

[0144] Reference Figure 7G , the source electrode SE and the drain electrode DE may be formed by etching the conductive layer CL. Thus, the thin film transistor TFT may be formed.

[0145] Reference Figure 7H , a via insulating layer 150 , a first electrode 181 , a pixel defining layer PDL, a light emitting layer 182 , a second electrode 183 , and a thin film encapsulation layer TFE may be formed on the thin film transistor TFT. Thus, a display device may be manufactured.

[0146] FIG. 8A to FIG. 8E It is used to explain the manufacturing Figure 5 A method for manufacturing a display device is a cross-sectional view of a method for manufacturing a display device. In addition to the buffer layer, the active pattern, the first gate insulating layer and the second gate insulating layer, the first gate pattern and the second gate pattern, the method for manufacturing a display device is similar to FIG. 6A to FIG. 6I Therefore, repeated description will be simplified or omitted.

[0147] Reference Fig. 8A , a buffer layer 110 may be formed on the base substrate 100. An active pattern ACT may be formed on the buffer layer 110. The active pattern ACT may be formed by forming an amorphous silicon layer, crystallizing the amorphous silicon layer, and patterning the amorphous silicon layer by photolithography or the like. A first gate insulating layer 120 may be formed on the active pattern ACT. A first gate pattern including a second gate electrode GE2 may be formed on the first gate insulating layer 120. A second gate insulating layer 130 may be formed on the first gate insulating layer 120 on which the first gate pattern is formed. A second gate pattern including a storage electrode CE and a first gate electrode GE1 may be formed on the second gate insulating layer 130.

[0148] Reference Figure 8B , an interlayer insulating layer 140 may be formed on the second gate insulating layer 130 on which the second gate pattern is formed. A contact hole CNT may be formed through the interlayer insulating layer 140. An oxide semiconductor OS and an etch stopper ES may be formed on the interlayer insulating layer 140. Here, the method of forming the oxide semiconductor OS and the etch stopper ES may be the same as that of FIG. 6B to FIG. 6F The method shown in is basically the same.

[0149] Reference Figure 8C , a conductive layer CL may be formed on the interlayer insulating layer 140 on which the etch stopper ES and the oxide semiconductor OS are formed. The conductive layer CL may include a plurality of metal layers.

[0150] Reference Fig.8D , a source-drain pattern including a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2 may be formed by etching the conductive layer CL. For example, the source-drain pattern may be formed by patterning the conductive layer CL using a photolithography process and / or an etching process using an additional etching mask. For example, the conductive layer CL may be dry-etched by a fluorine-based gas. Thus, a first thin film transistor TFT1 and a second thin film transistor TFT2 may be formed.

[0151] Reference Fig. 8E , a via insulating layer 150 , a first electrode 181 , a pixel defining layer PDL, a light emitting layer 182 , a second electrode 183 , and a thin film encapsulation layer TFE may be formed on the first thin film transistor TFT1 and the second thin film transistor TFT2 . Thus, a display device may be manufactured.

[0152] According to an exemplary embodiment of the present invention, a display device includes a thin film transistor having an oxide semiconductor and an etching stopper. The thin film transistor has a bottom gate structure, has a channel length shorter than that of a top gate structure, and does not require the formation of a separate contact hole. In addition, in the manufacturing process, since the etching stopper protects the oxide semiconductor, the thickness and size of the oxide semiconductor are constant, thereby reducing the dispersion of multiple thin film transistors included in the display device. In addition, since the source electrode and the drain electrode can be patterned by a dry etching process, the size of the thin film transistor can be further reduced. Therefore, this is advantageous for realizing a high-resolution display device.

[0153] Fig. 9 is a block diagram illustrating an electronic device according to an example embodiment. Fig. 10A It shows that Fig. 9 The electronic device is implemented as an example of a television. Fig. 10B It shows that Fig. 9 The electronic device is implemented as an example of a smart phone.

[0154] Reference Figures 9 to 10B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output (I / O) device 540, a power supply 550, and a display device 560. Here, the display device 560 may correspond to Figure 1In addition, the electronic device 500 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an exemplary embodiment, as Fig. 10A As shown in , the electronic device 500 may be implemented as a television. In another example embodiment, as Fig. 10B As shown in , the electronic device 500 can be implemented as a smart phone. However, the electronic device 500 is not limited thereto. For example, the electronic device 500 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer display, a notebook computer, a head mounted display (HMD), etc.

[0155] The processor 510 can perform various computing functions. The processor 510 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 510 can be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 520 can store data for the operation of the electronic device 500. For example, the memory device 520 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.). The storage device 530 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 540 may include an input device such as a keyboard, a pocket keyboard, a mouse device, a touch pad, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 550 may provide power for the operation of the electronic device 500.

[0156] The display device 560 may be coupled to other components via a bus or other communication lines. In some example embodiments, the display device 560 may be included in the I / O device 540. As described above, the display device 560 may include a thin film transistor having a bottom gate structure, an oxide semiconductor, and an etching stopper. Therefore, the dispersion of the thin film transistor can be reduced and high resolution can be achieved. However, since this has been described above, a repeated description thereof will be omitted.

[0157] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: base substrate; A first thin film transistor is disposed on the base substrate; A via insulating layer, disposed on the first thin film transistor; as well as A light emitting structure is arranged on the via insulating layer, wherein the first thin film transistor includes: a first gate electrode; an oxide semiconductor overlapping the first gate electrode and including tin; an etching stopper disposed on the oxide semiconductor and including an oxide semiconductor material that does not include tin; a first source electrode in contact with the oxide semiconductor; and a first drain electrode in contact with the oxide semiconductor and spaced apart from the first source electrode, The oxide semiconductor is composed of at least one selected from the group consisting of indium gallium tin oxide and indium gallium zinc tin oxide.

2. The display device according to claim 1, wherein: The first gate electrode is disposed between the base substrate and the oxide semiconductor.

3. The display device according to claim 2, wherein: The etch stopper covers only a portion of an upper surface of the oxide semiconductor; and The first source electrode and the first drain electrode contact the upper surface of the oxide semiconductor.

4. The display device according to claim 2, wherein: A contact hole is formed through the etch stopper to expose an upper surface of the oxide semiconductor; and The first source electrode and the first drain electrode contact the oxide semiconductor through the contact hole.

5. The display device according to claim 1, wherein: The etch stopper includes at least one selected from the group consisting of zinc oxide, gallium oxide, titanium oxide, indium oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, zinc magnesium oxide, zinc zirconium oxide, indium gallium zinc oxide, and indium gallium hafnium oxide.

6. The display device according to claim 1, further comprising: an interlayer insulating layer, disposed between the first gate electrode and the oxide semiconductor; as well as A second thin film transistor is disposed on the base substrate, The second thin film transistor includes: an active pattern disposed on the base substrate; a second gate electrode disposed on the active pattern; and a second source electrode and a second drain electrode disposed on the interlayer insulating layer and electrically connected to the active pattern.

7. The display device according to claim 6, wherein: The light emitting structure comprises: a first electrode electrically connected to the second thin film transistor; a light-emitting layer, disposed on the first electrode; and The second electrode is arranged on the light-emitting layer.

8. The display device according to claim 7, wherein: The display device includes a plurality of pixels to display an image; and Each of the plurality of pixels includes the first thin film transistor, the second thin film transistor, and the light emitting structure.

9. The display device according to claim 6, wherein: The display device also includes a storage electrode overlapping the second gate electrode.

10. A display device, comprising: base substrate; A gate electrode is disposed on the base substrate; an oxide semiconductor overlapping the gate electrode and including tin; an etch stopper disposed on the oxide semiconductor and comprising an oxide semiconductor material that does not contain tin; a source electrode in contact with the oxide semiconductor; as well as a drain electrode in contact with the oxide semiconductor and spaced apart from the source electrode, The oxide semiconductor is composed of at least one selected from the group consisting of indium gallium tin oxide and indium gallium zinc tin oxide.

11. A method for manufacturing a display device, the method comprising the following steps: forming a first gate electrode on the base substrate; forming an interlayer insulating layer on the first gate electrode; sequentially forming an oxide semiconductor layer and an etch stopper layer on the interlayer insulating layer; forming a photoresist pattern having a first thickness and a second thickness on the etch stop layer; forming an oxide semiconductor and an etch stopper pattern by etching the etch stopper layer and the oxide semiconductor layer using the photoresist pattern as an etch barrier; forming a first photoresist pattern by partially removing the photoresist pattern to expose a portion of an upper surface of the etch stopper pattern; forming an etch stopper by etching the etch stopper pattern using the first photoresist pattern as an etch barrier; forming a conductive layer on the etch stopper, the oxide semiconductor, and the interlayer insulating layer; as well as forming a first source electrode and a first drain electrode by etching the conductive layer, wherein the oxide semiconductor includes an oxide semiconductor material including tin, and the oxide semiconductor is composed of at least one selected from the group consisting of indium gallium tin oxide and indium gallium zinc tin oxide, and Wherein, the etching stopper comprises an oxide semiconductor material that does not contain tin.

12. The method according to claim 11, wherein: The etch stopper includes at least one selected from the group consisting of zinc oxide, gallium oxide, titanium oxide, indium oxide, indium gallium oxide, indium zinc oxide, gallium zinc oxide, zinc magnesium oxide, zinc zirconium oxide, indium gallium zinc oxide, and indium gallium hafnium oxide.

13. The method according to claim 11, wherein: The etching stopper layer and the oxide semiconductor layer are wet-etched by a hydrofluoric acid or oxalic acid series etching solution.

14. The method according to claim 13, wherein: The etch stopper pattern is wet-etched by an etching solution of a phosphoric acid-nitric acid-acetic acid series.

15. The method according to claim 14, wherein: The conductive layer is dry-etched by a fluorine-based gas.

16. The method according to claim 11, further comprising: forming an active pattern on the base substrate; as well as forming a second gate electrode on the active pattern, Wherein, a second source electrode and a second drain electrode electrically connected to the active pattern are also formed by etching the conductive layer.

17. The method according to claim 16, further comprising forming a storage electrode overlapping the second gate electrode on the second gate electrode before forming the interlayer insulating layer, in, The storage electrode and the first gate electrode are formed of a same layer.

18. The method according to claim 16, wherein: The active pattern includes polysilicon.

19. The method of claim 11, wherein: The etch stopper covers only a portion of an upper surface of the oxide semiconductor; and The first source electrode and the first drain electrode are in contact with the upper surface of the oxide semiconductor.

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