Semiconductor device including PN junction diode

Abstract

A semiconductor device including a pn junction diode and a method for manufacturing the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer positioned in the substrate. The device further includes a semiconductor region having a second conductivity type, the semiconductor region extending below the buried oxide layer to form a pn junction with the semiconductor region having the first conductivity type. The pn junction is positioned below the buried oxide layer and extends substantially orthogonally relative to the main surface of the substrate. The device also includes a field plate electrode, the field plate electrode including a semiconductor region positioned above the buried oxide layer for changing an electric field at the pn junction by applying an electric potential to the field plate electrode.

Description

Technical Field

[0001] The present specification relates to a semiconductor device including a pn junction diode and a method of manufacturing the semiconductor device including the pn junction diode. Background Art

[0002] In advanced fully depleted silicon on insulator (FDSOI) technology, while most active devices (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) are built on SOI regions where the insulator is a buried oxide layer, active devices with high current and high voltage (e.g., laterally diffused metal oxide semiconductor field effect transistors (LDMOS), PN junction diodes) are built on non-SOI regions (i.e., on a conventional bulk substrate that can be referred to as a hybrid region from which the oxide layer has been removed). The reverse bias junction breakdown voltage is one of the key figures of merit (FoM) for these devices.

[0003] Figure 1 An example of a pn junction diode 10 is shown. The diode includes a semiconductor substrate 2, which may be a p-type substrate. An n-well 4 is positioned on the substrate 2. A p-type (P+) region 14 forms a first electrode (cathode) of the diode 10. The other electrode (anode) of the diode 10 is formed by an n-type region 12. The electrodes 12, 14 are separated by an isolation region 6.

[0004] exist Figure 1 In devices of the type shown, the pn junction is located at the interface between the underside of the p-type region 14 and the n-well 4. Therefore, the point where the highest electric field occurs in such a device (and therefore the point where breakdown occurs - at Figure 1 The diode 14 is located deep in the substrate (ie, away from the silicon surface) and is indicated at 20 in FIG. 1. In such a device, the breakdown voltage is determined simply by the junction doping between the p-type region 14 and the n-well 4. This diode is a vertical device. Summary of the invention

[0005] Various aspects of the disclosure are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not exclusively as explicitly set out in the claims.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor device, the semiconductor device comprising:

[0007] a semiconductor substrate having a first conductivity type;

[0008] a buried oxide layer positioned in said substrate;

[0009] a semiconductor region having a second conductivity type, the semiconductor region extending below the buried oxide layer to form a pn junction with the semiconductor region having the first conductivity type, wherein the pn junction is positioned below the buried oxide layer and extends substantially orthogonally relative to a main surface of the substrate; and

[0010] A field plate electrode includes a semiconductor region positioned above the buried oxide layer for changing an electric field at the pn junction by applying an electric potential to the field plate electrode.

[0011] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device including a pn junction diode, the method comprising:

[0012] providing a semiconductor substrate having a first conductivity type;

[0013] forming a buried oxide layer in the substrate;

[0014] forming a semiconductor region having a second conductivity type, wherein the semiconductor region having the second conductivity type extends below the buried oxide layer to form a pn junction with the semiconductor region having the first conductivity type, and wherein the pn junction is positioned below the buried oxide layer and extends substantially orthogonally with respect to a main surface of the substrate; and

[0015] A field plate electrode is formed, the field plate electrode including a semiconductor region positioned over the buried oxide layer for changing an electric field at the pn junction by applying an electric potential to the field plate electrode.

[0016] Compared to the pn junction located deeper in the substrate (usually at the interface between the underside of the p-type region located in the n-well, such as Figure 1 In the known device of FIG. 1 , a pn junction arrangement positioned below a buried oxide layer and extending substantially orthogonally relative to a main surface of a substrate can allow a significant increase in the breakdown voltage of the device. Furthermore, the proximity of the pn junction to the buried oxide layer can allow the breakdown voltage and / or leakage current of the device to be adjusted by applying a bias voltage to the field plate electrode. This diode is a lateral device.

[0017] The semiconductor region of the first conductivity type that forms the pn junction with the semiconductor region of the second conductivity type may include a doped semiconductor region that is more highly doped than the substrate and is positioned directly below the buried oxide layer. In this way, a pn junction diode between a highly doped region and a lower doped semiconductor region of the first conductivity type may be formed. The more highly doped region may be positioned directly below the buried oxide layer so that the pn junction itself is closer to the field plate electrode in order to more closely control the breakdown voltage and / or leakage current of the device.

[0018] The device may include a semiconductor region of the first conductivity type, the semiconductor region being positioned in the substrate directly below the buried oxide layer and laterally spaced apart from the pn junction. This semiconductor region may be more highly doped than the substrate. This may improve performance by reducing the resistance of the device, thereby allowing a better trade-off between on-resistance and breakdown voltage of the device.

[0019] A portion of the semiconductor region having the second conductivity type extending below the buried oxide layer that is positioned directly below the buried oxide layer can be more highly doped than the remainder of the semiconductor region having the second conductivity type extending below the buried oxide layer. The more highly doped region can be positioned directly below the buried oxide layer so that the pn junction itself is closer to the field plate electrode in order to more closely control the breakdown voltage and / or leakage current of the device.

[0020] The semiconductor region forming the field plate electrode may have the second conductivity type.

[0021] The field plate electrode may extend over substantially the entire semiconductor region of the second conductivity type positioned below the buried oxide layer.

[0022] The field plate electrode may extend over the pn junction. Again, this may allow tighter control over the breakdown voltage and / or leakage current of the device.

[0023] A portion of the semiconductor region having the second conductivity type extending below the buried oxide layer that is positioned directly below the buried oxide layer can be more highly doped than the remainder of the semiconductor region having the second conductivity type extending below the buried oxide layer. The more highly doped region can be positioned directly below the buried oxide layer so that the pn junction itself is closer to the field plate electrode in order to more closely control the breakdown voltage and / or leakage current of the device.

[0024] The semiconductor region forming the field plate electrode may have the first conductivity type.

[0025] The field plate electrode may extend over substantially the entire semiconductor region of the first conductivity type positioned below the buried oxide layer.

[0026] The field plate electrode may extend over the pn junction. Again, this may allow tighter control over the breakdown voltage and / or leakage current of the device.

[0027] The device may include a first electrode, the first electrode includes a semiconductor region having the first conductivity type, the first electrode is positioned in the semiconductor region having the first conductivity type forming the pn junction. The device may also include a second electrode, the second electrode includes a semiconductor region having the second conductivity type, the second electrode is positioned in the semiconductor region having the second conductivity type.

[0028] The first electrode and the second electrode may each be separated from each other by one or more isolation regions.

[0029] In some embodiments, the semiconductor substrate may be a fully depleted silicon-on-insulator (FDSOI) substrate. In such embodiments, the buried oxide layer may be an insulating layer of the FDSOI substrate.

[0030] According to another aspect of the present disclosure, an ESD protection device is provided, the ESD protection device comprising the semiconductor device of the type described above.

[0031] According to another aspect of the present disclosure, a switch for a power management circuit is provided, wherein the switch includes a semiconductor device of the type described above.

[0032] According to another aspect of the present disclosure, a switch for an RF front-end circuit is provided, the switch comprising a semiconductor device of the type described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Some embodiments of the present disclosure will be described below by way of example only, with reference to the accompanying drawings, in which like reference numerals represent like elements, and in which:

[0034] Figure 1 An example of a semiconductor device including a pn junction diode is shown;

[0035] Figure 2 A semiconductor device including a pn junction diode according to an embodiment of the present disclosure is shown;

[0036] Figure 3 A semiconductor device including a pn junction diode according to another embodiment of the present disclosure is shown; and

[0037] Figure 4 A semiconductor device including a pn junction diode according to further embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0039] Figure 2 A semiconductor device 10 including a pn junction diode according to an embodiment of the present disclosure is shown.

[0040] The device 10 includes a semiconductor substrate, which may include silicon. In some embodiments, the substrate may be a silicon-on-insulator (SOI) substrate, and in particular, may be a fully depleted silicon-on-insulator (FDSOI) substrate.

[0041] like Figure 2 As shown, the substrate in this example may include a first region 8, on which a buried oxide layer 30 is positioned. In embodiments where the substrate includes an SOI (e.g., FDSOI) substrate, the buried oxide layer 30 may be formed by an insulating layer of the SOI / FDSOI substrate. A field plate electrode of the device may be formed on top of the buried oxide layer 30, as will be described in more detail below. The substrate may also include a region 2 that is not below the buried oxide layer 30. In embodiments where the substrate includes an SOI (e.g., FDSOI) substrate, the region 2 may include a so-called mixed region of the SOI / FDSOI substrate, in which the insulating layer of the SOI / FDSOI is not present.

[0042] The substrate (including regions 2, 8) has a first conductivity type. In the present embodiment, the first conductivity type is p-type conductivity, but it is contemplated that in other embodiments, the first conductivity type may be n-type conductivity.

[0043] The device 10 also includes a semiconductor region 4 extending below the buried oxide layer 30. The semiconductor region 4 has a second conductivity type, which is a conductivity type different from the first conductivity type. In the present embodiment, the second conductivity type is an n-type conductivity type, but it is contemplated that in other embodiments, the second conductivity type may be a p-type conductivity type.

[0044] The semiconductor region 4 forms a pn junction with a semiconductor region 8 of the first conductivity type. The pn junction extends substantially orthogonally relative to the main surface of the substrate. The pn junction is positioned below the buried oxide layer 30.

[0045] The device 10 also includes a field plate electrode 16. The field plate electrode 16 in this embodiment has a second conductivity type. The field plate electrode 16 extends over the semiconductor region 4 having the second conductivity type, and in this embodiment also extends over a portion of the first region 8 that forms a pn junction between the semiconductor region 4 and the first region 8. Therefore, the pn junction is positioned directly below the field plate electrode 16. The proximity of the pn junction to the buried oxide layer 30 can allow the field plate electrode 16 to be biased by applying a bias voltage (V FP ) to modify the electric field at the pn junction in order to adjust the breakdown voltage and / or leakage current of the device. In some examples, the device can be configured based on application requirements (e.g., based on whether a higher breakdown voltage or a lower on-resistance (R on ), or a combination of both) statically or dynamically connects the field plate 16 to ground, biases it positively or negatively.

[0046] In the present embodiment, the semiconductor region 8 is provided with a region 32 having a first conductivity type and being more highly doped than the rest of the substrate (e.g., region 8). In some embodiments, the highly doped region 32 may be provided as part of a layer (e.g., a ground plane) that is typically available in a variety of FDSOI technologies. By utilizing this layer, the device 10 may be constructed without having to make special preparations for the highly doped region 32 (e.g., without additional implants or associated costs).

[0047] In this embodiment, region 32 forms a pn junction with semiconductor region 4. Region 32 is positioned directly below buried oxide layer 30. In this way, location 20 where breakdown may occur can be positioned near field plate electrode 16 so that the breakdown voltage and / or leakage current of the device can be tightly controlled by applying a bias voltage to field plate electrode 16.

[0048] The device also includes a first electrode 14, which includes a semiconductor region having a first conductivity type. The first electrode 14 is positioned in the semiconductor substrate (specifically, in region 2). The first electrode 14 in this embodiment forms the cathode of the device 10. The first electrode 14 can be more highly doped than the rest of the substrate (e.g., region 2).

[0049] The device further comprises a second electrode 12 comprising a semiconductor region of the second conductivity type. The second electrode 12 is positioned in the semiconductor region 4 of the second conductivity type and in this embodiment forms the anode of the device 10. The second electrode 12 may be more highly doped than the rest of the semiconductor region 4.

[0050] In the present embodiment, the second electrode 12 and the first electrode 14 are each separated from each other by one or more isolation regions 6 .

[0051] Figure 3 A semiconductor device 10 including a pn junction diode according to another embodiment of the present disclosure is shown. Figure 3 The device 10 in some aspects is combined with the above Figure 2 The described apparatus 10 is similar and only the differences will be described below.

[0052] In the present embodiment, the semiconductor region 4 is provided with a region 34 having a second conductivity type and being more highly doped than the rest of the semiconductor region 4. In some embodiments, the highly doped region 34 may be provided as part of a layer (e.g., a ground plane) that is typically available in a variety of FDSOI technologies. By utilizing this layer, the device 10 may be constructed without having to make special preparations for the highly doped region 34 (e.g., without additional implants or associated costs).

[0053] In this embodiment, region 34 forms a pn junction with semiconductor region 8. Region 34 is positioned directly below buried oxide layer 30. In this way, location 20 where breakdown may occur can be positioned near field plate electrode 16 so that by applying a bias voltage (V FP ) to tightly control the breakdown voltage and / or leakage current of the device. This embodiment does not (necessarily) include the above-mentioned Figure 2 Area 32 describing the type.

[0054] In this embodiment, the field plate electrode 16 has a first conductivity type (p-type in this embodiment). Figure 2 In contrast to the embodiment of the present invention, the field plate electrode 16 extends over substantially the entire semiconductor region 8 of the first conductivity type positioned below the buried oxide layer 30. The field plate electrode 16 may also extend over the pn junction and optionally also over a portion of the region 4. Thus, the pn junction is positioned directly below the field plate electrode 16. The proximity of the pn junction to the buried oxide layer 30 may allow the field plate electrode 16 to be biased by applying a bias voltage (V FP ) to modify the electric field at the pn junction in order to adjust the breakdown voltage and / or leakage current of the device. Again, in some examples, the device can be configured to have a higher breakdown voltage or a lower on-resistance (R) based on application requirements (e.g., whether a higher breakdown voltage or a lower on-resistance (R) is preferred). on ), or a combination of both) statically or dynamically connects the field plate 16 to ground, biases it positively or negatively.

[0055] Figure 4 A semiconductor device 10 including a pn junction diode according to further embodiments of the present disclosure is shown. Figure 4 The device 10 in some aspects is combined with the above Figure 3 The described apparatus 10 is similar and only the differences will be described below.

[0056] The field plate electrode 16 in this embodiment has the second conductivity type. The field plate electrode 16 extends over the semiconductor region 4 having the second conductivity type, and in this embodiment also extends over a portion of the first region 8 that forms a pn junction between the semiconductor region 4 and the first region 8. Therefore, the pn junction is positioned directly below the field plate electrode 16. The proximity of the pn junction to the buried oxide layer 30 can allow the field plate electrode 16 to be biased by applying a bias voltage (V FP ) to modify the electric field at the pn junction in order to adjust the breakdown voltage and / or leakage current of the device. Again, in some examples, the device can be configured to have a higher breakdown voltage or a lower on-resistance (R) based on application requirements (e.g., whether a higher breakdown voltage or a lower on-resistance (R) is preferred). on ), or a combination of both) statically or dynamically connects the field plate 16 to ground, biases it positively or negatively.

[0057] In this embodiment, device 10 includes a semiconductor region 38 having a first conductivity type, which is positioned in region 8 of the substrate directly below buried oxide layer 30. Semiconductor region 38 can be more highly doped than the rest of the substrate (e.g., region 8). Semiconductor region 38 is laterally spaced apart from the pn junction formed between region 34 and region 8. Including semiconductor region 38 can improve performance by reducing the resistance of device 10, thereby allowing a better trade-off between the on-resistance and breakdown voltage of device 10.

[0058] Semiconductor devices 10 of the kind described herein may be provided in an ESD protection device.Semiconductor devices 10 of the kind described herein may be provided in a switch for a power management circuit.Semiconductor devices 10 of the kind described herein may be provided in a switch for an RF front-end circuit.

[0059] A method of manufacturing a semiconductor device 10 including a pn junction diode of the type described herein may include providing a semiconductor substrate having a first conductivity type. The method may also include forming (e.g., depositing) a buried oxide layer 30 in the substrate. The method may further include forming a semiconductor region 4 having a second conductivity type, wherein the semiconductor region 4 having the second conductivity type extends below the buried oxide layer 30 to form a pn junction with a semiconductor region 8 of the substrate having the first conductivity type. The pn junction is positioned below the buried oxide layer 30 and extends substantially orthogonally relative to the main surface of the substrate. The method also includes forming (e.g., depositing and patterning) a field plate electrode 16, the field plate electrode 16 including a semiconductor region positioned above the buried oxide layer 30 for changing the electric field at the pn junction by applying an electric potential to the field plate electrode.

[0060] Thus, a semiconductor device including a pn junction diode and a method for manufacturing the same have been described. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer positioned in the substrate. The device further includes a semiconductor region having a second conductivity type, the semiconductor region extending below the buried oxide layer to form a pn junction with the semiconductor region having the first conductivity type. The pn junction is positioned below the buried oxide layer and extends substantially orthogonally relative to a major surface of the substrate. The device also includes a field plate electrode, the field plate electrode including a semiconductor region positioned above the buried oxide layer for changing an electric field at the pn junction by applying an electric potential to the field plate electrode.

[0061] Although specific embodiments of the present disclosure have been described, it should be understood that modifications / additions and / or substitutions may be made within the scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate having a first conductivity type; a buried oxide layer positioned in said substrate; a semiconductor region of a second conductivity type extending below the buried oxide layer to form a pn junction with the semiconductor region of the first conductivity type, wherein the pn junction is positioned below the buried oxide layer in a direction orthogonal to the main surface of the substrate and extends substantially orthogonally relative to the main surface of the substrate; as well as A field plate electrode includes a second semiconductor region positioned above the buried oxide layer for changing the electric field at the pn junction by applying an electric potential to the field plate electrode, the second semiconductor region being positioned above the buried oxide layer in a direction orthogonal to the main surface of the substrate.

2. The semiconductor device according to claim 1, wherein: The semiconductor region of the first conductivity type forming the pn junction with the semiconductor region of the second conductivity type includes a doped semiconductor region that is more highly doped than the substrate and is positioned directly below the buried oxide layer.

3. The semiconductor device according to claim 1, wherein: A third semiconductor region of the first conductivity type is included, the third semiconductor region being positioned in the substrate directly below the buried oxide layer and laterally spaced apart from the pn junction, wherein the third semiconductor region is more highly doped than the substrate.

4. The semiconductor device according to claim 3, wherein: A portion of the semiconductor region of the second conductivity type extending below the buried oxide layer that is positioned directly below the buried oxide layer is more highly doped than a remaining portion of the semiconductor region of the second conductivity type extending below the buried oxide layer.

5. The semiconductor device according to claim 2, wherein: The second semiconductor region forming the field plate electrode has the second conductivity type.

6. The semiconductor device according to claim 1, wherein: A portion of the semiconductor region of the second conductivity type extending below the buried oxide layer that is positioned directly below the buried oxide layer is more highly doped than a remaining portion of the semiconductor region of the second conductivity type extending below the buried oxide layer.

7. The semiconductor device according to claim 1, wherein: include: a first electrode, the first electrode including a fourth semiconductor region of the first conductivity type, the first electrode being positioned in the semiconductor region of the first conductivity type forming the pn junction; as well as A second electrode includes a fifth semiconductor region having the second conductivity type, the second electrode being positioned in the semiconductor region having the second conductivity type.

8. The semiconductor device according to claim 1, wherein: The semiconductor substrate comprises a fully depleted silicon-on-insulator (FDSOI) substrate, and wherein the buried oxide layer comprises an insulating layer of the FDSOI substrate.

9. An ESD protection device, a switch for a power management circuit, or a switch for an RF front-end circuit, characterized in that: The semiconductor device according to claim 1 is included.

10. A method for manufacturing a semiconductor device including a pn junction diode, characterized in that The method comprises: providing a semiconductor substrate having a first conductivity type; forming a buried oxide layer in the substrate; forming a semiconductor region having a second conductivity type, wherein the semiconductor region having the second conductivity type extends below the buried oxide layer to form a pn junction with the semiconductor region having the first conductivity type, and wherein the pn junction is positioned below the buried oxide layer in a direction orthogonal to the main surface of the substrate and extends substantially orthogonally relative to the main surface of the substrate; and A field plate electrode is formed, the field plate electrode including a second semiconductor region positioned above the buried oxide layer for changing the electric field at the pn junction by applying an electric potential to the field plate electrode, the second semiconductor region being positioned above the buried oxide layer in a direction orthogonal to a major surface of the substrate.

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