Method of manufacturing an integrated circuit device

Abstract

A method of manufacturing an integrated circuit device, comprising: forming a molding layer on a main surface of a substrate. Forming a first hole having a first inner wall in the molding layer, the first inner wall having a first inclination angle. Forming a first conductive pattern in the first hole. Forming a block copolymer layer on the molding layer and the first conductive pattern. Forming a self-assembled layer having a first domain and a second domain by phase separation of the block copolymer layer. The first domain covers the first conductive pattern, and the second domain covers the molding layer. Forming a second hole having a second inner wall by removing the first domain, the second inner wall having a second inclination angle. Forming a second conductive pattern in the second hole.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2018 - 0117108, filed on October 1, 2018, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a method of manufacturing an integrated circuit device, and more particularly, to a method of manufacturing an integrated circuit device including a capacitor. Background art

[0004] As design rules are reduced in integrated circuit devices such as dynamic random access memories (DRAMs), there are limitations on storage nodes having a three - dimensional structure due to limited space in the region where capacitors are formed. Summary of the invention

[0005] The present inventive concept provides a method of manufacturing an integrated circuit device, which allows overcoming limitations of process technologies while providing a storage node having a large surface area, so that sufficient unit capacitance can be ensured in a limited area of a fine - sized integrated circuit device having an extremely small design rule.

[0006] According to an exemplary embodiment of the present inventive concept, there is provided a method of manufacturing an integrated circuit device. The method includes: forming a molding layer on a main surface of a substrate; forming a first hole in the molding layer by partially etching the molding layer, the first hole having a first inner wall having a first inclination angle with respect to a plane parallel to the main surface of the substrate; forming a first conductive pattern in the first hole; forming a block copolymer layer on the molding layer and the first conductive pattern; forming a self - assembled layer having a first domain and a second domain by performing phase separation of the block copolymer layer, the first domain covering the first conductive pattern and the second domain covering the molding layer; forming a second hole in the self - assembled layer by removing the first domain from the self - assembled layer, the second hole communicating with the first hole and having a second inner wall having a second inclination angle with respect to a plane parallel to the main surface of the substrate, the second inclination angle being different from the first inclination angle of the first inner wall of the first hole; and forming a second conductive pattern in the second hole, the second conductive pattern being in contact with the first conductive pattern.

[0007] According to another exemplary embodiment of the inventive concept, a method of manufacturing an integrated circuit device is provided. The method includes: forming a molding layer on a substrate; forming a plurality of first holes in the molding layer by partially etching the molding layer; forming a plurality of first conductive patterns in the plurality of first holes; forming at least one upper conductive pattern on the plurality of first conductive patterns, the at least one upper conductive pattern being connected to the first conductive patterns; and forming the at least one upper conductive pattern by performing at least one upper conductive pattern forming process. The upper conductive pattern forming process includes: forming a self-assembled layer having a plurality of first domains and second domains by using a block copolymer, the plurality of first domains covering the plurality of first conductive patterns, and the second domains surrounding the plurality of first domains and covering the molding layer; forming a plurality of second holes by removing the plurality of first domains, the plurality of second holes being respectively in communication with the plurality of first holes; and filling a conductive material inside each of the plurality of second holes.

[0008] According to still another exemplary embodiment of the inventive concept, a method of manufacturing an integrated circuit device is provided. The method includes: forming a molding layer on a substrate; forming a plurality of first holes in the molding layer by partially etching the molding layer; forming a plurality of first conductive patterns in the plurality of first holes; forming a self-assembled layer by using a block copolymer, the self-assembled layer including a plurality of first domains self-assembled on the plurality of first conductive patterns and a second domain self-assembled on the molding layer; forming a plurality of second holes by removing the plurality of first domains, the plurality of second holes exposing the plurality of first conductive patterns; converting the second domain into an inorganic oxide layer; forming a plurality of second conductive patterns in the plurality of second holes, the plurality of second conductive patterns being connected to the plurality of first conductive patterns; and removing the inorganic oxide layer and the molding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A and Figure 10A are perspective views showing processes of a method of manufacturing an integrated circuit device according to exemplary embodiments of the inventive concept;

[0011] Figure 1B 、 Figure 2B 、 Figure 3B 、 Figure 4B 、Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B are cross-sectional views taken along line B-B' of processes of a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept, respectively along Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A ;

[0012] Figure 11 and Figure 12 is a cross-sectional view taken along line B-B' of a process of a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0013] Figure 13A , Figure 14A and Figure 15A are perspective views of processes of a method of manufacturing an integrated circuit device according to an alternative exemplary embodiment of the inventive concept;

[0014] Figure 13B , Figure 14B and Figure 15B are cross-sectional views taken along line B-B' of processes of a method of manufacturing an integrated circuit device according to an alternative exemplary embodiment of the inventive concept, respectively along Figure 13A , Figure 14A and Figure 15A ;

[0015] Figure 16 is a cross-sectional view taken along line B-B' of a process of a method of manufacturing an integrated circuit device according to an alternative exemplary embodiment of the inventive concept;

[0016] Figure 17 is a schematic plan layout of main components of a cell array region of an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0017] Figures 18A to 18K is a cross-sectional view of a process of a method of manufacturing the integrated circuit device shown in Figure 17 according to an exemplary embodiment of the inventive concept;

[0018] Figures 19A to 19C is a cross-sectional view of a process of a method of manufacturing the integrated circuit device shown in Figure 17A cross-sectional view of a process of another method of an integrated circuit device shown therein; and

[0019] Figures 20A to 20E is a cross-sectional view of a process of a method of manufacturing an integrated circuit device according to other exemplary embodiments of the inventive concept. Detailed Description of the Invention

[0020] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, like components will be denoted by like reference numerals, and repetitive description of like components will be omitted.

[0021] Referring to Figures 1A to 1B , a molding layer 110 is formed on a main surface 102M of a substrate 102.

[0022] The substrate 102 may include a semiconductor substrate. In some exemplary embodiments, the substrate 102 may include a semiconductor such as silicon or germanium. In other exemplary embodiments, the substrate 102 may include a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The substrate 102 may include a conductive region. For example, the conductive region may be a well doped with impurities or a structure doped with impurities. In addition, the substrate 102 may have a device isolation structure such as a shallow trench isolation (STI) structure. In some embodiments, the substrate 102 may include a cell array region of a dynamic random access memory (DRAM).

[0023] In an exemplary embodiment, the molding layer 110 may include silicon oxide.

[0024] Referring to Figures 2A to 2B , a plurality of first holes 110H may be formed in the molding layer 110 by partially etching the molding layer 110.

[0025] To form the plurality of first holes 110H, a mask pattern may be formed on the molding layer 110, and then the molding layer 110 may be anisotropically etched using the mask pattern as an etch mask. In an exemplary embodiment, the mask pattern may include an oxide film, a nitride film, a polysilicon film, a photoresist film, or a combination thereof. After forming the plurality of first holes 110H, the remaining mask pattern on the molding layer 110 is removed to expose the upper surface of the molding layer 110.

[0026] In an exemplary embodiment, a plurality of first holes 110H may be formed in a hexagonal array in which the plurality of first holes 110H are regularly arranged at regular intervals. Each of the plurality of first holes 110H may have a first inner wall 110S that has a first inclination angle θ1 with respect to a plane parallel to the main surface 102M of the substrate 102. In some exemplary embodiments, the first inclination angle θ1 may be in the range from about 80° to about 85°, but is not limited thereto. Since the first inner wall 110S of each of the plurality of first holes 110H has the first inclination angle θ1, the width W1 of the bottom of each of the plurality of first holes 110H may be smaller than the width W2 of the top (e.g., the entrance) of each of the plurality of first holes 110H. For example, the width W1 of the bottom of each of the plurality of first holes 110H may be about 85% of the width W2 of the top (e.g., the entrance) of each of the plurality of first holes 110H, but is not limited thereto.

[0027] Referring to Figures 3A to 3B , a plurality of first conductive patterns 120 are respectively formed in the plurality of first holes 110H.

[0028] In some exemplary embodiments, in order to form the plurality of first conductive patterns 120, a conductive material may be deposited on a molding layer 110 having the plurality of first holes 110H as shown Figures 2A to 2B such that the conductive material has a thickness sufficient to fill the plurality of first holes 110H and form a first conductive layer. Subsequently, the first conductive layer may be partially removed to expose the upper surface of the molding layer 110. In an exemplary embodiment, after the first conductive layer is partially removed, only the portion of the first conductive layer disposed in the plurality of first holes 110H may remain. In an exemplary embodiment, a chemical vapor deposition (CVD), metal organic CVD (MOCVD), or atomic layer deposition (ALD) process may be used to form the first conductive layer.

[0029] In some exemplary embodiments, each of the plurality of first conductive patterns 120 may include a metal, a metal nitride, or a combination thereof. For example, each of the plurality of first conductive patterns 120 may include TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO 2 , SrRuO 3 , Ir, IrO 2 , Pt, PtO, SrRuO 3 (SRO), (Ba,Sr)RuO 3 (BSRO), CaRuO 3 (CRO), (La,Sr)CoO 3 (LSCo), or a combination thereof, but is not limited thereto.

[0030] After forming the plurality of first conductive patterns 120, the remaining native oxide film on the surface of the molding layer 110 can be removed by using oxygen plasma, and cleaning can be performed. This causes OH groups to be exposed at the surface of the molding layer 110. However, the exposed surfaces of the plurality of first conductive patterns 120 may not include OH groups.

[0031] Referring Figures 4A to 4B , among the surface of the molding layer 110 and the surfaces of the plurality of first conductive patterns 120 exposed on the substrate 102, a brush liner 132 can be selectively formed only on the surface of the molding layer 110.

[0032] The brush liner 132 can include an inorganic material or an organic material.

[0033] In some exemplary embodiments, the brush liner 132 can include: a monomer including silicon, an oligomer including silicon, or a polymer including silicon. For example, the brush liner 132 can include a polymer layer including polydimethylsiloxane (PDMS) as a main component. To form the brush liner 132 including PDMS, hydroxyl-terminated PDMS can be supplied as an anchor polymer to the surface of the molding layer 110. As a result, the brush liner 132 including PDMS can be selectively covalently bonded to the surface of the molding layer 110 through the mediation of oxygen atoms. In this exemplary embodiment, the brush liner 132 is not formed on the surfaces of the plurality of first conductive patterns 120.

[0034] In some exemplary embodiments, the brush liner 132 can include an organic monomer, an organic oligomer, or an organic polymer. For example, the brush liner 132 can include polystyrene (PS). To form the brush liner 132 including PS, hydroxyl-terminated PS can be supplied as an anchor polymer to the surface of the molding layer 110. As a result, the brush liner 132 including PS can be covalently bonded to the surface of the molding layer 110 through the mediation of oxygen atoms.

[0035] In an exemplary embodiment, the brush liner 132 may be formed by a spin-coating process. For example, a PDMS solution including PDMS-OH dissolved in an organic solvent (such as toluene, propylene glycol monomethyl ether acetate (PGMEA), or tetrahydrofuran (THF)) or a PS solution including PS-OH dissolved in the organic solvent as described above may be spin-coated on the molding layer 110 and the plurality of first conductive patterns 120. Then, the PDMS solution or the PS solution may be heat-treated at a temperature of about 180°C to about 250°C for about 5 minutes to about 24 hours in a vacuum or nitrogen environment. This results in the selective formation of the brush liner 132 only on the molding layer 110. Subsequently, the unreacted portion of the PDMS solution or the PS solution may be removed. To remove the unreacted portion of the PDMS solution or the PS solution, an organic solvent may be used. The organic solvent may include PGMEA, propylene glycol methyl ester (PGME), ethyl-3-ethoxypropionate (EEP), ethyl lactate (EL), methyl-2-hydroxybutyrate (HBM), gamma-butyrolactone (GBL), etc., but is not limited thereto.

[0036] In some exemplary embodiments, the brush liner 132 may be formed on the surface of the molding layer 110 to have a thickness of about 2 nm to about 15 nm, but is not limited thereto.

[0037] In some exemplary embodiments, the brush liner 132 described with reference to Figures 4A to 4B may be omitted.

[0038] With reference to Figures 5A to 5B , a block copolymer layer 134 is formed on the brush liner 132 and the plurality of first conductive patterns 120. However, in an exemplary embodiment in which the process of forming the brush liner 132 is omitted, the block copolymer layer 134 may be directly formed on the molding layer 110 and the plurality of first conductive patterns 120.

[0039] In some exemplary embodiments, the block copolymer layer 134 may include a copolymer of an organic polymer and an inorganic polymer. In other exemplary embodiments, the block copolymer layer 134 may include a copolymer of two different organic polymers.

[0040] In some exemplary embodiments, the block copolymer layer 134 may include a diblock copolymer in which a first polymer block having a first repeating unit and a second polymer block having a second repeating unit are covalently bonded. In some embodiments, the diblock copolymer may include a linear polymer or a branched polymer having a molecular weight of about 3000 g / mol to about 2000000 g / mol.

[0041] In other exemplary embodiments, the block copolymer layer 134 may include copolymers other than diblock copolymers. For example, triblock copolymers or multiblock copolymers may be included on the block copolymer layer. In some other embodiments, the block copolymer layer 134 may further include at least one homopolymer.

[0042] In an exemplary embodiment where the block copolymer layer 134 includes a copolymer of an organic polymer and an inorganic polymer in the diblock copolymer, the first polymer block may include PS, and the second polymer block may include PDMS, but is not limited thereto. For example, the diblock copolymer may include polybutadiene-b-polydimethylsiloxane, polyisobutylene-b-polydimethylsiloxane, polystyrene-b-ferrocenedimethylsilane, or polystyrene-b-ferroceneethylmethylsilane.

[0043] In an exemplary embodiment where the block copolymer layer 134 includes a copolymer of two different organic polymers in the diblock copolymer, the first copolymer block may include poly(methyl methacrylate) (PMMA), poly(ethylene oxide) (PEO), poly(lactic acid) (PLA), or polyisoprene (PI), and the second polymer block may include PS, but is not limited thereto.

[0044] In the block copolymer layer 134, the first polymer block may form a minor block, and the second polymer block may form a major block. In some exemplary embodiments, in the diblock copolymer, the volume ratio of the first polymer block to the second polymer block may be variously selected within the range of about 20:80 to about 40:60.

[0045] In some exemplary embodiments, to form the block copolymer layer 134, a block copolymer selected from the various copolymers described as examples above may be dissolved in an organic solvent. Subsequently, the obtained solvent may be coated on the brush pad 132 and the plurality of first conductive patterns 120 by dip coating, solution casting, or spin coating processes. The organic solvent may include PGMEA, PGME, EEP, EL, HBM, GBL, toluene, or THF, but is not limited thereto.

[0046] In forming with reference to Figures 4A to 4BIn an exemplary embodiment of the described brush gasket 132, a block copolymer layer 134 may be directly coated on the brush gasket 132 and the plurality of first conductive patterns 120. In some exemplary embodiments, when the block copolymer layer 134 includes a copolymer of an organic polymer and an inorganic polymer, the brush gasket 132 may have the same or a similar structure as the inorganic polymer. For example, the brush gasket 132 may include PDMS, and the block copolymer layer 134 may include PS-b-PDMS. In other exemplary embodiments, when the block copolymer layer 134 includes a copolymer of two different organic polymers, the brush gasket 132 may include an organic polymer. For example, the brush gasket 132 may include PS, and the block copolymer layer 134 may include PS-b-PMMA.

[0047] In an exemplary embodiment, the block copolymer layer 134 may have a thickness of about 50 nm to about 100 nm, but is not limited thereto.

[0048] Referring to Figures 6A to 6B , Figures 5A to 5B The block copolymer layer 134 of the device shown in may undergo phase separation to form a self-assembled layer 134A having a plurality of first domains 134D1 and second domains 134D2. The plurality of first domains 134D1 may cover the plurality of first conductive patterns 120. The second domains 134D2 may surround the plurality of first conductive layers 120 and cover the molding layer 110.

[0049] In an exemplary embodiment, the second domains 134D2 of the self-assembled layer 134A may include polymer segments having a higher affinity for the brush gasket 132. In some exemplary embodiments, when the brush gasket 132 includes PDMS and the block copolymer layer 134 includes PS-b-PDMS, each of the plurality of first domains 134D1 may include PS segments, and the second domains 134D2 may include PDMS segments. In other exemplary embodiments, when the brush gasket 132 includes PS and the block copolymer layer 134 includes PS-b-PMMA, each of the plurality of first domains 134D1 may include PMMA segments, and the second domains 134D2 may include PS segments.

[0050] For the phase separation of the block copolymer layer 134, the block copolymer layer 134 may be annealed at a temperature higher than the glass transition temperature (Tg) of the block copolymer in the block copolymer layer 134. For example, in an exemplary embodiment, to perform the phase separation of the block copolymer layer 134, the block copolymer layer 134 may be annealed at a temperature selected from the range of about 130 °C to about 190 °C for about 1 hour to about 24 hours.

[0051] A plurality of first domains 134D1 may form a hexagonal array in which the plurality of first domains 134D1 are regularly arranged at regular intervals, similar to the arrangement of the plurality of first holes 110H.

[0052] Referring Figures 7A to 7B , the plurality of first domains 134D1 of the self-assembled layer 134A can be removed from the device shown. In some exemplary embodiments, in order to selectively remove only the plurality of first domains 134D1 and leave the second domains 134D2 intact, the first domains can be selectively decomposed by applying a polymer decomposer to the self-assembled layer 134A and then stripping the decomposed plurality of first domains 134D1 by using a cleaning solution such as isopropyl alcohol (IPA). In some exemplary embodiments, radiation rays or plasma can be used as the polymer decomposer. For example, radiation rays can be provided in an oxygen environment, and the radiation rays can be deep ultraviolet (DUV), soft X-rays, or an electron beam (E-beam). The plasma can be an oxygen plasma. Figures 6A to 6B After removing the plurality of first domains 134D1, a plurality of second holes 134H are formed in the substrate 102. The plurality of second holes 134H penetrate the second domains 134D2. The plurality of second holes 124H can communicate with the plurality of first holes 110H respectively. The upper surfaces of the plurality of first conductive patterns 120 can be exposed by the plurality of second holes 134H.

[0053] Each of the plurality of second holes 134H may have a second inner wall 134S that has a second inclination angle θ2 with respect to a plane parallel to the main surface 102M of the substrate 102. The second inclination angle θ2 may be different from the first inclination angle θ1. In an exemplary embodiment, the second inclination angle θ2 may be greater than the first inclination angle θ1 and may be closer to the vertical direction (Z direction) compared to the first inclination angle θ1. In some exemplary embodiments, the second inner wall 134S of each second hole 134H may be approximately perpendicular to a plane parallel to the main surface 102M of the substrate 102.

[0054] In an exemplary embodiment, the width W3 of the top (e.g., the entrance) of each of the plurality of second holes 134H may be approximately equal to the width of the bottom of each of the plurality of second holes 134H. The width of the bottom of each of the plurality of second holes 134H may be approximately equal to or similar to the width W2 of the top (e.g., the entrance) of each of the plurality of first holes 110H described with reference to

[0055] Referring Figures 2A to 2B . The plurality of second holes 134H may form a hexagonal array in which the plurality of second holes 134H are regularly arranged at regular intervals, similar to the arrangement of the plurality of first holes 110H.

[0056] Referring Figures 8A to 8B , the can be oxidized by oxidizing the second domains 134D2Figures 7A to 7B The second domain 134D2 of the device is converted into the inorganic oxide layer 134B.

[0057] In some exemplary embodiments, the second domain 134D2 may be treated with oxygen plasma to oxidize the second domain 134D2 and convert the second domain 134D2 into an inorganic oxide layer 134B. In an exemplary embodiment where the second domain 134D2 includes a PDMS block, the PDMS block may be converted into a silicon oxide film as a result of the oxygen plasma treatment of the second domain 134D2. In an exemplary embodiment where the brush pad 132 includes PDMS, the brush pad 132 may also be converted into an inorganic oxide pad 132B. Each of the inorganic oxide pad 132B and the inorganic oxide layer 134B may include SiO x (where x is an integer from 1 to 4).

[0058] In other exemplary embodiments, when the brush pad 132 includes PS and the second domain 134D2 includes a PS block, the reference numeral 134D2 may be omitted. Figures 8A to 8B A process of oxidizing the second domain 134D2 is described.

[0059] Reference Figures 9A to 9B , a plurality of second conductive patterns 140 may be formed in the plurality of second holes 134H, respectively. The plurality of second conductive patterns 140 may contact upper surfaces of the plurality of first conductive patterns 120. The plurality of first conductive patterns 120 and the plurality of second conductive patterns 140 may constitute a plurality of lower electrodes LE1.

[0060] In order to form a plurality of second conductive patterns 140, Figures 8A to 8B A conductive material is deposited on the device including the plurality of second holes 134H to form a second conductive layer. The conductive material may have a thickness sufficient to fill the plurality of second holes 134H. The second conductive layer may then be partially removed so that the upper surface of the inorganic oxide layer 134B is exposed and only the portion of the second conductive layer disposed in the plurality of second holes 134H remains. In some exemplary embodiments, each of the plurality of second conductive patterns 140 may include a metal, a metal nitride, or a combination thereof. For example, each of the plurality of second conductive patterns 140 may include TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO 2 、SrRuO 3 、Ir、IrO 2 、Pt、PtO、SrRuO 3 (SRO), (Ba,Sr)RuO 3 (BSRO), CaRuO 3 (CRO), (La,Sr)CoO 3(LSCo) or combinations thereof, but not limited thereto. In some exemplary embodiments, the conductive material of each of the plurality of second conductive patterns 140 may be the same as the conductive material of each of the plurality of first conductive patterns 120.

[0061] In some embodiments, a CVD, MOCVD, or ALD process may be used to form the second conductive layer. For example, the second conductive layer may be formed by an ALD process performed at a relatively low temperature of about 100 °C to about 600 °C.

[0062] In an exemplary embodiment in which the process of oxidizing the second domain 134D2 described with reference to Figures 8A to 8B is omitted, the plurality of second conductive patterns 140 may be formed to respectively fill Figures 7A to 7B the plurality of second holes 134H of the device shown in Figures 7A to 7B In this exemplary embodiment, the second conductive layer may be formed by depositing a conductive material on the device shown in Figures 7A to 7B in which the plurality of second holes 134H are formed, such that the conductive material has a thickness sufficient to fill the plurality of second holes 134H. Subsequently, the second conductive layer may be partially removed such that the upper surface of the second domain 134D2 is exposed, so that only the portions of the second conductive layer disposed in the plurality of second holes 134H remain. In this embodiment, the second conductive layer may be formed in a relatively low-temperature environment, whereby deterioration of the second domain 134D2 due to a relatively high-temperature deposition environment can be prevented.

[0063] Referring to Figures 10A to 10B it is possible to remove the inorganic oxide layer 134B, the inorganic oxide liner 132B, and the molding layer 110 from the device shown in Figures 9A to 9B thereby exposing the outer sidewalls of each of the plurality of first conductive patterns 120 and the outer sidewalls of each of the plurality of second conductive patterns 140.

[0064] In some exemplary embodiments, each of the inorganic oxide layer 134B, the inorganic oxide liner 132B, and the molding layer 110 may include a silicon oxide-based material. In this embodiment, the inorganic oxide layer 134B, the inorganic oxide liner 132B, and the molding layer 110 may be removed simultaneously using the same etchant. In some exemplary embodiments, in order to remove the inorganic oxide layer 134B, the inorganic oxide liner 132B, and the molding layer 110, a stripping process using a LAL cleaning solution including ammonium fluoride (NH 4 F), hydrofluoric acid (HF), and water may be performed.

[0065] In other exemplary embodiments in which the process of oxidizing the second domain 134D2 is omitted, the plurality of second conductive patterns 140 may be formed to respectively fill Figures 7A to 7BMultiple second holes 134H in the device. In this embodiment, the outer sidewalls of each of the multiple second conductive patterns 140 may be covered by the second domain 134D2 and the brush pad 132. In this embodiment, the second domain 134D2, the brush pad 132, and the molding layer 110 may be removed in the order of the second domain 134D2, the brush pad 132, and the molding layer 110 to expose the outer sidewalls of each of the multiple first conductive patterns 120 and the outer sidewalls of each of the multiple second conductive patterns 140. For example, the outer sidewalls of each of the multiple second conductive patterns 140 and the upper surface of the molding layer 110 may be exposed by removing the second domain 134D2 and the brush pad 132, and then the outer sidewalls of each of the multiple first conductive patterns 120 may be exposed by removing the molding layer 110.

[0066] Each of the multiple lower electrodes LE1 may include a stacked structure in which the first conductive pattern 120 and the second conductive pattern 140 are stacked in the vertical direction (Z direction) on the substrate 102 in the order of the first conductive pattern 120 and the second conductive pattern 140. The first conductive pattern 120 closer to the substrate 102 than the second conductive pattern 140 may have a first outer sidewall 120W having a first tilt angle θ1 with respect to a plane parallel to the main surface 102M of the substrate 102. The second conductive pattern 140 is farther from the substrate 102 and may have a second outer sidewall 140W having a second tilt angle θ2 with respect to a plane parallel to the main surface 102M of the substrate 102. The second tilt angle θ2 may be greater than the first tilt angle θ1. Therefore, in the case where the multiple lower electrodes LE2 are formed on a relatively small cell region arranged on the substrate 102 with a relatively high density, even if the aspect ratio of each of the multiple lower electrodes LE1 is relatively high, a sufficient spacing distance can be ensured between the adjacent lower electrodes LE1 in the upper portions of the multiple lower electrodes LE1. Since the vertical (Z direction) length of each lower electrode LE1 can be increased from the vertical (Z direction) length of the first conductive pattern 120 by the vertical (Z direction) length of the second conductive pattern 140, the capacitance of the capacitor including the lower electrode LE1 can be increased.

[0067] Referring to Figure 11 , a dielectric thin film 150 may be formed on the multiple lower electrodes LE1. The dielectric thin film 150 may be formed to conformally cover the surfaces of the multiple lower electrodes LE1 and the surface of the substrate 102.

[0068] The dielectric thin film 150 may include nitrides, oxides, metal oxides, or combinations thereof. For example, the dielectric thin film 150 may have a composition including silicon nitride, silicon oxide, metal oxides (such as HfO 2 , ZrO 2 , Al2O 3 , La 2 O3 , Ta 2 O 3 , or TiO), a dielectric material with a perovskite structure (such as, SrTiO 3 (STO), (Ba, Sr)TiO 3 (BST), BaTiO 3 , PZT or PLZT) or a single - layer or multi - layer structure of their combination. In an exemplary embodiment, the dielectric film 150 may have a thickness of about to about , but is not limited thereto. In an exemplary embodiment, the dielectric film 150 may be formed by CVD, PVD or ALD processes.

[0069] Referring to Figure 12 , an upper electrode UE may be formed on the dielectric film 150. This results in the formation of an integrated circuit device 100 including a capacitor C1, where the capacitor C1 includes each lower electrode LE1, the dielectric film 150, and the upper electrode UE.

[0070] In an exemplary embodiment, the upper electrode UE may be formed to face the plurality of first conductive patterns 120 and the plurality of second conductive patterns 140, with the dielectric film 150 between the upper electrode and the plurality of first conductive patterns 120 and the plurality of second conductive patterns 140.

[0071] The upper electrode UE may include a doped semiconductor, a conductive metal nitride, a metal, a metal silicide, a conductive oxide, or a combination thereof. For example, although the upper electrode UE may include TiN, TiAlN, TaN, TaAlN, W, WN, Ru, RuO 2 , SrRuO 3 , Ir, IrO 2 , Pt, PtO, SrRuO 3 (SRO), (Ba, Sr)RuO3(BSRO), CaRuO 3 (CRO), (La, Sr)CoO 3 (LSCo) or a combination thereof, the constituent materials of the upper electrode are not limited to the examples set forth above. In an exemplary embodiment, the upper electrode UE may be formed using CVD, MOCVD, PVD or ALD processes.

[0072] Although a method of manufacturing an integrated circuit device 100 including a capacitor C1 (the capacitor C1 includes a columnar lower electrode LE1) has been described with reference to Figures 1A to 12 , without departing from the spirit and scope of the inventive concept, it is possible to, by referring to Figures 1A to 12Various modifications or changes are made to the given description to fabricate integrated circuit devices of various structures. For example, different from the columnar lower electrode LE1, a cylindrical lower electrode having an empty space therein can be formed. To form the cylindrical lower electrode, in the process described with reference to Figures 5A to 5B different from the columnar first conductive pattern 120, a cylindrical first conductive pattern can be formed. In addition, in the process described with reference to Figures 9A to 9B different from the columnar second conductive pattern 140, a cylindrical second conductive pattern can be formed, which has an end in contact with the upper surface of the cylindrical first conductive pattern.

[0073] According to an exemplary embodiment of the method for manufacturing the integrated circuit device 100 that has been described with reference to FIGS. 1 to Figure 12 to increase the capacitance of the capacitor C1, the vertical height of each lower electrode LE1 can be increased by a self-assembly process. In this embodiment, since the vertical height of each lower electrode LE1 is increased by using the self-assembly process, even if the aspect ratio of each of the plurality of lower electrodes LE1 is relatively high, a sufficient spacing distance can be ensured between adjacent lower electrodes LE1 in the upper portions of the plurality of lower electrodes LE1, whereby the insulation margin between adjacent lower electrodes LE1 can be ensured. Therefore, the capacitance of the capacitor C1 can be effectively increased in a relatively small cell area on the substrate 102. The electrical performance of the capacitor C1 and the reliability of the integrated circuit device 100 can be improved.

[0074] With reference to Figures 13A to 13B in other exemplary embodiments, a plurality of first domains 134D1 of the self-assembly layer 134A can be removed from the device shown in Figures 6A to 6B Subsequently, a plurality of protective spacers 236 are formed to cover the second inner walls 134S of the plurality of second holes 134H.

[0075] In some exemplary embodiments, the plurality of protective spacers 236 can include a material that is the same as the constituent material of the molding layer 110. For example, each of the plurality of protective spacers 236 can include a silicon oxide thin film.

[0076] In an exemplary embodiment of the method for forming the plurality of protective spacers 236, a protective insulating film can be formed to have a uniform thickness to conformally cover Figures 7A to 7B the exposed surface of the second domain 134D2 obtained by removing the first domain 134D1 in the device of. Subsequently, the protective insulating film can be etchback to form the plurality of protective spacers 236, which include the portions of the protective insulating film covering the sidewalls of the second domain 134D2 in the plurality of second holes 134H. After forming the plurality of protective spacers 236, the upper surfaces of the plurality of first conductive patterns 120 can be exposed through the plurality of second holes 134H defined by the plurality of protective spacers 236.

[0077] In some exemplary embodiments, each of the plurality of protective spacers 236 may be formed to have a thickness of about 2 nm to about 15 nm to cover the second inner wall 134S of each second hole 134H, but is not limited thereto.

[0078] The sidewall of each protective spacer 236 exposed by each of the plurality of second holes 134H may have a second inclination angle θ22 with respect to a plane parallel to the main surface 102M of the substrate 102. In an exemplary embodiment, the second inclination angle θ22 may be greater than the first inclination angle θ1 and may be closer to the vertical direction (Z direction) compared to the first inclination angle θ1. In some exemplary embodiments, the sidewall of each protective spacer 236 exposed by each of the plurality of second holes 134H may be approximately perpendicular to a plane parallel to the main surface 102M of the substrate 102.

[0079] After the plurality of protective spacers 236 are respectively formed in the plurality of second holes 134H, the top (entrance) of each of the plurality of second holes 134H may have a width W23 defined by each protective spacer 236. The width W23 of the top (e.g., entrance) of each of the plurality of second holes 134H defined by each protective spacer 236 may be smaller than the width W2 of the entrance of each of the plurality of first holes 110H described with reference to Figures 2A to 2B the width of the entrance of each of the plurality of first holes 110H described with reference to

[0080] With reference to Figures 14A to 14B , a plurality of second conductive patterns 240 may be formed in the plurality of second holes 134H respectively defined by the plurality of protective spacers 236.

[0081] The plurality of first conductive patterns 120 and the plurality of second conductive patterns 240 may constitute a plurality of lower electrodes LE2.

[0082] The plurality of second conductive patterns 240 may be in contact with the upper surface of the plurality of first conductive patterns 120. In the horizontal direction (e.g., the X direction or the Y direction), the width of each of the plurality of second conductive patterns 240 may be smaller than the maximum width of each of the plurality of first conductive patterns 120.

[0083] For more descriptions regarding the formation method and constituent materials of the plurality of second conductive patterns 240, reference may be made to the description of the plurality of second conductive patterns 140 already given with reference to Figures 9A to 9B the description of the plurality of second conductive patterns 140 already given with reference to

[0084] With reference to Figures 15A to 15B , the second domain 134D2, the brush gasket 132, the protective spacer 236, and the molding layer 110 may be removed from the Figures 14A to 14B device of

[0085] In some exemplary embodiments, it may be possible to expose the protection spacer 236 and the molding layer 110 by first removing the second domain 134D2 and the brush gasket 132 from the device of Figures 14A to 14B Subsequently, the protection spacer 236 and the molding layer 110 may be removed simultaneously.

[0086] After removing the second domain 134D2, the brush gasket 132, the protection spacer 236, and the molding layer 110, the outer sidewalls of each of the plurality of first conductive patterns 120 and the outer sidewalls of each of the plurality of second conductive patterns 240 may be exposed.

[0087] Each of the plurality of lower electrodes LE2 may include a stacked structure in which the first conductive pattern 120 and the second conductive pattern 240 are stacked in this order on the substrate 102 in the vertical direction (Z direction). The first conductive pattern 120 may be closer to the substrate 102 than the second conductive pattern 240. The first conductive pattern 120 may have a first outer sidewall 120W that has a first inclination angle θ1 with respect to a plane parallel to the main surface 102M of the substrate 102. The second conductive pattern 240 may have a second outer sidewall 240W that has a second inclination angle θ22 with respect to a plane parallel to the main surface 102M of the substrate 102, and the second inclination angle θ22 is greater than the first inclination angle θ1. Therefore, in the case where the plurality of lower electrodes LE2 are formed to be arranged at a relatively high density on a relatively small unit area on the substrate 102, even if the aspect ratio of each of the plurality of lower electrodes LE2 is relatively high, a sufficient spacing distance can be ensured between the adjacent lower electrodes LE2 in the upper portions of the plurality of lower electrodes LE2. Since the vertical (Z direction) length of each lower electrode LE2 can be increased by the vertical (Z direction) length of the second conductive pattern 240 from the vertical (Z direction) length of the first conductive pattern 120, the capacitance of the capacitor including the lower electrode LE2 can be increased.

[0088] Referring to Figure 16 , in a manner similar to that described with reference to Figure 11 and Figure 12 , the dielectric thin film 250 and the upper electrode UE2 may be formed on the plurality of lower electrodes LE2 in the order of the dielectric thin film 250 and the upper electrode UE2. As a result, an integrated circuit device 200 including a capacitor C2 can be obtained, and the capacitor C2 includes each lower electrode LE2, the dielectric thin film 250, and the upper electrode UE2.

[0089] For more description of the dielectric thin film 250 and the upper electrode UE2, reference may be made to the description of the dielectric thin film 150 and the upper electrode UE given with reference to Figure 11 and Figure 12 .

[0090] Although reference has been made toFigures 13A to 16 A method of manufacturing an integrated circuit device including a capacitor C1 (the capacitor C1 includes a columnar lower electrode LE2) is described, but various modifications and changes can be made to the description given without departing from the spirit and scope of the inventive concept. For example, instead of the columnar lower electrode LE2, a cylindrical lower electrode having an empty space therein can be formed. Figures 13A to 16

[0091] According to an exemplary embodiment of a method of manufacturing an integrated circuit device 200 (which has been described with reference to FIGS. 13 to Figure 16 ), in order to increase the capacitance of the capacitor C2, the vertical height of each lower electrode LE2 can be increased by a self-assembly process. In this embodiment, since the vertical height of each lower electrode LE2 is increased by using a self-assembly process, even if the aspect ratio of each of the plurality of lower electrodes LE2 is relatively high, a sufficient spacing distance can be ensured between the adjacent lower electrodes LE2 in the upper portions of the plurality of lower electrodes LE2, whereby an insulation margin between the adjacent lower electrodes LE2 can be ensured. Therefore, the capacitance of the capacitor C2 can be effectively increased in a relatively small cell area on the substrate 102, whereby the electrical performance of the capacitor C2 and the reliability of the integrated circuit device 200 can be improved.

[0092] Figure 17 is a schematic plan layout showing main elements of a cell array region of an integrated circuit device 400 that can be implemented by a method of manufacturing an integrated circuit device according to an exemplary embodiment.

[0093] Referring to Figure 17 , the integrated circuit device 400 may include a plurality of active regions ACT. The plurality of active regions ACT may be arranged in an inclined direction with respect to the X direction and the Y direction.

[0094] A plurality of word lines WL may extend parallel to each other in the X direction across the plurality of active regions ACT. A plurality of bit lines BL may extend parallel to each other in the Y direction on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of active regions ACT via direct contacts DC.

[0095] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged in rows in each of the X direction and the Y direction.

[0096] A plurality of electrodes LE4 may be formed on the plurality of buried contacts BC. The plurality of lower electrodes LE4 may be connected to the plurality of active regions ACT via the plurality of buried contacts BC.

[0097] Figures 18A to 18K is according to an exemplary embodiment showing the manufacturing of Figure 17 ​Cross-sectional views of the respective sequential processes of the method of the integrated circuit device 400 shown in. In Figures 18A to 18K , the same reference numerals as in Figures 1A to 16 respectively indicate the same components, and a detailed description thereof will be omitted.

[0098] Referring to Figure 18A , an etch stop layer 404, a molding layer 410, a first support layer 412, and a sacrificial layer 413 can be formed on the substrate 102 in the order of the etch stop layer 404, the molding layer 410, the first support layer 412, and the sacrificial layer 413. Subsequently, a mask pattern M4 can be formed on the sacrificial layer 413, and the mask pattern M4 has a plurality of holes M4H.

[0099] A plurality of active regions ACT and a plurality of conductive regions can be formed in the substrate 102.

[0100] In some exemplary embodiments, the etch stop layer 404 can include silicon nitride, silicon oxynitride, or a combination thereof. The molding layer 410 can include silicon oxide. The first support layer 412 can include silicon nitride, silicon carbonitride, tantalum oxide, titanium oxide, or a combination thereof. The sacrificial layer 413 can include borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), spin-on dielectric (SOD), or an oxide formed by a high-density plasma (HDP) CVD process. However, the materials set forth above are merely examples, and the inventive concept is not limited thereto. In addition, although a configuration in which one first support layer 412 is disposed on the molding layer 410 is shown in the present exemplary embodiment, the molding layer 410 can include a plurality of local molding layers, and at least one intermediate support layer disposed between the plurality of local molding layers can also be provided.

[0101] The upper surface of the sacrificial layer 413 can be exposed through the plurality of holes M4H formed in the mask pattern M4. The plurality of holes M4H can form a hexagonal array in which the plurality of holes M4H are regularly arranged at regular intervals. The mask pattern M4 can include at least one layer used as an etch mask in patterning the etch stop layer 404, the molding layer 410, the first support layer 412, and the sacrificial layer 413. For example, the mask pattern M4 can include a polysilicon thin film, a silicon oxide thin film, a SiCN thin film, a carbon-containing film including a spin-on hard mask (SOH) material, or a combination thereof. In an exemplary embodiment, the carbon-containing film including the SOH material can include an organic compound having a relatively high carbon content of about 85% by weight (85 wt%) to about 99% by weight based on its total weight. The organic compound can include a hydrocarbon or a derivative thereof containing an aromatic ring.

[0102] Referring to Figure 18B, the sacrificial layer 413, the first support layer 412, and the molding layer 410 can be etched in the device of Figure 18A in this order by using the mask pattern M4 as an etching mask and using the etch stop layer 404 as an etching end point. The etch stop layer 404 can be continuously etched by over-etching, thereby forming a plurality of lower electrode holes LH that expose a plurality of conductive regions in the substrate 102. Subsequently, the upper surface of the sacrificial layer 413 can be exposed by removing the mask pattern M4.

[0103] Referring to Figure 18C , a lower electrode is formed to form a conductive thin film to cover the upper surface of the sacrificial layer 413 and simultaneously fill the interior of each of the plurality of lower electrode holes LH. Subsequently, the upper portion of the lower electrode forming conductive thin film and the sacrificial layer 413 can be removed by a back-etching process or a chemical mechanical polishing (CMP) process, such that the upper surface of the first support layer 412 is exposed to form a plurality of first conductive patterns 420 that fill the interior of the plurality of lower electrode holes LH. A more detailed description of the plurality of first conductive patterns 420 has been provided with reference to Figures 3A to 3B .

[0104] After forming the plurality of first conductive patterns 420, the remaining native oxide film on the surface of the first support layer 412 can be removed by using oxygen plasma and a cleaning process. As a result, OH groups can be exposed on the surface of the first support layer 412. However, the exposed surfaces of the plurality of first conductive patterns 420 may not include OH groups.

[0105] Referring to Figure 18D , for Figure 18C the device shown in Figures 4A to 9B a process same as that described with reference to

[0106] is performed, thereby forming an inorganic oxide liner 132B and an inorganic oxide layer 134B that cover the first support layer 412 in the order of the inorganic oxide liner 132B and the inorganic oxide layer 134B. A plurality of second conductive patterns 140 that cover the plurality of first conductive patterns 420 are also formed.

[0107] The plurality of first conductive patterns 420 and the plurality of second conductive patterns 140 can constitute a plurality of lower electrodes LE4. Figure 18E Referring to

[0108] , the inorganic oxide layer 134B can be partially removed (for example, the upper portion of the inorganic oxide layer 134B is removed), thereby forming a support space S41 that exposes the upper outer sidewalls of each of the plurality of second conductive patterns 140.

[0109] Referring to Figure 18F , a second support layer 414 can be formed to fill the Figure 18E support space S41 shown in

[0110] The second support layer 414 can include silicon nitride, silicon carbonitride, tantalum oxide, titanium oxide, or a combination thereof. In some exemplary embodiments, the first support layer 412 and the second support layer 414 can include the same material.

[0111] Referring to Figure 18G , the second support layer 414 can then be partially removed from the Figure 18F device shown in. A second support pattern 414P having a plurality of openings 414H can be formed by partially removing the second support layer 414. A plurality of portions of the upper surface of the inorganic oxide layer 134B can be exposed through the plurality of openings 414H formed in the second support pattern 414P.

[0112] Referring to Figure 18H , the inorganic oxide layer 134B and the inorganic oxide liner 132B can be removed through the plurality of openings 414H formed in the second support pattern 414P, thereby exposing the outer sidewalls of each of the plurality of second conductive patterns 140 and the upper surface of the first support layer 412.

[0113] Referring to Figure 18I , the first support layer 412 can be partially removed from the Figure 18H device of, thereby forming a first support pattern 412P having a plurality of openings 412H. A plurality of portions of the upper surface of the molding layer 410 can be exposed through the plurality of openings 412H formed in the first support pattern 412P.

[0114] Referring to Figure 18J , the molding layer 410 can be removed through the openings 412H formed in the first support pattern 412P, thereby exposing the outer sidewalls of each of the plurality of first conductive patterns 420 and the upper surface of the etch stop layer 404.

[0115] Although a configuration in which one first support layer 412 is disposed on the molding layer 410 is shown in this example, when the molding layer 410 includes a plurality of local molding layers and at least one intermediate support layer disposed between the plurality of local molding layers is also provided, the processes of removing each of the local molding layers constituting the molding layer 410 and patterning the at least one intermediate support layer can be sequentially performed in a top-to-bottom order such that the upper surface of the etch stop layer 404 is exposed.

[0116] Referring to Figure 18K , in a manner similar to that with reference to Figure 11 and Figure 12In a manner similar to the described manner of forming the dielectric film 150 and the upper electrode UE, a dielectric film 450 and an upper electrode UE4 are formed in this order on a plurality of lower electrodes LE4 including a plurality of first conductive patterns 420 and a plurality of second conductive patterns 140. As a result, an integrated circuit device 400 including a capacitor C4 can be obtained, and the capacitor C4 includes each lower electrode LE4, the dielectric film 450, and the upper electrode UE4.

[0117] The dielectric film 450 may be formed to have a uniform thickness to conformally cover the outer sidewalls of each of the plurality of first conductive patterns 420, the outer sidewalls of each of the plurality of second conductive patterns 140, the upper surface of the etch stop layer 404, the surface of the first support pattern 412P, and the surface of the second support pattern 414P. For a more detailed description of the dielectric film 450 and the upper electrode UE4, reference may be made to the description of the dielectric film 150 and the upper electrode UE already provided. Figure 11 and Figure 12 the description of the dielectric film 150 and the upper electrode UE.

[0118] Figures 19A to 19C is a cross-sectional view showing the respective processes in sequence of another method of manufacturing the integrated circuit device 400 shown in accordance with an exemplary embodiment. In Figure 17 the same reference numerals as those in FIGS. 1 to Figures 19A to 19C indicate the same components, and a detailed description thereof will be omitted. Figure 18K the same reference numerals as those in FIGS. 1 to

[0119] Referring to Figure 19A and in the same manner as described with reference to Figures 18A to 18C an etch stop layer 404, a molding layer 410, and a first support layer 412 may be formed on the substrate 102 in this order. A plurality of first conductive patterns 420 are formed on the substrate 102 through these components. Subsequently, a brush pad 132, a second domain 134D2, and a plurality of second holes 134H penetrating the second domain 134D2 may be formed by performing the same processes as described with reference to Figures 4A to 7B and the brush pad 132 and the second domain 134D2 cover the first support layer 412 in this order. Subsequently, a plurality of second conductive patterns 140 may be formed in the plurality of second holes 134H in a manner similar to the described manner with reference to Figures 9A to 9B In this embodiment, the process of oxidizing the second domain 134D2 described with reference to Figures 8A to 8B may be omitted.

[0120] Referring to Figure 19B and in the same manner as described with reference to Figure 18EIn a similar manner as described, by partially removing the second domain 134D2 (e.g., removing the upper portion of the second domain 134D2), a support space S51 is formed on the Figure 19A device shown, which exposes the upper outer sidewalls of each of the plurality of second conductive patterns 140. Subsequently, a second support layer 514 filling the support space S51 can be formed in a manner similar to the manner described with reference to Figure 18F A detailed description of the second support layer has been provided with reference to Figure 18F Referring to

[0121] Referring to Figure 19C and in a manner similar to the manner described with reference to Figure 18G a second support pattern 514P having a plurality of openings 514H can be formed by partially removing the second support layer 514. A plurality of portions of the upper surface of the second domain 134D2 can be exposed through the plurality of openings 514H formed in the second support pattern 514P.

[0122] Subsequently, the second domain 134D2 and the brush pad 132 can be removed through the plurality of openings 514H formed in the second support pattern 514P, thereby exposing the outer sidewalls of each of the plurality of second conductive patterns 140 and the upper surface of the first support layer 412.

[0123] Subsequently, the same process as described with reference to Figures 18I to 18K can be performed to form a first support pattern 412P having a plurality of openings 412H, remove the molding layer 410 through the plurality of openings 412H formed in the first support pattern 412P, and form a dielectric thin film 450 and an upper electrode UE4 in this order on a plurality of lower electrodes LE4 including a plurality of first conductive patterns 420 and a plurality of second conductive patterns 140. Thereby, an integrated circuit device 400 including a capacitor C4 can be manufactured, and the capacitor C4 includes each lower electrode LE4, the dielectric thin film 450, and the upper electrode UE4.

[0124] Figures 20A to 20E is a cross-sectional view showing sequential processes of a method for manufacturing an integrated circuit device according to other exemplary embodiments. In Figures 20A to 20E the same reference numerals respectively denote the same components as in Figures 1A to 19C and a detailed description thereof will be omitted.

[0125] Referring to Figure 20A and in the same manner as described with reference to Figures 18A to 18C an etch stop layer 404, a molding layer 410, and a first support layer 412 are formed on the substrate 102 in this order. A plurality of first conductive patterns 420 are formed on the substrate 102 through these components.

[0126] Subsequently, each process using the self-assembly process described with reference to Figures 4A to 7B is performed at least once, thereby forming upper conductive patterns 640A, 640B, and 640C. In the present exemplary embodiment, the upper conductive patterns 640A, 640B, and 640C have a three-layer structure including a plurality of second conductive patterns 640A, a plurality of third conductive patterns 640B, and a plurality of fourth conductive patterns 640C.

[0127] By performing the self-assembly process described with reference to Figures 4A to 7B it is possible to form a brush pad 132, a second domain 134D2, and a plurality of second holes 134H on a device in which a plurality of first conductive patterns 420 are formed as shown in Figure 18C . Among them, the brush pad 132 and the second domain 134D2 cover the first support layer 412 in the order of the brush pad 132 and the second domain 134D2, and the plurality of holes 134H penetrate the second domain 134D2. Subsequently, a plurality of second conductive patterns 640A are formed in the plurality of second holes 134H in a manner similar to the manner of forming the plurality of second conductive patterns 140 described with reference to Figures 9A to 9B . A detailed description of the plurality of second conductive patterns has been provided with reference to Figures 9A to 9B .

[0128] Subsequently, a second domain 134D2 in which a plurality of second holes 134H are formed is formed on a device in which a plurality of second conductive patterns 640A and a second domain 134D2 surrounding the plurality of second conductive patterns 640A are formed. Among them, the plurality of second holes 134H are formed by using the method of the self-assembly process described with reference to Figures 5A to 7B . Subsequently, a plurality of third conductive patterns 640B are formed in the plurality of second holes 134H in a manner similar to the manner of forming the plurality of second conductive patterns 140 described with reference to Figures 9A to 9B . A detailed description of the plurality of third conductive patterns has been provided with reference to Figures 9A to 9B .

[0129] A second domain 134D2 in which a plurality of second holes 134H are formed is further formed on a device in which a plurality of third conductive patterns 640B and a second domain 134D2 surrounding the plurality of third conductive patterns 640B are formed. Among them, the plurality of second holes 134H are formed by using the method of the self-assembly process described with reference to Figures 5A to 7B . Subsequently, a plurality of fourth conductive patterns 640C are formed in the plurality of second holes 134H in a manner similar to the manner of forming the plurality of second conductive patterns 140 described with reference to Figures 9A to 9B . A detailed description of the plurality of fourth conductive patterns has been provided with reference to Figures 9A to 9B .

[0130] A plurality of first conductive patterns 420 and upper conductive patterns 640A, 640B, and 640C may constitute a plurality of lower electrodes LE6. In the present exemplary embodiment, although the plurality of second conductive patterns 640A, the plurality of third conductive patterns 640B, and the plurality of fourth conductive patterns 640C are sequentially formed on the plurality of first conductive patterns 420 in the vertical direction in the order of the plurality of second conductive patterns 640A, the plurality of third conductive patterns 640B, and the plurality of fourth conductive patterns 640C by performing the self-assembly process three times to form the plurality of lower electrodes LE6, the inventive concept is not limited thereto. According to the inventive concept, by performing at least once the self-assembly process described with reference to Figures 5A to 7B an upper conductive pattern including at least one conductive pattern is formed on each of the plurality of first conductive patterns 420. Thereby, the vertical height of the lower electrode can be increased by the vertical height of at least one conductive pattern from the vertical height of each of the plurality of first conductive patterns 420. In the process of forming the plurality of lower electrodes with an increased vertical height, the number of times of applying the self-assembly process as described above can be variously selected according to needs.

[0131] In some exemplary embodiments, different from the description given with reference to Figure 20A when forming a stacked structure including at least one second domain 134D2 having a plurality of second holes 134H on the first support layer 412, various processes of forming the plurality of first conductive patterns 420, forming the plurality of second conductive patterns 640A, forming the plurality of third conductive patterns 640B, and forming the plurality of fourth conductive patterns 640C may be omitted. In this embodiment, different from forming the plurality of first conductive patterns 420, the plurality of second conductive patterns 640A, the plurality of third conductive patterns 640B, and the plurality of fourth conductive patterns 640C, a sacrificial thin film may be formed to fill the electrode space in which the above-described components will be formed, or subsequent processes may be performed when the electrode space is empty. The sacrificial thin film may be removed from the device in which the stacked structure including at least one second domain 134D2 (having a plurality of second holes 134H) is formed. Thereby, the inside of the electrode space (e.g., the inside of the plurality of lower electrode holes LH) and the inside of the plurality of second holes 134H included in the at least one vertically stacked second domain 134D2 may be empty. The plurality of second holes 134H communicate with the plurality of lower electrode holes LH. The inside of the plurality of lower electrode holes LH and the inside of the plurality of second holes 134H may then be filled with a conductive material to form an integral lower electrode. In this embodiment, the process of forming the conductive layer for forming the integral lower electrode may be performed only once, which is different from the case where the process of forming the conductive layer is performed several times to form the lower electrode LE6 including the plurality of first conductive patterns 420, the plurality of second conductive patterns 640A, the plurality of third conductive patterns 640B, and the plurality of fourth conductive patterns 640C.

[0132] With reference toFigure 20B , in a manner similar to that described with reference to Figure 19B , a support space S51 exposing the upper outer sidewalls of each of the plurality of fourth conductive patterns 640C is formed by partially removing the second domain 134D2 surrounding the plurality of fourth conductive patterns 640C, and a second support layer 514 filling the support space S51 is formed.

[0133] Reference Figure 20C , in the same manner as that described with reference to Figure 19C , a second support pattern 514P having a plurality of openings 514H can be formed by partially removing the second support layer 514. A plurality of portions of the upper surface of the second domain 134D2 surrounding the plurality of fourth conductive patterns 640C can be exposed through the plurality of openings 514H formed in the second support pattern 514P.

[0134] Reference Figure 20D , the second domain 134D2 and the brush pad 132 can be removed through the plurality of openings 514H formed in the second support pattern 514, thereby exposing the outer sidewalls of each of the plurality of second conductive patterns 640A, the outer sidewalls of each of the plurality of third conductive patterns 640B, the outer sidewalls of each of the plurality of fourth conductive patterns 640C, and the upper surface of the first support layer 412.

[0135] Reference Figure 20E , in the same manner as that described with reference to Figure 18I and Figure 18J , a first support pattern 412P having a plurality of openings 412H can be formed by partially removing the first support layer 412, and the outer sidewalls of each of the plurality of first conductive patterns 420 and the upper surface of the etch stop layer 404 are exposed by removing the molding layer 410.

[0136] Subsequently, a dielectric film 650 and an upper electrode UE6 can be formed in this order on a plurality of lower electrodes LE6 including the plurality of first conductive patterns 410, the plurality of second conductive patterns 640A, the plurality of third conductive patterns 640B, and the plurality of fourth conductive patterns 640C. Thereby, an integrated circuit device 600 including a capacitor C6 can be manufactured, and the capacitor C6 includes each lower electrode LE6, the dielectric film 650, and the upper electrode UE6.

[0137] The dielectric film 650 may be formed to have a uniform thickness to conformally cover the outer sidewalls of each of the plurality of first conductive patterns 420, the outer sidewalls of each of the plurality of second conductive patterns 640A, the outer sidewalls of each of the plurality of third conductive patterns 640B, the outer sidewalls of each of the plurality of fourth conductive patterns 640C, the upper surface of the etch stop layer 404, the surface of the first support pattern 412P, and the surface of the second support pattern 514P. For a more detailed description of the dielectric film 650 and the upper electrode UE6, reference may be made to the description of the dielectric film 150 and the upper electrode UE provided with reference to Figure 11 and Figure 12 the description of the dielectric film 150 and the upper electrode UE.

[0138] Although a method of manufacturing the integrated circuit device 400 including the capacitor C4 including the columnar lower electrode LE4 and the integrated circuit device 600 including the capacitor C6 including the columnar lower electrode LE6 has been described with reference to Figures 17 to 20E the integrated circuit devices having various structures may be manufactured by making various changes and modifications to the description given with reference to Figures 17 to 20E without departing from the spirit and scope of the inventive concept.

[0139] The method of manufacturing an integrated circuit device according to an exemplary embodiment increases the capacitance of the capacitor and may increase the vertical height of the lower electrode through a self-assembly process. Since the self-assembly process is used to increase the height of the lower electrode, even if the aspect ratio of each of the plurality of lower electrodes is relatively high, a sufficient spacing distance between the adjacent lower electrodes can be ensured in the respective upper portions of the plurality of lower electrodes, whereby the insulation margin between the adjacent lower electrodes can be ensured. Therefore, the capacitance of the capacitor can be effectively increased in a relatively small cell area on the substrate, whereby the electrical performance of the capacitor and the reliability of the integrated circuit device can be improved.

[0140] Although the inventive concept has been shown and described in detail with reference to exemplary embodiments of the inventive concept, it will be understood that various changes may be made in form and detail without departing from the spirit and scope of the appended claims.

Claims

1. A method of manufacturing an integrated circuit device, the method comprising: forming a molding layer on a main surface of a substrate; forming a first hole in the molding layer by partially etching the molding layer, the first hole having a first inner wall that has a first inclination angle with respect to a plane parallel to the main surface of the substrate; forming a first conductive pattern in the first hole; forming a block copolymer layer on the molding layer and the first conductive pattern; forming a self-assembled layer having a first domain and a second domain by performing phase separation of the block copolymer layer, wherein the first domain covers the first conductive pattern and the second domain covers the molding layer; forming a second hole in the self-assembled layer by removing the first domain from the self-assembled layer, wherein the second hole communicates with the first hole and has a second inner wall that has a second inclination angle with respect to a plane parallel to the main surface of the substrate, and the second inclination angle is different from the first inclination angle of the first inner wall of the first hole; and forming a second conductive pattern in the second hole, the second conductive pattern being in contact with the first conductive pattern.

2. The method according to claim 1, wherein the block copolymer layer comprises a copolymer of an organic polymer and an inorganic polymer.

3. The method according to claim 2, further comprising: converting the second domain into an inorganic oxide layer after forming the second hole and before forming the second conductive pattern; and exposing an outer sidewall of the first conductive pattern and an outer sidewall of the second conductive pattern by removing the molding layer and the second domain simultaneously.

4. The method according to claim 1, wherein the block copolymer layer comprises a copolymer of two different organic polymers.

5. The method according to claim 1, further comprising: forming a protective spacer covering the second inner wall of the second hole before forming the second conductive pattern, wherein the second conductive pattern has a width smaller than a maximum width of the first conductive pattern in a horizontal direction.

6. The method according to claim 1, wherein the second inclination angle of the second inner wall is greater than the first inclination angle of the first inner wall of the first hole.

7. The method according to claim 1, further comprising: selectively forming a brush liner on a surface of the molding layer before forming the block copolymer layer, wherein the brush liner is not formed on the first conductive pattern.

8. The method according to claim 7, wherein: the block copolymer layer comprises a copolymer of an organic polymer and an inorganic polymer, and the brush liner comprises silicon atoms.

9. The method according to claim 7, wherein: the block copolymer layer comprises a copolymer of a first organic polymer and a second organic polymer, the first organic polymer and the second organic polymer having different structures from each other; and the brush liner comprises an organic polymer.

10. A method of manufacturing an integrated circuit device, the method comprising: forming a molding layer on a substrate; forming a plurality of first holes in the molding layer by partially etching the molding layer; Form a plurality of first conductive patterns in the plurality of first holes; And Form at least one upper conductive pattern on the plurality of first conductive patterns, the at least one upper conductive pattern being connected to the first conductive patterns, Wherein, the at least one upper conductive pattern is formed by performing at least one upper conductive pattern forming process, and the upper conductive pattern forming process includes: Form a self-assembled layer having a plurality of first domains and second domains by using a block copolymer, the plurality of first domains covering the plurality of first conductive patterns, and the second domains surrounding the plurality of first domains and covering the molding layer; Form a plurality of second holes by removing the plurality of first domains, the plurality of second holes being respectively in communication with the plurality of first holes; and Fill a conductive material inside each of the plurality of second holes.

11. The method according to claim 10, Wherein: The block copolymer includes a copolymer of an organic polymer and an inorganic polymer, wherein each of the plurality of first domains includes the organic polymer, and the second domain includes the inorganic polymer.

12. The method according to claim 11, Wherein, The upper conductive pattern forming process further includes: after forming the plurality of second holes, converting the second domain into an inorganic oxide layer.

13. The method according to claim 12, Wherein, The upper conductive pattern forming process further includes: after filling the conductive material inside each of the plurality of second holes, removing the molding layer and the inorganic oxide layer simultaneously.

14. The method according to claim 10, Wherein, The block copolymer includes a copolymer of a first organic polymer and a second organic polymer, and the first organic polymer and the second organic polymer have different structures from each other.

15. The method according to claim 10, further Includes: After forming the at least one upper conductive pattern, form a support space by removing a part of the second domain; Form a support pattern in the support space, the support pattern having a plurality of openings; Remove the remaining part of the second domain through the plurality of openings; And Remove the molding layer through the plurality of openings.

16. A method of manufacturing an integrated circuit device, the method Includes: Form a molding layer on a substrate; Form a plurality of first holes in the molding layer by partially etching the molding layer; Form a plurality of first conductive patterns in the plurality of first holes; Form a self-assembled layer by using a block copolymer, the self-assembled layer including a plurality of first domains self-assembled on the plurality of first conductive patterns and a second domain self-assembled on the molding layer; Form a plurality of second holes by removing the plurality of first domains, the plurality of second holes exposing the plurality of first conductive patterns; Convert the second domain into an inorganic oxide layer; Form a plurality of second conductive patterns in the plurality of second holes, the plurality of second conductive patterns being connected to the plurality of first conductive patterns; And Remove the inorganic oxide layer and the molding layer.

17. The method according to claim 16, Wherein, The block copolymer includes a copolymer of an organic polymer and an inorganic polymer, wherein each of the plurality of first domains includes the organic polymer and the second domain includes the inorganic polymer.

18. The method according to claim 16, wherein, the second domain is converted into the inorganic oxide layer by treating the second domain with oxygen plasma.

19. The method according to claim 16, further comprising: after forming the plurality of second conductive patterns, forming a support space by partially removing the inorganic oxide layer, the support space exposing the outer sidewalls of each of the plurality of second conductive patterns; and forming a support pattern in the support space, the support pattern having a plurality of openings, wherein the inorganic oxide layer and the molding layer are removed through the plurality of openings.

20. The method according to claim 16, further comprising: forming a dielectric thin film covering the surface of each of the plurality of second conductive patterns; and forming an upper electrode covering the plurality of second conductive patterns, the dielectric thin film being interposed between the upper electrode and the plurality of second conductive patterns.

Images