Image sensor including amorphous region and electron inhibition region and method of manufacturing the same

Abstract

An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate containing a plurality of pixel regions. The substrate has a first surface and a second surface opposite to the first surface. The image sensor includes a deep pixel isolation region extending from the second surface of the substrate toward the first surface of the substrate and separating the plurality of pixel regions from each other. The image sensor includes an amorphous region adjacent to the sidewalls of the deep pixel isolation region. Furthermore, the image sensor includes an electron suppression region between the amorphous region and the sidewalls of the deep pixel isolation region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0120034, filed on October 8, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an image sensor. Background Technology

[0004] Image sensors convert optical images into electrical signals. Image sensors can be classified as either charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS) type. The term "CIS" is an abbreviation for CMOS type image sensor. A CIS can contain multiple pixels arranged in a two-dimensional array. Each pixel includes a photodiode (PD). The photodiode is used to convert incident light into an electrical signal. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide an image sensor capable of suppressing dark current.

[0006] Some exemplary embodiments of the present invention provide a method for manufacturing an image sensor capable of improving photosensitivity.

[0007] An image sensor according to some exemplary embodiments of the present invention may include: a substrate comprising a plurality of pixel regions. The substrate may include a first surface and a second surface opposite to the first surface. The image sensor may include a transmission gate on the first surface of the substrate. The image sensor includes a deep pixel isolation region extending from the second surface of the substrate toward the first surface of the substrate and separating the plurality of pixel regions from each other. The image sensor may include an amorphous region adjacent to the sidewalls of the deep pixel isolation region. Furthermore, the image sensor may include an electron suppression region located between the amorphous region and the sidewalls of the deep pixel isolation region. The electron suppression region may include boron ions.

[0008] An image sensor according to some exemplary embodiments of the present invention may include: a substrate comprising a plurality of pixel regions. The substrate may have a first surface and a second surface opposite to the first surface. The image sensor may include a shallow device isolation region in the substrate adjacent to the first surface. The image sensor may include a deep pixel isolation region extending from the second surface to the first surface and separating the plurality of pixel regions from each other. The deep pixel isolation region may contact the shallow device isolation region. The image sensor may include an amorphous region adjacent to the sidewalls of the deep pixel isolation region and the sidewalls of the shallow device isolation region, respectively. Furthermore, the image sensor may include an electron suppression region located between the amorphous region and the sidewalls of the deep pixel isolation region and the shallow device isolation region.

[0009] Image sensors according to some exemplary embodiments of the present invention may include: a substrate comprising a plurality of pixel regions. The substrate may have a first surface and a second surface opposite to the first surface. The image sensor may include a device isolation region in the substrate adjacent to the first surface. The image sensor may include a deep pixel isolation region extending from the second surface to the first surface and separating the plurality of pixel regions from each other. The image sensor may include an amorphous region adjacent to the sidewalls of the deep pixel isolation region. Furthermore, the image sensor may include an electron suppression region located between the amorphous region and the sidewalls of the deep pixel isolation region. A portion of the device isolation region may include carbon ions, germanium ions, or both carbon ions and germanium ions.

[0010] A method for manufacturing an image sensor according to some exemplary embodiments of the present invention may include: etching a substrate to form a plurality of deep pixel trenches separating a plurality of pixel regions from each other. The method may include: performing a first plasma doping process to dope the substrate with carbon ions, germanium ions, or both carbon ions and germanium ions, thereby forming a first amorphous region in the substrate adjacent to the sidewalls and bottom surface of the plurality of deep pixel trenches. The method may include: performing a second plasma doping process to dope the substrate with boron ions, thereby forming a first charge suppression region in the substrate adjacent to the sidewalls and bottom surface of the plurality of deep pixel trenches. The method may include: performing an annealing process. Furthermore, the method may include: forming a plurality of deep pixel isolation regions in the plurality of deep pixel trenches. Attached Figure Description

[0011] Figure 1 A plan view of an image sensor illustrating some example embodiments of a concept according to the present invention is shown.

[0012] Figure 2 It shows along Figure 1 The cross-sectional view taken by line I-I' in the diagram.

[0013] Figure 3A circuit diagram illustrating some example embodiments of an image sensor according to a concept of the present invention is shown.

[0014] Figures 4 to 8 The display shows that it has Figure 2 A cross-sectional view of the manufacturing method of an image sensor.

[0015] Figure 9 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0016] Figures 10 to 12 The display shows that it has Figure 9 A cross-sectional view of the manufacturing method of an image sensor.

[0017] Figure 13 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0018] Figure 14 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0019] Figure 15 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0020] Figure 16 and Figure 17 The display shows that it has Figure 15 A cross-sectional view of the manufacturing method of an image sensor.

[0021] Figure 18 A plan view of an image sensor illustrating some example embodiments of a concept according to the present invention is shown.

[0022] Figure 19 It shows along Figure 18 The cross-sectional view taken from line II-II'.

[0023] Figure 20 The display shows that it has Figure 19 A cross-sectional view of the manufacturing method of an image sensor.

[0024] Figure 21 It shows along Figure 18 The cross-sectional view taken from line II-II'. Detailed Implementation

[0025] Some exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] Figure 1 A plan view of an image sensor illustrating some example embodiments of a concept according to the present invention is shown. Figure 2It shows along Figure 1 The cross-sectional view taken from line I-I'. Figure 3 A circuit diagram illustrating some example embodiments of an image sensor according to a concept of the present invention is shown.

[0027] Reference Figure 1 and Figure 2 A substrate 1 can be provided, comprising multiple pixel regions UP1 and UP2. The multiple pixel regions UP1 and UP2 may include a first pixel region UP1 and a second pixel region UP2. The first pixel region UP1 may be arranged linearly along a first direction X. The second pixel region UP2 may be arranged linearly along the first direction X. The first pixel region UP1 is spaced apart from the second pixel region UP2 in a second direction Y, wherein the second direction Y intersects the first direction X. The substrate 1 may have a first surface 1a and a second surface 1b facing each other. The first surface 1a of the substrate 1 may be referred to as the front side, on which a driving transistor is disposed. The second surface 1b may be referred to as the back side. Light can enter through the second surface 1b. The image sensor according to an embodiment of the present invention can be a back-side light-receiving image sensor. The substrate 1 may be a single-crystal silicon wafer or an epitaxial silicon layer. The substrate 1 may be doped with a P-type impurity. For example, the substrate 1 may be doped with boron.

[0028] A deep pixel isolation region (DTI) separating a first pixel region UP1 and a second pixel region UP2 may be disposed in the substrate 1. Herein, the term "region" refers to an area, such as an isolation region. The deep pixel isolation region (DTI) may be disposed in a deep pixel trench 5 formed in the substrate 1. The deep pixel isolation region (DTI) may extend from a first surface 1a of the substrate 1 to reach a second surface 1b. The deep pixel isolation region (DTI) may penetrate the substrate 1. The deep pixel isolation region (DTI) may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The width of the deep pixel isolation region (DTI) may decrease as it moves from the first surface 1a toward the second surface 1b.

[0029] The substrate 1 may contain a first photoelectric conversion region PD1 within each of a first pixel region UP1 separated from each other by a deep pixel isolation region DTI. In some embodiments, the substrate 1 may also contain a second photoelectric conversion region PD2 within each of a second pixel region UP2 separated from each other by a deep pixel isolation region DTI. Figure 3 The first photoelectric conversion region PD1 can be doped with an impurity whose conductivity type is opposite to that of the impurities doped in the substrate 1, such as an N-type impurity. A PN junction can be formed between the first photoelectric conversion region PD1, the second photoelectric conversion region PD2, and the P-type impurity region of the substrate 1, generating electron-hole pairs when light enters.

[0030] On each of the first pixel region UP1 and the second pixel region UP2, a shallow device isolation region (STI) may be formed in the substrate 1, defining an active region for forming a driving transistor. The shallow device isolation region STI may be formed within a shallow device trench 3. The shallow device isolation region STI may be positioned adjacent to the first surface 1a. A deep pixel isolation region (DTI) may penetrate the shallow device isolation region STI. The top surface of the deep pixel isolation region DTI may be coplanar with the top surface of the shallow device isolation region STI. The shallow device isolation region STI may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0031] On the first pixel region UP1, a first transmission gate TG1 may be disposed on the first surface 1a of the substrate 1. On the second pixel region UP2, a second transmission gate TG2 may be disposed on the first surface 1a of the substrate 1. On each of the first pixel region UP1 and the second pixel region UP2, the substrate 1 may have a groove 13 adjacent to the first surface 1a. The groove 13 may correspondingly cover (or be covered by) the first transmission gate TG1 and the second transmission gate TG2. A portion of the first transmission gate TG1 and the second transmission gate TG2 may extend into and fill the groove 13. A gate dielectric layer Gox may be inserted between the substrate 1 and each of the first transmission gate TG1 and the second transmission gate TG2. The gate dielectric layer Gox may be separated from the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2. The gate dielectric layer Gox may include a silicon oxide layer.

[0032] The gate overlay pattern 15 may be disposed on the top surface of each of the first transmission gate TG1 and the second transmission gate TG2. The gate spacer 17 may be located on the sidewall of each of the first transmission gate TG1 and the second transmission gate TG2 (e.g., may cover the sidewall of each of the first transmission gate TG1 and the second transmission gate TG2). The gate overlay pattern 15 and the gate spacer 17 may be formed of, for example, a silicon nitride layer.

[0033] A first floating diffusion region FD1 can be disposed within the substrate 1 and adjacent to the first transmission gate TG1, and a second floating diffusion region FD2 can be disposed within the substrate 1 and adjacent to the second transmission gate TG2. Both the first and second floating diffusion regions FD1 and FD2 can be doped with impurities whose conductivity type is opposite to that of the impurities doped in the substrate 1, such as N-type impurities. An ohmic layer 19 can be disposed on each of the first and second floating diffusion regions FD1 and FD2. The ohmic layer 19 can be formed of a metal silicide layer.

[0034] like Figure 1As shown, in each first pixel region UP1, a reset gate RG can be disposed on the first surface 1a of the substrate 1. The reset gate RG can be separated from the first transmission gate TG1. A source / drain region can be disposed in the substrate 1 and adjacent to the reset gate RG. In each second pixel region UP2, a select gate SEL and a source follower gate SF can be disposed on the surface 1a of the substrate 1, separated from each other. The select gate SEL and the source follower gate SF can be separated from the second transmission gate TG2. A source / drain region can be disposed in the substrate 1 and adjacent to the select gate SEL and the source follower gate SF.

[0035] Gates TG1, TG2, RG, SEL, and SF can be covered by multiple interlayer dielectric layers 21. The lowest layer of the multiple interlayer dielectric layers 21 may have contact plugs 23 therein, which are respectively electrically connected to the first floating diffusion region FD1 and the second floating diffusion region FD2. The interlayer dielectric layers 21 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous dielectric layer. The contact plugs 23 may be coupled to the connection lines 25 between the interlayer dielectric layers 21. A passivation layer 30 may be disposed on the interlayer dielectric layers 21. For example, the passivation layer 30 may include a silicon nitride layer.

[0036] The second surface 1b of the substrate 1 can be in contact with the fixed charge layer 35. The fixed charge layer 35 can be formed of a metal oxide layer with an oxygen content (e.g., concentration) less than its stoichiometric ratio, or a metal fluoride layer with a fluorine content (e.g., concentration) less than its stoichiometric ratio. The fixed charge layer 35 can have a negative fixed charge. The fixed charge layer 35 can include one of a metal oxide and a metal fluoride, wherein the metal oxide and metal fluoride include at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), ytterbium (Y), and lanthanides. The fixed charge layer 35 can be disposed at the edge of the deep pixel isolation region (DTI) and can be in contact with the substrate 1. Additionally, the fixed charge layer 35 can extend to cover the second surface 1b of the substrate 1. The fixed charge layer 35 can suppress dark current and white spot problems.

[0037] A color filter CF can be disposed on a fixed charge layer 35. A microlens ML can be disposed on a corresponding color filter CF. The color filter CF can be, for example, red, green, or blue.

[0038] An amorphous region 7 may be disposed in the substrate 1 adjacent to the sidewall of the deep pixel isolation region (DTI). The amorphous region 7 may be separated from the first photoelectric conversion region (PD1) and the second photoelectric conversion region (PD2). The amorphous region 7 may be doped with carbon ions and / or germanium ions. An electron suppression region 9 may be located between the amorphous region 7 and the sidewall of the deep pixel isolation region (DTI). As used herein, the term "electron suppression" refers to suppressing / blocking electrons. The electron suppression region 9 may be doped with impurities of the same conductivity type as the impurities doped in the substrate 1. The concentration of impurities doped in the electron suppression region 9 may be higher than the concentration of impurities doped in the substrate 1. For example, the electron suppression region 9 may be doped with boron ions. The concentration of boron doped in the electron suppression region 9 may be higher than the concentration of boron doped in the substrate 1. The electron suppression region 9 may be additionally doped with carbon ions and / or germanium ions. The electron suppression region 9 may be in contact with the sidewall of the deep pixel isolation region (DTI) or the inner wall / sidewall of the deep pixel trench 5. The electron suppression region 9 and the amorphous region 7 can be uniformly distributed along the sidewalls of the deep pixel isolation region DTI, from the second surface 1b of the substrate 1 to the bottom surface of the shallow device isolation region STI (e.g., they can extend to the same length in the Z direction, which intersects the first direction X and the second direction Y). In some embodiments, the electron suppression region 9 and the amorphous region 7 can be longer than the first photoelectric conversion region PD1 in the Z direction.

[0039] The first pixel region UP1 and the second pixel region UP2, which are adjacent to each other in the second direction Y, can share the reset gate RG, the source follower gate SF, and the select gate SEL. In some embodiments, the connecting line and the contact plug can respectively electrically connect the first floating diffusion region FD1 of the first pixel region UP1 and the second floating diffusion region FD2 of the second pixel region UP2, which are adjacent to each other in the second direction Y. The charges generated in the first pixel region UP1 and the second pixel region UP2 can be transferred sequentially.

[0040] Reference Figures 1 to 3 First, a power supply voltage can be applied to the drain of the reset transistor (including the reset gate RG) and the drain of the source follower transistor (including the source follower gate SF) to discharge the remaining charge in the first floating diffusion region FD1 and the second floating diffusion region FD2. Then, when the reset transistor is turned off and a voltage is applied to the first transfer gate TG1, the charge generated in the first photoelectric conversion region PD1 can be transferred to the first floating diffusion region FD1 and accumulate there. The bias of the source follower gate SF can be changed proportionally to the amount of accumulated charge, which causes a change in the source potential of the source follower transistor. In this case, when the select transistor (including the select gate SEL) is turned on, the signal caused by the charge / signal including the charge can be read from the signal readout line Vout. The same steps / processes can then be performed on the second pixel region UP2.

[0041] The image sensor conceived according to the present invention may include an electron suppression region 9 and an amorphous region 7 adjacent to the sidewalls of the deep pixel isolation region (DTI). The sidewalls of the DTI or the inner / sidewalls of the deep pixel trench 5 may have crystal defects or dangling bonds due to etching damage. Annealing can be performed to correct such crystal defects; however, it may be difficult to completely correct them. Furthermore, annealing may not completely remove dangling bonds. Crystal defects or dangling bonds can become trap points. When a light-emitting diode generates photoelectrons from light in the presence of trap points, some photoelectrons may be trapped by the trap points, potentially causing light loss. Dangling bonds may generate electrons, and these generated electrons may flow into the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2, leading to deterioration of dark current characteristics. Therefore, white spots appear in a completely dark state. However, boron ions doped in the electron suppression region 9 can prevent electron migration to suppress light loss and improve dark current characteristics.

[0042] Figures 4 to 8 The demonstration shows the manufacturing process with Figure 2 A cross-sectional view of an image sensor method.

[0043] like Figure 1 and Figure 4 As shown, a substrate 1 comprising multiple pixel regions UP1 and UP2 can be fabricated. A shallow device trench 3 can be formed by etching a portion of the first surface 1a adjacent to the substrate 1. The shallow device trench 3 can be filled with a dielectric layer and subsequently planarized to form a shallow device isolation region (STI) defining the active region of the substrate 1 within the shallow device trench 3.

[0044] like Figure 1 and Figure 5 As shown, a first mask pattern MK1 can be formed on the first surface 1a of the substrate 1. The first mask pattern MK1 can be, for example, a photoresist pattern. The first mask pattern MK1 can have an opening defining the location of the deep pixel isolation region (DTI), as shown in the figure. Figure 7 This will be explained below. An etching process can be performed to form the deep pixel trench 5, in which a first mask pattern MK1 is used as an etching mask to pattern a portion of the shallow device isolation region (STI) and the substrate 1. The etching process may cause etching damage on the inner walls / sidewalls of the deep pixel trench 5 (at one or more locations), which may result in crystal defects or dangling bonds. The deep pixel trench 5 can be formed with a bottom surface spaced apart from the second surface 1b of the substrate 1.

[0045] A first plasma doping process P1 can be performed to form an amorphous region 7 on a portion of the substrate 1 adjacent to (and / or defining) the bottom surface and inner / sidewalls of the deep pixel trench 5. The first plasma doping process P1 can implant carbon ions and / or germanium ions into the amorphous region 7 to transform that portion of the substrate 1 from a crystalline structure to an amorphous structure. At least one of methane and ethane can be provided as a source material for implanting carbon ions. Alternatively, a germanium source material can be provided for implanting germanium ions. The processing chamber can receive these source materials in a gaseous state. When a high voltage bias is applied to an electrostatic chuck on which the substrate 1 is mounted after the source material has been plasma-plated, the carbon cations or germanium cations of the plasma can be accelerated and implanted into the substrate 1. Plasma doping can achieve uniform doping even at very deep portions and can increase the doping rate. Because the deep pixel trench 5 is relatively narrower and deeper than the shallow device trench 3, it is difficult or impossible for the beamline ion implantation process to uniformly form the amorphous region 7 in the depth direction. The amorphous region 7 can be formed as having a bottom surface spaced apart from the second surface 1b of the substrate 1.

[0046] Reference Figure 1 and Figure 6 The substrate 1, on which the amorphous region 7 is formed, can undergo a second plasma doping process P2 to form an electron suppression region 9 on a portion of the amorphous region 7. For example, the second plasma doping process P2 can implant boron ions into the amorphous region 7 to form the electron suppression region 9. At least one of BF3 and B2H6 can be provided as a source material for implanting boron ions. The processing chamber can receive such a source material in a gaseous state. When a high voltage bias is applied to an electrostatic chuck on which the substrate 1 is mounted after the source material has been plasma-plated, the boron cations in the plasma can be accelerated and implanted into the substrate 1. Compared with beam-wire ion implantation, plasma doping can achieve uniform doping even at very deep locations and can increase the doping rate. Since the electron suppression region 9 is formed on a portion of the amorphous region 7, the electron suppression region 9 can also be doped with carbon ions and / or germanium ions implanted into the amorphous region 7.

[0047] like Figure 7 As shown, the first mask pattern MK1 can be removed to expose the first surface 1a of the substrate 1. When the first mask pattern MK1 is formed by a photoresist pattern, it can be removed by ashing. Annealing can be performed. Annealing can be performed at a temperature of about 1000°C or higher. Annealing can compensate for / repair crystal defects caused by etching damage to the inner / sidewalls of the deep pixel trench 5. When the amorphous region 7 is missing, boron ions implanted into the electron suppression region 9 may diffuse into the substrate 1. When the boron ions doped into the electron suppression region 9 diffuse close to the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2 (to be referred to) Figure 1 and Figure 8 When the depletion region of the PN junction is affected (as will be explained below), the full capacitance (FWC) characteristic is reduced, which leads to a decrease in photosensitivity. However, according to the present invention, the amorphous region 7 may include an amorphous crystal structure to hinder / prevent / suppress the diffusion of boron ions. The amorphous region 7 can act as a diffusion blocking layer to prevent / prevent boron ions from diffusing from the electron suppression region 9. Thus, the amorphous region 7 can prevent the degradation of FWC characteristics and improve photosensitivity.

[0048] The dielectric layer can be stacked on the entire surface of the substrate 1 (e.g., the entire first surface 1a) and can be planarized to form a deep pixel isolation region (DTI) within the deep pixel trench 5.

[0049] Although this article is about Figure 7 The discussion describes an example of annealing after the formation of the deep pixel isolation region (DTI), but the annealing process can also be performed before the formation of the DTI.

[0050] Reference Figure 1 and Figure 8 Ion implantation can be performed to dope substrate 1 with impurities whose conductivity type is opposite to that of the impurities doped in substrate 1, thereby forming a first photoelectric conversion region PD1 and a second photoelectric conversion region PD2 in the first pixel region UP1 and the second pixel region UP2, respectively, in substrate 1. The first photoelectric conversion region PD1 and the second photoelectric conversion region PD2 can be formed... Figure 4 The shallow device isolation region (STI) is formed before, or during, the formation of Figure 4 The shallow device isolation region (STI) is formed afterward. A recess 13 can be formed by locally etching the first surface 1a of the substrate 1. Thermal oxidation can be performed to form the gate dielectric layer Gox on the first surface 1a of the substrate 1. A conductive layer and a capping layer can be stacked on the first surface 1a of the substrate 1 and then patterned to form a first transport gate TG1 and a second transport gate TG2, a reset gate RG, a select gate SEL, a source follower gate SF, and a gate capping pattern 15. A spacer layer can be conformally stacked on the first surface 1a of the substrate 1 and then anisotropically etched to form a gate spacer 17, which covers the sidewalls of the first transport gate TG1 and the second transport gate TG2, the sidewalls of the reset gate RG, the sidewalls of the select gate SEL, the sidewalls of the source follower gate SF, and the sidewalls of the gate capping pattern 15.

[0051] Ion implantation can be performed to form a first floating diffusion region FD1 and a second floating diffusion region FD2 adjacent to the first transmission gate TG1 and the second transmission gate TG2, respectively, in the substrate 1. In this step, the source / drain regions can be formed in the substrate 1 adjacent to the reset gate RG, the select gate SEL, and the source follower gate SF. Siliconization can be performed to form an ohmic layer 19 on the exposed first surface 1a of the substrate 1. An interlayer dielectric layer 21, contact plugs 23, interconnects 25, and a passivation layer 30 can be formed on the first surface 1a of the substrate 1.

[0052] like Figure 1 and Figure 2 As shown, a polishing process can be performed to partially remove the second surface 1b of the substrate 1, exposing the bottom surface of the deep pixel isolation region (DTI). The polishing process can also remove portions of the amorphous region 7 and the electron suppression region 9 adjacent to the bottom surface of the deep pixel trench 5. A fixed charge layer 35 can be formed on the second surface 1b of the substrate 1. A color filter CF and a microlens ML can be sequentially formed on the fixed charge layer 35.

[0053] Figure 9 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0054] Reference Figure 9 According to some embodiments, the image sensor can be configured such that a first amorphous region 7 can be positioned in the substrate 1 as a sidewall adjacent to a deep pixel isolation region (DTI). A first electron suppression region 9 can be located between the amorphous region 7 and the sidewall of the deep pixel isolation region (DTI). A second amorphous region 37 can be positioned in the substrate 1 as a sidewall adjacent to a shallow device isolation region (STI). A second electron suppression region 39 can be located between the second amorphous region 37 and the sidewall of the shallow device isolation region (STI). The second amorphous region 37 and the second electron suppression region 39 can be adjacent to the bottom surface of the shallow device isolation region (STI). The second electron suppression region 39 can be in contact with the bottom surface and sidewall of the shallow device isolation region (STI). Both the first electron suppression region 9 and the second electron suppression region 39 can be doped with the same impurities as those doped in the substrate 1, and can have a higher impurity concentration than that of the substrate 1. For example, the first electron suppression region 9 and the second electron suppression region 39 can be doped with boron ions. The first electron suppression region 9 and the second electron suppression region 39 can also be additionally doped with carbon ions and / or germanium ions. The first amorphous region 7 and the second amorphous region 37 can be doped with carbon ions and / or germanium ions.

[0055] The second amorphous region 37 and the second electron suppression region 39 can extend to the first floating diffusion region FD1 and the second floating diffusion region FD2. Therefore, each of the first floating diffusion region FD1 and the second floating diffusion region FD2 can include a portion of the second amorphous region 37 doped with carbon ions and / or germanium ions. Figure 9 Other constructions of the image sensor shown can be compared with those of the reference sensor. Figure 1 as well as Figure 2 The structures discussed are the same or similar.

[0056] like Figure 9 The image sensor shown can be configured such that the deep pixel isolation region (DTI) has sidewalls adjacent to the first electron suppression region 9 to suppress electron migration, and the shallow device isolation region (STI) has sidewalls adjacent to the second electron suppression region 39 to suppress electron migration. In this way, the image sensor can successfully prevent light loss and reliably improve dark current characteristics. The first amorphous region 7 and the second amorphous region 37 can suppress the diffusion of boron ions doped into the first electron suppression region 9 and the second electron suppression region 39.

[0057] Figures 10 to 12 The demonstration shows the manufacturing process with Figure 9 A cross-sectional view of an image sensor method.

[0058] like Figure 1 and Figure 10 As shown, a second mask pattern MK2 can be formed on the first surface 1a of the substrate 1 to have an opening defining the location of the shallow device isolation region (STI). The second mask pattern MK2 can be formed, for example, by a photoresist pattern. The shallow device trench 3 can be formed by an etching process in which the first surface 1a of the substrate 1 is partially etched using the second mask pattern MK2 as an etching mask. A first process P3 can be performed to form a second amorphous region 37 on a portion of the bottom surface and sidewalls of the shallow device trench 3 adjacent to the substrate 1. The first process P3 can be a plasma doping process or a beam-wire ion implantation process. The second amorphous region 37 can be doped with carbon ions and / or germanium ions. When the second amorphous region 37 is doped with carbon ions, at least one of methane and ethane can be supplied as a source material.

[0059] Reference Figure 11 A second treatment P4 can be performed to form a second electron suppression region 39 in a portion of the second amorphous region 37. The second treatment P4 can be a plasma doping treatment or a beam-implantation treatment. The second electron suppression region 39 can be doped with boron ions. At least one of BF3 and B2H6 can be supplied as a source material to form the second electron suppression region 39.

[0060] like Figure 12As shown, the shallow device trench 3 can be filled with one or more dielectric layers including at least one selected from silicon oxide, silicon nitride and silicon oxynitride, and then planarization can be performed to form a shallow device isolation region (STI).

[0061] The reference can be executed subsequently. Figures 5 to 8 The processing discussed. After the formation of the second electron suppression region 39 or the shallow device isolation region (STI), annealing can be performed to compensate for / repair etching damage on the inner / sidewalls of the shallow device trench 3. Alternatively, after the formation of the first electron suppression region 9 or the deep pixel isolation region (DTI), annealing can be performed to compensate for / repair etching damage on the inner / sidewalls of the shallow device trench 3 and the deep pixel trench 5.

[0062] Figure 13 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0063] Reference Figure 13 According to some embodiments, an image sensor can be configured such that a deep pixel isolation region (DTI) may include a first fixed charge layer 41 and a dielectric buried layer 43. The first fixed charge layer 41 may be in contact with a first electron suppression region 9. The first fixed charge layer 41 may be located between the dielectric buried layer 43 and a shallow device isolation region (STI). A second surface 1b of the substrate 1 may be in contact with a second fixed charge layer 35. The first fixed charge layer 41 and the second fixed charge layer 35 may be composed of a metal oxide layer with an oxygen content (e.g., concentration) less than its stoichiometric ratio, or a metal fluoride layer with a fluorine content (e.g., concentration) less than its stoichiometric ratio. The dielectric buried layer 43 may be composed of a single layer or multiple layers including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Figure 13 Other constructions of the image sensor shown can be referenced above. Figure 9 The image sensors discussed have the same or similar construction.

[0064] It can be manufactured in the following ways Figure 13 Image sensor: when in such Figure 7 In the steps / processes shown, when forming the deep pixel isolation region (DTI), a first fixed charge layer 41 is conformally formed on the inner wall / side wall and bottom surface of the deep pixel trench 5, the deep pixel trench 5 is filled with a dielectric buried layer 43, and then a planarization process is performed.

[0065] Figure 14 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0066] Reference Figure 14According to some embodiments, an image sensor can be configured such that a deep pixel isolation region (DTI) may include a dielectric liner 45 conformally covering the inner walls / sidewalls and bottom surface of a deep pixel trench 5, and also includes a conductive pattern 47 filling the deep pixel trench 5. The dielectric liner 45 may be in contact with a first electron suppression region 9. The dielectric liner 45 may be located between the conductive pattern 47 and a shallow device isolation region (STI). The dielectric liner 45 may be a single-layer or multi-layer structure including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The conductive pattern 47 may include a polysilicon pattern doped with impurities or a metal-containing layer. The conductive pattern 47 may serve as a common bias line. A negative voltage may be supplied to the conductive pattern 47. Therefore, dark current characteristics can be improved by retaining holes (or positive charges) that may appear on the surface of the deep pixel isolation region (DTI). Figure 14 Other construction and manufacturing processes of the image sensor shown can be compared with those in the reference. Figure 13 The image sensors discussed are constructed and manufactured using the same or similar processes.

[0067] Figure 15 It shows along Figure 1 The cross-sectional view taken from line I-I'.

[0068] like Figure 15 As shown, an image sensor according to some embodiments can be configured such that the shallow device isolation region (STI) and the deep pixel isolation region (DTI) can be jointly connected into a single structure. The shallow device trench 3 and the deep pixel trench 5 can be jointly formed as a dual damascene hole structure. An amorphous region 7 can be configured in the substrate 1 adjacent to the sidewalls of the deep pixel isolation region (DTI) and the sidewalls and bottom surface of the shallow device isolation region (STI). An electron suppression region 9 can be located between the amorphous region 7 and the sidewalls of the deep pixel isolation region (DTI), between the amorphous region 7 and the shallow device isolation region (STI), and between the amorphous region 7 and the bottom surface of the shallow device isolation region (STI). The amorphous region 7 and the electron suppression region 9 can extend into the first floating diffusion region FD1 and the second floating diffusion region FD2. Therefore, each of the first floating diffusion region FD1 and the second floating diffusion region FD2 can have a portion doped with boron ions and / or germanium ions.

[0069] Figure 16 and Figure 17 The display shows that it has Figure 15 A cross-sectional view of the manufacturing method of an image sensor.

[0070] like Figure 1 and Figure 16As shown, substrate 1 can be etched multiple times using a third mask pattern MK3 and an auxiliary mask pattern to form a double trench 4 comprising shallow device trenches 3 and deep pixel trenches 5. As used herein, the term "auxiliary" refers to an additional / alternate pattern or region. A first plasma doping process P1 can be performed to form an amorphous region 7 on a portion of the inner wall / sidewall and bottom surface (and / or defining the inner wall / sidewall and bottom surface) of substrate 1 adjacent to the double trench 4. The amorphous region 7 can be doped with carbon ions and / or germanium ions. At least one of methane and ethane can be provided as a source material for implanting carbon ions. Alternatively, a germanium source material can be provided for implanting germanium ions.

[0071] Reference Figure 17 A second plasma doping process P2 can be performed to form an electron suppression region 9 on a portion of the substrate 1 adjacent to the inner wall / sidewall and bottom surface of the double trench 4. The electron suppression region 9 can have a smaller doping depth than the amorphous region 7. The electron suppression region 9 can be doped with boron ions. At least one of BF3 and B2H6 can be provided as a source material for boron ion implantation.

[0072] Then, refer to Figure 15 The third mask pattern MK3 can be removed to expose the first surface 1a of the substrate 1. The double trench 4 can be filled with an insulating layer stacked on the first surface 1a of the substrate 1, and then a planarization process can be performed to simultaneously form a shallow device isolation region (STI) and a deep pixel isolation region (DTI) within the double trench 4. In some embodiments, even in a substrate 1 with a relatively complex double trench 4, the first plasma doping process P1 and the second plasma doping process P2 can form an amorphous region 7 and an electron suppression region 9 with uniform depth (e.g., length in the Z direction). Therefore, the manufacturing process can be further simplified.

[0073] Figure 18 A plan view of an image sensor illustrating some example embodiments of a concept according to the present invention is shown. Figure 19 It shows along Figure 18 The cross-sectional view taken from line II-II'.

[0074] Reference Figure 18 and Figure 19Pixel regions UP1, UP2, UP3, and UP4 may include a first pixel region UP1, a second pixel region UP2, a third pixel region UP3, and a fourth pixel region UP4 that are adjacent to each other. Adjacent first pixel regions UP1 to fourth pixel regions UP4 may share a single floating diffusion region FD. First pixel region UP1 may include a first transmission gate TG1 and a first photoelectric conversion region PD1 disposed in the substrate 1. First pixel region UP1 may have a first transmission gate TG1 located at a corner adjacent to the second pixel regions UP2 to the fourth pixel regions UP4. Second pixel region UP2 may include a second transmission gate TG2 and a second photoelectric conversion region PD2 disposed in the substrate 1. Second pixel region UP2 may have a second transmission gate TG2 located at a corner adjacent to the first pixel region UP1, the third pixel region UP3, and the fourth pixel region UP4.

[0075] The reset gate RG, the select gate SEL, and the source follower gate SF can be disposed on portions of the third pixel region UP3 and the fourth pixel region UP4. For example, the third pixel region UP3 may include a third transmission gate TG3, a third photoelectric conversion region PD3 disposed in the substrate 1, a portion of the reset gate RG and the source follower gate SF. The fourth pixel region UP4 may include a fourth transmission gate TG4, a fourth photoelectric conversion region PD4 disposed on the substrate 1, the remaining portions of the select gate SEL and the source follower gate SF.

[0076] The first photoelectric conversion regions PD1 to the fourth photoelectric conversion regions PD4 may include impurity-doped regions containing impurities whose conductivity type (e.g., N-type) is opposite to that of the impurities doped in the substrate 1. The floating diffusion region FD may contain impurities whose conductivity type (e.g., N-type) is opposite to that of the impurities doped in the substrate 1.

[0077] According to some embodiments, the image sensor may not include... Figure 2 The image sensor according to some embodiments can be configured such that a deep pixel trench 5 can be formed extending from a second surface 1b of a substrate 1 to a first surface 1a of the substrate 1. The deep pixel isolation region DTI can be separated from the first surface 1a of the substrate 1. The deep pixel isolation region DTI may include a fixed charge layer 41 covering the inner walls / sidewalls and bottom surface of the deep pixel trench 5, and also includes a dielectric buried layer 43 filling the deep pixel trench 5. The width of the deep pixel isolation region DTI may decrease as the deep pixel isolation region DTI approaches the first surface 1a from the second surface 1b. The fixed charge layer 41 may extend onto and contact the second surface 1b. The dielectric buried layer 43 may extend onto and cover the second surface 1b.

[0078] On the second surface 1b, a second passivation layer 63 may be formed on the dielectric buried layer 43. The second passivation layer 63 may be formed of a silicon nitride layer. A color filter CF and a microlens ML may be formed on the second passivation layer 63.

[0079] The image sensor may include a device isolation region 53 in the substrate 1 and adjacent to the first surface 1a. Similar to the shallow device isolation region (STI), the device isolation region 53 may be formed before the deep pixel trench 5 is formed, and may define an active region on which a driving transistor is disposed. The device isolation region 53 may be doped with impurities of the same conductivity type as the impurities doped in the substrate 1, and may have a higher impurity concentration than the impurity concentration of the substrate 1. The floating diffusion region FD and the deep pixel isolation region DTI may be configured to have an auxiliary device isolation region 54 located between the floating diffusion region FD and the deep pixel isolation region DTI, between adjacent first pixel regions UP1 to fourth pixel regions UP4. The auxiliary device isolation region 54 may include impurities of the same conductivity type as the impurities doped in the device isolation region 53. The auxiliary device isolation region 54 may have an impurity concentration equal to or similar to the impurity concentration of the device isolation region 53. Below the floating diffusion region FD, the auxiliary device isolation region 54 may impede / prevent the diffusion of impurities from the floating diffusion region FD toward the second surface 1b.

[0080] The amorphous region 7 and the electron suppression region 9 can be disposed on a portion of the sidewall adjacent to the deep pixel isolation region (DTI) of the substrate 1. The amorphous region 7 and the electron suppression region 9 can extend to the vicinity of the bottom surface of the deep pixel trench 5. The amorphous region 7 and the electron suppression region 9 can be located between the device isolation region 53 and the bottom surface of the deep pixel trench 5, and between the auxiliary device isolation region 54 and the bottom surface of the deep pixel isolation trench 5. Alternatively, the amorphous region 7 and the electron suppression region 9 can extend within the device isolation region 53 and the auxiliary device isolation region 54. Therefore, the device isolation region 53 and the auxiliary device isolation region 54 can have portions doped with carbon ions and / or germanium ions.

[0081] like Figure 19 Other configurations of the image sensor shown can be compared with those of the reference sensor. Figure 1 and Figure 2 The structures discussed are the same or similar. Image sensors can be compared with reference sensors. Figure 3 The image sensor discussed in the circuit diagram shown operates similarly and can be sensed through the first pixel region UP1 to the fourth pixel region UP4.

[0082] Figure 20 The display shows that it has Figure 19 A cross-sectional view of the manufacturing method of an image sensor.

[0083] Reference Figures 18 to 20A first photoelectric conversion region PD1, a second photoelectric conversion region PD2, a third photoelectric conversion region PD3, and a fourth photoelectric conversion region PD4 can be formed in substrate 1. Device isolation region 53 and auxiliary device isolation region 54 can be formed on a portion of the first surface 1a of substrate 1 adjacent to substrate 1. First transmission gate TG1, second transmission gate TG2, third transmission gate TG3, and fourth transmission gate TG4, reset gate RG, select gate SEL, and source follower gate SF can be formed on the first surface 1a of substrate 1. Floating diffusion region FD can be formed on substrate 1 between adjacent first pixel regions UP1, second pixel region UP2, third pixel region UP3, and fourth pixel region UP4. Multiple interlayer dielectric layers 21, contact plugs 23, interconnects 25, and a first passivation layer 30 can be formed on the first surface 1a of substrate 1. A polishing process can be performed to partially remove the second surface 1b of substrate 1, allowing substrate 1 to have a desired thickness. A fourth mask pattern MK4 can be formed on the second surface 1b of the substrate 1. The fourth mask pattern MK4 can have an opening defining the deep pixel isolation region DTI, which will be discussed below. The fourth mask pattern MK4 can be used as an etching mask to etch the substrate 1 to form the deep pixel trench 5. The deep pixel trench 5 can expose the device isolation region 53 and the auxiliary device isolation region 54. The amorphous region 7 and the electron suppression region 9 can be as described in reference. Figure 5 and Figure 6 The amorphous region 7 and the electron suppression region 9 can be formed adjacent to the bottom surface of the deep pixel trench 5. Therefore, the amorphous region 7 can be formed within the device isolation region 53 and the auxiliary device isolation region 54.

[0084] Then, return to the reference. Figure 19 The fourth mask pattern MK4 can be removed to expose the second surface 1b. A fixed charge layer 41 can be conformally formed on the second surface 1b of the substrate 1. A dielectric buried layer 43 can be formed on the fixed charge layer 41 to form a deep pixel isolation region (DTI) filling the deep pixel trench 5. A second passivation layer 63, a color filter CF, and a microlens ML can be formed on the dielectric buried layer 43.

[0085] Figure 21 It shows along Figure 18 The cross-sectional view taken from line II-II'.

[0086] Reference Figure 21According to some embodiments, an image sensor can be configured such that a deep pixel isolation region (DTI) may include a dielectric liner 45 conformally covering the inner walls / sidewalls and bottom surface of a deep pixel trench 5, and also includes a conductive pattern 47 filling the deep pixel trench 5. The dielectric liner 45 may extend onto a second surface 1b of a substrate 1. The conductive pattern 47 may have a top surface coplanar with the dielectric liner 45 on the second surface 1b. A planarization layer 61 may be disposed on the dielectric liner 45 and the conductive pattern 47. The planarization layer 61 may be formed of a silicon oxide layer or a pigment-free photoresist layer. A second passivation layer 63, a color filter CF, and a microfilter ML may be sequentially disposed on the planarization layer 61.

[0087] In the image sensor and its manufacturing method according to some exemplary embodiments of the present invention, light loss and dark current characteristics can be suppressed. Furthermore, FWC characteristic degradation can be prevented and photosensitivity improved.

[0088] While the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes / modifications / substitutions can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An image sensor, comprising: A substrate comprising a plurality of pixel regions, the substrate having a first surface and a second surface opposite to the first surface; A transmission gate on the first surface of the substrate; A shallow device isolation region, which is adjacent to the first surface in the substrate; A deep pixel isolation region extends from the second surface of the substrate toward the first surface of the substrate and separates the plurality of pixel regions from one another. Amorphous region, which is adjacent to the sidewall of the deep pixel isolation region; An electron suppression region is located between the sidewalls of the amorphous region and the deep pixel isolation region; and A first fixed charge layer extends to cover a second surface of the substrate. The electron suppression region includes boron ions. The deep pixel isolation region penetrates the shallow device isolation region. The first fixed charge layer is in contact with both the electron suppression region and the amorphous region.

2. The image sensor according to claim 1 further includes a photoelectric conversion region in the substrate. in, The photoelectric conversion region is separated from the amorphous region in a first direction, and The amorphous region is longer than the photoelectric conversion region in a second direction intersecting the first direction.

3. The image sensor according to claim 1, wherein, The amorphous region and the electron suppression region extend adjacent to the bottom surface of the shallow device isolation region.

4. The image sensor according to claim 3, in, The amorphous region and the electron suppression region respectively include a first amorphous region and a first electron suppression region, and The image sensor further includes: The second amorphous region, adjacent to the sidewall of the shallow device isolation region; and The second electron suppression region is located between the second amorphous region and the sidewall of the shallow device isolation region.

5. The image sensor according to claim 1, further comprising a floating diffusion region in the substrate on one side of the transmission gate, in, A portion of the floating diffusion region includes carbon ions, germanium ions, or both carbon ions and germanium ions.

6. The image sensor according to claim 1, in, The deep pixel isolation region is separated from the first surface, and The image sensor further includes a device isolation region located between the deep pixel isolation region and the first surface. The amorphous region and the electron suppression region extend between the deep pixel isolation region and the device isolation region.

7. The image sensor according to claim 1, in, The deep pixel isolation region is separated from the first surface, and The image sensor further includes a device isolation region located between the deep pixel isolation region and the first surface. The isolation region of the device includes carbon ions, germanium ions, or both carbon ions and germanium ions.

8. The image sensor according to claim 1, in, The deep pixel isolation region is separated from the first surface, and The image sensor further includes: A floating diffusion region located in the substrate between the plurality of pixel regions, the floating diffusion region being adjacent to the first surface; and The device isolation region between the floating diffusion region and the deep pixel isolation region The isolation region of the device includes carbon ions, germanium ions, or both carbon ions and germanium ions.

9. The image sensor according to claim 1, wherein, The deep pixel isolation region includes a second fixed charge layer that contacts the side surface of the electron suppression region.

10. The image sensor according to claim 1, wherein, The deep pixel isolation region includes: The dielectric layer in contact with the electron suppression region; and Conductive patterns separated from the electron suppression region.

11. The image sensor according to claim 1, wherein, The electron suppression region includes carbon ions, germanium ions, or both carbon ions and germanium ions.

12. The image sensor according to claim 1, in, The substrate includes boron ions, and In this region, the first concentration of boron ions in the electron suppression region is higher than the second concentration of boron ions in the substrate.

13. An image sensor, comprising: A substrate comprising a plurality of pixel regions, the substrate having a first surface and a second surface opposite to the first surface; A shallow device isolation region, which is adjacent to the first surface in the substrate; A deep pixel isolation region extends from the second surface toward the first surface and separates the plurality of pixel regions from each other, the deep pixel isolation region being in contact with the shallow device isolation region; Amorphous regions, which are respectively adjacent to the sidewalls of the deep pixel isolation region and the sidewalls of the shallow device isolation region; An electron suppression region is located between the amorphous region and the sidewall of the deep pixel isolation region and the sidewall of the shallow device isolation region; as well as A first fixed charge layer extends to cover a second surface of the substrate. The deep pixel isolation region penetrates the shallow device isolation region. The first fixed charge layer is in contact with both the electron suppression region and the amorphous region.

14. The image sensor of claim 13, further comprising a photoelectric conversion region in the substrate, in, The photoelectric conversion region is separated from the amorphous region.

15. The image sensor of claim 13, further comprising a floating diffusion region in the substrate adjacent to the first surface. in, The amorphous region and the electron suppression region extend into the floating diffusion region.

16. The image sensor of claim 13, further comprising a floating diffusion region in the substrate adjacent to the first surface, in, A portion of the floating diffusion region includes carbon ions, germanium ions, or both carbon ions and germanium ions.

17. An image sensor, comprising: A substrate comprising a plurality of pixel regions, the substrate having a first surface and a second surface opposite to the first surface; A device isolation region, which is adjacent to the first surface in the substrate; A deep pixel isolation region extends from the second surface toward the first surface and separates the plurality of pixel regions from each other; Amorphous region, which is adjacent to the sidewall of the deep pixel isolation region; An electron suppression region is located between the sidewalls of the amorphous region and the deep pixel isolation region; and A first fixed charge layer extends to cover a second surface of the substrate. A portion of the isolation region of the device includes carbon ions, germanium ions, or both carbon ions and germanium ions. The deep pixel isolation region penetrates the device isolation region. The first fixed charge layer is in contact with both the electron suppression region and the amorphous region.

18. The image sensor according to claim 17, in, The deep pixel isolation region is separated from the first surface. The device isolation region includes a first device isolation region. The image sensor further includes: A floating diffusion region located in the substrate between the plurality of pixel regions, the floating diffusion region being adjacent to the first surface; and A second device isolation region between the floating diffusion region and the deep pixel isolation region, and The isolation region of the first device includes carbon ions, germanium ions, or both carbon ions and germanium ions.

19. The image sensor according to claim 17, in, The deep pixel isolation region is separated from the first surface, and The image sensor further includes a floating diffusion region located in the substrate between the plurality of pixel regions, the floating diffusion region being adjacent to the first surface. The floating diffusion region is separated from the amorphous region and the electron suppression region.

20. A method for manufacturing an image sensor, the method comprising: A shallow device isolation region is formed in the substrate; The substrate is etched to form multiple deep pixel trenches that separate multiple pixel regions from each other and penetrate the shallow device isolation region; A first plasma doping process is performed to dope the substrate with carbon ions, germanium ions, or both carbon ions and germanium ions, thereby forming a first amorphous region in the substrate adjacent to the sidewalls and bottom surface of the plurality of deep pixel trenches. A second plasma doping process is performed to dope the substrate with boron ions, thereby forming a first electron suppression region in the substrate adjacent to the sidewalls and bottom surface of the plurality of deep pixel trenches; Perform annealing; Multiple deep pixel isolation regions are formed in the multiple deep pixel trenches; as well as A polishing process is performed to remove portions of the substrate, the first amorphous region, and the first electron suppression region located beneath the plurality of deep pixel isolation regions and to expose the bottom surface of the plurality of deep pixel isolation regions.

21. The method according to claim 20, wherein, Forming the plurality of deep pixel trenches also includes etching the shallow device isolation region.

22. The method of claim 21, further comprising, before forming the shallow device isolation region: A portion of the substrate is etched to form shallow device trenches; A second amorphous region is formed by implanting carbon ions, germanium ions, or both carbon ions and germanium ions into a substrate adjacent to the sidewalls and bottom surface of the shallow device trench. as well as A second electron suppression region is formed by implanting boron ions into the substrate adjacent to the sidewalls and bottom surface of the shallow device trench. The shallow device isolation region is formed in the shallow device trench.

23. The method of claim 20, wherein, Each of the plurality of deep pixel trenches is formed to have a dual trench structure, the dual trench structures having different widths.

24. The method according to claim 20, in, The substrate has a first surface and a second surface opposite to the first surface. The formation of the plurality of deep pixel trenches includes: etching the substrate from the second surface toward the first surface, and The method further includes forming a device isolation region in the substrate adjacent to the first surface before forming the plurality of deep pixel trenches.

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