Display panel and method for manufacturing the same

Abstract

A display panel and a method for manufacturing the display panel are provided. The display panel includes an upper display substrate and a lower display substrate. The upper display substrate includes: a base substrate; a first partition wall located on the base substrate, overlapping the light blocking area, and configured to define a first inner area, a second inner area, and a third inner area corresponding to a first pixel area, a second pixel area, and a third pixel area; a second partition wall extending from the first partition wall, overlapping at least one pixel area of ​​the first pixel area, the second pixel area, and the third pixel area, and configured to separate the inner area corresponding to the at least one pixel area into partial areas; and a first color control layer, a second color control layer, and a third color control layer, respectively located in the first inner area, the second inner area, and the third inner area.

Description

Technical Field

[0001] Aspects of embodiments of the present disclosure relate to a display panel and a method for manufacturing the display panel. Background Art

[0002] The display panel includes a transmissive display panel that selectively transmits source light generated from a light source and an emissive display panel that generates source light in the display panel itself. The display panel may include different types of color control layers according to pixels to produce a color image. The color control layer may transmit only a portion of the wavelength range of the source light, or may convert the color of the source light. A portion of the color control layer may not convert the color of the source light, but may convert the characteristics of the light. Summary of the invention

[0003] According to one aspect of an embodiment of the present disclosure, a display panel including a partition wall is provided. According to another aspect of an embodiment of the present disclosure, a display panel having reduced pixel defects is provided.

[0004] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a display panel having a simplified manufacturing process is provided.

[0005] According to one or more embodiments of the inventive concept, a display panel includes an upper display substrate and a lower display substrate. The upper display substrate includes a first pixel area, a second pixel area, and a third pixel area, and a light blocking area around the first pixel area, the second pixel area, and the third pixel area. The lower display substrate includes a first display element, a second display element, and a third display element corresponding to the first pixel area, the second pixel area, and the third pixel area. The upper display substrate includes: a base substrate; a first partition wall, located on the base substrate, overlapping the light blocking area, and configured to define a first inner area, a second inner area, and a third inner area corresponding to the first pixel area, the second pixel area, and the third pixel area; a second partition wall, overlapping at least one pixel area of ​​the first pixel area, the second pixel area, and the third pixel area, and configured to separate the inner area corresponding to the at least one pixel area into partial areas; and a first color control layer, a second color control layer, and a third color control layer, respectively located in the first inner area, the second inner area, and the third inner area.

[0006] In an embodiment, each of the first display element, the second display element, and the third display element may include a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode, and the light-emitting layers of the first display element, the second display element, and the third display element may have an integral shape to generate blue light.

[0007] In an embodiment, the first color control layer may include first quantum dots to convert blue light into red light, the second color control layer may include second quantum dots to convert blue light into green light, and the third color control layer may be configured to transmit blue light.

[0008] In an embodiment, an inner region corresponding to the at least one pixel region may be a first inner region, and the second partition wall may overlap the first electrode of the first display element.

[0009] In an embodiment, the second partition wall may extend in the first direction, and the second partition wall may be arranged such that the first electrode of the first display element is bisected in a second direction perpendicular to the first direction.

[0010] In an embodiment, the partial regions may have the same surface area in a plane.

[0011] In an embodiment, the first pixel region may have a surface area larger than a surface area of ​​each of the second pixel region and the third pixel region on a plane.

[0012] In an embodiment, the upper display substrate may further include: a black matrix located on the base substrate to overlap with the light blocking area; a red filter, a green filter, and a blue filter located on the base substrate to correspond to the first pixel area, the second pixel area, and the third pixel area, respectively; a first encapsulation layer covering the red filter, the green filter, and the blue filter; and a second encapsulation layer covering the first partition wall, the second partition wall, and the first color control layer, the second color control layer, and the third color control layer.

[0013] In an embodiment, the second partition wall may partition each of the first inner region, the second inner region, and the third inner region into partial regions.

[0014] In an embodiment, the display panel may further include a liquid crystal layer between the upper display substrate and the lower display substrate.

[0015] In an embodiment, the first color control layer may include a red color filter, the second color control layer may include a green color filter, and the third color control layer may include a blue color filter.

[0016] According to one or more embodiments of the inventive concept, a display panel includes an upper display substrate and a lower display substrate. The lower display substrate includes a first electrode, a second electrode having a surface area larger than that of the first electrode, and a light-emitting layer located between the first electrode and the second electrode. The upper display substrate includes: a base substrate; a black matrix located on the base substrate, and an opening corresponding to the first electrode is defined in the black matrix; a partition wall including a first portion overlapping the black matrix on a plane and having a closed line shape, and a second portion overlapping the opening and extending from one side of the first portion to the other side of the first portion; and a first quantum dot and a second quantum dot, respectively located in two partition areas defined by the first portion and the second portion.

[0017] In an embodiment, the first quantum dot and the second quantum dot may include the same material. In an embodiment, the second portion may bisect the first electrode on a plane.

[0018] According to one or more embodiments of the inventive concept, a method for manufacturing a display panel includes the following steps: forming a first display substrate including a first display element, a second display element, and a third display element; forming a second display substrate including a first pixel area, a second pixel area, and a third pixel area corresponding to the first display element, the second display element, and the third display element, and a light blocking area around the first pixel area, the second pixel area, and the third pixel area; and combining the first display substrate to the second display substrate.

[0019] The step of forming the second display substrate includes the following steps: forming a black matrix on a base substrate to overlap with the light blocking area; forming a partition wall including a first part and a second part on the base substrate, the first part defining a first internal area, a second internal area and a third internal area corresponding to the first pixel area, the second pixel area and the third pixel area, the second part extending from the first part, overlapping with the first pixel area and dividing the first internal area into two partial areas; forming a first part of a first color control layer in one partial area of ​​the two partial areas, and forming a second color control layer in the second internal area; and forming a second part of the first color control layer in the other partial area of ​​the two partial areas, and forming a third color control layer in the third internal area.

[0020] In an embodiment, a first color composition may be provided in the one partial region, and a second color composition different from the first color composition may be provided in the second inner region.

[0021] In an embodiment, the first color composition may include a solvent and solids dispersed in the solvent, the solids may be in a range of about 20 wt % to about 30 wt % based on the first color composition, and the solids may include a base resin and quantum dots.

[0022] In an embodiment, the same composition as the first color composition may be provided in the another partial region.

[0023] In an embodiment, the method may further include: drying the first color composition and the second color composition under a vacuum state to form a first preliminary color control layer and a second preliminary color control layer; first baking the first preliminary color control layer and the second preliminary color control layer at a first temperature; and second baking the first preliminary color control layer and the second preliminary color control layer at a second temperature higher than the first temperature.

[0024] In an embodiment, the forming step of the partition wall may further include forming a second portion that partitions each of the second inner region and the third inner region into two partial regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate some exemplary embodiments of the inventive concept and together with the description are used to explain the principles of the inventive concept. In the drawings:

[0026] Figure 1A is a perspective view of a display panel according to an embodiment of the inventive concept;

[0027] Figure 1B is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0028] Figure 2 is a plan view of a display panel according to an embodiment of the inventive concept;

[0029] Figure 3A is a plan view showing a pixel area of ​​a display panel according to an embodiment of the inventive concept;

[0030] Figure 3B is a cross-sectional view showing a pixel region of a display panel according to an embodiment of the inventive concept;

[0031] FIG. 3C to FIG. 3E is a cross-sectional view of a pixel region of an upper display substrate according to an embodiment of the inventive concept;

[0032] Figure 4A is a plan view showing an arrangement relationship between a pixel area and a partition wall according to an embodiment of the inventive concept;

[0033] Figure 4B is a plan view showing an arrangement relationship between a first electrode and a partition wall according to an embodiment of the inventive concept;

[0034] Figure 4Cis a cross-sectional view of a display panel corresponding to a first pixel area according to an embodiment of the inventive concept;

[0035] Figure 5 is a cross-sectional view of a display panel according to an embodiment of the inventive concept;

[0036] Figure 6 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the inventive concept;

[0037] 7A to 7I is a diagram illustrating a method for manufacturing an upper display substrate according to an embodiment of the inventive concept;

[0038] Fig. 8A is a plan view illustrating an arrangement relationship between a pixel area and a partition wall according to an embodiment of the inventive concept; and

[0039] FIG. 8B to FIG. 8C is a diagram illustrating a method for manufacturing an upper display substrate according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0040] Although some specific embodiments are shown in the drawings and described in the specific embodiments of the inventive concept, the present disclosure may have different, modified embodiments. However, this does not limit the present disclosure to specific embodiments, and it will be understood that the present disclosure covers all modifications, equivalents and replacements within the concept and technical scope of the present disclosure.

[0041] The same reference numerals always represent the same elements. In the accompanying drawings, the size and dimensions of each structure may be exaggerated or reduced for ease of description and clarity. It will be understood that although terms such as "first" and "second" are used to describe various elements here, these elements should not be limited by these terms. These terms are used to distinguish one component from other components. For example, without departing from the scope of the claims, a first element referred to as a "first" element in one embodiment may be referred to as a "second" element in another embodiment. Unless otherwise indicated, terms in the singular may include plural forms.

[0042] The meaning of “include” or “comprising” is to list properties, regions, fixed values, steps, processes, elements and / or components, but not to exclude other properties, regions, fixed values, steps, processes, elements and / or components.

[0043] In addition, for ease of description, spatially relative terms such as "below", "below", "above", and "on" may be used here to describe the relationship between an element and / or feature as shown in the drawings and another (other) element and / or feature. However, the terms are relative concepts and are described relative to the directions indicated in the drawings. It will be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations described in the drawings. For example, if the device in the drawings is turned over, the element described as "below" or "beneath" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary term "below" can include both above and below orientations. The device can be oriented otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used here are interpreted accordingly.

[0044] When an element is described as being related to another element such as being “on” another element or layer or being “located on” a different element or layer, this includes both a case where the element is directly on the other element or layer and a case where the element is on the other element or layer via another layer or yet another element. Conversely, when an element is described as being related to another element such as being “directly on” another element or layer or being “directly on” a different element or layer, this means that the element is on the other element or layer with no intervening elements or layers therebetween.

[0045] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the exemplary embodiments of the inventive concepts belong. It will also be understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0047] Figure 1A is a perspective view of a display panel DP according to an embodiment of the inventive concept; Figure 1B is a cross-sectional view of a display panel DP according to an embodiment of the inventive concept; Figure 2 is a plan view of a display panel DP according to an embodiment of the inventive concept.

[0048] Reference Figure 1A to Figure 2The display panel DP may be one of a liquid crystal display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, and an organic light emitting display panel, but is not particularly limited thereto.

[0049] Although not separately shown, the display panel DP may further include a support member of the molding member and may also include a backlight unit according to the kind of the display panel DP.

[0050] The display panel DP may include a first display substrate 100 (or a lower display substrate) and a second display substrate 200 (or an upper display substrate) spaced apart from the first display substrate 100 to face the first display substrate 100. A cell gap (e.g., a predetermined cell gap) may be defined between the first display substrate 100 and the second display substrate 200. The cell gap may be maintained by a sealant SLM, and the first display substrate 100 and the second display substrate 200 are bonded to each other by the sealant SLM. A grayscale display layer for generating an image may be provided between the first display substrate 100 and the second display substrate 200. Depending on the type of the display panel DP, the grayscale display layer may include a liquid crystal layer, an organic light emitting layer, and an electrophoretic layer.

[0051] like Figure 1A As shown in , the display panel DP may display an image through a display surface DP-IS. The display surface DP-IS is parallel to a surface defined by a first direction axis DR1 and a second direction axis DR2. The display surface DP-IS may include a display area DA and a non-display area NDA. The pixel PX is disposed in the display area DA and not in the non-display area NDA. In an embodiment, the non-display area NDA is defined along an edge of the display surface DP-IS. In an embodiment, the display area DA may be surrounded by the non-display area NDA.

[0052] The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) is represented as a third directional axis DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each of the layers or units described below are distinguished by the third directional axis DR3. However, the first directional axis to the third directional axis shown in the present embodiment may be only an example. Here, the first direction to the third direction may be a direction represented by the first directional axis to the third directional axis DR1, DR2, and DR3, and are represented by the same reference numerals, respectively.

[0053] Although the display panel DP having a flat display surface DP-IS is shown in the embodiment of the inventive concept, the embodiment of the inventive concept is not limited thereto. In the embodiment, the display panel DP may include a curved display surface or a stereoscopic display surface. The stereoscopic display surface may include a plurality of display areas representing different directions.

[0054] Figure 2 An arrangement relationship between the signal lines GL1 to GLn and DL1 to DLm and the pixels PX11 to PXnm on a plane is shown. The signal lines GL1 to GLn and DL1 to DLm may include a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm.

[0055] Each of the pixels PX11 to PXnm is connected to a corresponding gate line among a plurality of gate lines GL1 to GLn and a corresponding data line among a plurality of data lines DL1 to DLm, respectively. Each of the pixels PX11 to PXnm may include a pixel driver circuit and a display element. According to the configuration of the pixel driver circuit of the pixels PX11 to PXnm, more kinds of signal lines may be provided on the display panel DP.

[0056] Although the pixels PX11 to PXnm in the form of a matrix are shown as an example, the embodiments of the inventive concept are not limited thereto. In an embodiment, the pixels PX11 to PXnm may be arranged in the form of a pentile. In an embodiment, the pixels PX11 to PXnm may be arranged in the form of a rhombus. The gate driver circuit GDC may be integrated with the display panel DP by an oxide silicon gate driver circuit (OSG) process or an amorphous silicon gate driver circuit (ASG) process.

[0057] Figure 3A is a plan view illustrating pixel areas PXA-R, PXA-G, and PXA-B of a display panel DP according to an embodiment of the inventive concept. Figure 3B is a cross-sectional view illustrating a pixel area PXA-G of a display panel DP according to an embodiment of the inventive concept. FIG. 3C to FIG. 3E is a cross-sectional view of a pixel region of an upper display substrate 200 according to an embodiment of the inventive concept.

[0058] Figure 3A yes Figure 1A 1 is a partial enlarged view of the display area DA of FIG. Three pixel areas PXA-R, PXA-G and PXA-B are mainly shown. Figure 3A The three pixel areas PXA-R, PXA-G, and PXA-B may be repeatedly disposed in the entire display area DA.

[0059] The light blocking area NPXA is disposed around the first to third pixel areas PXA-R, PXA-G, and PXA-B. The light blocking area NPXA sets a boundary between the first to third pixel areas PXA-R, PXA-G, and PXA-B to prevent or substantially prevent colors from being mixed with each other between the first to third pixel areas PXA-R, PXA-G, and PXA-B.

[0060] Although the first pixel region to the third pixel region PXA-R, PXA-G and PXA-B having different surface areas on a plane are illustrated in the embodiment, the embodiment of the inventive concept is not limited thereto. At least two surface areas of the first pixel region to the third pixel region PXA-R, PXA-G and PXA-B may be the same. Although the first pixel region to the third pixel region PXA-R, PXA-G and PXA-B each having a rectangular shape on a plane are shown in the present embodiment, the embodiment of the inventive concept is not limited thereto. The first pixel region to the third pixel region PXA-R, PXA-G and PXA-B may have other polygonal shapes on a plane. Alternatively, each of the first pixel region to the third pixel region PXA-R, PXA-G and PXA-B may be in a rectangular shape with a rounded corner area or a regular polygonal shape with a rounded corner area.

[0061] One of the first to third pixel regions PXA-R, PXA-G, and PXA-B provides a first color light corresponding to the source light, another provides a second color light different from the first color light, and the remaining one provides a third color light different from the first color light and the second color light. In an embodiment, the third pixel region PXA-B provides the first color light. In an embodiment, the first pixel region PXA-R may provide red light, the second pixel region PXA-G may provide green light, and the third pixel region PXA-B may provide blue light.

[0062] A portion of the light incident from the outside into the display area DA (here, referred to as reflected light) is reflected from the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B. The wavelength range and spectrum of the reflected light may be different according to the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B. The surface area of ​​the first pixel area to the third pixel area PXA-R, PXA-G, and PXA-B may be adjusted to control the reflected light reflected by the entire display area DA so that the reflected light does not have a specific color. In an embodiment, the first pixel area PXA-R providing red light may have the largest surface area, and the third pixel area PXA-B providing blue light may have the smallest surface area.

[0063] Figure 3B A cross-sectional view of the display panel DP corresponding to the second pixel area PXA-G is shown. Figure 3B An example of a cross section corresponding to the driving transistor TD and the light emitting element OLED is shown. Figure 3B , an upper display substrate 200 is schematically illustrated. The upper display substrate 200 and the lower display substrate 100 may form a gap (eg, a predetermined gap) GP.

[0064] like Figure 3B As shown in FIG. 1 , the lower display substrate 100 includes: a first base substrate BS1 ; a circuit element layer DP-CL disposed on the first base substrate BS1 ; and a display element layer DP-OLED disposed on the circuit element layer DP-CL.

[0065] The first base substrate BS1 may include a synthetic resin substrate or a glass substrate. The circuit element layer DP-CL includes a circuit element and at least one insulating layer. The circuit element includes a signal line and a driver circuit of a pixel. The circuit element layer DP-CL may be formed by a process of forming an insulating layer, a semiconductor layer and a conductive layer by coating or deposition and a process of patterning the insulating layer, the semiconductor layer and the conductive layer by a photolithography process.

[0066] In an embodiment, the circuit element layer DP-CL may include a buffer layer BFL, a first insulating layer 10, a second insulating layer 20, and a third insulating layer 30. In an embodiment, each of the first insulating layer 10 and the second insulating layer 20 may be an inorganic layer, and the third insulating layer 30 may be an organic layer.

[0067] Figure 3B An example of an arrangement relationship of the semiconductor pattern OSP, the control electrode GE, the input electrode DE, and the output electrode SE constituting the drive transistor TD is shown. A first through hole CH1, a second through hole CH2, and a third through hole CH3 are exemplarily shown.

[0068] The display element layer DP-OLED includes a light emitting element or a light emitting diode OLED. The light emitting element OLED can generate the above-mentioned source light. The light emitting element OLED includes a first electrode, a second electrode and a light emitting layer arranged between the first electrode and the second electrode. In an embodiment, the display element layer DP-OLED may include an organic light emitting diode as a light emitting diode. The display element layer DP-OLED includes a pixel defining layer PDL. For example, the pixel defining layer PDL may be an organic layer.

[0069] The first electrode AE ​​is disposed on the intermediate organic layer 30. The first electrode AE ​​is connected to the output electrode SE through a third through hole CH3 passing through the third insulating layer or the intermediate organic layer 30. An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE. In the current embodiment, the light emitting region PXA-G may be defined to correspond to a portion of the first electrode AE ​​exposed through the opening OP.

[0070] In an embodiment, the hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be commonly disposed in the pixel region PXA-G and the light blocking region NPXA. In an embodiment, the hole control layer HCL, the light emitting layer EML, and the electron control layer ECL may be commonly disposed in the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0071] The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. The light emitting layer EML may generate blue light. The blue light may include a wavelength of about 410nm to about 480nm. The emission spectrum of the blue light may have a maximum peak within a wavelength of about 440nm to about 460nm. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer.

[0072] The second electrode CE is disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed in the first pixel region to the third pixel region PXA-R, PXA-G, and PXA-B. Therefore, the second electrode CE may have a surface area larger than that of the first electrode AE. A cover layer CL protecting the second electrode CE may also be disposed on the second electrode CE. The cover layer CL may include an organic material or an inorganic material.

[0073] The lower display substrate 100 may include Figure 3A The first display element, the second display element, and the third display element corresponding to the first pixel region to the third pixel region PXA-R, PXA-G, and PXA-B. The first display element, the second display element, and the third display element may have the same stacked structure as each other, and may also have the same stacked structure as each other. Figure 3B The stacked structure of the light-emitting element OLED is the same as the stacked structure.

[0074] Reference Figure 3A and Figure 3B , the first display element, the second display element, and the third display element have surface areas corresponding to the first to third pixel regions PXA-R, PXA-G, and PXA-B on a plane, and thus may have surface areas different from each other. Specifically, the first electrode AE ​​of the first display element may have the largest surface area, and the first electrode AE ​​of the third display element may have the smallest surface area.

[0075] like Figure 3C As shown in FIG. 1 , the upper display substrate 200 may include: a second base substrate BS2; a black matrix BM disposed on the bottom surface of the second base substrate BS2; a color filter CF-G; a partition wall WP; and a color conversion layer CCF-G. In an embodiment, each of the color filter CF-G and the color conversion layer CCF-G may be a color control layer that converts the characteristics of incident light.

[0076] The second base substrate BS2 may include a synthetic resin substrate or a glass substrate. The black matrix BM is disposed on the bottom surface of the second base substrate BS2. The black matrix BM is disposed in the light blocking area NPXA. Figure 3A Openings corresponding to the first to third pixel regions PXA-R, PXA-G, and PXA-B are defined in the black matrix BM. Figure 3C An opening BM-OP is shown in FIG. The opening BM-OP can be connected to Figure 3B The opening BM-OP may correspond to the first electrode AE. Figure 3B Corresponding to the opening OP of the pixel defining layer PDL.

[0077] The color filter CF-G is disposed on the bottom surface of the second base substrate BS2. The color filter CF-G includes a base resin and a dye and / or pigment dispersed in the base resin. The color filter CF-G overlaps the second pixel area PXA-G. The edge area of ​​the color filter CF-G may overlap the light blocking area NPXA. A portion of the black matrix BM may be disposed between the color filter CF-G and the bottom surface of the second base substrate BS2.

[0078] Reference FIG. 3A to FIG. 3C , the first to third color filters are arranged to correspond to the first to third pixel regions PXA-R, PXA-G, and PXA-B. The first to third color filters may include dyes and / or pigments that absorb different wavelengths from each other. In an embodiment, the first color filter may be a red color filter, the second color filter may be a green color filter, and the third color filter may be a blue color filter. The second color filter may be Figure 3C The first to third color filters can reduce the reflection of external light. Each of the first to third color filters transmits light having a specific wavelength range and blocks light having a corresponding wavelength range.

[0079] The first encapsulation layer ENL1 is disposed on the color filter CF-G. The first encapsulation layer ENL1 seals the color filter CF-G. The first encapsulation layer ENL1 may be commonly disposed on the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0080] The first encapsulation layer ENL1 may include an inorganic layer. In an embodiment, the first encapsulation layer ENL1 may include one of silicon oxide, silicon nitride, and silicon oxynitride. The first encapsulation layer ENL1 may further include an organic layer providing a flat bottom surface.

[0081] The partition wall WP is disposed on the bottom surface of the first encapsulation layer ENL1. The partition wall WP overlaps the light blocking area NPXA. The partition wall WP defines first to third inner areas (or inner spaces) corresponding to the first to third pixel areas PXA-R, PXA-G, and PXA-B. Figure 3C An inner area WP-IG is shown in FIG.

[0082] In the process of forming the color conversion layer CCF-G, the partition wall WP prevents or substantially prevents different compositions from mixing between the first to third pixel regions PXA-R, PXA-G, and PXA-B. Further description of this function will be described with reference to the method for manufacturing a display panel.

[0083] The color conversion layer CCF-G is disposed inside the partition wall WP. In an embodiment, the color conversion layer CCF-G can absorb Figure 3B The color conversion layer CCF-G can transmit and scatter the first color light.

[0084] In an embodiment, the color conversion layer CCF-G may include a base resin and quantum dots mixed or dispersed in the base resin. The base resin may be a medium in which the quantum dots are dispersed. Typically, the base resin may include any of various resin compositions referred to as binders. However, the embodiments of the inventive concept are not limited thereto. In this specification, a medium capable of dispersing quantum dots may be referred to as a base resin (BR), regardless of its name, other functions attached, constituent materials, etc. The base resin may be a polymer resin. For example, the base resin may include any of an acrylic resin, a urethane resin, a silicone resin, and an epoxy resin. The base resin may be a transparent resin.

[0085] Quantum dots can be particles that convert the wavelength of incident light. Each quantum dot can be a material with a crystal structure of a few nanometers in size. Quantum dots can be composed of hundreds to thousands of atoms to provide a quantum confinement effect in which the energy band gap is increased due to the small size. When light of a certain wavelength with energy greater than the energy of the band gap is incident on the quantum dot, the quantum dot can absorb the light and is therefore in an excited state to emit light with a specific wavelength, thereby becoming a ground state. The emitted light has a value corresponding to the band gap. When the size and composition of the quantum dots are adjusted, the luminescence characteristics caused by the quantum confinement effect can be adjusted.

[0086] In an embodiment, the quantum dots may be selected from Group II-VI compounds, Group I-III-VI compounds, Group III-V compounds, Group IV-VI compounds, Group IV elements, Group IV compounds, and combinations thereof.

[0087] The II-VI compounds can be selected from binary element compounds, ternary element compounds and quaternary element compounds, the binary element compound being selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and combinations thereof, and the ternary element compound being selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZn S, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and combinations thereof, the quaternary element compound is selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and combinations thereof. The I-III-VI group compound can be selected from a ternary element compound or a quaternary element compound, the ternary element compound is selected from the group consisting of AgInS 2 、CuInS 2 、AgGaS 2 、CuGaS 2 and mixtures thereof, the quaternary element compound is selected from the group consisting of AgInGaS 2 and CuInGaS 2 Select in.

[0088] The III-V compound may be selected from a binary element compound, a ternary element compound, and a quaternary element compound, wherein the binary element compound is selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and combinations thereof, the ternary element compound is selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and combinations thereof, and the quaternary element compound is selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and combinations thereof. The III-V compound may also include a Group II metal. For example, InZnP or the like may be selected as the III-II-V group compound.

[0089] The IV-VI group compound may be selected from a binary element compound, a ternary element compound and a quaternary element compound, the binary element compound being selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and combinations thereof, the ternary element compound being selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and combinations thereof, and the quaternary element compound being selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and combinations thereof. The IV group element may be selected from the group consisting of Si, Ge and combinations thereof. The IV group compound may be a binary element compound selected from the group consisting of SiC, SiGe and combinations thereof.

[0090] Here, the binary element compound, the ternary element compound, and the quaternary element compound may exist in the particle at a uniform concentration, or in a state in which the concentration distribution is partitioned into a locally different state.

[0091] In an embodiment, the quantum dot may have a core-shell structure including a shell surrounding a core. Alternatively, the quantum dot may have a core-shell structure in which one quantum dot surrounds another quantum dot. In an embodiment, the interface between the core and the shell may have a concentration gradient in which the element present in the shell has a concentration that gradually decreases toward the center.

[0092] Each quantum dot may have a particle size of nanometers. In an embodiment, the quantum dot may have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less (about 40 nm or less in one embodiment, about 30 nm or less in one embodiment). In this range, color purity and color reproducibility may be improved. In addition, light emitted by the quantum dots may be emitted in all directions to improve the optical viewing angle.

[0093] In addition, each quantum dot can have a shape commonly used in the art, and is not particularly limited in shape. For example, the quantum dot can have a spherical shape, a pyramid shape, a multi-arm shape, a cubic nanoparticle shape, a nanotube shape, a nanowire shape, a nanofiber shape, a nanoplate particle shape, etc.

[0094] Reference FIG. 3A to FIG. 3C , the first to third color conversion layers are arranged to correspond to the first to third pixel regions PXA-R, PXA-G, and PXA-B. The first color conversion layer absorbs blue light to generate red light, and the second color conversion layer absorbs blue light to generate green light. That is, the first color conversion layer and the second color conversion layer may include quantum dots different from each other. The third color conversion layer may transmit blue light. The second color conversion layer may be Figure 3C The first to third color conversion layers may further include scattering particles. In an embodiment, the scattering particles may be titanium oxide (TiO 2 ) or silica-based nanoparticles.

[0095] The second encapsulation layer ENL2 is disposed on the partition wall WP and the color conversion layer CCF-G. The second encapsulation layer ENL2 seals the partition wall WP and the color conversion layer CCF-G. The second encapsulation layer ENL2 may be commonly disposed on the first to third pixel regions PXA-R, PXA-G, and PXA-B.

[0096] In an embodiment, the second encapsulation layer ENL2 may include an inorganic layer in contact with the partition wall WP and the color conversion layer CCF-G. In an embodiment, the inorganic layer may include one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second encapsulation layer ENL2 may further include an organic layer disposed on the inorganic layer. The organic layer may provide a flat bottom surface.

[0097] Figure 3D and Figure 3E Shows that with Figure 3C The stacking structure of the upper display substrate 200 is an example of the upper display substrate 200 with different stacking structures.

[0098] like Figure 3D As shown in FIG. , the partition wall WP may be disposed on the black matrix BM. Figure 3C Compared with the upper display substrate 200 , the color filter CF-G and the first encapsulation layer ENL1 may be omitted.

[0099] like Figure 3E As shown in FIG. 1 , a partition wall WP-S disposed on the black matrix BM may be further provided. The color filter CF-G of the partition wall WP-S may have substantially the same function as that of the color conversion layer CCF-G of the partition wall WP described above. Although not separately shown, in an embodiment of the inventive concept, the color filter CF-G may be omitted. Figure 3E The partition wall WP.

[0100] Figure 4A is a plan view illustrating an arrangement relationship between pixel regions PXA-R, PXA-G, and PXA-B and partition walls WP1 and WP2 according to an embodiment of the inventive concept. Figure 4B is a plan view showing the arrangement relationship between the first electrode AE-R and the partition walls WP1 and WP2. Figure 4C is a cross-sectional view of the display panel DP corresponding to the first pixel region PXA-R.

[0101] According to an embodiment, the partition wall WP includes a first partition wall WP1 and a second partition wall WP2 extending from the first partition wall WP1. In an embodiment, the first partition wall WP1 and the second partition wall WP2 may be formed by the same process and may be defined as a first portion and a second portion of the partition wall WP.

[0102] The first partition wall WP1 overlaps the light blocking area NPXA. The first partition wall WP1 defines a first inner area WP-IR, a second inner area WP-IG, and a third inner area WP-IB corresponding to the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B. In an embodiment, the first partition wall WP1 may form a closed line for each of the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B.

[0103] The second partition wall WP2 overlaps with at least one of the first pixel area PXA-R, the second pixel area PXA-G, and the third pixel area PXA-B, and at least one of the first internal area WP-IR, the second internal area WP-IG, and the third internal area WP-IB can be separated into partial areas.

[0104] According to an embodiment, the second partition wall WP2 may partition the first inner region WP-IR into two partial regions WP-IR1 and WP-IR2. In an embodiment, the second partition wall WP2 extends from one side of the first partition wall WP1 to the other side of the first partition wall WP1 in the second direction DR2.

[0105] In an embodiment, the second partition wall WP2 may overlap the widest first pixel region PXA-R to compensate for the reduction in brightness caused by the second partition wall WP2 by increasing the driving voltage by a small amount. This may be because the first pixel region PXA-R has a larger light receiving area than the light receiving areas of the other pixel regions PXA-G and PXA-B.

[0106] Figure 4B A first electrode AE-R overlapping the first pixel region PXA-R is shown; Figure 4C Shown with Figure 3B The corresponding lower display substrate 100 and Figure 3C The second partition wall WP2 overlaps the first electrode AE-R. The second partition wall WP2 may extend in the second direction DR2. In an embodiment, the second partition wall WP2 may be disposed at a position where the first electrode AE-R is bisected (bisected or substantially bisected) by it in the first direction DR1. In an embodiment, the second partition wall WP2 may be disposed on an area overlapping a range of about 45% to about 55% of the width of the first electrode AE-R in the first direction DR1.

[0107] The two partial regions WP-IR1 and WP-IR2 may have substantially the same surface area on a plane. The plane area may be calculated as the surface area of ​​a region defined by the inner edges of the first partition wall WP1 and the second partition wall WP2.

[0108] The color conversion layer CCF-R made of the same material is disposed in the two partial regions WP-IR1 and WP-IR2, respectively. In an embodiment, the color conversion layer CCF-R may be a quantum dot that absorbs blue light to generate red light.

[0109] Figure 5 is a cross-sectional view of a display panel DP according to an embodiment of the inventive concept. Figures 1A to 4C The components described are described in further detail.

[0110] and Figure 4C similar, Figure 5 A cross section corresponding to one pixel region PXA-G is shown. In this embodiment, a liquid crystal display panel DP is shown as an example. A pixel of the liquid crystal display panel DP may include a transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst in an equivalent circuit.

[0111] The liquid crystal display panel DP includes a first display substrate 100, a second display substrate 200, and a liquid crystal layer LCL disposed between the first display substrate 100 and the second display substrate 200. A spacer CS overlapping the light blocking area NPXA may be disposed between the first display substrate 100 and the second display substrate 200. In an embodiment, the liquid crystal display panel DP includes a first polarizer layer PL1 and a second polarizer layer PL2. The first polarizer layer PL1 may be disposed under the first display substrate 100, and the second polarizer layer PL2 may constitute the second display substrate 200. In an embodiment, the second polarizer layer PL2 may include a wire grid.

[0112] The control electrode GE and the storage line STL are disposed on one surface of the first base substrate BS1. The first base substrate BS1 may be a glass substrate or a plastic substrate. A first insulating layer 10 covering the control electrode GE and the storage line STL is disposed on one surface of the first base substrate BS1. The first insulating layer 10 may include at least one of an inorganic material and an organic material. An active portion AL overlapping the control electrode GE is disposed on the first insulating layer 10. The active portion AL may include a semiconductor layer SCL and an ohmic contact layer OCL. The semiconductor layer SCL is disposed on the first insulating layer 10, and the ohmic contact layer OCL is disposed on the semiconductor layer SCL.

[0113] The semiconductor layer SCL may include amorphous silicon or polycrystalline silicon. In addition, the semiconductor layer SCL may include a metal oxide semiconductor. The ohmic contact layer OCL may include a dopant doped at a higher density than that of the semiconductor layer SCL. The ohmic contact layer OCL may include two parts separated from each other. In an embodiment of the inventive concept, the ohmic contact layer OCL may have an integral shape.

[0114] The input electrode DE and the output electrode SE are disposed on the active portion AL. The input electrode DE and the output electrode SE are disposed to be separated from each other. The second insulating layer 20 covering the active portion AL, the input electrode DE, and the output electrode SE is disposed on the first insulating layer 10. The third insulating layer 30 is disposed on the second insulating layer 20. Each of the second insulating layer 20 and the third insulating layer 30 may include at least one of an inorganic material and an organic material. The third insulating layer 30 is disposed on the second insulating layer 20. The third insulating layer 30 may be an organic layer that provides a planarized surface. The fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 may be an inorganic layer.

[0115] like Figure 5As shown in FIG. 1 , the pixel electrode PE is disposed on the fourth insulating layer 40. The pixel electrode PE is connected to the output electrode SE through a contact hole CH10 passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. An alignment layer (not shown) covering the pixel electrode PE may be disposed on the fourth insulating layer 40.

[0116] The second base substrate BS2 may be a glass substrate or a plastic substrate. An intermediate layer IL, a second polarizer layer PL2, and a common electrode CE are disposed on the bottom surface of the second base substrate BS2. The liquid crystal capacitor Clc may be charged or discharged so that the liquid crystal layer LCL operates. The first color light provided from the backlight unit may be selectively provided to the intermediate layer IL through the first polarizer layer PL1, the liquid crystal layer LCL, and the second polarizer layer PL2.

[0117] Although the intermediate layer IL is schematically shown in the present embodiment, the intermediate layer IL may have a FIG. 3C to FIG. 3E The stacked structure described above is disposed on the bottom surface of the second base substrate BS2. For example, the intermediate layer IL may have a structure as shown in FIG. Figure 3C The stacked structure from the black matrix BM to the second encapsulation layer ENL2 is shown in FIG.

[0118] Reference FIG. 4A to FIG. 4C The described configurations of the first to third pixel regions PXA-R, PXA-G, and PXA-B may also be equally applied to the second display substrate 200 of the liquid crystal display panel DP.

[0119] exist Figure 5 The cross-section shown in may be only an example. Figure 5 A vertical alignment (VA) mode liquid crystal display panel is exemplarily described in the specification, but according to an embodiment of the inventive concept, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, a plane line switching (PLS) mode, a super vertical alignment (SVA) mode, or a surface stabilized vertical alignment (SS-VA) mode liquid crystal display panel may be applied.

[0120] Figure 6 is a flowchart illustrating a method for manufacturing a display panel DP according to an embodiment of the inventive concept; 7A to 7I 2 is a diagram showing a method for manufacturing an upper display substrate 200 according to an embodiment of the inventive concept. Figures 1A to 5 The components described are the same as those described in further detail.

[0121] Reference Figure 6 , manufacturing a first display substrate including first to third display elements (S10). The first display substrate may be a reference Figures 1A to 5The lower display substrate 100 described above is an array substrate. The first display substrate can be manufactured by a known method. FIG. 3C to FIG. 3E The organic light emitting display panel DP shown in FIG. 1 may form an organic light emitting diode as a display element. Figure 5 The liquid crystal display panel DP may form a pixel electrode PE as a display element.

[0122] In addition, a second display substrate is manufactured (S20). However, the order of manufacturing the first display substrate and the second display substrate is not particularly limited.

[0123] Subsequently, the first display substrate and the second display substrate are bonded to each other (S30). Figure 1A ), and then, the first display substrate and the second display substrate may be bonded to each other. After being bonded, the preliminary sealant may be cured. In order to manufacture a liquid crystal display panel, a liquid crystal composition may be further provided to a display area DA (see FIG. 1 ) of the first display substrate and the second display substrate. Figure 1A According to an embodiment, after the first display substrate and the second display substrate are combined with each other, the liquid crystal composition may be injected into the gap.

[0124] Will refer to 7A to 7I A method for manufacturing the second display substrate 200 is described in further detail. 7A to 7I Shown with Figure 3C The corresponding cross section.

[0125] like Fig. 7A As shown in , a black matrix BM is formed on the second base substrate BS2. In an embodiment of the inventive concept, an organic material having a specific color may be printed on a portion of an area of ​​the second base substrate BS2 to form the black matrix BM. In an embodiment of the inventive concept, an organic layer having a specific color may be formed on one surface of the second base substrate BS2, and then exposed and developed to form the black matrix BM.

[0126] like Figure 7B As shown in FIG. 1 , a color filter CF-G is formed on the second base substrate BS2. In an embodiment of the inventive concept, an organic layer having a specific color may be formed on one surface of the second base substrate BS2, and then exposed and developed to form the color filter CF-G. In order to form three color filters, each of the process of forming the organic layer and the process of patterning the organic layer may be performed three times.

[0127] like Figure 7CAs shown in FIG. 1 , a first encapsulation layer ENL1 is formed on the second base substrate BS2. The first encapsulation layer ENL1 is commonly formed in the light blocking area NPXA and the first to third pixel areas PXA-R, PXA-G, and PXA-B (see FIG. 1 ). Figure 4A ). An inorganic material may be deposited to form an inorganic encapsulation layer. An organic material may be deposited or applied to form an organic encapsulation layer.

[0128] like Fig.7D As shown in , a partition wall WP is formed on the first encapsulation layer ENL1. An organic layer is formed on the first encapsulation layer ENL1, and then exposed and developed so that the organic layer is patterned. A first inner region WP-IR, a second inner region WP-IG, and a third inner region WP-IB are defined.

[0129] Can be formed simultaneously Figure 4A The first partition wall WP1 and the second partition wall WP2 are shown in FIG. Therefore, two partial regions WP-IR1 and WP-IR2 of the first inner region WP-IR are defined.

[0130] like Fig. 7E and Figure 7F As shown in FIG. 1 , a color control layer is formed in a portion of the first inner region WP-IR, the second inner region WP-IG, and the third inner region WP-IB. In an embodiment, the color control layer may be a color conversion layer. Fig. 7E and Figure 7F Two pairs of first to third pixel regions PXA-R, PXA-G, and PXA-B arranged along the first direction DR1 are shown.

[0131] like Fig. 7E and Figure 7FAs shown in, a first color composition CCF-S1 is provided in a first partial region WP-IR1 of a first inner region WP-IR, and a second color composition CCF-S2 different from the first color composition CCF-S1 is provided in a second inner region WP-IG. In an embodiment, the color composition may be provided in an inkjet manner. The first color composition CCF-S1 and the second color composition CCF-S2 may be provided without overflowing over the first partition wall WP1 and the second partition wall WP2. Even if the first color composition CCF-S1 and the second color composition CCF-S2 may be provided in large quantities relative to the volume of the corresponding region or space, the first color composition CCF-S1 and the second color composition CCF-S2 may not overflow due to surface tension. Although a large amount of the first color composition CCF-S1 and the second color composition CCF-S2 can be provided, since the second partial area WP-IR2 of the first internal area WP-IR is arranged between the first partial area WP-IR1 of the first internal area WP-IR and the second internal area WP-IG, the mixing of the first color composition CCF-S1 and the second color composition CCF-S2 caused by the contact between the first color composition CCF-S1 and the second color composition CCF-S2 can be prevented or substantially prevented.

[0132] Each of the first color composition CCF-S1 and the second color composition CCF-S2 may include a solvent and a solid dispersed in the solvent. In an embodiment, the solid may be included in a range of about 20wt% to about 30wt% based on the color composition. The type of solvent is not specifically limited, and various known solvents may be used. For example, the solvent may be any one of ketones (such as acetone, methyl ethyl ketone and cyclohexanone), acetates (such as ethyl acetate, butyl acetate, cellosolve acetate, propylene glycol monomethyl ether acetate and carbitol acetate), cellosolves (such as cellosolves and butyl carbitol), aromatic hydrocarbons (such as solvent naphtha, toluene and xylene), amide solvents (such as dimethylformamide, dimethylacetamide and N-methylpyrrolidone), etc. In an embodiment, the two solvents may be used in combination.

[0133] In an embodiment, the solid includes a matrix resin and quantum dots. The matrix resin may include epoxy polymers and / or monomers. The solid may also include scattering particles. The first color composition CCF-S1 and

[0134] The second color composition CCF-S2 includes quantum dots that are different from each other.

[0135] The first color composition CCF-S1 and the second color composition CCF-S2 may be dried in a vacuum state to form a first preliminary color control layer and a second preliminary color control layer. When the chamber in which the first color composition CCF-S1 and the second color composition CCF-S2 are disposed becomes a vacuum state, the solvent of the composition is removed.

[0136] The first preliminary color control layer and the second preliminary color control layer may be baked at a first temperature (first baking process). In an embodiment, the first temperature may be approximately 90° C. to 130° C. The first preliminary color control layer and the second preliminary color control layer may be baked at a second temperature higher than the first temperature (second baking process). In an embodiment, the second temperature may be approximately 180° C. to 240° C. A two-stage baking process may be performed to form a uniformly dried color conversion layer.

[0137] like Figure 7G and Figure 7H As shown in FIG. 1 , a color conversion layer is formed in the remaining portions of the first inner region WP-IR, the second inner region WP-IG, and the third inner region WP-IB. Figure 7G and Figure 7H As shown in the figure, a first color composition CCF-S1 is provided in a second partial region WP-IR2 of the first inner region WP-IR, and a third color composition CCF-S3 different from the first color composition CCF-S1 and the second color composition CCF-S2 is provided in a third inner region WP-IB. The first color composition CCF-S1 and the third color composition CCF-S3 are not mixed with each other for the same reason as the first color composition CCF-S1 and the second color composition CCF-S2 are not mixed with each other.

[0138] The third color composition CCF-S3 includes a solvent and a solid dispersed in the solvent. In an embodiment, the solid may be included in a range of about 20wt% to about 30wt% based on the color composition. The solid may include a matrix resin and scattering particles. As described above, a vacuum drying and a two-stage baking process may be performed to form a uniformly dried color conversion layer.

[0139] like Fig.7I As shown in FIG. 1 , a second encapsulation layer ENL2 is formed on the partition wall WP. An inorganic material may be deposited to form an inorganic encapsulation layer. An organic material may be deposited or applied to form an organic encapsulation layer. 7A to 7I As shown in , according to an embodiment, three color control layers can be formed by a two-stage inkjet process. Therefore, the time spent on manufacturing a display panel can be reduced.

[0140] In the embodiment, although not shown separately, Figure 3D On the display substrate 200, when 7A to 7I When compared with the manufacturing method of , the process of forming the color filter CF-G and the first encapsulation layer ENL1 may be omitted. The partition wall WP may be directly formed on the black matrix BM. The subsequent processes may be the same as described above.

[0141] When with 7A to 7I When compared with the manufacturing method, Figure 3E The upper display substrate 200 further includes a process for forming a partition wall WP-S. The process for forming the partition wall WP-S may be the same as that described in reference to Fig.7D The method for manufacturing the partition wall WP is described to be the same. In the embodiment, the partition wall WP-S and the partition wall WP include the same material and have the same structure.

[0142] The color filter may be formed in the inner region of the partition wall WP-S. The color filter may include a first color filter disposed in two partial regions defined by the partition wall WP-S, and second and third color filters disposed in the inner region defined by the partition wall WP-S.

[0143] The method for forming the first to third color filters may be the same as that for manufacturing the reference FIG. 7E to FIG. 7H The method of the color conversion layers CCF-R, CCF-G and CCF-B described is the same. Each composition used to form the first color filter to the third color filter includes a solvent and a solid dispersed in the solvent. The solid may include a base resin and a dye and / or a pigment.

[0144] In an embodiment of the present invention, the second display substrate 200 may be omitted. The display panel DP may include one base substrate, and the one base substrate may be Figure 3B The first base substrate BS1 shown in FIG. The thin film encapsulation layer may cover Figure 3B The display element layer DP-OLED in the thin film encapsulation layer includes at least one inorganic layer. The thin film encapsulation layer may include at least one inorganic layer and at least one organic layer.

[0145] Another insulating layer may be provided on the thin film encapsulation layer. The thin film encapsulation layer or the other insulating layer provides a substrate surface. A partition wall WP is provided on the substrate surface. And a color conversion layer CCF-G is formed inside the partition wall WP. A method for manufacturing the color conversion layer CCF-G is similar to FIG. 7E to FIG. 7H The manufacturing method is the same. FIG. 7E to FIG. 7H The first encapsulation layer ENL1 shown in FIG. 5 may be the above-mentioned thin film encapsulation layer or another insulating layer providing the substrate surface in this embodiment.

[0146] An additional encapsulation layer may be formed on the color conversion layer CCF-G. A color filter CF-G and a black matrix BM are formed on the additional encapsulation layer. An insulating layer covering the black matrix BM and the color filter CF-G may be further formed to provide a flat surface.

[0147] Fig. 8A is a plan view illustrating an arrangement relationship between pixel regions PXA-R, PXA-G, and PXA-B and partition walls WP1 and WP2 according to an embodiment of the inventive concept. FIG. 8B to FIG. 8C is a diagram illustrating a method for manufacturing an upper display substrate 200 according to an embodiment of the inventive concept.

[0148] Fig. 8A An example of pixel areas PXA-R, PXA-G, and PXA-B having the same surface area is shown. The second partition wall WP2 may partition each of the first inner area WP-IR, the second inner area WP-IG, and the third inner area WP-IB into two partial areas WP-IR1, WP-IR2, WP-IG1, WP-IG2, WP-IB1, and WP-IB2.

[0149] In an embodiment, the method for manufacturing the upper display substrate 200 is similar to that of the reference 7A to 7I The methods described are very similar. Figure 8B and Figure 8C As shown in , after the color control layer is formed in each of the partial areas of the first internal area WP-IR, the second internal area WP-IG and the third internal area WP-IB, the color control layer is formed in each of the remaining internal areas WP-IR2, WP-IG2 and WP-IB2.

[0150] like Figure 8B As shown in the figure, a first color composition CCF-S1 is provided in a first partial region WP-IR1 of a first inner region WP-IR, a second color composition CCF-S2 is provided in a first partial region WP-IG1 of a second inner region WP-IG, and a third color composition CCF-S3 is provided in a first partial region WP-IB1 of a third inner region WP-IB. A vacuum drying and two-stage baking process may be performed to form uniformly dried three color conversion layers.

[0151] Although the first color composition CCF-S1, the second color composition CCF-S2 and the third color composition CCF-S3 can be provided in large quantities relative to the volumes of the partial regions WP-IR1, WP-IG1 and WP-IB1, since the empty second partial regions WP-IR2, WP-IG2 and WP-IB2 are arranged between the first partial regions WP-IR1, WP-IG1 and WP-IB1, the first color composition CCF-S1, the second color composition CCF-S2 and the third color composition CCF-S3 can be prevented or substantially prevented from mixing with each other due to the contact between them.

[0152] like Figure 8C As shown in the figure, a first color composition CCF-S1 is provided in the second partial region WP-IR2 of the first inner region WP-IR, a second color composition CCF-S2 is provided in the second partial region WP-IG2 of the second inner region WP-IG, and a third color composition CCF-S3 is provided in the second partial region WP-IB2 of the third inner region WP-IB. A vacuum drying and two-stage baking process can be performed to form uniformly dried three color conversion layers.

[0153] like FIG. 8A to FIG. 8C As shown in , according to an embodiment, three color control layers can be formed by a two-stage inkjet process. Therefore, the time spent on manufacturing a display panel can be reduced.

[0154] As described above, the second partition wall can prevent or substantially prevent the color composition from being mixed between the pixel regions adjacent to each other during the manufacturing process. Therefore, the defect rate of the display panel can be reduced.

[0155] The three color control layers can be formed by a two-stage inkjet process, thereby reducing the manufacturing time of the display panel.

[0156] It will be clear to those skilled in the art that various modifications and changes can be made in the inventive concept. Therefore, it is intended that the present disclosure covers all modifications and changes of the present invention within the scope of the claims and their equivalents.

[0157] Therefore, the protection scope of the inventive concept will be determined by the technical scope of the claims.

Claims

1. A display panel, comprising: an upper display substrate, comprising a first pixel region, a second pixel region, and a third pixel region and a light blocking region around the first pixel region, the second pixel region, and the third pixel region; as well as a lower display substrate, comprising a first display element, a second display element and a third display element corresponding to the first pixel region, the second pixel region and the third pixel region, Wherein, the upper display substrate comprises: base substrate; a first partition wall located on the base substrate, overlapping the light blocking region, and configured to define a first inner region, a second inner region, and a third inner region corresponding to the first pixel region, the second pixel region, and the third pixel region; A first color control layer, a second color control layer, and a third color control layer are located in the first inner region, the second inner region, and the third inner region, respectively; and A second partition wall overlaps with at least one of the first pixel area, the second pixel area and the third pixel area, and is constructed to separate an internal area corresponding to the at least one pixel area into partial areas, so that the color control layer located in the partial area is divided into two parts by the second partition wall.

2. The display panel according to claim 1, wherein: Each of the first display element, the second display element, and the third display element includes a first electrode, a second electrode, and a light emitting layer located between the first electrode and the second electrode, and The light emitting layers of the first display element, the second display element, and the third display element have an integral shape to generate blue light.

3. The display panel according to claim 2, wherein: The first color control layer includes first quantum dots to convert the blue light into red light, The second color control layer includes second quantum dots to convert the blue light into green light, and The third color control layer is configured to transmit the blue light.

4. The display panel according to claim 3, wherein: The inner region corresponding to the at least one pixel region is the first inner region, and The second partition wall overlaps the first electrode of the first display element.

5. The display panel according to claim 4, wherein: The second partition wall extends along a first direction, and The second partition wall is arranged so that the first electrode of the first display element is bisected in a second direction perpendicular to the first direction.

6. The display panel according to claim 4, wherein: The partial regions have the same surface area on a plane.

7. The display panel according to claim 3, wherein: The first pixel region has a surface area larger than a surface area of ​​each of the second pixel region and the third pixel region on a plane.

8. The display panel according to claim 3, wherein: The upper display substrate further comprises: a black matrix, located on the base substrate to overlap the light blocking area; A red color filter, a green color filter and a blue color filter are located on the base substrate to correspond to the first pixel area, the second pixel area and the third pixel area respectively; a first encapsulation layer covering the red color filter, the green color filter and the blue color filter; and The second encapsulation layer covers the first partition wall, the second partition wall, the first color control layer, the second color control layer, and the third color control layer.

9. The display panel according to claim 3, wherein: The second partition wall partitions each of the first inner region, the second inner region, and the third inner region into the partial regions. 10 . The display panel of claim 1 , further comprising a liquid crystal layer between the upper display substrate and the lower display substrate.

11. The display panel according to claim 1, wherein: The first color control layer includes a red color filter, The second color control layer includes a green color filter, and The third color control layer includes a blue color filter.

12. A display panel, comprising: a lower display substrate including a first electrode, a second electrode having a surface area larger than that of the first electrode, and a light emitting layer located between the first electrode and the second electrode; as well as an upper display substrate, separated from the lower display substrate, Wherein, the upper display substrate comprises: base substrate; a black matrix, located on the base substrate, and an opening corresponding to the first electrode is defined in the black matrix; a partition wall including a first portion overlapping the black matrix on a plane and having a closed line shape, and a second portion overlapping the opening and extending from one side of the first portion to the other side of the first portion; and The color control layer includes first quantum dots and second quantum dots respectively located in two separated regions defined by the first portion and the second portion, and is separated into two portions by the second portion.

13. The display panel according to claim 12, wherein: The first quantum dot and the second quantum dot include the same material.

14. The display panel according to claim 12, wherein: The second portion bisects the first electrode on the plane.

15. A method for manufacturing a display panel, the method comprising the following steps: forming a first display substrate including a first display element, a second display element, and a third display element; forming a second display substrate including first, second and third pixel regions corresponding to the first, second and third display elements and light blocking regions around the first, second and third pixel regions; as well as bonding the first display substrate to the second display substrate, Wherein, the step of forming the second display substrate comprises the following steps: forming a black matrix on the base substrate to overlap the light blocking area; forming a partition wall including a first portion and a second portion on the base substrate, the first portion defining a first inner region, a second inner region, and a third inner region corresponding to the first pixel region, the second pixel region, and the third pixel region, the second portion extending from the first portion, overlapping the first pixel region, and dividing the first inner region into two partial regions; forming a first portion of a first color control layer in one of the two partial regions, and forming a second color control layer in the second inner region; and A second portion of the first color control layer is formed in the other partial region of the two partial regions, and a third color control layer is formed in the third inner region.

16. The method of claim 15, wherein: A first color composition is provided in the one partial region, and A second color composition different from the first color composition is provided in the second interior region.

17. The method of claim 16, wherein: The first color composition includes a solvent and a solid dispersed in the solvent. The solid content is in the range of 20 wt % to 30 wt % based on the first color composition, and The solid material includes a matrix resin and quantum dots.

18. The method of claim 16, wherein: The same composition as the first color composition is provided in the another partial region.

19. The method according to claim 16, further comprising the steps of: Drying the first color composition and the second color composition under vacuum to form a first preliminary color control layer and a second preliminary color control layer; first baking the first preliminary color control layer and the second preliminary color control layer at a first temperature; and The first preliminary color control layer and the second preliminary color control layer are second-baked at a second temperature greater than the first temperature.

20. The method of claim 16, wherein: The forming step of the partition wall further includes forming a second portion that partitions each of the second inner region and the third inner region into two partial regions.

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