Semiconductor Devices

Abstract

A semiconductor device is provided, comprising: a substrate; an active region protruding upward from the substrate; a plurality of active fins protruding upward from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being arranged in a second direction parallel to the upper surface of the substrate and intersecting the first direction; and an isolation structure arranged on the substrate, the isolation structure covering a side wall of the active region and a lower portion of a side wall of each of the plurality of active fins, wherein a first side wall of the active region adjacent to a first active fin among the plurality of active fins has a stepped shape, and the first active fin is arranged on a first edge of the active region in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0120153 filed on October 10, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to semiconductor devices. More particularly, example embodiments relate to semiconductor devices including fin field effect transistors (finFETs). Background Art

[0004] When forming finFETs, after performing a shallow trench isolation (STI) process to form active fins, an isolation layer is formed between active fins, and a so-called deep trench isolation (DTI) process may be performed, in which only some active fins in a desired area are left, and other active fins in the remaining area are removed by an etching process using an etching mask. However, when the DTI process is performed to remove the isolation layer and the active fins, the etching profile may not be vertical, so a portion of the adjacent active fin to be removed may remain to produce a ghost fin. An undesirable source / drain layer may be formed on the ghost fin, so an electrical short may occur. Summary of the invention

[0005] Example embodiments provide a semiconductor device including a finFET having improved characteristics.

[0006] According to an aspect of an example embodiment, a semiconductor device is provided, comprising: a substrate; an active region protruding upward from the substrate; a plurality of active fins protruding upward from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being arranged in a second direction parallel to the upper surface of the substrate and intersecting the first direction; and an isolation structure arranged on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins, wherein a first sidewall of the active region adjacent to a first active fin of the plurality of active fins has a stepped shape, and the first active fin is arranged on a first edge of the active region in the second direction.

[0007] According to another aspect of an example embodiment, a semiconductor device is provided, comprising: a substrate; an active region protruding upward from the substrate, the active region comprising: a lower portion having a first width in a second direction parallel to an upper surface of the substrate; and an upper portion disposed on the lower portion, the upper portion having a second width in the second direction that is smaller than the first width; an active fin protruding upward from the active region and extending in a first direction, the first direction being parallel to the upper surface of the substrate and intersecting the second direction; and an isolation structure disposed on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of the sidewall of the active fin.

[0008] According to another aspect of an example embodiment, a semiconductor device is provided, comprising: a substrate; an active region protruding upward from the substrate; a plurality of active fins protruding upward from the active region and extending in a first direction parallel to an upper surface of the substrate, the active fins being arranged in a second direction parallel to the upper surface of the substrate and intersecting the first direction; an isolation structure arranged on the substrate, the isolation structure covering a sidewall of the active region and a lower portion of a sidewall of each of the plurality of active fins; a gate structure respectively arranged on the plurality of active fins and the isolation structure, the gate structure extending in the second direction; and a source / drain layer arranged on the plurality of active fins adjacent to the gate structure, wherein a first sidewall of the active region adjacent to a first active fin of the plurality of active fins has a stepped shape, the first active fin being arranged on a first edge of the active region in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and / or other aspects will become apparent and more readily understood from the following description of example embodiments in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 19 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0011] Figure 20 to Figure 22 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a related example;

[0012] Figure 23 to Figure 28 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments; and

[0013] Fig.29 and Fig.30 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a related example. DETAILED DESCRIPTION

[0014] Semiconductor devices according to example embodiments will be described more fully hereinafter with reference to the accompanying drawings.

[0015] It will be understood that when an element or layer is referred to as being "above," "over," "on," "connected to," or "coupled to" another element or layer, it may be directly above, above, on, directly connected to, or coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "over," "on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. Throughout the accompanying drawings, similar reference numerals represent similar elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] Hereinafter, two directions substantially parallel to the upper surface of the substrate and intersecting each other are defined as a first direction and a second direction, respectively, and a vertical direction substantially perpendicular to the upper surface of the substrate is defined as a third direction. In example embodiments, the first direction and the second direction may be substantially orthogonal to each other.

[0017] Figures 1 to 19 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 1 , 3 , 6, 8, 11 and 15 are plan views, and Figure 2 , 4 -5, 7, 9-10, 12-14 and 16-19 are cross-sectional views.

[0018] Figure 2 , 4 , 9, 12 and 16 are respectively along Figure 1 , 3 , 8, 11 and 15 are cross-sectional views taken along line AA' corresponding to the plan views. Figure 5 , 13 and 17 are respectively along Figure 3 , 11 and a cross-sectional view taken along line BB' of the corresponding plan view in FIG. 15 . Figure 7 , 10 , 14 and 18 are respectively along Figure 6 , 8 , 11 and 15 are cross-sectional views taken along line CC' of the corresponding plan views. Fig.19 is along Fig.15 The cross-sectional view taken along the line D-D' corresponding to the plane view.

[0019] refer to Figure 1 and Figure 2, an upper portion of the substrate 100 may be etched through a first etching process using a first etching mask to form the active fins 110 .

[0020] The substrate 100 may include a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a III-V compound such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium telluride (GaSb), etc. In some example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0021] Hereinafter, a lower portion of the substrate 100 , that is, a portion of the substrate 100 having a height lower than the lower surface of the active fin 110 may be referred to as the substrate 100 , which may be distinguished from the active fin 110 .

[0022] In example embodiments, each active fin 110 may extend in a first direction, and a plurality of active fins 110 may be formed to be spaced apart from each other at regular intervals along a second direction perpendicular to the first direction, such as Figure 1 shown.

[0023] Due to the characteristics of a general etching process, each active fin 110 formed by the first etching process does not have a sidewall vertical to the upper surface of the substrate 100 in a third direction perpendicular to the first direction and the second direction, respectively, and may be formed to have an angle of, for example, greater than 80 degrees and less than 90 degrees relative to the upper surface of the substrate 100. Therefore, the width of each active fin 110 may gradually increase from its upper portion to its lower portion toward the upper surface of the substrate 100, and the width of the first recess 125 between the active fins 110 may gradually decrease from its upper portion to its lower portion.

[0024] After forming a first isolation layer on the substrate 100 to cover the active fin 110 , the first isolation layer may be planarized until an upper surface of the active fin 110 may be exposed, so that a first isolation pattern 120 may be formed to fill the first recess 125 .

[0025] The first isolation pattern 120 may include an oxide, for example, silicon oxide. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0026] refer to Figures 3 to 5 After forming the second etching mask 130 on the active fin 110 and the first isolation pattern 120, some of the active fins 110 and the first isolation pattern 120 adjacent thereto may be partially removed by a second etching process using the second etching mask 130, and thus, a first opening 140 may be formed to expose the upper surface of the substrate 100.

[0027] In example embodiments, a plurality of first openings 140 may be formed along the first direction, spaced apart from each other, and may extend along the second direction at different given lengths. In some regions, the first openings 140 extending in the second direction may be connected to each other.

[0028] In addition, when the distance between the first openings 140 is very small, it may be difficult to form all the first openings 140 using one second etching mask 130. Therefore, some first openings 140 may be formed by a second etching process using the second etching mask 130, and the remaining first openings 140 may be formed by additionally performing a third etching process using a third etching mask.

[0029] In example embodiments, the first opening 140 formed by the second etching process may expose the upper surface of the substrate 100, and the upper portion of the substrate 100 may be partially removed in the second etching process, so that the lower surface of the first opening 140 may be lower than the upper surface of the substrate 100 in the third direction, as shown in FIG. Figure 4 Therefore, the lower surface of the first opening 140 may be lower than the lower surface of the active fin 110 in the third direction.

[0030] The second etching process may be performed on the upper surface of the substrate 100 at an angle (eg, greater than 80 degrees and less than 90 degrees) along a third direction.

[0031] refer to Figure 6 and Figure 7 , the second etch mask 130 may be removed, and a second isolation pattern 150 may be formed to fill the first opening 140 .

[0032] The second isolation pattern 150 may be formed by forming a second isolation layer on the substrate 100, the active fin 110, and the first isolation pattern 120 to fill the first opening 140, and planarizing the second isolation layer until the upper surface of the active fin 110 may be exposed. The second isolation pattern 150 may include an oxide, such as silicon oxide. In example embodiments, the second isolation pattern 150 may include a material substantially the same as that of the first isolation pattern 120, and thus may be merged with the first isolation pattern 120. However, example embodiments are not limited thereto.

[0033] A fourth etching mask 160 may be formed on the active fin 110, the first isolation pattern 120, and the second isolation pattern 150. Portions of the active fin 110 and portions of the first isolation pattern 120 and the second isolation pattern 150 adjacent thereto may be partially removed by a fourth etching process using the fourth etching mask 160, and thus a second opening 170 may be formed to expose the upper surface of the substrate 100.

[0034] In example embodiments, a plurality of second openings 170 may be formed in the second direction, spaced apart, and may extend in the first direction at different given lengths. In some regions, the second openings 170 extending in the first direction may be connected to each other.

[0035] In example embodiments, the second opening 170 formed by the fourth etching process may expose the upper surface of the substrate 100, and the upper portion of the substrate 100 may be partially removed in the fourth etching process, so that the lower surface of the second opening 170 may be lower than the upper surface of the substrate 100 in the third direction, as shown in FIG. Figure 7 As shown. Therefore, the lower surface of the second opening 170 may be lower than the lower surface of the active fin 110 in the third direction. In example embodiments, the lower surface of the second opening 170 may be formed at a height substantially the same as that of the lower surface of the first opening 140. However, example embodiments are not limited thereto, and the height of the lower surface of the second opening 170 may be different from that of the lower surface of the first opening 140.

[0036] The fourth etching process may be performed on the upper surface of the substrate 100 at an angle (eg, greater than 80 degrees and less than 90 degrees) along the third direction.

[0037] refer to Figures 8 to 10 , the fourth etch mask 160 may be removed, and a third isolation pattern 180 may be formed to fill the second opening 170 .

[0038] The third isolation pattern 180 may be formed by forming a third isolation layer on the substrate 100, the active fin 110, and the first and second isolation patterns 120 and 150 to fill the second opening 170, and planarizing the third isolation layer until the upper surface of the active fin 110 may be exposed. The third isolation pattern 180 may include an oxide, such as silicon oxide. In example embodiments, the third isolation pattern 180 may include a material substantially the same as that of the first and second isolation patterns 120 and 150, and thus may be merged with the first and second isolation patterns 120 and 150. However, example embodiments are not limited thereto.

[0039] A fifth etching mask 190 may be formed on the active fin 110 and the first to third isolation patterns 120, 150, and 180. Some of the active fins 110 and the first to third isolation patterns 120, 150, and 180 adjacent thereto may be partially removed by a fifth etching process using the fifth etching mask 190, and thus a third opening 200 may be formed to expose the upper surface of the substrate 100.

[0040] In example embodiments, a plurality of third openings 200 may be formed in the second direction, spaced apart, and may extend in the first direction at different given lengths. In some regions, the third openings 200 extending in the first direction may be connected to each other.

[0041] In example embodiments, some of the third openings 200 may be formed at a distance very close to some of the second openings 170 formed by the fourth etching mask 160. When the distance between the second openings 170 is very small, it may be difficult to form all of the second openings 170 using only one fourth etching mask 160. Therefore, except for some of the second openings 170 formed by the fourth etching process, Figures 8 to 10 The fifth etching process described in EMBODIMENT 3 may form the remaining second openings 170 to be formed to extend in the first direction.

[0042] In example embodiments, the third opening 200 formed by the fifth etching process may expose the upper surface of the substrate 100, and further, the upper portion of the substrate 100 may be partially removed in the fifth etching process so that the lower surface of the third opening 200 may be lower than the upper surface of the substrate 100 in the third direction, as shown in FIG. Fig. 9 As shown. Therefore, the lower surface of the third opening 200 may be lower than the lower surface of the active fin 110 in the third direction. In example embodiments, the lower surface of the third opening 200 may be formed at a height substantially the same as the height of the lower surfaces of the first opening 140 and the second opening 170. However, example embodiments are not limited thereto, and the height of the lower surface of the third opening 200 may be different from the height of the lower surfaces of the first opening 140 and the second opening 170.

[0043] The fifth etching process may be performed on the upper surface of the substrate 100 along the third direction at an angle (eg, greater than 80 degrees and less than 90 degrees).

[0044] refer to Figures 11 to 15 , the fifth etch mask 190 may be removed, and a fourth isolation pattern 210 may be formed to fill the third opening 200 .

[0045] The fourth isolation pattern 210 may be formed by forming a fourth isolation layer on the substrate 100, the active fin 110, and the first to third isolation patterns 120, 150, and 180 to fill the third opening 200, and planarizing the fourth isolation layer until the upper surface of the active fin 110 may be exposed. The fourth isolation pattern 210 may include an oxide, such as silicon oxide. In example embodiments, the fourth isolation pattern 210 may include a material substantially the same as that of the first to third isolation patterns 120, 150, and 180, and thus may be merged with the first to third isolation patterns 120, 150, and 180. However, example embodiments are not limited thereto.

[0046] The sixth etching mask 220 can be formed on the active fin 110 and the first to fourth isolation patterns 120, 150, 180 and 210, and the sixth etching mask 220 can be used to partially remove some of the active fins 110 and the first to fourth isolation patterns 120, 150, 180 and 210 adjacent to them, as well as the upper portion of the substrate 100 through a sixth etching process, so that a second recess 230 can be formed on the upper surface of the substrate 100.

[0047] In example embodiments, the lower surface of the second recess 230 formed by the sixth etching process may be lower than the lower surface of the active fin 110 in the third direction and lower than the lower surfaces of the first to fourth isolation patterns 120, 150, 180, and 210. Fig.12 As shown. Therefore, the active area 102 defined by the second recess 230 may be formed on the substrate 100. Hereinafter, the lower portion of the substrate 100, that is, a portion of the substrate 100 whose height is lower than the lower surface of the active area 102 may be referred to as the substrate 100, which may be separated from the active area 102. As a result, the active area 102 may be formed on the substrate 100, and the active fin 110 may be formed on the active area 102.

[0048] The sixth etching process may be performed on the upper surface of the substrate 100 at an angle (eg, greater than 80 degrees and less than 90 degrees) along the third direction.

[0049] Misalignment may occur during the process for forming the sixth etching mask 220 used in the sixth etching process, and thus, for example, the second recess 230 may be formed at a region offset by a given length from a desired position in the second direction. Fig.12 and Fig.14 As described above, for example, a portion of the fourth isolation pattern 210 covering the first sidewall of the first active fin 110 on the first edge in the second direction among the active fins 110 on the active region 102 may not be completely removed during the process of forming the second recess 230 .

[0050] in the case of Figures 8 to 10 In the example embodiment, the fifth etching process is performed to completely remove the second active fins 110, and therefore, even when misalignment occurs during the process for forming the sixth etching mask 220, all desired active fins 110 including the second active fins 110 may be removed. Figure 20 to Figure 22 This is described in more detail.

[0051] refer to Figures 16 to 19 , the sixth etch mask 220 may be removed, and a fifth isolation pattern 240 may be formed to fill the second recess 230 .

[0052] The fifth isolation pattern 240 may be formed by forming a fifth isolation layer on the substrate 100, the active fin 110, and the first to fourth isolation patterns 120, 150, 180, and 210 to fill the second recess 230, and planarizing the fifth isolation layer until the upper surface of the active fin 110 may be exposed. The fifth isolation pattern 240 may include an oxide, such as silicon oxide. In example embodiments, the fifth isolation pattern 240 may include a material substantially the same as that of the first to fourth isolation patterns 120, 150, 180, and 210, and thus may be merged with the first to fourth isolation patterns 120, 150, 180, and 210. However, example embodiments are not limited thereto.

[0053] Hereinafter, the first to fifth isolation patterns 120 , 150 , 180 , 210 , and 240 may be referred to as an isolation structure 250 .

[0054] The upper portion of the isolation structure 250 may be removed to expose the upper portion of the active fin 110. Therefore, each active fin 110 may include a lower active pattern 110b whose sidewall may be covered by the isolation structure 250 and an upper active pattern 110a protruding upward from the isolation structure 250 in the third direction.

[0055] Through the above processes, a semiconductor device including the active fin 110 , the active region 102 , and the isolation structure 250 at least partially covering the sidewalls thereof may be formed on the substrate 100 .

[0056] As described above, before the sixth etching process is performed to define the active area 102 by forming the second recess 230 on the substrate 100, the fourth etching process and the fifth etching process using the fourth etching mask 160 and the fifth etching mask 190 may be performed. The second opening 170 and the third opening 200 formed by the fourth etching process and the fifth etching process may be formed on both sides of the active area 102 to be finally realized in the second direction, and thus the active fins 110 on both sides of the active area 102 in the second direction may be removed by the fourth etching process and the fifth etching process. Therefore, even when misalignment occurs during the process for forming the sixth etching mask used in the sixth etching process, which is performed to form the active area 102, the active fins 110 may not remain outside the active area 102.

[0057] For example, the semiconductor device may have a region X including an active region 102 on which two active fins 110 are formed, as described below. In this case, the two active fins 110 are referred to as a first active fin 112 and a second active fin 114, respectively.

[0058] refer to Fig.19 , the active region 102 protruding upward from the substrate 100 may include a lower portion 102b and an upper portion 102a, the lower portion 102b having a first width W1 in a second direction substantially parallel to the upper surface of the substrate 100, and the upper portion 102a is formed on the lower portion 102b, and the upper portion 102a has a second width W2 in the second direction that is smaller than the first width W1. That is, of the two sidewalls of the active region 102 in the second direction, the first sidewall of the active region 102 adjacent to the first active fin 112 may be bent or curved at a boundary between the lower portion 102b and the upper portion 102a, and since the first sidewall may have a stepped shape as a whole, the width of the upper portion 102a may be smaller than the width of the lower portion 102b.

[0059] Therefore, a distance from an upper portion of the first sidewall of the active region 102 (i.e., a sidewall of the upper portion 102 a of the active region 102 ) to the first active fin 112 along the second direction may be smaller than a distance from a lower portion of the first sidewall of the active region 102 (i.e., a sidewall of the lower portion 102 b of the active region 102 ) to the first active fin 112 along the second direction.

[0060] The second sidewall of the active region 102 opposite to the first sidewall may not be curved or bent, but may be flat along the third direction, and thus may have a constant slope with respect to the upper surface of the substrate 100 .

[0061] Each of the first and second active fins 112 and 114 may protrude upward from the active region 102 and extend in the first direction, and sidewalls of the active region 102 and lower sidewalls of the first and second active fins 112 and 114 may be covered by an isolation structure 250 on the substrate 100 .

[0062] In example embodiments, a first protrusion 115 may be formed between the first active fin 112 and the first sidewall of the active region 102, and the first protrusion 115 may be a residue of the active fin 110 removed by the fifth etching process using the fifth etching mask 190. The height of the upper surface of the first protrusion 115 may be lower than the height of the upper surface of the isolation structure 250, so the source / drain layer 370 may not be grown by the selective epitaxial growth process (which will be referred to as the epitaxial growth process). Fig.24 and 25 Description) is formed on the first protrusion 115.

[0063] The sidewall of the second active fin 114 may directly contact the second sidewall of the active region 102 , and the first protrusion 115 may not be formed therebetween.

[0064] As described above, the isolation structure 250 may include first to fifth isolation patterns 120, 150, 180, 210, and 240. The first to fifth isolation patterns 120, 150, 180, 210, and 240 may all have upper surfaces formed at the same height in the third direction and be arranged in a horizontal direction substantially parallel to the upper surface of the substrate 100. However, in the region X, the first isolation pattern 120 and the second isolation pattern 150, the fourth isolation pattern 210, and the fifth isolation pattern 240 may be formed, the first isolation pattern 120 and the second isolation pattern 150 respectively covering the lower sidewalls of the first active fin 112 and the second active fin 114, the fourth isolation pattern 210 covering the upper portion of the first sidewall of the active region, and the fifth isolation pattern 240 covering the lower portion of the first sidewall of the active region 102.

[0065] Figure 20 to Figure 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a related example.

[0066] refer to Fig. 20 , the sixth etching process may be performed immediately after the first to third etching processes. Therefore, when misalignment occurs during the process for forming the sixth etching mask 220 used in the sixth etching process, some of the active fins 110 to be removed by the second recess 230 may not be removed and remain as the second protrusion 117. In this case, the second protrusion 117 may have an upper surface higher than an upper surface of the first protrusion 115 in the third direction.

[0067] refer to Fig.21 and 22 , can be executed with Figures 15 to 19 The processes described in the accompanying drawings are basically the same or similar processes to complete the manufacture of the semiconductor device.

[0068] However, the second protrusion 117 may not be completely covered by the isolation structure 250, and a portion of the second protrusion 117 may protrude upward. Therefore, the second protrusion 117 may include a lower portion 117b and an upper portion 117a, the sidewall of the lower portion 117b may be covered by the isolation structure 250, and the upper portion 117a protrudes upward from the isolation structure 250 and is exposed. Fig.29 The described selective epitaxial growth (SEG) process forms the source / drain layer 370 on the second protrusion 117 .

[0069] Figure 23 to Figure 28 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig.23 , 24 and 26 is along Fig.15 A cross-sectional view taken along line BB', and Fig.25 , 27 and 28 is along Fig.15 Cross-sectional view taken along line D-D'.

[0070] The method of manufacturing a semiconductor device involves forming a transistor and a contact plug on an active fin and Figures 1 to 19 A method for manufacturing a logic device using an isolation structure formed by the process described in the invention.

[0071] refer to Fig.23 , a dummy gate structure 330 may be formed on the substrate 100 .

[0072] Specifically, a dummy gate insulation layer, a dummy gate electrode layer and a dummy gate mask layer can be sequentially formed on the active fin 110 and the isolation structure 250, the dummy gate mask layer can be patterned to form a dummy gate mask 320, and the dummy gate electrode layer and the dummy gate insulation layer can be sequentially etched using the dummy gate mask 320 as an etching mask to form a dummy gate structure 330.

[0073] Thus, a dummy gate structure 330 including a dummy gate insulating pattern 300, a dummy gate electrode 310, and a dummy gate mask 320 sequentially stacked may be formed on the substrate 100. The dummy gate insulating pattern 300 may include an oxide such as silicon oxide, the dummy gate electrode 310 may include, for example, polysilicon, and the dummy gate mask 320 may include a nitride such as silicon nitride.

[0074] In example embodiments, the dummy gate structure 330 may extend in the second direction, and a plurality of dummy gate structures 330 may be formed along the first direction.

[0075] refer to Fig.24 and 25 , the gate spacer 340 may be formed on the sidewall of the dummy gate structure 330 .

[0076] The gate spacer 340 may be formed by forming a spacer layer on the active fin 110 and the isolation structure 250 to cover the dummy gate structure 330, and anisotropically etching the spacer layer. In this case, the gate spacer 340 may be formed on the sidewall of the dummy gate structure 330, and the fin spacer 350 may be further formed on each sidewall of the active pattern 110a. The gate spacer 340 and the fin spacer 350 may include a nitride, such as silicon nitride.

[0077] An upper portion of the active fin 110 adjacent to the dummy gate structure 330 may be etched to form a third recess 360 , and a source / drain layer 370 may be formed to fill the third recess 360 .

[0078] Specifically, the third recess 360 may be formed by performing a seventh etching process using the dummy gate structure 330 and the gate spacer 340 on the sidewall thereof as an etching mask to remove the upper portion of the active fin 110. When the third recess 360 may be formed, most of the fin spacer 350 adjacent to the active fin 110 may be removed, however, the lower portion of the fin spacer 350 may be partially retained.

[0079] Fig.24 It is shown that only a portion of the upper active pattern 110a on each of the active fins 110 is removed, so the lower surface of the third recess 360 is higher than the upper surface of the lower active pattern 110b in the third direction, however, example embodiments are not limited thereto, and the lower surface of the third recess 360 may be equal to or lower than the upper surface of the lower active pattern 110b.

[0080] In example embodiments, the source / drain layer 370 may be formed by performing a selective epitaxial growth (SEG) process using the upper surface of the active fin 110 exposed by the third recess 360 .

[0081] In example embodiments, a SEG process may be performed so that a single crystal silicon germanium layer may be formed as the source / drain layer 370. The SEG process may be performed with a p-type impurity source gas, and thus a single crystal silicon germanium layer doped with p-type impurities may be formed as the source / drain layer 370. Therefore, the source / drain layer 370 may be used as a source / drain of a PMOS transistor.

[0082] The source / drain layer 370 may expand vertically and horizontally to fill the third recess 360 , and an upper portion of the source / drain layer 370 may contact a sidewall of the gate spacer 340 .

[0083] In example embodiments, the source / drain layers 370 respectively extended on adjacent active fins 110 (ie, the first active fin 112 and the second active fin 114 ) in the second direction may be connected to each other to be merged.

[0084] Although the source / drain layer 370 used as the source / drain of the PMOS transistor has been described above, example embodiments are not limited thereto, and the source / drain layer 370 may be formed to function as the source / drain of an NMOS transistor.

[0085] Therefore, a single crystal silicon carbide layer or a single crystal silicon layer may be formed as the source / drain layer 370. The SEG process may be performed with an n-type impurity source gas (eg, phosphine (PH 3)) are performed together, so a single-crystal silicon carbide layer doped with n-type impurities or a single-crystal silicon layer doped with n-type impurities can be formed.

[0086] refer to Fig.26 and 27 After the first insulating interlayer 380 is formed on the substrate 100 to a sufficient height in the third direction to cover the dummy gate structure 330, the gate spacer 340, the source / drain layer 370 and the fin spacer 350, the first insulating interlayer 380 can be planarized until the upper surface of the dummy gate electrode 310 in the dummy gate structure 330 can be exposed.

[0087] The dummy gate mask 320 may also be removed, and the upper portion of the gate spacer 340 may also be removed. The first insulating interlayer 380 may not completely fill the space between the merged source / drain layer 370 and the isolation structure 250, and thus an air gap 385 may be formed. The first insulating interlayer 380 may include an oxide, such as silicon oxide.

[0088] The exposed dummy gate electrode 310 and the dummy gate insulating pattern 300 thereunder may be removed to form a fourth opening 390 exposing inner sidewalls of the gate spacer 340 and an upper surface of the active fin 110 , and a gate structure 440 may be formed to fill the fourth opening 390 .

[0089] For example, the gate structure 440 may be formed by performing the following process.

[0090] After performing a thermal oxidation process on the upper surface of the active fin 110 exposed by the fourth opening 390 to form the interface pattern 400, a gate insulation layer and a work function control layer can be sequentially formed on the interface pattern 400, the isolation structure 250, the gate spacer 340 and the first insulating interlayer 380, and a gate electrode layer can be formed on the work function control layer to fill the remaining portion of the fourth opening 390.

[0091] The interface pattern 400 may also be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc., and in this case, the interface pattern 400 may be formed not only on the upper surface of the active fin 110 , but also on the upper surface of the isolation structure 250 and the inner sidewall of the gate spacer 340 .

[0092] The gate electrode layer, the work function control layer, and the gate insulating layer may be planarized until the upper surface of the first insulating interlayer 380 may be exposed, and a gate insulating pattern 410 and a work function control pattern 420 may be sequentially stacked on the upper surface of the interface pattern 400, the upper surface of the isolation structure 250, and the inner sidewall of the gate spacer 340. In addition, a gate electrode 430 may be formed on the work function control pattern 420 to fill the remaining portion of the fourth opening 390. Therefore, the lower surface and the sidewall of the gate electrode 430 may be covered by the work function control pattern 420.

[0093] The sequentially stacked interface pattern 400, gate insulating pattern 410, work function control pattern 420 and gate electrode 430 may form a gate structure 440 and may form a transistor together with the source / drain layer 370. Depending on the conductivity type of the source / drain layer 370, the transistor may form an NMOS transistor or a PMOS transistor.

[0094] The interface pattern 400 may include an oxide, such as silicon oxide, the gate insulation pattern 410 may include a metal oxide, such as hafnium oxide, zirconium oxide, etc., the work function control pattern 420 may include a metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, etc., and the gate electrode 430 may include a low-resistance metal, such as aluminum, copper, titanium, tantalum, etc., their nitrides or their alloys.

[0095] An upper portion of the gate structure 440 may be removed to form a fourth recess, and a capping pattern 450 may be formed to fill the fourth recess. The capping pattern 450 may include a nitride, such as silicon nitride.

[0096] refer to Fig.28 , a second insulating interlayer 460 may be formed on the first insulating interlayer 380, the capping pattern 450, and the gate spacer 340. A first contact plug 480 may be formed through the first insulating interlayer 380 and the second insulating interlayer 460 to contact an upper surface of the source / drain layer 370.

[0097] For example, the first contact plug 480 may be formed by performing the following process.

[0098] A fifth opening can be formed through the first insulating interlayer 380 and the second insulating interlayer 460 to expose the upper surface of the source / drain layer 370, a first metal layer can be formed on the exposed upper surface of the source / drain layer 370, on the sidewalls of the fifth opening, and on the upper surface of the second insulating interlayer 460, and a heat treatment process can be performed to form a metal silicide pattern 470 on the upper portion of the source / drain layer 370.

[0099] A first barrier layer may be formed on the upper surface of the metal silicide pattern 470, on the sidewalls of the fifth opening, and on the upper surface of the second insulating interlayer 460, a second metal layer may be formed on the first barrier layer to fill the fifth opening, and the second metal layer and the first barrier layer may be planarized until the upper surface of the second insulating interlayer 460 may be exposed.

[0100] Thus, a first contact plug 480 filling the fifth opening may be formed on the metal silicide pattern 470. The first contact plug 480 may include a first barrier pattern covering the second metal pattern as well as a lower surface and sidewalls thereof.

[0101] A second contact plug contacting an upper portion of the gate structure 440 and a wiring electrically connected to the first contact plug 480 and the second contact plug may be further formed to complete the manufacture of the semiconductor device.

[0102] As described above, all active fins 110 to be removed may be removed more efficiently, so that desired active fins 110 may be formed only on the active region 102, and source / drain layers 370 may be formed only on desired active fins 110. The source / drain layers 370 may not be formed on the remaining first protrusions 115 in the active fins 110, so that electrical shorts with, for example, adjacent gate structures 440 may be reduced or prevented.

[0103] Fig.29 and Fig.30 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a related example. Specifically, Fig.29 and 30 is along Fig.15 Cross-sectional view taken along line D-D'.

[0104] refer to Fig.29 , can be executed with reference Figure 23 to Figure 25 The processes described are substantially the same or similar processes.

[0105] However, the second protrusion 117 adjacent to the active fin 110 may include an upper portion 117a protruding upward from the isolation structure 250. Therefore, the parasitic source / drain layer 375 may be formed not only on the upper portion of the active fin 110 but also on the upper portion of the second protrusion 117 and may merge with the source / drain layer 370 adjacent thereto.

[0106] refer to Fig.30 , can be executed with Figures 26 to 28 The processes described in the accompanying drawings are basically the same or similar processes to complete the manufacture of the semiconductor device.

[0107] The first contact plug 480 on the source / drain layer 370 may be electrically connected to the parasitic source / drain layer 375 merged with the source / drain layer 370 , and thus an electrical short may occur due to an undesired current path.

[0108] The semiconductor device described above can be applied to various types of memory devices and systems including finFETs. For example, the semiconductor device can be applied to logic devices such as a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP) including finFETs. In addition, the semiconductor device can be applied to volatile memory devices such as SRAM devices or DRAM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, etc.

[0109] Although example embodiments have been described with reference to the drawings, workers skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the claims.

Claims

1. A semiconductor device, comprising: substrate; an active region protruding upward from the substrate, the active region comprising an upper portion and a lower portion; a plurality of active fins protruding upward from the active region and extending in a first direction parallel to an upper surface of the substrate, the plurality of active fins being arranged in a second direction parallel to the upper surface of the substrate and intersecting the first direction; an isolation structure disposed on the substrate, the isolation structure covering the first sidewall of the active region and a lower portion of the sidewall of each of the plurality of active fins, A gate structure, disposed on the plurality of active fins and the isolation structure, respectively, the gate structure extending in the second direction; as well as a source layer / drain layer disposed on the plurality of active fins adjacent to the gate structure, The first sidewall of the active region is arranged to be adjacent to a first active fin among the plurality of active fins, and the first active fin is arranged on a first edge of the active region in the second direction. wherein an upper portion of the first sidewall of the active region, an upper surface of the upper portion of the active region, and a sidewall of the first active fin form a stepped shape, and The semiconductor device further includes: a protrusion between the first active fin and the first side wall of the active region, and the source layer / drain layer is not disposed on the protrusion.

2. The semiconductor device according to claim 1, wherein A first distance from the upper portion of the first sidewall of the active region to the sidewall of the first active fin in the second direction is smaller than a second distance from the lower portion of the first sidewall of the active region to the sidewall of the first active fin in the second direction, and both the first distance and the second distance are greater than zero.

3. The semiconductor device according to claim 1, wherein A second sidewall of the active region adjacent to a second active fin of the plurality of active fins has a constant slope relative to the upper surface of the substrate, and the second active fin is disposed on a second edge of the active region opposite to the first edge in the second direction.

4. The semiconductor device according to claim 1, wherein: An upper surface of the protrusion is lower than an upper surface of the isolation structure.

5. The semiconductor device according to claim 3, wherein: A sidewall of the second active fin directly contacts the second sidewall of the active region.

6. The semiconductor device according to claim 3, wherein: The isolation structure includes a first isolation pattern, a second isolation pattern, and a third isolation pattern disposed in the second direction.

7. The semiconductor device according to claim 6, wherein: An upper surface of the first isolation pattern, an upper surface of the second isolation pattern, and an upper surface of the third isolation pattern are disposed at the same height.

8. The semiconductor device according to claim 6, wherein: The first isolation pattern covers a lower portion of a sidewall of each of the plurality of active fins, the second isolation pattern covers an upper portion of the second sidewall of the active region, and the third isolation pattern covers a lower portion of the second sidewall of the active region.

9. The semiconductor device according to claim 1, wherein: Two active fins of the plurality of active fins are disposed on the active region.

10. A semiconductor device comprising: substrate; An active region protrudes upward from the substrate, the active region comprising: a lower portion having a first width in a second direction parallel to the upper surface of the substrate; and an upper portion disposed on the lower portion, the upper portion having a second width in the second direction that is smaller than the first width; an active fin protruding upward from the active region and extending in a first direction, the first direction being parallel to the upper surface of the substrate and intersecting the second direction; An isolation structure, disposed on the substrate, the isolation structure covering the first sidewall of the active region and the lower portion of the sidewall of the active fin; A gate structure, disposed on the active fin and the isolation structure respectively, the gate structure extending in the second direction; a source / drain layer disposed on the active fin adjacent to the gate structure, and a protrusion between the active fin and the first sidewall of the active region, and the source layer / drain layer is not disposed on the protrusion, The first side wall of the active region in the second direction is bent at a boundary between the upper portion of the active region and the lower portion of the active region.

11. The semiconductor device according to claim 10, wherein: A second sidewall of the active region opposite to the first sidewall in the second direction is flat at a boundary between the upper portion of the active region and the lower portion of the active region.

12. The semiconductor device according to claim 10, in, The height of the upper surface of the protrusion is lower than the height of the upper surface of the isolation structure.

13. The semiconductor device according to claim 10, further comprising: A plurality of active fins are arranged on the active region in the second direction, and the plurality of active fins include the active fin.

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